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Differential D73259

[VE][NFC] re-write RR* isel class using null_frag
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Authored by simoll on Jan 23 2020, 2:10 AM.

Details

Reviewers
arsenm
rengolin
craig.topper
k-ishizaka
Commits
rG9187073f3e05: [VE][NFC] re-write RR* isel class using null_frag
Summary

Re-write RR* using null_frag to avoid duplication in upcoming patches.

Diff Detail

Event Timeline

simoll created this revision.Jan 23 2020, 2:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 23 2020, 2:10 AM
Herald added subscribers: llvm-commits, hiraditya, wdng. · View Herald Transcript
simoll planned changes to this revision.Jan 23 2020, 2:12 AM
  • more de-duplication..
simoll updated this revision to Diff 239820.Jan 23 2020, 2:23 AM
simoll retitled this revision from [VE][NFC] re-write RRm isel class using null_frag to [VE][NFC] re-write RR* isel class using null_frag.
simoll edited the summary of this revision. (Show Details)
  • map RRNDm to RRm with null_frag
simoll updated this revision to Diff 239821.Jan 23 2020, 2:26 AM

typo

merge_guards_bot added a subscriber: merge_guards_bot.Jan 23 2020, 2:35 AM

Unit tests: pass. 62129 tests passed, 0 failed and 808 were skipped.

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Harbormaster completed remote builds in B44687: Diff 239815.Jan 23 2020, 2:36 AM
simoll added a child revision: D73207: [VE] add, sub, left/right shift isel patterns.Jan 23 2020, 2:42 AM
merge_guards_bot added a comment.Jan 23 2020, 2:47 AM

Unit tests: pass. 62129 tests passed, 0 failed and 808 were skipped.

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Harbormaster completed remote builds in B44688: Diff 239820.Jan 23 2020, 2:48 AM
merge_guards_bot added a comment.Jan 23 2020, 2:49 AM

Unit tests: pass. 62130 tests passed, 0 failed and 808 were skipped.

clang-tidy: fail. clang-tidy found 0 errors and 1 warnings.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Harbormaster failed remote builds in B44689: Diff 239821!Jan 23 2020, 2:53 AM
arsenm added inline comments.Jan 23 2020, 4:44 AM
llvm/lib/Target/VE/VEInstrInfo.td
227

Usually this is the last parameter with a default value of null_frag

simoll updated this revision to Diff 239860.Jan 23 2020, 5:13 AM
  • moved OpNode=null_frag to last position.
  • Stripped RRNDm
arsenm accepted this revision.Jan 23 2020, 5:32 AM
This revision is now accepted and ready to land.Jan 23 2020, 5:32 AM
merge_guards_bot added a comment.Jan 23 2020, 5:50 AM

Unit tests: pass. 62133 tests passed, 0 failed and 808 were skipped.

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Pre-merge checks is in beta. Report issue. Please join beta or enable it for your project.

Harbormaster completed remote builds in B44705: Diff 239860.Jan 23 2020, 5:53 AM
Closed by commit rG9187073f3e05: [VE][NFC] re-write RR* isel class using null_frag (authored by simoll). · Explain WhyJan 23 2020, 6:21 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
98 lines

Diff 239879

llvm/lib/Target/VE/VEInstrInfo.td

Show First 20 Lines • Show All 218 Lines • ▼ Show 20 Lines
def CC_GENAN : CC_VAL<19>; // Greater or Equal or NaN def CC_GENAN : CC_VAL<19>; // Greater or Equal or NaN
def CC_LENAN : CC_VAL<20>; // Less or Equal or NaN def CC_LENAN : CC_VAL<20>; // Less or Equal or NaN
def CC_AT : CC_VAL<21>; // Always true def CC_AT : CC_VAL<21>; // Always true
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VE Multiclasses for common instruction formats // VE Multiclasses for common instruction formats
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
multiclass RMm<string opcStr, bits<8>opc, multiclass RMm<string opcStr, bits<8>opc,
arsenmUnsubmitted
Not Done
ReplyInline Actions

Usually this is the last parameter with a default value of null_frag

arsenm: Usually this is the last parameter with a default value of null_frag
RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> { RegisterClass RC, ValueType Ty,
Operand immOp, Operand immOp2,
SDPatternOperator OpNode=null_frag> {
def rri : RM< def rri : RM<
opc, (outs RC:$sx), (ins RC:$sy, RC:$sz, immOp2:$imm32), opc, (outs RC:$sx), (ins RC:$sy, RC:$sz, immOp2:$imm32),
!strconcat(opcStr, " $sx, ${imm32}($sy, ${sz})")> { !strconcat(opcStr, " $sx, ${imm32}($sy, ${sz})")> {
let cy = 1; let cy = 1;
let cz = 1; let cz = 1;
let hasSideEffects = 0; let hasSideEffects = 0;
} }
def rzi : RM< def rzi : RM<
opc, (outs RC:$sx), (ins RC:$sz, immOp2:$imm32), opc, (outs RC:$sx), (ins RC:$sz, immOp2:$imm32),
!strconcat(opcStr, " $sx, ${imm32}(${sz})")> { !strconcat(opcStr, " $sx, ${imm32}(${sz})"),
[(set Ty:$sx, (OpNode Ty:$sz, (Ty simm32:$imm32)))]> {
let cy = 0; let cy = 0;
let sy = 0; let sy = 0;
let cz = 1; let cz = 1;
let hasSideEffects = 0; let hasSideEffects = 0;
} }
def zzi : RM< def zzi : RM<
opc, (outs RC:$sx), (ins immOp2:$imm32), opc, (outs RC:$sx), (ins immOp2:$imm32),
!strconcat(opcStr, " $sx, $imm32")> { !strconcat(opcStr, " $sx, $imm32")> {
let cy = 0; let cy = 0;
let sy = 0; let sy = 0;
let cz = 0; let cz = 0;
let sz = 0; let sz = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
} }
} }
// Multiclass for RR type instructions // Multiclass for RR type instructions
multiclass RRmrr<string opcStr, bits<8>opc, SDNode OpNode, multiclass RRmrr<string opcStr, bits<8>opc,
RegisterClass RCo, ValueType Tyo, RegisterClass RCo, ValueType Tyo,
RegisterClass RCi, ValueType Tyi> { RegisterClass RCi, ValueType Tyi,
SDPatternOperator OpNode=null_frag> {
def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz), def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz),
!strconcat(opcStr, " $sx, $sy, $sz"), !strconcat(opcStr, " $sx, $sy, $sz"),
[(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]> [(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]>
{ let cy = 1; let cz = 1; let hasSideEffects = 0; } { let cy = 1; let cz = 1; let hasSideEffects = 0; }
} }
multiclass RRNDmrr<string opcStr, bits<8>opc, multiclass RRmri<string opcStr, bits<8>opc,
RegisterClass RCo, ValueType Tyo, RegisterClass RCo, ValueType Tyo,
RegisterClass RCi, ValueType Tyi> { RegisterClass RCi, ValueType Tyi, Operand immOp,
def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz), SDPatternOperator OpNode=null_frag> {
!strconcat(opcStr, " $sx, $sy, $sz")>
{ let cy = 1; let cz = 1; let hasSideEffects = 0; }
}
multiclass RRmri<string opcStr, bits<8>opc, SDNode OpNode,
RegisterClass RCo, ValueType Tyo,
RegisterClass RCi, ValueType Tyi, Operand immOp> {
// VE calculates (OpNode $sy, $sz), but llvm requires to have immediate // VE calculates (OpNode $sy, $sz), but llvm requires to have immediate
// in RHS, so we use following definition. // in RHS, so we use following definition.
def ri : RR<opc, (outs RCo:$sx), (ins RCi:$sz, immOp:$sy), def ri : RR<opc, (outs RCo:$sx), (ins RCi:$sz, immOp:$sy),
!strconcat(opcStr, " $sx, $sy, $sz"), !strconcat(opcStr, " $sx, $sy, $sz"),
[(set Tyo:$sx, (OpNode Tyi:$sz, (Tyi simm7:$sy)))]> [(set Tyo:$sx, (OpNode Tyi:$sz, (Tyi simm7:$sy)))]>
{ let cy = 0; let cz = 1; let hasSideEffects = 0; } { let cy = 0; let cz = 1; let hasSideEffects = 0; }
} }
multiclass RRmiz<string opcStr, bits<8>opc, SDNode OpNode, multiclass RRmiz<string opcStr, bits<8>opc,
RegisterClass RCo, ValueType Tyo, RegisterClass RCo, ValueType Tyo,
RegisterClass RCi, ValueType Tyi, Operand immOp> { RegisterClass RCi, ValueType Tyi, Operand immOp,
SDPatternOperator OpNode=null_frag> {
def zi : RR<opc, (outs RCo:$sx), (ins immOp:$sy), def zi : RR<opc, (outs RCo:$sx), (ins immOp:$sy),
!strconcat(opcStr, " $sx, $sy"), !strconcat(opcStr, " $sx, $sy"),
[(set Tyo:$sx, (OpNode (Tyi simm7:$sy), 0))]> [(set Tyo:$sx, (OpNode (Tyi simm7:$sy), 0))]>
{ let cy = 0; let cz = 0; let sz = 0; let hasSideEffects = 0; } { let cy = 0; let cz = 0; let sz = 0; let hasSideEffects = 0; }
} }
multiclass RRNDmrm<string opcStr, bits<8>opc, multiclass RRNDmrm<string opcStr, bits<8>opc,
RegisterClass RCo, ValueType Tyo, RegisterClass RCo, ValueType Tyo,
Show All 25 Lines def im1 : RR<opc, (outs RCo:$sx), (ins immOp:$sy, immOp2:$sz),
let cz = 0; let cz = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
} }
} }
// Used by add, mul, div, and similar commutative instructions // Used by add, mul, div, and similar commutative instructions
// The order of operands are "$sx, $sy, $sz" // The order of operands are "$sx, $sy, $sz"
multiclass RRm<string opcStr, bits<8>opc, SDNode OpNode, multiclass RRm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty,
RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> : Operand immOp, Operand immOp2,
RRmrr<opcStr, opc, OpNode, RC, Ty, RC, Ty>, SDPatternOperator OpNode=null_frag> :
RRmri<opcStr, opc, OpNode, RC, Ty, RC, Ty, immOp>, RRmrr<opcStr, opc, RC, Ty, RC, Ty, OpNode>,
RRmiz<opcStr, opc, OpNode, RC, Ty, RC, Ty, immOp>, RRmri<opcStr, opc, RC, Ty, RC, Ty, immOp, OpNode>,
RRmiz<opcStr, opc, RC, Ty, RC, Ty, immOp, OpNode>,
RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, immOp2>, RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, immOp2>,
RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, immOp2>; RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, immOp2>;
// Used by cmp instruction
// The order of operands are "$sx, $sy, $sz"
multiclass RRNDm<string opcStr, bits<8>opc,
RegisterClass RC, ValueType Ty,
Operand immOp, Operand immOp2> :
RRNDmrr<opcStr, opc, RC, Ty, RC, Ty>,
//RRNDmir<opcStr, opc, RC, Ty, RC, Ty, immOp>,
//RRNDmiz<opcStr, opc, RC, Ty, RC, Ty, immOp>,
RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, immOp2>,
RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, immOp2>;
// Multiclass for RR type instructions // Multiclass for RR type instructions
// Used by sra, sla, sll, and similar instructions // Used by sra, sla, sll, and similar instructions
// The order of operands are "$sx, $sz, $sy" // The order of operands are "$sx, $sz, $sy"
multiclass RRIm<string opcStr, bits<8>opc, SDNode OpNode, multiclass RRIm<string opcStr, bits<8>opc, SDNode OpNode,
RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> { RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> {
def ri : RR< def ri : RR<
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
defm LEA32 : RMm<"lea", 0x06, I32, i32, simm7Op32, simm32Op32>; defm LEA32 : RMm<"lea", 0x06, I32, i32, simm7Op32, simm32Op32>;
} }
// 5.3.2.2. Fixed-Point Arithmetic Operation Instructions // 5.3.2.2. Fixed-Point Arithmetic Operation Instructions
// ADS instruction // ADS instruction
let cx = 0 in let cx = 0 in
defm ADS : RRm<"adds.w.sx", 0x4A, add, I32, i32, simm7Op32, uimm6Op32>; defm ADS : RRm<"adds.w.sx", 0x4A, I32, i32, simm7Op32, uimm6Op32, add>;
let cx = 1 in let cx = 1 in
defm ADSU : RRm<"adds.w.zx", 0x4A, add, I32, i32, simm7Op32, uimm6Op32>; defm ADSU : RRm<"adds.w.zx", 0x4A, I32, i32, simm7Op32, uimm6Op32, add>;
// ADX instruction // ADX instruction
let cx = 0 in let cx = 0 in
defm ADX : RRm<"adds.l", 0x59, add, I64, i64, simm7Op64, uimm6Op64>; defm ADX : RRm<"adds.l", 0x59, I64, i64, simm7Op64, uimm6Op64, add>;
// CMP instruction // CMP instruction
let cx = 0 in let cx = 0 in
defm CMP : RRNDm<"cmpu.l", 0x55, I64, i64, simm7Op64, uimm6Op64>; defm CMP : RRm<"cmpu.l", 0x55, I64, i64, simm7Op64, uimm6Op64>;
let cx = 1 in let cx = 1 in
defm CMPUW : RRNDm<"cmpu.w", 0x55, I32, i32, simm7Op32, uimm6Op32>; defm CMPUW : RRm<"cmpu.w", 0x55, I32, i32, simm7Op32, uimm6Op32>;
// CPS instruction // CPS instruction
let cx = 0 in let cx = 0 in
defm CPS : RRNDm<"cmps.w.sx", 0x7A, I32, i32, simm7Op32, uimm6Op32>; defm CPS : RRm<"cmps.w.sx", 0x7A, I32, i32, simm7Op32, uimm6Op32>;
let cx = 1 in let cx = 1 in
defm CPSU : RRNDm<"cmps.w.zx", 0x7A, I32, i32, simm7Op32, uimm6Op32>; defm CPSU : RRm<"cmps.w.zx", 0x7A, I32, i32, simm7Op32, uimm6Op32>;
// CPX instruction // CPX instruction
let cx = 0 in let cx = 0 in
defm CPX : RRNDm<"cmps.l", 0x6A, I64, i64, simm7Op64, uimm6Op64>; defm CPX : RRm<"cmps.l", 0x6A, I64, i64, simm7Op64, uimm6Op64>;
// cx: sx/zx, cw: max/min // cx: sx/zx, cw: max/min
let cw = 0 in defm CMXa : let cw = 0 in defm CMXa :
RRNDm<"maxs.l", 0x68, I64, i64, simm7Op64, uimm6Op64>; RRm<"maxs.l", 0x68, I64, i64, simm7Op64, uimm6Op64>;
let cx = 0, cw = 0 in defm CMSa : let cx = 0, cw = 0 in defm CMSa :
RRNDm<"maxs.w.zx", 0x78, I32, i32, simm7Op32, uimm6Op32>; RRm<"maxs.w.zx", 0x78, I32, i32, simm7Op32, uimm6Op32>;
let cw = 1 in defm CMXi : let cw = 1 in defm CMXi :
RRNDm<"mins.l", 0x68, I64, i64, simm7Op64, uimm6Op64>; RRm<"mins.l", 0x68, I64, i64, simm7Op64, uimm6Op64>;
let cx = 1, cw = 0 in defm CMSi : let cx = 1, cw = 0 in defm CMSi :
RRNDm<"mins.w.zx", 0x78, I32, i32, simm7Op32, uimm6Op32>; RRm<"mins.w.zx", 0x78, I32, i32, simm7Op32, uimm6Op32>;
// 5.3.2.3. Logical Arithmetic Operation Instructions // 5.3.2.3. Logical Arithmetic Operation Instructions
let cx = 0 in { let cx = 0 in {
defm AND : RRm<"and", 0x44, and, I64, i64, simm7Op64, uimm6Op64>; defm AND : RRm<"and", 0x44, I64, i64, simm7Op64, uimm6Op64, and>;
defm OR : RRm<"or", 0x45, or, I64, i64, simm7Op64, uimm6Op64>; defm OR : RRm<"or", 0x45, I64, i64, simm7Op64, uimm6Op64, or>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
defm AND32 : RRm<"and", 0x44, and, I32, i32, simm7Op32, uimm6Op32>; defm AND32 : RRm<"and", 0x44, I32, i32, simm7Op32, uimm6Op32, and>;
defm OR32 : RRm<"or", 0x45, or, I32, i32, simm7Op32, uimm6Op32>; defm OR32 : RRm<"or", 0x45, I32, i32, simm7Op32, uimm6Op32, or>;
defm XOR32 : RRm<"xor", 0x46, xor, I32, i32, simm7Op32, uimm6Op32>; defm XOR32 : RRm<"xor", 0x46, I32, i32, simm7Op32, uimm6Op32, xor>;
} }
} }
// 5.3.2.4 Shift Instructions // 5.3.2.4 Shift Instructions
let cx = 0 in let cx = 0 in
defm SRAX : RRIm<"sra.l", 0x77, sra, I64, i64, simm7Op32, uimm6Op64>; defm SRAX : RRIm<"sra.l", 0x77, sra, I64, i64, simm7Op32, uimm6Op64>;
let cx = 0 in let cx = 0 in
defm SRA : RRIm<"sra.w.sx", 0x76, sra, I32, i32, simm7Op32, uimm6Op32>; defm SRA : RRIm<"sra.w.sx", 0x76, sra, I32, i32, simm7Op32, uimm6Op32>;
let cx = 0 in let cx = 0 in
defm SLL : RRIm<"sll", 0x65, shl, I64, i64, simm7Op32, uimm6Op64>; defm SLL : RRIm<"sll", 0x65, shl, I64, i64, simm7Op32, uimm6Op64>;
let cx = 0 in let cx = 0 in
defm SLA : RRIm<"sla.w.sx", 0x66, shl, I32, i32, simm7Op32, uimm6Op32>; defm SLA : RRIm<"sla.w.sx", 0x66, shl, I32, i32, simm7Op32, uimm6Op32>;
// FCP instruction // FCP instruction
let cx = 0 in let cx = 0 in
defm FCP : RRNDm<"fcmp.d", 0x7E, I64, f64, simm7Op64, uimm6Op64>; defm FCP : RRm<"fcmp.d", 0x7E, I64, f64, simm7Op64, uimm6Op64>;
let cx = 1 in let cx = 1 in
defm FCPS : RRNDm<"fcmp.s", 0x7E, F32, f32, simm7Op32, uimm6Op32>; defm FCPS : RRm<"fcmp.s", 0x7E, F32, f32, simm7Op32, uimm6Op32>;
// FCM // FCM
let cw = 0 in { let cw = 0 in {
let cx = 0 in let cx = 0 in
defm FCMA : RRNDm<"fmax.d", 0x3E, I64, f64, simm7Op64, uimm6Op64>; defm FCMA : RRm<"fmax.d", 0x3E, I64, f64, simm7Op64, uimm6Op64>;
let cx = 1 in let cx = 1 in
defm FCMAS : RRNDm<"fmax.s", 0x3E, F32, f32, simm7Op32, uimm6Op32>; defm FCMAS : RRm<"fmax.s", 0x3E, F32, f32, simm7Op32, uimm6Op32>;
} }
let cw = 1 in { let cw = 1 in {
let cx = 0 in let cx = 0 in
defm FCMI : RRNDm<"fmin.d", 0x3E, I64, f64, simm7Op64, uimm6Op64>; defm FCMI : RRm<"fmin.d", 0x3E, I64, f64, simm7Op64, uimm6Op64>;
let cx = 1 in let cx = 1 in
defm FCMIS : RRNDm<"fmin.s", 0x3E, F32, f32, simm7Op32, uimm6Op32>; defm FCMIS : RRm<"fmin.s", 0x3E, F32, f32, simm7Op32, uimm6Op32>;
} }
// Load and Store instructions // Load and Store instructions
// As 1st step, only uses sz and imm32 to represent $addr // As 1st step, only uses sz and imm32 to represent $addr
let mayLoad = 1, hasSideEffects = 0 in { let mayLoad = 1, hasSideEffects = 0 in {
let cy = 0, sy = 0, cz = 1 in { let cy = 0, sy = 0, cz = 1 in {
let cx = 0 in let cx = 0 in
def LDSri : RM< def LDSri : RM<
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