LLVM_FALLTHROUGH => [[fallthrough]]. NFC

[MaskRay]

Thanks!

clang/lib/AST/TemplateBase.cpp

void TemplateArgument::Profile(llvm::FoldingSetNodeID &ID,
 
   case Declaration:
     getParamTypeForDecl().Profile(ID);
     ID.AddPointer(getAsDecl());
     break;
 
   case TemplateExpansion:
     ID.AddInteger(TemplateArg.NumExpansions);
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   case Template:
     ID.AddPointer(TemplateArg.Name);
     break;
 
   case Integral:
     getAsIntegral().Profile(ID);
     getIntegralType().Profile(ID);
     break;

clang/lib/Basic/SourceManager.cpp

do {
       Buf += N / 8 + 1;
       unsigned char Byte = Word;
       switch (Byte) {
       case '\r':
         // If this is \r\n, skip both characters.
         if (*Buf == '\n') {
           ++Buf;
         }
-        LLVM_FALLTHROUGH;
+        [[fallthrough]];
       case '\n':
         LineOffsets.push_back(Buf - Start);
       };
     } while (Buf < End - sizeof(Word) - 1);
   }
 
   // Handle tail using a regular check.
   while (Buf < End) {

clang/lib/Sema/SemaChecking.cpp

bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
   switch (BuiltinID) {
   default:
     break;
   case LoongArch::BI__builtin_loongarch_cacop_d:
     if (!TI.hasFeature("64bit"))
       return Diag(TheCall->getBeginLoc(),
                   diag::err_loongarch_builtin_requires_la64)
              << TheCall->getSourceRange();
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   case LoongArch::BI__builtin_loongarch_cacop_w: {
     if (BuiltinID == LoongArch::BI__builtin_loongarch_cacop_w &&
         !TI.hasFeature("32bit"))
       return Diag(TheCall->getBeginLoc(),
                   diag::err_loongarch_builtin_requires_la32)
              << TheCall->getSourceRange();
     SemaBuiltinConstantArgRange(TheCall, 0, 0, llvm::maxUIntN(5));
     SemaBuiltinConstantArgRange(TheCall, 2, llvm::minIntN(12),

lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp

case lldb::eLanguageTypeObjC:
     // cause compiler error when evaluating expressions (e.g. nullptr not found
     // as it's a C++11 feature). Currently lldb evaluates C++14 as C++11 (see
     // two lines below) so we decide to be consistent with that, but this could
     // be re-evaluated in the future.
     lang_opts.CPlusPlus11 = true;
     break;
   case lldb::eLanguageTypeC_plus_plus_20:
     lang_opts.CPlusPlus20 = true;
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   case lldb::eLanguageTypeC_plus_plus_17:
     // FIXME: add a separate case for CPlusPlus14. Currently folded into C++17
     // because C++14 is the default standard for Clang but enabling CPlusPlus14
     // expression evaluatino doesn't pass the test-suite cleanly.
     lang_opts.CPlusPlus14 = true;
     lang_opts.CPlusPlus17 = true;
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   case lldb::eLanguageTypeC_plus_plus:
   case lldb::eLanguageTypeC_plus_plus_11:
   case lldb::eLanguageTypeC_plus_plus_14:
     lang_opts.CPlusPlus11 = true;
     m_compiler->getHeaderSearchOpts().UseLibcxx = true;
     [[fallthrough]];
   case lldb::eLanguageTypeC_plus_plus_03:
     lang_opts.CPlusPlus = true;

llvm/lib/Analysis/MemoryLocation.cpp

if (TLI && TLI->getLibFunc(*Call, F) && TLI->has(F)) {
     case LibFunc_strcpy:
     case LibFunc_strcat:
     case LibFunc_strncat:
       assert((ArgIdx == 0 || ArgIdx == 1) && "Invalid argument index for str function");
       return MemoryLocation::getAfter(Arg, AATags);
 
     case LibFunc_memset_chk:
       assert(ArgIdx == 0 && "Invalid argument index for memset_chk");
-      LLVM_FALLTHROUGH;
+      [[fallthrough]];
     case LibFunc_memcpy_chk: {
       assert((ArgIdx == 0 || ArgIdx == 1) &&
              "Invalid argument index for memcpy_chk");
       LocationSize Size = LocationSize::afterPointer();
       if (const auto *Len = dyn_cast<ConstantInt>(Call->getArgOperand(2))) {
         // memset_chk writes at most Len bytes, memcpy_chk reads/writes at most
         // Len bytes. They may read/write less, if Len exceeds the specified max
         // size and aborts.

llvm/lib/Analysis/ScalarEvolution.cpp

auto CollectCondition = [&](ICmpInst::Predicate Predicate, const SCEV *LHS,
     // with non-strict ones against plus or minus one of RHS depending on the
     // predicate.
     const SCEV *One = getOne(RHS->getType());
     switch (Predicate) {
       case CmpInst::ICMP_ULT:
         if (RHS->getType()->isPointerTy())
           return;
         RHS = getUMaxExpr(RHS, One);
-        LLVM_FALLTHROUGH;
+        [[fallthrough]];
       case CmpInst::ICMP_SLT: {
         RHS = getMinusSCEV(RHS, One);
         RHS = DividesBy ? GetPreviousSCEVDividesByDivisor(RHS, DividesBy) : RHS;
         break;
       }
       case CmpInst::ICMP_UGT:
       case CmpInst::ICMP_SGT:
         RHS = getAddExpr(RHS, One);

llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp

while (Begin < End) {
     case MCDisassembler::Fail:
       LLVM_DEBUG({ dbgs() << "Invalid instruction\n"; });
       if (BytesConsumed == 0)
         // Skip invalid bytes
         BytesConsumed = 1;
       break;
     case MCDisassembler::SoftFail:
       LLVM_DEBUG({ dbgs() << "Potentially undefined instruction:"; });
-      LLVM_FALLTHROUGH;
+      [[fallthrough]];
     case MCDisassembler::Success: {
       std::string Buffer;
       raw_string_ostream Stream(Buffer);
       StringRef AnnotationsStr = Annotations.str();
       MIP->printInst(&Instruction, Address, AnnotationsStr, *STI, Stream);
       LLVM_DEBUG({
         std::string BufferCodes;
         raw_string_ostream StreamCodes(BufferCodes);

llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp

OpenMPIRBuilder::InsertPointTy OpenMPIRBuilder::applyWorkshareLoop(
   case OMPScheduleType::BaseAuto:
   case OMPScheduleType::BaseGreedy:
   case OMPScheduleType::BaseBalanced:
   case OMPScheduleType::BaseSteal:
   case OMPScheduleType::BaseGuidedSimd:
   case OMPScheduleType::BaseRuntimeSimd:
     assert(!ChunkSize &&
            "schedule type does not support user-defined chunk sizes");
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   case OMPScheduleType::BaseDynamicChunked:
   case OMPScheduleType::BaseGuidedChunked:
   case OMPScheduleType::BaseGuidedIterativeChunked:
   case OMPScheduleType::BaseGuidedAnalyticalChunked:
   case OMPScheduleType::BaseStaticBalancedChunked:
     return applyDynamicWorkshareLoop(DL, CLI, AllocaIP, EffectiveScheduleType,
                                      NeedsBarrier, ChunkSize);
 

llvm/lib/ProfileData/InstrProf.cpp

switch (GET_VERSION(H.formatVersion())) {
     // populate it.
     static_assert(
         IndexedInstrProf::ProfVersion::CurrentVersion == Version10,
         "Please update the reading code below if a new field has been added, "
         "if not add a case statement to fall through to the latest version.");
   case 10ull:
     H.TemporalProfTracesOffset =
         read(Buffer, offsetOf(&Header::TemporalProfTracesOffset));
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   case 9ull:
     H.BinaryIdOffset = read(Buffer, offsetOf(&Header::BinaryIdOffset));
     [[fallthrough]];
   case 8ull:
     H.MemProfOffset = read(Buffer, offsetOf(&Header::MemProfOffset));
     [[fallthrough]];
   default: // Version7 (when the backwards compatible header was introduced).
     H.HashType = read(Buffer, offsetOf(&Header::HashType));

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
   case ISD::FSUB:
     // Increase the cost for half and bfloat types if not architecturally
     // supported.
     if ((Ty->getScalarType()->isHalfTy() && !ST->hasFullFP16()) ||
         (Ty->getScalarType()->isBFloatTy() && !ST->hasBF16()))
       return 2 * LT.first;
     if (!Ty->getScalarType()->isFP128Ty())
       return LT.first;
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   case ISD::FMUL:
   case ISD::FDIV:
     // These nodes are marked as 'custom' just to lower them to SVE.
     // We know said lowering will incur no additional cost.
     if (!Ty->getScalarType()->isFP128Ty())
       return 2 * LT.first;
 
     return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

case ISD::SRL:
     // uses the BRH instruction.
     if (Subtarget->isISA3_1() && N->getValueType(0) == MVT::i32 &&
         N->getOperand(0).getOpcode() == ISD::BSWAP) {
       auto &OpRight = N->getOperand(1);
       ConstantSDNode *SRLConst = dyn_cast<ConstantSDNode>(OpRight);
       if (SRLConst && SRLConst->getSExtValue() == 16)
         return false;
     }
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   case ISD::ROTL:
   case ISD::SHL:
   case ISD::AND:
   case ISD::OR: {
     BitPermutationSelector BPS(CurDAG);
     if (SDNode *New = BPS.Select(N)) {
       ReplaceNode(N, New);
       return true;

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (Subtarget.isISAFuture()) {
       Extract = DAG.getNode(
           PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8,
           Subtarget.isLittleEndian() ? Value : Value2,
           DAG.getConstant(Subtarget.isLittleEndian() ? 0 : 1,
                           dl, getPointerTy(DAG.getDataLayout())));
       RetOps.push_back(Extract);
       return DAG.getMergeValues(RetOps, dl);
     }
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   }
   case Intrinsic::ppc_vsx_disassemble_pair: {
     int NumVecs = 2;
     SDValue WideVec = Op.getOperand(1);
     if (IntrinsicID == Intrinsic::ppc_mma_disassemble_acc) {
       NumVecs = 4;
       WideVec = DAG.getNode(PPCISD::XXMFACC, dl, MVT::v512i1, WideVec);
     }

llvm/lib/Target/PowerPC/PPCRegisterInfo.h

static const char *stripRegisterPrefix(const char *RegName) {
     switch (RegName[0]) {
       case 'a':
         if (RegName[1] == 'c' && RegName[2] == 'c')
           return RegName + 3;
         break;
       case 'f':
         if (RegName[1] == 'p')
           return RegName + 2;
-        LLVM_FALLTHROUGH;
+        [[fallthrough]];
       case 'r':
       case 'v':
         if (RegName[1] == 's') {
           if (RegName[2] == 'p')
             return RegName + 3;
           return RegName + 2;
         }
         return RegName + 1;

llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp

 bool SPIRVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
                                              const CallInst &I,
                                              MachineFunction &MF,
                                              unsigned Intrinsic) const {
   unsigned AlignIdx = 3;
   switch (Intrinsic) {
   case Intrinsic::spv_load:
     AlignIdx = 2;
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   case Intrinsic::spv_store: {
     if (I.getNumOperands() >= AlignIdx + 1) {
       auto *AlignOp = cast<ConstantInt>(I.getOperand(AlignIdx));
       Info.align = Align(AlignOp->getZExtValue());
     }
     Info.flags = static_cast<MachineMemOperand::Flags>(
         cast<ConstantInt>(I.getOperand(AlignIdx - 1))->getZExtValue());
     Info.memVT = MVT::i64;

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

if (CM.isPredicatedInst(I)) {
           ConstantInt::get(I->getType(), 1u, false));
       auto *SafeRHS =
          new VPInstruction(Instruction::Select, {Mask, Ops[1], One},
                            I->getDebugLoc());
       VPBB->appendRecipe(SafeRHS);
       Ops[1] = SafeRHS;
       return new VPWidenRecipe(*I, make_range(Ops.begin(), Ops.end()));
     }
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   }
   case Instruction::Add:
   case Instruction::And:
   case Instruction::AShr:
   case Instruction::FAdd:
   case Instruction::FCmp:
   case Instruction::FDiv:
   case Instruction::FMul: