yaxunl (Yaxun Liu)
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User Since
May 13 2015, 10:16 AM (131 w, 6 d)

Recent Activity

Yesterday

yaxunl committed rL318727: [AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type.
[AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type
Mon, Nov 20, 6:30 PM
yaxunl closed D40148: [AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type by committing rL318727: [AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type.
Mon, Nov 20, 6:30 PM
yaxunl added a comment to D40117: [AMDGPU] Update test nullptr.ll to use amdgiz environment.

Changing the size of the other address spaces seems like a problem, but I'm not sure what they are for. If we actually care about them, they need to be added to the datalayout

Mon, Nov 20, 11:44 AM
yaxunl added inline comments to D40148: [AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type.
Mon, Nov 20, 8:55 AM
yaxunl committed rL318660: [AMDGPU] Update test r600.amdgpu-alias-analysis.ll.
[AMDGPU] Update test r600.amdgpu-alias-analysis.ll
Mon, Nov 20, 8:54 AM
yaxunl closed D40131: [AMDGPU] Update test r600.amdgpu-alias-analysis.ll by committing rL318660: [AMDGPU] Update test r600.amdgpu-alias-analysis.ll.
Mon, Nov 20, 8:53 AM
yaxunl created D40255: CodeGen: Fix SelectionDAGISel::LowerArguments for sret addr space.
Mon, Nov 20, 8:26 AM

Fri, Nov 17

yaxunl updated the diff for D40148: [AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type.

Revised by Matt's comments.

Fri, Nov 17, 8:46 AM
yaxunl added a comment to D40148: [AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type.

SplitInteger,
where default pointer type is used for the constant 16.

This is wrong. This should not be using getIntPtrConstant. For AMDGPU the shift type is always 32. If somewhere is creating a shift mask with something other than getScalarShiftAmountTy, that is a bug there.

Fri, Nov 17, 8:05 AM

Thu, Nov 16

yaxunl created D40148: [AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type.
Thu, Nov 16, 2:15 PM
yaxunl added inline comments to D33989: [OpenCL] Allow targets to select address space per type.
Thu, Nov 16, 1:55 PM
yaxunl committed rL318414: Update tests for llvm.invariant.group.barrier becoming mangled.
Update tests for llvm.invariant.group.barrier becoming mangled
Thu, Nov 16, 8:33 AM
yaxunl closed D40062: Update tests for llvm.invariant.group.barrier becoming mangled by committing rL318414: Update tests for llvm.invariant.group.barrier becoming mangled.
Thu, Nov 16, 8:33 AM
yaxunl committed rL318413: Let llvm.invariant.group.barrier accepts pointer to any address space.
Let llvm.invariant.group.barrier accepts pointer to any address space
Thu, Nov 16, 8:32 AM
yaxunl closed D39973: Let llvm.invariant.group.barrier accepts pointer to any address space by committing rL318413: Let llvm.invariant.group.barrier accepts pointer to any address space.
Thu, Nov 16, 8:32 AM
yaxunl created D40131: [AMDGPU] Update test r600.amdgpu-alias-analysis.ll.
Thu, Nov 16, 8:06 AM
yaxunl committed rL318392: Fix pointer EVT in SelectionDAGBuilder::visitAlloca.
Fix pointer EVT in SelectionDAGBuilder::visitAlloca
Thu, Nov 16, 4:22 AM
yaxunl closed D40095: Fix pointer EVT in SelectionDAGBuilder::visitAlloca by committing rL318392: Fix pointer EVT in SelectionDAGBuilder::visitAlloca.
Thu, Nov 16, 4:22 AM

Wed, Nov 15

yaxunl created D40117: [AMDGPU] Update test nullptr.ll to use amdgiz environment.
Wed, Nov 15, 7:55 PM
yaxunl committed rL318370: Fix APInt bit size in processDbgDeclares.
Fix APInt bit size in processDbgDeclares
Wed, Nov 15, 6:55 PM
yaxunl closed D40085: Fix APInt bit size in processDbgDeclares by committing rL318370: Fix APInt bit size in processDbgDeclares.
Wed, Nov 15, 6:55 PM
yaxunl added inline comments to D40095: Fix pointer EVT in SelectionDAGBuilder::visitAlloca.
Wed, Nov 15, 6:53 PM
yaxunl updated the diff for D40085: Fix APInt bit size in processDbgDeclares.

Revised by Matt's comments.

Wed, Nov 15, 6:34 PM
yaxunl added a comment to D40085: Fix APInt bit size in processDbgDeclares.

Should it just be the type size? There seems like no reason to use the low level pointer size query

Wed, Nov 15, 5:50 PM
yaxunl added inline comments to D40085: Fix APInt bit size in processDbgDeclares.
Wed, Nov 15, 1:29 PM
yaxunl created D40095: Fix pointer EVT in SelectionDAGBuilder::visitAlloca.
Wed, Nov 15, 12:38 PM
yaxunl created D40085: Fix APInt bit size in processDbgDeclares.
Wed, Nov 15, 8:59 AM
yaxunl added a comment to D39740: CodeGen: Fix pointer info and index type when splitting vector.

ping

Wed, Nov 15, 8:09 AM

Tue, Nov 14

yaxunl added inline comments to D40040: [AMDGPU] Fix SITargetLowering::LowerCall for pointer info of byval argument.
Tue, Nov 14, 8:17 PM
yaxunl updated the summary of D40062: Update tests for llvm.invariant.group.barrier becoming mangled.
Tue, Nov 14, 6:26 PM
yaxunl updated the summary of D39973: Let llvm.invariant.group.barrier accepts pointer to any address space.
Tue, Nov 14, 6:25 PM
yaxunl created D40062: Update tests for llvm.invariant.group.barrier becoming mangled.
Tue, Nov 14, 6:24 PM
yaxunl updated the diff for D39973: Let llvm.invariant.group.barrier accepts pointer to any address space.

Make llvm.invariant.group.barrier mangled by Matt's comments.

Tue, Nov 14, 6:19 PM
yaxunl added inline comments to D39973: Let llvm.invariant.group.barrier accepts pointer to any address space.
Tue, Nov 14, 11:11 AM
yaxunl committed rL318167: CodeGen: Fix TargetLowering::LowerCallTo for sret value type.
CodeGen: Fix TargetLowering::LowerCallTo for sret value type
Tue, Nov 14, 10:47 AM
yaxunl closed D39996: CodeGen: Fix TargetLowering::LowerCallTo for sret value type by committing rL318167: CodeGen: Fix TargetLowering::LowerCallTo for sret value type.
Tue, Nov 14, 10:47 AM
yaxunl created D40040: [AMDGPU] Fix SITargetLowering::LowerCall for pointer info of byval argument.
Tue, Nov 14, 9:56 AM
yaxunl added a comment to D39973: Let llvm.invariant.group.barrier accepts pointer to any address space.

Firstly, are you sure that the invariant.group.barrier is the problem here? I didn't hear that it is used anywhere besides devirtualization, that is not turned on by default.
Here is my old path that was never reviewed:
https://reviews.llvm.org/D32673

As you can see, in order to check if the pointer passed to the barrier is captured, we need to check if all uses of the pointer returned by the barrier is not captured.

Tue, Nov 14, 8:36 AM

Mon, Nov 13

yaxunl created D39996: CodeGen: Fix TargetLowering::LowerCallTo for sret value type .
Mon, Nov 13, 8:19 PM
yaxunl added inline comments to D39973: Let llvm.invariant.group.barrier accepts pointer to any address space.
Mon, Nov 13, 6:45 PM
yaxunl updated the diff for D39973: Let llvm.invariant.group.barrier accepts pointer to any address space.

Revised by Stas' comments.

Mon, Nov 13, 2:41 PM
yaxunl added inline comments to D39973: Let llvm.invariant.group.barrier accepts pointer to any address space.
Mon, Nov 13, 2:34 PM
yaxunl added a comment to D39560: [AMDGPU] Convert lit tests to new addr space mapping, part 1.

ping

Mon, Nov 13, 1:50 PM
yaxunl added inline comments to D39973: Let llvm.invariant.group.barrier accepts pointer to any address space.
Mon, Nov 13, 1:47 PM
yaxunl created D39973: Let llvm.invariant.group.barrier accepts pointer to any address space.
Mon, Nov 13, 12:54 PM
yaxunl updated the diff for D39560: [AMDGPU] Convert lit tests to new addr space mapping, part 1.

Fixed some script issue and added more passing tests.

Mon, Nov 13, 4:04 AM

Fri, Nov 10

yaxunl updated the diff for D39560: [AMDGPU] Convert lit tests to new addr space mapping, part 1.

Update all passing ll tests under AMDGPU for new addr space mapping.

Fri, Nov 10, 8:23 AM

Thu, Nov 9

yaxunl committed rL317862: [AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz….
[AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz…
Thu, Nov 9, 6:03 PM
yaxunl closed D39698: [AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment by committing rL317862: [AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz….
Thu, Nov 9, 6:03 PM
yaxunl committed rL317861: [AMDGPU] Fix pointer info for pseudo source for r600.
[AMDGPU] Fix pointer info for pseudo source for r600
Thu, Nov 9, 5:53 PM
yaxunl closed D39670: [AMDGPU] Fix pointer info for pseudo source for r600 by committing rL317861: [AMDGPU] Fix pointer info for pseudo source for r600.
Thu, Nov 9, 5:53 PM
yaxunl added a comment to D39560: [AMDGPU] Convert lit tests to new addr space mapping, part 1.

The script isn't that big, so in the past the policy has been to just put the body of the script literally in the commit message rather than adding a temporary file that will be forgotten.

This is adding the amdgiz environment to all the tests, which is not what I expected. I expected that to be removed and to change the default to the new mapping thus removing the need for the triple changes in all of these tests. Is your plan to do that as a separate step after?

Thu, Nov 9, 5:11 PM
yaxunl added inline comments to D39670: [AMDGPU] Fix pointer info for pseudo source for r600.
Thu, Nov 9, 12:22 PM
yaxunl added a comment to D39670: [AMDGPU] Fix pointer info for pseudo source for r600.

! In D39670#919711, @yaxunl wrote:

As Matt said, the risk of having two sets of address space mapping is high. Also I estimate the workload to switch r600 to the new addr space mapping is moderate. On the hand, the workload for separating r600 from amdgcn is high.

I disagree with this, but it's also possible I'm wrong. If you are willing to do the work and deal with the fallout, then I'm OK with this change. Just make sure @jvesely is aware so he can help test/check for regressions.

Sure. I will keep Jan updated.

One problem I have with this specific test is you are essentially removing a test for the current mapping and replacing it with a test for the new mapping, even though the new mapping isn't actually being used anywhere outside of LLVM. What is your timeframe for migrating r600 to the new mapping?

I plan to get it done ASAP. Hopefully in one month. I think the new address space mapping and old address space mapping share most of the code path in llvm/clang, so any regression for the old address space mapping is likely causes regression in the new address space mapping. On the other hand, since new address space mapping has non-zero alloca address space therefore some extra code path, regressions in new address space mapping may not cause regressions in old address space mapping.

Thu, Nov 9, 9:42 AM

Wed, Nov 8

yaxunl added a comment to D39670: [AMDGPU] Fix pointer info for pseudo source for r600.

We discussed this internally and concluded that having a static address space mapping is more important. Most of issues are due to using dummy pointer info. Such places should be few in r600 code, therefore we will continue fixing these issues unless we found there need excessive efforts to do so.

It would be nice to have these discussions on the mailing list so more people could participate, and it would be helpful for convincing people like me that this is the right approach, but as of right now I don't see why it is so important to have a static address space mapping that is the same for r600 and amdgcn. I think the better approach would be to share less code between the two subtargets such that it's possible for each to have their own static mapping. I think this kind of code separation is something should be done anyway independent of address space mapping work.

Wed, Nov 8, 11:57 AM

Tue, Nov 7

yaxunl added a comment to D39670: [AMDGPU] Fix pointer info for pseudo source for r600.

r600 doesn't support generic address space, so in that case, I would recommend only defining an intrinsic to be used by amdgcn. I understand the problem with non-constant address spaces, but I think the best solution here would be to try to make more of a separation between the amdgcn code and the r600 code in the backend rather than trying to change the address space mapping for r600. r600 should really be mostly read-only at this point.

Tue, Nov 7, 6:58 PM
yaxunl added inline comments to D39758: CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT.
Tue, Nov 7, 5:56 PM
yaxunl added inline comments to D39758: CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT.
Tue, Nov 7, 4:41 PM
yaxunl added inline comments to D39758: CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT.
Tue, Nov 7, 3:04 PM
yaxunl created D39758: CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT.
Tue, Nov 7, 1:51 PM
yaxunl added a comment to D39670: [AMDGPU] Fix pointer info for pseudo source for r600.

Which intrinsic functions are you refering to? To me it seems easier to not touch r600 at all, but I guess I'm not as deep into the code as you. Can you give me some specific examples for how adding support to r600 for this alternative mapping simplifies the backend?

For example, if we want to define a intrinsic function returning generic pointer, we have to define two versions. one for amdgiz environment, one for other environment, because they have different address space value for generic pointer. And we have to let the backend choose which version based on target environment.

Also, because address space values depends on target triple, we can not define them as constants. Instead it has to be a structure returned by function getAMDGPUAS(triple) and use it. If we only supports one address space mapping, we can define it as an enum and use it.

Tue, Nov 7, 10:24 AM
yaxunl added a comment to D39670: [AMDGPU] Fix pointer info for pseudo source for r600.

Which intrinsic functions are you refering to? To me it seems easier to not touch r600 at all, but I guess I'm not as deep into the code as you. Can you give me some specific examples for how adding support to r600 for this alternative mapping simplifies the backend?

Tue, Nov 7, 10:16 AM
yaxunl updated the diff for D39670: [AMDGPU] Fix pointer info for pseudo source for r600.

Revised by Jan's comment.

Tue, Nov 7, 10:06 AM
yaxunl added a comment to D39670: [AMDGPU] Fix pointer info for pseudo source for r600.

Why are we trying to use this alternative address space mapping for r600?

Tue, Nov 7, 9:53 AM
yaxunl added a comment to D39739: [HCC] Add flag to Import Weak Functions in Function Importer.

Could you please upload a diff with full context? Also, need a lit test.

Tue, Nov 7, 9:27 AM
yaxunl created D39740: CodeGen: Fix pointer info and index type when splitting vector.
Tue, Nov 7, 9:17 AM
yaxunl added a comment to D39670: [AMDGPU] Fix pointer info for pseudo source for r600.

Ping. D39698 depends on this.

Tue, Nov 7, 9:02 AM
yaxunl added a reviewer for D39670: [AMDGPU] Fix pointer info for pseudo source for r600: jsjodin.
Tue, Nov 7, 9:00 AM

Mon, Nov 6

yaxunl created D39698: [AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment.
Mon, Nov 6, 2:20 PM
yaxunl updated the diff for D39670: [AMDGPU] Fix pointer info for pseudo source for r600.

Remove unnecessary changes to CodeGen since the PointerInfo can be inferred.

Mon, Nov 6, 1:12 PM
yaxunl committed rL317479: [AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environment.
[AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environment
Mon, Nov 6, 6:33 AM
yaxunl closed D39657: [AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environment by committing rL317479: [AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environment.
Mon, Nov 6, 6:33 AM
yaxunl committed rL317476: [AMDGPU] Fix assertion due to assuming pointer in default addr space is 32 bit.
[AMDGPU] Fix assertion due to assuming pointer in default addr space is 32 bit
Mon, Nov 6, 5:02 AM
yaxunl closed D39643: [AMDGPU] Fix assertion due to assuming pointer in default addr space is 32 bit by committing rL317476: [AMDGPU] Fix assertion due to assuming pointer in default addr space is 32 bit.
Mon, Nov 6, 5:02 AM

Sun, Nov 5

yaxunl created D39670: [AMDGPU] Fix pointer info for pseudo source for r600.
Sun, Nov 5, 6:23 PM
yaxunl added inline comments to D39643: [AMDGPU] Fix assertion due to assuming pointer in default addr space is 32 bit.
Sun, Nov 5, 6:19 PM
yaxunl updated the diff for D39560: [AMDGPU] Convert lit tests to new addr space mapping, part 1.

Update tests.

Sun, Nov 5, 12:20 PM
yaxunl updated the diff for D39657: [AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environment.

Fix test datalayout.

Sun, Nov 5, 11:56 AM
yaxunl created D39657: [AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environment.
Sun, Nov 5, 11:21 AM
yaxunl created D39643: [AMDGPU] Fix assertion due to assuming pointer in default addr space is 32 bit.
Sun, Nov 5, 10:34 AM

Sat, Nov 4

yaxunl committed rL317409: [AMDGPU] Remove hardcoded address space value from AMDGPULibFunc.
[AMDGPU] Remove hardcoded address space value from AMDGPULibFunc
Sat, Nov 4, 10:38 AM
yaxunl closed D39616: [AMDGPU] Remove hardcoded address space value from AMDGPULibFunc by committing rL317409: [AMDGPU] Remove hardcoded address space value from AMDGPULibFunc.
Sat, Nov 4, 10:38 AM

Fri, Nov 3

yaxunl updated the diff for D39616: [AMDGPU] Remove hardcoded address space value from AMDGPULibFunc.

Revised by Stas' comments.

Fri, Nov 3, 8:26 PM
yaxunl added inline comments to D39616: [AMDGPU] Remove hardcoded address space value from AMDGPULibFunc.
Fri, Nov 3, 7:47 PM
yaxunl created D39616: [AMDGPU] Remove hardcoded address space value from AMDGPULibFunc.
Fri, Nov 3, 1:22 PM
yaxunl added a comment to D39560: [AMDGPU] Convert lit tests to new addr space mapping, part 1.

the script is chaddr.sh.

Fri, Nov 3, 8:32 AM
yaxunl updated the diff for D39560: [AMDGPU] Convert lit tests to new addr space mapping, part 1.

Add the script for converting .ll from old addr space to new addr space.

Fri, Nov 3, 8:22 AM
yaxunl added a comment to D39560: [AMDGPU] Convert lit tests to new addr space mapping, part 1.

You should put the script you used to convert in the commit message since I'll undoubtedly need to convert some tests at some point

Fri, Nov 3, 7:15 AM

Thu, Nov 2

yaxunl created D39560: [AMDGPU] Convert lit tests to new addr space mapping, part 1.
Thu, Nov 2, 11:19 AM

Wed, Nov 1

yaxunl accepted D39499: AMDGPU: Fix set but not used warnings related to AMDGPUAS.

LGTM. Thanks!

Wed, Nov 1, 12:11 PM

Mon, Oct 30

yaxunl committed rL316957: InferAddressSpaces: Fix bug about replacing addrspacecast.
InferAddressSpaces: Fix bug about replacing addrspacecast
Mon, Oct 30, 2:20 PM
yaxunl closed D39432: InferAddressSpaces: Fix bug about replacing addrspacecast by committing rL316957: InferAddressSpaces: Fix bug about replacing addrspacecast.
Mon, Oct 30, 2:20 PM
yaxunl created D39432: InferAddressSpaces: Fix bug about replacing addrspacecast.
Mon, Oct 30, 1:53 PM
yaxunl committed rL316909: CodeGen: Fix insertion position of addrspace cast for alloca.
CodeGen: Fix insertion position of addrspace cast for alloca
Mon, Oct 30, 7:39 AM
yaxunl closed D39374: CodeGen: Fix insertion position of addrspace cast for alloca by committing rL316909: CodeGen: Fix insertion position of addrspace cast for alloca.
Mon, Oct 30, 7:38 AM
yaxunl committed rL316907: [AMDGPU] Emit metadata for hidden arguments for kernel enqueue.
[AMDGPU] Emit metadata for hidden arguments for kernel enqueue
Mon, Oct 30, 7:31 AM
yaxunl closed D39255: [AMDGPU] Emit metadata for hidden arguments for kernel enqueue by committing rL316907: [AMDGPU] Emit metadata for hidden arguments for kernel enqueue.
Mon, Oct 30, 7:31 AM

Fri, Oct 27

yaxunl created D39374: CodeGen: Fix insertion position of addrspace cast for alloca.
Fri, Oct 27, 7:59 AM

Thu, Oct 26

yaxunl added inline comments to D39255: [AMDGPU] Emit metadata for hidden arguments for kernel enqueue.
Thu, Oct 26, 7:03 AM

Wed, Oct 25

yaxunl updated the diff for D39255: [AMDGPU] Emit metadata for hidden arguments for kernel enqueue.

Emit dummy hidden argument when necessary.

Wed, Oct 25, 10:03 AM