[RISCV] Move RISCV::RVVBitsPerBlock to be a static member of RISCVISAInfo class.

[craig.topper]

Summary

This constant is used by clang and llvm so needs to be shared.

It can't be in RISCVTargetParser.h where it is today because that
file depends on a tablegen output.

I don't want to create a new header file so I figured RISCVISAInfo.h
could be a new home for it.

lld imports RISCVISAInfo.h and lld has a class named llvm::RISCV.
So we can't expose the llvm::RISCV namespace to lld.

Thus this patch to put it inside the RISCVISAInfo class.

Note that in order to support VLEN=32 with vscale we will need to make
RVVBitsPerBlock a dynamic value based on Zve32* vs Zve64*/V being
enabled. So at that point it would probably need to be queried from
RISCVISAInfo anyway.

[craig.topper]

fa42e7b made this unnecessary.

clang/lib/AST/ASTContext.cpp

 //===- ASTContext.cpp - Context to hold long-lived AST nodes --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 #include "llvm/ADT/StringRef.h"
 #include "llvm/Frontend/OpenMP/OMPIRBuilder.h"
 #include "llvm/Support/Capacity.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MD5.h"
 #include "llvm/Support/MathExtras.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
 #include "llvm/TargetParser/Triple.h"
 #include <algorithm>
 #include <cassert>
 #include <cstddef>
 #include <cstdint>
 #include <cstdlib>
 #include <map>
 #include <memory>
bool ASTContext::areLaxCompatibleSveTypes(QualType FirstType,
   return IsLaxCompatible(FirstType, SecondType) ||
          IsLaxCompatible(SecondType, FirstType);
 }
 
 /// getRVVTypeSize - Return RVV vector register size.
 static uint64_t getRVVTypeSize(ASTContext &Context, const BuiltinType *Ty) {
   assert(Ty->isRVVVLSBuiltinType() && "Invalid RVV Type");
   auto VScale = Context.getTargetInfo().getVScaleRange(Context.getLangOpts());
-  return VScale ? VScale->first * llvm::RISCV::RVVBitsPerBlock : 0;
+  return VScale ? VScale->first * llvm::RISCVISAInfo::RVVBitsPerBlock : 0;
 }
 
 bool ASTContext::areCompatibleRVVTypes(QualType FirstType,
                                        QualType SecondType) {
   assert(
       ((FirstType->isRVVSizelessBuiltinType() && SecondType->isVectorType()) ||
        (FirstType->isVectorType() && SecondType->isRVVSizelessBuiltinType())) &&
       "Expected RVV builtin type and vector type!");

clang/lib/AST/Type.cpp

 //===- Type.cpp - Type representation and manipulation --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/APSInt.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/FoldingSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
 #include <cstring>
 #include <optional>
 #include <type_traits>
 
 using namespace clang;
QualType Type::getSveEltType(const ASTContext &Ctx) const {
   else
     return Ctx.getBuiltinVectorTypeInfo(BTy).ElementType;
 }
 
 bool Type::isRVVVLSBuiltinType() const {
   if (const BuiltinType *BT = getAs<BuiltinType>()) {
     switch (BT->getKind()) {
     // FIXME: Support more than LMUL 1.
-#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, IsFP) \
-    case BuiltinType::Id: \
-      return NF == 1 && (NumEls * ElBits) == llvm::RISCV::RVVBitsPerBlock;
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,   \
+                        IsFP)                                                  \
+  case BuiltinType::Id:                                                        \
+    return NF == 1 && (NumEls * ElBits) == llvm::RISCVISAInfo::RVVBitsPerBlock;
 #include "clang/Basic/RISCVVTypes.def"
     default:
       return false;
     }
   }
   return false;
 }
 

clang/lib/Basic/Targets/RISCV.cpp

 //===--- RISCV.cpp - Implement RISC-V target feature support --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
   if (ISAInfo->hasExtension("zve32x")) {
     Builder.defineMacro("__riscv_vector");
     // Currently we support the v0.11 RISC-V V intrinsics.
     Builder.defineMacro("__riscv_v_intrinsic", Twine(getVersionValue(0, 11)));
   }
 
   auto VScale = getVScaleRange(Opts);
   if (VScale && VScale->first && VScale->first == VScale->second)
-    Builder.defineMacro("__riscv_v_fixed_vlen",
-                        Twine(VScale->first * llvm::RISCV::RVVBitsPerBlock));
+    Builder.defineMacro(
+        "__riscv_v_fixed_vlen",
+        Twine(VScale->first * llvm::RISCVISAInfo::RVVBitsPerBlock));
 }
 
 static constexpr Builtin::Info BuiltinInfo[] = {
 #define BUILTIN(ID, TYPE, ATTRS)                                               \
   {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
   {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
 #include "clang/Basic/BuiltinsRISCVVector.def"
for (const std::string &Feature : FeaturesVec)
     if (!llvm::is_contained(ImpliedFeatures, Feature))
       ImpliedFeatures.push_back(Feature);
 
   return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
 std::optional<std::pair<unsigned, unsigned>>
 RISCVTargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
-  // RISCV::RVVBitsPerBlock is 64.
-  unsigned VScaleMin = ISAInfo->getMinVLen() / llvm::RISCV::RVVBitsPerBlock;
+  // RISCVISAInfo::RVVBitsPerBlock is 64.
+  unsigned VScaleMin =
+      ISAInfo->getMinVLen() / llvm::RISCVISAInfo::RVVBitsPerBlock;
 
   if (LangOpts.VScaleMin || LangOpts.VScaleMax) {
     // Treat Zvl*b as a lower bound on vscale.
     VScaleMin = std::max(VScaleMin, LangOpts.VScaleMin);
     unsigned VScaleMax = LangOpts.VScaleMax;
     if (VScaleMax != 0 && VScaleMax < VScaleMin)
       VScaleMax = VScaleMin;
     return std::pair<unsigned, unsigned>(VScaleMin ? VScaleMin : 1, VScaleMax);
   }
 
   if (VScaleMin > 0) {
-    unsigned VScaleMax = ISAInfo->getMaxVLen() / llvm::RISCV::RVVBitsPerBlock;
+    unsigned VScaleMax =
+        ISAInfo->getMaxVLen() / llvm::RISCVISAInfo::RVVBitsPerBlock;
     return std::make_pair(VScaleMin, VScaleMax);
   }
 
   return std::nullopt;
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
 bool RISCVTargetInfo::hasFeature(StringRef Feature) const {

clang/lib/CodeGen/TargetInfo.cpp

 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/IntrinsicsNVPTX.h"
 #include "llvm/IR/IntrinsicsS390.h"
 #include "llvm/IR/Type.h"
 #include "llvm/Support/MathExtras.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
 #include "llvm/TargetParser/Triple.h"
 #include <algorithm>
 
 using namespace clang;
 using namespace CodeGen;
 
 // Helper for coercing an aggregate argument or return value into an integer
 // array of the same size (including padding) and alignment.  This alternate
ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty) const {
   const auto *VT = Ty->castAs<VectorType>();
   assert(VT->getVectorKind() == VectorType::RVVFixedLengthDataVector &&
          "Unexpected vector kind");
 
   assert(VT->getElementType()->isBuiltinType() && "expected builtin type!");
 
   const auto *BT = VT->getElementType()->castAs<BuiltinType>();
   unsigned EltSize = getContext().getTypeSize(BT);
-  llvm::ScalableVectorType *ResType =
-        llvm::ScalableVectorType::get(CGT.ConvertType(VT->getElementType()),
-                                      llvm::RISCV::RVVBitsPerBlock / EltSize);
+  llvm::ScalableVectorType *ResType = llvm::ScalableVectorType::get(
+      CGT.ConvertType(VT->getElementType()),
+      llvm::RISCVISAInfo::RVVBitsPerBlock / EltSize);
   return ABIArgInfo::getDirect(ResType);
 }
 
 ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
                                               int &ArgGPRsLeft,
                                               int &ArgFPRsLeft) const {
   assert(ArgGPRsLeft <= NumArgGPRs && "Arg GPR tracking underflow");
   Ty = useFirstFieldIfTransparentUnion(Ty);

clang/lib/Driver/ToolChains/Clang.cpp

 //===-- Clang.cpp - Clang+LLVM ToolChain Implementations --------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 

 #include "llvm/Support/Error.h"
 #include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/Process.h"
 #include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/YAMLParser.h"
 #include "llvm/TargetParser/ARMTargetParserCommon.h"
 #include "llvm/TargetParser/Host.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
 #include <cctype>
 
 using namespace clang::driver;
 using namespace clang::driver::tools;
 using namespace clang;
 using namespace llvm::opt;
 
 static void CheckPreprocessingOptions(const Driver &D, const ArgList &Args) {
if (!ISAInfo) {
       consumeError(ISAInfo.takeError());
     } else {
       MinVLen = (*ISAInfo)->getMinVLen();
     }
 
     // If the value is "zvl", use MinVLen from march. Otherwise, try to parse
     // as integer as long as we have a MinVLen.
     unsigned Bits = 0;
-    if (Val.equals("zvl") && MinVLen >= llvm::RISCV::RVVBitsPerBlock) {
+    if (Val.equals("zvl") && MinVLen >= llvm::RISCVISAInfo::RVVBitsPerBlock) {
       Bits = MinVLen;
     } else if (!Val.getAsInteger(10, Bits)) {
       // Only accept power of 2 values beteen RVVBitsPerBlock and 65536 that
       // at least MinVLen.
-      if (Bits < MinVLen || Bits < llvm::RISCV::RVVBitsPerBlock ||
+      if (Bits < MinVLen || Bits < llvm::RISCVISAInfo::RVVBitsPerBlock ||
           Bits > 65536 || !llvm::isPowerOf2_32(Bits))
         Bits = 0;
     }
 
     // If we got a valid value try to use it.
     if (Bits != 0) {
-      unsigned VScaleMin = Bits / llvm::RISCV::RVVBitsPerBlock;
+      unsigned VScaleMin = Bits / llvm::RISCVISAInfo::RVVBitsPerBlock;
       CmdArgs.push_back(
           Args.MakeArgString("-mvscale-max=" + llvm::Twine(VScaleMin)));
       CmdArgs.push_back(
           Args.MakeArgString("-mvscale-min=" + llvm::Twine(VScaleMin)));
     } else if (!Val.equals("scalable")) {
       // Handle the unsupported values passed to mrvv-vector-bits.
       D.Diag(diag::err_drv_unsupported_option_argument)
           << A->getSpelling() << Val;

clang/lib/Sema/CMakeLists.txt

add_clang_library(clangSema
   SemaTemplateInstantiateDecl.cpp
   SemaTemplateVariadic.cpp
   SemaType.cpp
   TypeLocBuilder.cpp
 
   DEPENDS
   ClangOpenCLBuiltinsImpl
   omp_gen
-  RISCVTargetParserTableGen
 
   LINK_LIBS
   clangAST
   clangAnalysis
   clangBasic
   clangEdit
   clangLex
   clangSupport
   )

clang/lib/Sema/SemaType.cpp

 //===--- SemaType.cpp - Semantic Analysis for Types -----------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 #include "clang/Sema/SemaInternal.h"
 #include "clang/Sema/Template.h"
 #include "clang/Sema/TemplateInstCallback.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/Support/ErrorHandling.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include <bitset>
 #include <optional>
 
 using namespace clang;
 
 enum TypeDiagSelector {
   TDS_Function,
   TDS_Pointer,
static void HandleRISCVRVVVectorBitsTypeAttr(QualType &CurType,
   if (!verifyValidIntegerConstantExpr(S, Attr, RVVVectorSizeInBits))
     return;
 
   unsigned VecSize = static_cast<unsigned>(RVVVectorSizeInBits.getZExtValue());
 
   // The attribute vector size must match -mrvv-vector-bits.
   // FIXME: Add support for types with LMUL!=1. Need to make sure size passed
   // to attribute is equal to LMUL*VScaleMin*RVVBitsPerBlock.
-  if (VecSize != VScale->first * llvm::RISCV::RVVBitsPerBlock) {
+  if (VecSize != VScale->first * llvm::RISCVISAInfo::RVVBitsPerBlock) {
     S.Diag(Attr.getLoc(), diag::err_attribute_bad_rvv_vector_size)
-        << VecSize << VScale->first * llvm::RISCV::RVVBitsPerBlock;
+        << VecSize << VScale->first * llvm::RISCVISAInfo::RVVBitsPerBlock;
     Attr.setInvalid();
     return;
   }
 
   // Attribute can only be attached to a single RVV vector type.
   if (!CurType->isRVVVLSBuiltinType()) {
     S.Diag(Attr.getLoc(), diag::err_attribute_invalid_rvv_type)
         << Attr << CurType;

llvm/include/llvm/Support/RISCVISAInfo.h

 //===-- RISCVISAInfo.h - RISC-V ISA Information -----------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
public:
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext, unsigned MajorVersion,
                                    unsigned MinorVersion);
   static llvm::Expected<std::unique_ptr<RISCVISAInfo>>
   postProcessAndChecking(std::unique_ptr<RISCVISAInfo> &&ISAInfo);
 
+  static constexpr unsigned RVVBitsPerBlock = 64;
+
 private:
   RISCVISAInfo(unsigned XLen)
       : XLen(XLen), FLen(0), MinVLen(0), MaxELen(0), MaxELenFp(0) {}
 
   unsigned XLen;
   unsigned FLen;
   unsigned MinVLen;
   unsigned MaxELen, MaxELenFp;

llvm/include/llvm/TargetParser/RISCVTargetParser.h

 //===-- RISCVTargetParser - Parser for target features ----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 #include <vector>
 
 namespace llvm {
 
 class Triple;
 
 namespace RISCV {
 
-// We use 64 bits as the known part in the scalable vector types.
-static constexpr unsigned RVVBitsPerBlock = 64;
-
 enum CPUKind : unsigned {
 #define PROC(ENUM, NAME, DEFAULT_MARCH) CK_##ENUM,
 #define TUNE_PROC(ENUM, NAME) CK_##ENUM,
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
 };
 
 bool checkCPUKind(CPUKind Kind, bool IsRV64);
 bool checkTuneCPUKind(CPUKind Kind, bool IsRV64);

llvm/lib/Target/RISCV/RISCVISelLowering.h

 //===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the interfaces that RISC-V uses to lower LLVM code into a
 // selection DAG.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
 
 #include "RISCV.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/TargetLowering.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
 #include <optional>
 
 namespace llvm {
 class RISCVSubtarget;
 struct RISCVRegisterInfo;
 namespace RISCVISD {
 enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
public:
   // Return the value of VLMax for the given vector type (i.e. SEW and LMUL)
   SDValue computeVLMax(MVT VecVT, SDLoc DL, SelectionDAG &DAG) const;
 
   static RISCVII::VLMUL getLMUL(MVT VT);
   inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,
                                       unsigned MinSize) {
     // Original equation:
     //   VLMAX = (VectorBits / EltSize) * LMUL
-    //   where LMUL = MinSize / RISCV::RVVBitsPerBlock
+    //   where LMUL = MinSize / RISCVISAInfo::RVVBitsPerBlock
     // The following equations have been reordered to prevent loss of precision
     // when calculating fractional LMUL.
-    return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
+    return ((VectorBits / EltSize) * MinSize) / RISCVISAInfo::RVVBitsPerBlock;
   };
   static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
   static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
   static unsigned getRegClassIDForVecVT(MVT VT);
   static std::pair<unsigned, unsigned>
   decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT,
                                            unsigned InsertExtractIdx,
                                            const RISCVRegisterInfo *TRI);

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation  -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
static const MVT::SimpleValueType F32VecVTs[] = {
       MVT::nxv1f32, MVT::nxv2f32, MVT::nxv4f32, MVT::nxv8f32, MVT::nxv16f32};
   static const MVT::SimpleValueType F64VecVTs[] = {
       MVT::nxv1f64, MVT::nxv2f64, MVT::nxv4f64, MVT::nxv8f64};
 
   if (Subtarget.hasVInstructions()) {
     auto addRegClassForRVV = [this](MVT VT) {
       // Disable the smallest fractional LMUL types if ELEN is less than
       // RVVBitsPerBlock.
-      unsigned MinElts = RISCV::RVVBitsPerBlock / Subtarget.getELEN();
+      unsigned MinElts = RISCVISAInfo::RVVBitsPerBlock / Subtarget.getELEN();
       if (VT.getVectorMinNumElements() < MinElts)
         return;
 
       unsigned Size = VT.getSizeInBits().getKnownMinValue();
       const TargetRegisterClass *RC;
-      if (Size <= RISCV::RVVBitsPerBlock)
+      if (Size <= RISCVISAInfo::RVVBitsPerBlock)
         RC = &RISCV::VRRegClass;
-      else if (Size == 2 * RISCV::RVVBitsPerBlock)
+      else if (Size == 2 * RISCVISAInfo::RVVBitsPerBlock)
         RC = &RISCV::VRM2RegClass;
-      else if (Size == 4 * RISCV::RVVBitsPerBlock)
+      else if (Size == 4 * RISCVISAInfo::RVVBitsPerBlock)
         RC = &RISCV::VRM4RegClass;
-      else if (Size == 8 * RISCV::RVVBitsPerBlock)
+      else if (Size == 8 * RISCVISAInfo::RVVBitsPerBlock)
         RC = &RISCV::VRM8RegClass;
       else
         llvm_unreachable("Unexpected size");
 
       addRegisterClass(VT, RC);
     };
 
     for (MVT VT : BoolVecVTs)
static MVT getContainerForFixedLengthVector(const TargetLowering &TLI, MVT VT,
   case MVT::i64:
   case MVT::f16:
   case MVT::f32:
   case MVT::f64: {
     // We prefer to use LMUL=1 for VLEN sized types. Use fractional lmuls for
     // narrower types. The smallest fractional LMUL we support is 8/ELEN. Within
     // each fractional LMUL we support SEW between 8 and LMUL*ELEN.
     unsigned NumElts =
-        (VT.getVectorNumElements() * RISCV::RVVBitsPerBlock) / MinVLen;
-    NumElts = std::max(NumElts, RISCV::RVVBitsPerBlock / MaxELen);
+        (VT.getVectorNumElements() * RISCVISAInfo::RVVBitsPerBlock) / MinVLen;
+    NumElts = std::max(NumElts, RISCVISAInfo::RVVBitsPerBlock / MaxELen);
     assert(isPowerOf2_32(NumElts) && "Expected power of 2 NumElts");
     return MVT::getScalableVectorVT(EltVT, NumElts);
   }
   }
 }
 
 static MVT getContainerForFixedLengthVector(SelectionDAG &DAG, MVT VT,
                                             const RISCVSubtarget &Subtarget) {
static SDValue lowerScalarSplat(SDValue Passthru, SDValue Scalar, SDValue VL,
   // Otherwise use the more complicated splatting algorithm.
   return splatSplitI64WithVL(DL, VT, Passthru, Scalar, VL, DAG);
 }
 
 static MVT getLMUL1VT(MVT VT) {
   assert(VT.getVectorElementType().getSizeInBits() <= 64 &&
          "Unexpected vector MVT");
   return MVT::getScalableVectorVT(
-      VT.getVectorElementType(),
-      RISCV::RVVBitsPerBlock / VT.getVectorElementType().getSizeInBits());
+      VT.getVectorElementType(), RISCVISAInfo::RVVBitsPerBlock /
+                                     VT.getVectorElementType().getSizeInBits());
 }
 
 // This function lowers an insert of a scalar operand Scalar into lane
 // 0 of the vector regardless of the value of VL.  The contents of the
 // remaining lanes of the result vector are unspecified.  VL is assumed
 // to be non-zero.
 static SDValue lowerScalarInsert(SDValue Scalar, SDValue VL,
                                  MVT VT, SDLoc DL, SelectionDAG &DAG,
SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   }
   case ISD::VSCALE: {
     MVT VT = Op.getSimpleValueType();
     SDLoc DL(Op);
     SDValue VLENB = DAG.getNode(RISCVISD::READ_VLENB, DL, VT);
     // We define our scalable vector types for lmul=1 to use a 64 bit known
     // minimum size. e.g. <vscale x 2 x i32>. VLENB is in bytes so we calculate
     // vscale as VLENB / 8.
-    static_assert(RISCV::RVVBitsPerBlock == 64, "Unexpected bits per block!");
-    if (Subtarget.getRealMinVLen() < RISCV::RVVBitsPerBlock)
+    static_assert(RISCVISAInfo::RVVBitsPerBlock == 64,
+                  "Unexpected bits per block!");
+    if (Subtarget.getRealMinVLen() < RISCVISAInfo::RVVBitsPerBlock)
       report_fatal_error("Support for VLEN==32 is incomplete.");
     // We assume VLENB is a multiple of 8. We manually choose the best shift
     // here because SimplifyDemandedBits isn't always able to simplify it.
     uint64_t Val = Op.getConstantOperandVal(0);
     if (isPowerOf2_64(Val)) {
       uint64_t Log2 = Log2_64(Val);
       if (Log2 < 3)
         return DAG.getNode(ISD::SRL, DL, VT, VLENB,
SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
   // to use vrgatherei16.vv.
   // TODO: It's also possible to use vrgatherei16.vv for other types to
   // decrease register width for the index calculation.
   if (MaxVLMAX > 256 && EltSize == 8) {
     // If this is LMUL=8, we have to split before can use vrgatherei16.vv.
     // Reverse each half, then reassemble them in reverse order.
     // NOTE: It's also possible that after splitting that VLMAX no longer
     // requires vrgatherei16.vv.
-    if (MinSize == (8 * RISCV::RVVBitsPerBlock)) {
+    if (MinSize == (8 * RISCVISAInfo::RVVBitsPerBlock)) {
       auto [Lo, Hi] = DAG.SplitVectorOperand(Op.getNode(), 0);
       auto [LoVT, HiVT] = DAG.GetSplitDestVTs(VecVT);
       Lo = DAG.getNode(ISD::VECTOR_REVERSE, DL, LoVT, Lo);
       Hi = DAG.getNode(ISD::VECTOR_REVERSE, DL, HiVT, Hi);
       // Reassemble the low and high pieces reversed.
       // FIXME: This is a CONCAT_VECTORS.
       SDValue Res =
           DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VecVT, DAG.getUNDEF(VecVT), Hi,

 
 bool RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo() const {
   // We define vscale to be VLEN/RVVBitsPerBlock.  VLEN is always a power
   // of two >= 64, and RVVBitsPerBlock is 64.  Thus, vscale must be
   // a power of two as well.
   // FIXME: This doesn't work for zve32, but that's already broken
   // elsewhere for the same reason.
   assert(Subtarget.getRealMinVLen() >= 64 && "zve32* unsupported");
-  static_assert(RISCV::RVVBitsPerBlock == 64,
+  static_assert(RISCVISAInfo::RVVBitsPerBlock == 64,
                 "RVVBitsPerBlock changed, audit needed");
   return true;
 }
 
 bool RISCVTargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
                                                  SDValue &Offset,
                                                  ISD::MemIndexedMode &AM,
                                                  bool &IsInc,

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISC-V ----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
std::string FS =
       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
 
   unsigned RVVBitsMin = RVVVectorBitsMinOpt;
   unsigned RVVBitsMax = RVVVectorBitsMaxOpt;
 
   Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);
   if (VScaleRangeAttr.isValid()) {
     if (!RVVVectorBitsMinOpt.getNumOccurrences())
-      RVVBitsMin = VScaleRangeAttr.getVScaleRangeMin() * RISCV::RVVBitsPerBlock;
+      RVVBitsMin =
+          VScaleRangeAttr.getVScaleRangeMin() * RISCVISAInfo::RVVBitsPerBlock;
     std::optional<unsigned> VScaleMax = VScaleRangeAttr.getVScaleRangeMax();
     if (VScaleMax.has_value() && !RVVVectorBitsMaxOpt.getNumOccurrences())
-      RVVBitsMax = *VScaleMax * RISCV::RVVBitsPerBlock;
+      RVVBitsMax = *VScaleMax * RISCVISAInfo::RVVBitsPerBlock;
   }
 
   if (RVVBitsMin != -1U) {
     // FIXME: Change to >= 32 when VLEN = 32 is supported.
     assert((RVVBitsMin == 0 || (RVVBitsMin >= 64 && RVVBitsMin <= 65536 &&
                                 isPowerOf2_32(RVVBitsMin))) &&
            "V or Zve* extension requires vector length to be in the range of "
            "64 to 65536 and a power 2!");

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

 //===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
bool RISCVTTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {
   case Intrinsic::vector_reduce_mul:
   case Intrinsic::vector_reduce_fmul:
     return true;
   }
 }
 
 std::optional<unsigned> RISCVTTIImpl::getMaxVScale() const {
   if (ST->hasVInstructions())
-    return ST->getRealMaxVLen() / RISCV::RVVBitsPerBlock;
+    return ST->getRealMaxVLen() / RISCVISAInfo::RVVBitsPerBlock;
   return BaseT::getMaxVScale();
 }
 
 std::optional<unsigned> RISCVTTIImpl::getVScaleForTuning() const {
   if (ST->hasVInstructions())
     if (unsigned MinVLen = ST->getRealMinVLen();
-        MinVLen >= RISCV::RVVBitsPerBlock)
-      return MinVLen / RISCV::RVVBitsPerBlock;
+        MinVLen >= RISCVISAInfo::RVVBitsPerBlock)
+      return MinVLen / RISCVISAInfo::RVVBitsPerBlock;
   return BaseT::getVScaleForTuning();
 }
 
 TypeSize
 RISCVTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
   unsigned LMUL =
       llvm::bit_floor(std::clamp<unsigned>(RVVRegisterWidthLMUL, 1, 8));
   switch (K) {
   case TargetTransformInfo::RGK_Scalar:
     return TypeSize::getFixed(ST->getXLen());
   case TargetTransformInfo::RGK_FixedWidthVector:
     return TypeSize::getFixed(
         ST->useRVVForFixedLengthVectors() ? LMUL * ST->getRealMinVLen() : 0);
   case TargetTransformInfo::RGK_ScalableVector:
     return TypeSize::getScalable(
         (ST->hasVInstructions() &&
-         ST->getRealMinVLen() >= RISCV::RVVBitsPerBlock)
-            ? LMUL * RISCV::RVVBitsPerBlock
+         ST->getRealMinVLen() >= RISCVISAInfo::RVVBitsPerBlock)
+            ? LMUL * RISCVISAInfo::RVVBitsPerBlock
             : 0);
   }
 
   llvm_unreachable("Unsupported register kind");
 }
 
 InstructionCost
 RISCVTTIImpl::getConstantPoolLoadCost(Type *Ty,  TTI::TargetCostKind CostKind) {
InstructionCost RISCVTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
   }
   return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
 }
 
 unsigned RISCVTTIImpl::getEstimatedVLFor(VectorType *Ty) {
   if (isa<ScalableVectorType>(Ty)) {
     const unsigned EltSize = DL.getTypeSizeInBits(Ty->getElementType());
     const unsigned MinSize = DL.getTypeSizeInBits(Ty).getKnownMinValue();
-    const unsigned VectorBits = *getVScaleForTuning() * RISCV::RVVBitsPerBlock;
+    const unsigned VectorBits =
+        *getVScaleForTuning() * RISCVISAInfo::RVVBitsPerBlock;
     return RISCVTargetLowering::computeVLMAX(VectorBits, EltSize, MinSize);
   }
   return cast<FixedVectorType>(Ty)->getNumElements();
 }
 
 InstructionCost
 RISCVTTIImpl::getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
                                      bool IsUnsigned, FastMathFlags FMF,
void RISCVTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE,
                                          TTI::PeelingPreferences &PP) {
   BaseT::getPeelingPreferences(L, SE, PP);
 }
 
 unsigned RISCVTTIImpl::getRegUsageForType(Type *Ty) {
   TypeSize Size = DL.getTypeSizeInBits(Ty);
   if (Ty->isVectorTy()) {
     if (Size.isScalable() && ST->hasVInstructions())
-      return divideCeil(Size.getKnownMinValue(), RISCV::RVVBitsPerBlock);
+      return divideCeil(Size.getKnownMinValue(), RISCVISAInfo::RVVBitsPerBlock);
 
     if (ST->useRVVForFixedLengthVectors())
       return divideCeil(Size, ST->getRealMinVLen());
   }
 
   return BaseT::getRegUsageForType(Ty);
 }