[llvm] Use std::size instead of llvm::array_lengthof

[jloser]

Summary

LLVM contains a helpful function for getting the size of a C-style
array: llvm::array_lengthof. This is useful prior to C++17, but not as
helpful for C++17 or later: std::size already has support for C-style
arrays.

Change call sites to use std::size instead.

[dblaikie]

As a follow-up, probably good to deprecate the API with the necessary recommended alternative for at least a little while, to client code migrations easier.

@kazu - this might be something you'd be interested in helping with, or pointing @jloser to the right tools/directions.

[jloser]

In D133429#3776384, @dblaikie wrote:

As a follow-up, probably good to deprecate the API with the necessary recommended alternative for at least a little while, to client code migrations easier.

@kazu - this might be something you'd be interested in helping with, or pointing @jloser to the right tools/directions.

Sounds good to me. I just opened https://reviews.llvm.org/D133502 to mark the function deprecated, but let me know if you or @kazu had something else in mind. I've fixed downstream callers in MLIR and LLDB (https://reviews.llvm.org/D133501) with Clang being on my list to do as well. This only accounts for the call sites in LLVM codebase though rather than external downstream. Is there a process (e.g. wait two weeks after deprecating before removal) or something of the like?

[kazu]

In D133429#3777310, @jloser wrote:

In D133429#3776384, @dblaikie wrote:

As a follow-up, probably good to deprecate the API with the necessary recommended alternative for at least a little while, to client code migrations easier.

@kazu - this might be something you'd be interested in helping with, or pointing @jloser to the right tools/directions.

Sounds good to me. I just opened https://reviews.llvm.org/D133502 to mark the function deprecated, but let me know if you or @kazu had something else in mind. I've fixed downstream callers in MLIR and LLDB (https://reviews.llvm.org/D133501) with Clang being on my list to do as well. This only accounts for the call sites in LLVM codebase though rather than external downstream. Is there a process (e.g. wait two weeks after deprecating before removal) or something of the like?

This is a great cleanup. Thank you!

I am not aware of any documented process. For my recent deprecation of Optional::hasValue, I am waiting for 3 months or so, but some call it too long. So, wait as long as reasonable in your terms.

In any event, I think it's a good idea to clean up internal downstream users first before deprecating array_lengthof. The llvm codebase and internal downstream build cleanly even with -Werror (with clang being the host compiler), so we don't want to introduce a lot of deprecation warnings all of a sudden.

[dblaikie]

(yep, @kazu's covered everything I can think of here - I'll leave it to you two to work it through)

llvm/include/llvm/CodeGen/TargetLowering.h

virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const {
     return true;
   }
 
   /// Return true if the target has native support for the specified value type.
   /// This means that it has a register that directly holds it without
   /// promotions or expansions.
   bool isTypeLegal(EVT VT) const {
     assert(!VT.isSimple() ||
-           (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
+           (unsigned)VT.getSimpleVT().SimpleTy < std::size(RegClassForVT));
     return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
   }
 
   class ValueTypeActionImpl {
     /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
     /// that indicates how instruction selection should deal with the type.
     LegalizeTypeAction ValueTypeActions[MVT::VALUETYPE_SIZE];
 
public:
 
   /// Return how this operation should be treated: either it is legal, needs to
   /// be promoted to a larger size, needs to be expanded to some other code
   /// sequence, or the target has a custom expander for it.
   LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
     if (VT.isExtended()) return Expand;
     // If a target-specific SDNode requires legalization, require the target
     // to provide custom legalization for it.
-    if (Op >= array_lengthof(OpActions[0])) return Custom;
+    if (Op >= std::size(OpActions[0]))
+      return Custom;
     return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
   }
 
   /// Custom method defined by each target to indicate if an operation which
   /// may require a scale is supported natively by the target.
   /// If not, the operation is illegal.
   virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT,
                                               unsigned Scale) const {
virtual bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const {
     return false;
   }
 
   /// Return how the condition code should be treated: either it is legal, needs
   /// to be expanded to some other code sequence, or the target has a custom
   /// expander for it.
   LegalizeAction
   getCondCodeAction(ISD::CondCode CC, MVT VT) const {
-    assert((unsigned)CC < array_lengthof(CondCodeActions) &&
-           ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
+    assert((unsigned)CC < std::size(CondCodeActions) &&
+           ((unsigned)VT.SimpleTy >> 3) < std::size(CondCodeActions[0]) &&
            "Table isn't big enough!");
     // See setCondCodeAction for how this is encoded.
     uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
     uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
     LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
     assert(Action != Promote && "Can't promote condition code!");
     return Action;
   }
#include "llvm/IR/ConstrainedOps.def"
 
   /// Return the desired alignment for ByVal or InAlloca aggregate function
   /// arguments in the caller parameter area.  This is the actual alignment, not
   /// its logarithm.
   virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
 
   /// Return the type of registers that this ValueType will eventually require.
   MVT getRegisterType(MVT VT) const {
-    assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
+    assert((unsigned)VT.SimpleTy < std::size(RegisterTypeForVT));
     return RegisterTypeForVT[VT.SimpleTy];
   }
 
   /// Return the type of registers that this ValueType will eventually require.
   MVT getRegisterType(LLVMContext &Context, EVT VT) const {
     if (VT.isSimple()) {
       assert((unsigned)VT.getSimpleVT().SimpleTy <
-                array_lengthof(RegisterTypeForVT));
+             std::size(RegisterTypeForVT));
       return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
     }
     if (VT.isVector()) {
       EVT VT1;
       MVT RegisterVT;
       unsigned NumIntermediates;
       (void)getVectorTypeBreakdown(Context, VT, VT1,
                                    NumIntermediates, RegisterVT);
#include "llvm/IR/ConstrainedOps.def"
   ///
   /// RegisterVT may be passed as a way to override the default settings, for
   /// instance with i128 inline assembly operands on SystemZ.
   virtual unsigned
   getNumRegisters(LLVMContext &Context, EVT VT,
                   Optional<MVT> RegisterVT = None) const {
     if (VT.isSimple()) {
       assert((unsigned)VT.getSimpleVT().SimpleTy <
-                array_lengthof(NumRegistersForVT));
+             std::size(NumRegistersForVT));
       return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
     }
     if (VT.isVector()) {
       EVT VT1;
       MVT VT2;
       unsigned NumIntermediates;
       return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
     }
#include "llvm/IR/ConstrainedOps.def"
   /// for ppcf128, where the Hi part always comes first.
   bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
     return DL.isBigEndian() || VT == MVT::ppcf128;
   }
 
   /// If true, the target has custom DAG combine transformations that it can
   /// perform for the specified node.
   bool hasTargetDAGCombine(ISD::NodeType NT) const {
-    assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
+    assert(unsigned(NT >> 3) < std::size(TargetDAGCombineArray));
     return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
   }
 
   unsigned getGatherAllAliasesMaxDepth() const {
     return GatherAllAliasesMaxDepth;
   }
 
   /// Returns the size of the platform's va_list object.
protected:
   void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
     BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
   }
 
   /// Add the specified register class as an available regclass for the
   /// specified value type. This indicates the selector can handle values of
   /// that class natively.
   void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
-    assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
+    assert((unsigned)VT.SimpleTy < std::size(RegClassForVT));
     RegClassForVT[VT.SimpleTy] = RC;
   }
 
   /// Return the largest legal super-reg register class of the register class
   /// for the specified type and its associated "cost".
   virtual std::pair<const TargetRegisterClass *, uint8_t>
   findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
 
   /// Once all of the register classes are added, this allows us to compute
   /// derived properties we expose.
   void computeRegisterProperties(const TargetRegisterInfo *TRI);
 
   /// Indicate that the specified operation does not work with the specified
   /// type and indicate what to do about it. Note that VT may refer to either
   /// the type of a result or that of an operand of Op.
   void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action) {
-    assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
+    assert(Op < std::size(OpActions[0]) && "Table isn't big enough!");
     OpActions[(unsigned)VT.SimpleTy][Op] = Action;
   }
   void setOperationAction(ArrayRef<unsigned> Ops, MVT VT,
                           LegalizeAction Action) {
     for (auto Op : Ops)
       setOperationAction(Op, VT, Action);
   }
   void setOperationAction(ArrayRef<unsigned> Ops, ArrayRef<MVT> VTs,
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT,
     setIndexedModeAction(IdxMode, VT, IMAB_MaskedStore, Action);
   }
 
   /// Indicate that the specified condition code is or isn't supported on the
   /// target and indicate what to do about it.
   void setCondCodeAction(ArrayRef<ISD::CondCode> CCs, MVT VT,
                          LegalizeAction Action) {
     for (auto CC : CCs) {
-      assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
+      assert(VT.isValid() && (unsigned)CC < std::size(CondCodeActions) &&
              "Table isn't big enough!");
       assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
       /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the
       /// 32-bit value and the upper 29 bits index into the second dimension of
       /// the array to select what 32-bit value to use.
       uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
       CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
       CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
     AddPromotedToType(Opc, OrigVT, DestVT);
   }
 
   /// Targets should invoke this method for each target independent node that
   /// they want to provide a custom DAG combiner for by implementing the
   /// PerformDAGCombine virtual method.
   void setTargetDAGCombine(ArrayRef<ISD::NodeType> NTs) {
     for (auto NT : NTs) {
-      assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
+      assert(unsigned(NT >> 3) < std::size(TargetDAGCombineArray));
       TargetDAGCombineArray[NT >> 3] |= 1 << (NT & 7);
     }
   }
 
   /// Set the target's minimum function alignment.
   void setMinFunctionAlignment(Align Alignment) {
     MinFunctionAlignment = Alignment;
   }

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

for (unsigned High = 0; High < 2; ++High) {
     bool UseBuildVector = false;
     for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
       // The mask element.  This indexes into the input.
       int Idx = Mask[FirstMaskIdx + MaskOffset];
 
       // The input vector this mask element indexes into.
       unsigned Input = (unsigned)Idx / NewElts;
 
-      if (Input >= array_lengthof(Inputs)) {
+      if (Input >= std::size(Inputs)) {
         // The mask element does not index into any input vector.
         Ops.push_back(-1);
         continue;
       }
 
       // Turn the index into an offset from the start of the input vector.
       Idx -= Input * NewElts;
 
       // Find or create a shuffle vector operand to hold this input.
       unsigned OpNo;
-      for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
+      for (OpNo = 0; OpNo < std::size(InputUsed); ++OpNo) {
         if (InputUsed[OpNo] == Input) {
           // This input vector is already an operand.
           break;
         } else if (InputUsed[OpNo] == -1U) {
           // Create a new operand for this input vector.
           InputUsed[OpNo] = Input;
           break;
         }
       }
 
-      if (OpNo >= array_lengthof(InputUsed)) {
+      if (OpNo >= std::size(InputUsed)) {
         // More than two input vectors used!  Give up on trying to create a
         // shuffle vector.  Insert all elements into a BUILD_VECTOR instead.
         UseBuildVector = true;
         break;
       }
 
       // Add the mask index for the new shuffle vector.
       Ops.push_back(Idx + OpNo * NewElts);
     }
 
     if (UseBuildVector) {
       LLT EltTy = NarrowTy.getElementType();
       SmallVector<Register, 16> SVOps;
 
       // Extract the input elements by hand.
       for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
         // The mask element.  This indexes into the input.
         int Idx = Mask[FirstMaskIdx + MaskOffset];
 
         // The input vector this mask element indexes into.
         unsigned Input = (unsigned)Idx / NewElts;
 
-        if (Input >= array_lengthof(Inputs)) {
+        if (Input >= std::size(Inputs)) {
           // The mask element is "undef" or indexes off the end of the input.
           SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0));
           continue;
         }
 
         // Turn the index into an offset from the start of the input vector.
         Idx -= Input * NewElts;
 

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
   // express it as a vector shuffle of those two inputs.  Otherwise extract the
   // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
   SmallVector<int> OrigMask(N->getMask());
   // Try to pack incoming shuffles/inputs.
   auto &&TryPeekThroughShufflesInputs = [&Inputs, &NewVT, this, NewElts,
                                          &DL](SmallVectorImpl<int> &Mask) {
     // Check if all inputs are shuffles of the same operands or non-shuffles.
     MapVector<std::pair<SDValue, SDValue>, SmallVector<unsigned>> ShufflesIdxs;
-    for (unsigned Idx = 0; Idx < array_lengthof(Inputs); ++Idx) {
+    for (unsigned Idx = 0; Idx < std::size(Inputs); ++Idx) {
       SDValue Input = Inputs[Idx];
       auto *Shuffle = dyn_cast<ShuffleVectorSDNode>(Input.getNode());
       if (!Shuffle ||
           Input.getOperand(0).getValueType() != Input.getValueType())
         continue;
       ShufflesIdxs[std::make_pair(Input.getOperand(0), Input.getOperand(1))]
           .push_back(Idx);
       ShufflesIdxs[std::make_pair(Input.getOperand(1), Input.getOperand(0))]
for (auto &P : ShufflesIdxs) {
       // 2. Update inputs.
       Inputs[P.second[0]] = P.first.first;
       Inputs[P.second[1]] = P.first.second;
       // Clear the pair data.
       P.second.clear();
       ShufflesIdxs[std::make_pair(P.first.second, P.first.first)].clear();
     }
     // Check if any concat_vectors can be simplified.
-    SmallBitVector UsedSubVector(2 * array_lengthof(Inputs));
+    SmallBitVector UsedSubVector(2 * std::size(Inputs));
     for (int &Idx : Mask) {
       if (Idx == UndefMaskElem)
         continue;
       unsigned SrcRegIdx = Idx / NewElts;
       if (Inputs[SrcRegIdx].isUndef()) {
         Idx = UndefMaskElem;
         continue;
       }
       TargetLowering::LegalizeTypeAction TypeAction =
           getTypeAction(Inputs[SrcRegIdx].getValueType());
       if (Inputs[SrcRegIdx].getOpcode() == ISD::CONCAT_VECTORS &&
           Inputs[SrcRegIdx].getNumOperands() == 2 &&
           !Inputs[SrcRegIdx].getOperand(1).isUndef() &&
           (TypeAction == TargetLowering::TypeLegal ||
            TypeAction == TargetLowering::TypeWidenVector))
         UsedSubVector.set(2 * SrcRegIdx + (Idx % NewElts) / (NewElts / 2));
     }
     if (UsedSubVector.count() > 1) {
       SmallVector<SmallVector<std::pair<unsigned, int>, 2>> Pairs;
-      for (unsigned I = 0; I < array_lengthof(Inputs); ++I) {
+      for (unsigned I = 0; I < std::size(Inputs); ++I) {
         if (UsedSubVector.test(2 * I) == UsedSubVector.test(2 * I + 1))
           continue;
         if (Pairs.empty() || Pairs.back().size() == 2)
           Pairs.emplace_back();
         if (UsedSubVector.test(2 * I)) {
           Pairs.back().emplace_back(I, 0);
         } else {
           assert(UsedSubVector.test(2 * I + 1) &&
if (UsedSubVector.count() > 1) {
         }
       }
     }
     bool Changed;
     do {
       // Try to remove extra shuffles (except broadcasts) and shuffles with the
       // reused operands.
       Changed = false;
-      for (unsigned I = 0; I < array_lengthof(Inputs); ++I) {
+      for (unsigned I = 0; I < std::size(Inputs); ++I) {
         auto *Shuffle = dyn_cast<ShuffleVectorSDNode>(Inputs[I].getNode());
         if (!Shuffle)
           continue;
         if (Shuffle->getOperand(0).getValueType() != NewVT)
           continue;
         int Op = -1;
         if (!Inputs[I].hasOneUse() && Shuffle->getOperand(1).isUndef() &&
             !Shuffle->isSplat()) {
auto &&MakeUniqueInputs = [&Inputs, &IsConstant,
     for (const auto &I : Inputs) {
       if (IsConstant(I))
         UniqueConstantInputs.insert(I);
       else if (!I.isUndef())
         UniqueInputs.insert(I);
     }
     // Adjust mask in case of reused inputs. Also, need to insert constant
     // inputs at first, otherwise it affects the final outcome.
-    if (UniqueInputs.size() != array_lengthof(Inputs)) {
+    if (UniqueInputs.size() != std::size(Inputs)) {
       auto &&UniqueVec = UniqueInputs.takeVector();
       auto &&UniqueConstantVec = UniqueConstantInputs.takeVector();
       unsigned ConstNum = UniqueConstantVec.size();
       for (int &Idx : Mask) {
         if (Idx == UndefMaskElem)
           continue;
         unsigned SrcRegIdx = Idx / NewElts;
         if (Inputs[SrcRegIdx].isUndef()) {
void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
   SDValue OrigInputs[4];
   copy(Inputs, std::begin(OrigInputs));
   for (unsigned High = 0; High < 2; ++High) {
     SDValue &Output = High ? Hi : Lo;
 
     // Build a shuffle mask for the output, discovering on the fly which
     // input vectors to use as shuffle operands.
     unsigned FirstMaskIdx = High * NewElts;
-    SmallVector<int> Mask(NewElts * array_lengthof(Inputs), UndefMaskElem);
+    SmallVector<int> Mask(NewElts * std::size(Inputs), UndefMaskElem);
     copy(makeArrayRef(OrigMask).slice(FirstMaskIdx, NewElts), Mask.begin());
     assert(!Output && "Expected default initialized initial value.");
     TryPeekThroughShufflesInputs(Mask);
     MakeUniqueInputs(Mask);
     SDValue TmpInputs[4];
     copy(Inputs, std::begin(TmpInputs));
     // Track changes in the output registers.
     int UsedIdx = -1;
     bool SecondIteration = false;
     auto &&AccumulateResults = [&UsedIdx, &SecondIteration](unsigned Idx) {
       if (UsedIdx < 0) {
         UsedIdx = Idx;
         return false;
       }
       if (UsedIdx >= 0 && static_cast<unsigned>(UsedIdx) == Idx)
         SecondIteration = true;
       return SecondIteration;
     };
     processShuffleMasks(
-        Mask, array_lengthof(Inputs), array_lengthof(Inputs),
+        Mask, std::size(Inputs), std::size(Inputs),
         /*NumOfUsedRegs=*/1,
         [&Output, &DAG = DAG, NewVT]() { Output = DAG.getUNDEF(NewVT); },
         [&Output, &DAG = DAG, NewVT, &DL, &Inputs,
          &BuildVector](ArrayRef<int> Mask, unsigned Idx, unsigned /*Unused*/) {
           if (Inputs[Idx]->getOpcode() == ISD::BUILD_VECTOR)
             Output = BuildVector(Inputs[Idx], Inputs[Idx], Mask);
           else
             Output = DAG.getVectorShuffle(NewVT, DL, Inputs[Idx],

llvm/lib/CodeGen/TargetLoweringBase.cpp

if (!JumpIsExpensiveOverride.getNumOccurrences())
     JumpIsExpensive = isExpensive;
 }
 
 TargetLoweringBase::LegalizeKind
 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
   // If this is a simple type, use the ComputeRegisterProp mechanism.
   if (VT.isSimple()) {
     MVT SVT = VT.getSimpleVT();
-    assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
+    assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
     MVT NVT = TransformToType[SVT.SimpleTy];
     LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
 
     assert((LA == TypeLegal || LA == TypeSoftenFloat ||
             LA == TypeSoftPromoteHalf ||
             (NVT.isVector() ||
              ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
            "Promote may not follow Expand or Promote");

llvm/lib/DWP/DWP.cpp

void writeStringsAndOffsets(MCStreamer &Out, DWPStringPool &Strings,
   }
 }
 
 void writeIndexTable(
     MCStreamer &Out, ArrayRef<unsigned> ContributionOffsets,
     const MapVector<uint64_t, UnitIndexEntry> &IndexEntries,
     uint32_t DWARFUnitIndex::Entry::SectionContribution::*Field) {
   for (const auto &E : IndexEntries)
-    for (size_t I = 0; I != array_lengthof(E.second.Contributions); ++I)
+    for (size_t I = 0; I != std::size(E.second.Contributions); ++I)
       if (ContributionOffsets[I])
         Out.emitIntValue(E.second.Contributions[I].*Field, 4);
 }
 
 void writeIndex(MCStreamer &Out, MCSection *Section,
                 ArrayRef<unsigned> ContributionOffsets,
                 const MapVector<uint64_t, UnitIndexEntry> &IndexEntries,
                 uint32_t IndexVersion) {

llvm/lib/IR/DebugInfoMetadata.cpp

if (Storage == Uniqued) {                                                  \
       if (!ShouldCreate)                                                       \
         return nullptr;                                                        \
     } else {                                                                   \
       assert(ShouldCreate &&                                                   \
              "Expected non-uniqued nodes to always be created");               \
     }                                                                          \
   } while (false)
 #define DEFINE_GETIMPL_STORE(CLASS, ARGS, OPS)                                 \
-  return storeImpl(new (array_lengthof(OPS), Storage)                          \
+  return storeImpl(new (std::size(OPS), Storage)                               \
                        CLASS(Context, Storage, UNWRAP_ARGS(ARGS), OPS),        \
                    Storage, Context.pImpl->CLASS##s)
 #define DEFINE_GETIMPL_STORE_NO_OPS(CLASS, ARGS)                               \
   return storeImpl(new (0u, Storage)                                           \
                        CLASS(Context, Storage, UNWRAP_ARGS(ARGS)),             \
                    Storage, Context.pImpl->CLASS##s)
 #define DEFINE_GETIMPL_STORE_NO_CONSTRUCTOR_ARGS(CLASS, OPS)                   \
-  return storeImpl(new (array_lengthof(OPS), Storage)                          \
-                       CLASS(Context, Storage, OPS),                           \
+  return storeImpl(new (std::size(OPS), Storage) CLASS(Context, Storage, OPS), \
                    Storage, Context.pImpl->CLASS##s)
 #define DEFINE_GETIMPL_STORE_N(CLASS, ARGS, OPS, NUM_OPS)                      \
   return storeImpl(new (NUM_OPS, Storage)                                      \
                        CLASS(Context, Storage, UNWRAP_ARGS(ARGS), OPS),        \
                    Storage, Context.pImpl->CLASS##s)
 
 DISubrange::DISubrange(LLVMContext &C, StorageType Storage,
                        ArrayRef<Metadata *> Ops)
Metadata *Ops[] = {File,
                      SplitDebugFilename,
                      EnumTypes,
                      RetainedTypes,
                      GlobalVariables,
                      ImportedEntities,
                      Macros,
                      SysRoot,
                      SDK};
-  return storeImpl(new (array_lengthof(Ops), Storage) DICompileUnit(
+  return storeImpl(new (std::size(Ops), Storage) DICompileUnit(
                        Context, Storage, SourceLanguage, IsOptimized,
                        RuntimeVersion, EmissionKind, DWOId, SplitDebugInlining,
                        DebugInfoForProfiling, NameTableKind, RangesBaseAddress,
                        Ops),
                    Storage);
 }
 
 Optional<DICompileUnit::DebugEmissionKind>

llvm/lib/MC/MCAsmBackend.cpp

static const MCFixupKindInfo Builtins[] = {
       {"FK_TPRel_4", 0, 32, 0},
       {"FK_TPRel_8", 0, 64, 0},
       {"FK_SecRel_1", 0, 8, 0},
       {"FK_SecRel_2", 0, 16, 0},
       {"FK_SecRel_4", 0, 32, 0},
       {"FK_SecRel_8", 0, 64, 0},
   };
 
-  assert((size_t)Kind <= array_lengthof(Builtins) && "Unknown fixup kind");
+  assert((size_t)Kind <= std::size(Builtins) && "Unknown fixup kind");
   return Builtins[Kind];
 }
 
 bool MCAsmBackend::fixupNeedsRelaxationAdvanced(
     const MCFixup &Fixup, bool Resolved, uint64_t Value,
     const MCRelaxableFragment *DF, const MCAsmLayout &Layout,
     const bool WasForced) const {
   if (!Resolved)
     return true;
   return fixupNeedsRelaxation(Fixup, Value, DF, Layout);
 }

llvm/lib/MC/MCDwarf.cpp

static const char StandardOpcodeLengths[] = {
       0, // length of DW_LNS_negate_stmt
       0, // length of DW_LNS_set_basic_block
       0, // length of DW_LNS_const_add_pc
       1, // length of DW_LNS_fixed_advance_pc
       0, // length of DW_LNS_set_prologue_end
       0, // length of DW_LNS_set_epilogue_begin
       1  // DW_LNS_set_isa
   };
-  assert(array_lengthof(StandardOpcodeLengths) >=
+  assert(std::size(StandardOpcodeLengths) >=
          (Params.DWARF2LineOpcodeBase - 1U));
   return Emit(
       MCOS, Params,
       makeArrayRef(StandardOpcodeLengths, Params.DWARF2LineOpcodeBase - 1),
       LineStr);
 }
 
 static const MCExpr *forceExpAbs(MCStreamer &OS, const MCExpr* Expr) {

llvm/lib/Object/MachOObjectFile.cpp

case Triple::aarch64_32: {
         "ARM64_RELOC_UNSIGNED",           "ARM64_RELOC_SUBTRACTOR",
         "ARM64_RELOC_BRANCH26",           "ARM64_RELOC_PAGE21",
         "ARM64_RELOC_PAGEOFF12",          "ARM64_RELOC_GOT_LOAD_PAGE21",
         "ARM64_RELOC_GOT_LOAD_PAGEOFF12", "ARM64_RELOC_POINTER_TO_GOT",
         "ARM64_RELOC_TLVP_LOAD_PAGE21",   "ARM64_RELOC_TLVP_LOAD_PAGEOFF12",
         "ARM64_RELOC_ADDEND"
       };
 
-      if (RType >= array_lengthof(Table))
+      if (RType >= std::size(Table))
         res = "Unknown";
       else
         res = Table[RType];
       break;
     }
     case Triple::ppc: {
       static const char *const Table[] =  {
         "PPC_RELOC_VANILLA",

llvm/lib/Support/ARMAttributeParser.cpp

 
 Error ARMAttributeParser::ABI_align_needed(AttrType tag) {
   static const char *strings[] = {"Not Permitted", "8-byte alignment",
                                   "4-byte alignment", "Reserved"};
 
   uint64_t value = de.getULEB128(cursor);
 
   std::string description;
-  if (value < array_lengthof(strings))
+  if (value < std::size(strings))
     description = strings[value];
   else if (value <= 12)
     description = "8-byte alignment, " + utostr(1ULL << value) +
                   "-byte extended alignment";
   else
     description = "Invalid";
 
   printAttribute(tag, value, description);
   return Error::success();
 }
 
 Error ARMAttributeParser::ABI_align_preserved(AttrType tag) {
   static const char *strings[] = {"Not Required", "8-byte data alignment",
                                   "8-byte data and code alignment", "Reserved"};
 
   uint64_t value = de.getULEB128(cursor);
 
   std::string description;
-  if (value < array_lengthof(strings))
+  if (value < std::size(strings))
     description = std::string(strings[value]);
   else if (value <= 12)
     description = std::string("8-byte stack alignment, ") +
                   utostr(1ULL << value) + std::string("-byte data alignment");
   else
     description = "Invalid";
 
   printAttribute(tag, value, description);

llvm/lib/Support/CrashRecoveryContext.cpp

 // This implementation does not attempt to chain signal handlers in any
 // reliable fashion -- if we get a signal outside of a crash recovery context we
 // simply disable crash recovery and raise the signal again.
 
 #include <signal.h>
 
 static const int Signals[] =
     { SIGABRT, SIGBUS, SIGFPE, SIGILL, SIGSEGV, SIGTRAP };
-static const unsigned NumSignals = array_lengthof(Signals);
+static const unsigned NumSignals = std::size(Signals);
 static struct sigaction PrevActions[NumSignals];
 
 static void CrashRecoverySignalHandler(int Signal) {
   // Lookup the current thread local recovery object.
   const CrashRecoveryContextImpl *CRCI = getCurrentContext().get();
 
   if (!CRCI) {
     // We didn't find a crash recovery context -- this means either we got a

llvm/lib/Support/NativeFormatting.cpp

bool Prefix = (Style == HexPrintStyle::PrefixLower ||
                  Style == HexPrintStyle::PrefixUpper);
   bool Upper =
       (Style == HexPrintStyle::Upper || Style == HexPrintStyle::PrefixUpper);
   unsigned PrefixChars = Prefix ? 2 : 0;
   unsigned NumChars =
       std::max(static_cast<unsigned>(W), std::max(1u, Nibbles) + PrefixChars);
 
   char NumberBuffer[kMaxWidth];
-  ::memset(NumberBuffer, '0', llvm::array_lengthof(NumberBuffer));
+  ::memset(NumberBuffer, '0', std::size(NumberBuffer));
   if (Prefix)
     NumberBuffer[1] = 'x';
   char *EndPtr = NumberBuffer + NumChars;
   char *CurPtr = EndPtr;
   while (N) {
     unsigned char x = static_cast<unsigned char>(N) % 16;
     *--CurPtr = hexdigit(x, !Upper);
     N /= 16;

llvm/lib/Support/Triple.cpp

std::string Triple::normalize(StringRef Str) {
   Found[0] = Arch != UnknownArch;
   Found[1] = Vendor != UnknownVendor;
   Found[2] = OS != UnknownOS;
   Found[3] = Environment != UnknownEnvironment;
 
   // If they are not there already, permute the components into their canonical
   // positions by seeing if they parse as a valid architecture, and if so moving
   // the component to the architecture position etc.
-  for (unsigned Pos = 0; Pos != array_lengthof(Found); ++Pos) {
+  for (unsigned Pos = 0; Pos != std::size(Found); ++Pos) {
     if (Found[Pos])
       continue; // Already in the canonical position.
 
     for (unsigned Idx = 0; Idx != Components.size(); ++Idx) {
       // Do not reparse any components that already matched.
-      if (Idx < array_lengthof(Found) && Found[Idx])
+      if (Idx < std::size(Found) && Found[Idx])
         continue;
 
       // Does this component parse as valid for the target position?
       bool Valid = false;
       StringRef Comp = Components[Idx];
       switch (Pos) {
       default: llvm_unreachable("unexpected component type!");
       case 0:
for (unsigned Idx = 0; Idx != Components.size(); ++Idx) {
         // example, a-b-i386 -> i386-a-b when moving i386 to the front.
         StringRef CurrentComponent(""); // The empty component.
         // Replace the component we are moving with an empty component.
         std::swap(CurrentComponent, Components[Idx]);
         // Insert the component being moved at Pos, displacing any existing
         // components to the right.
         for (unsigned i = Pos; !CurrentComponent.empty(); ++i) {
           // Skip over any fixed components.
-          while (i < array_lengthof(Found) && Found[i])
+          while (i < std::size(Found) && Found[i])
             ++i;
           // Place the component at the new position, getting the component
           // that was at this position - it will be moved right.
           std::swap(CurrentComponent, Components[i]);
         }
       } else if (Pos > Idx) {
         // Push right by inserting empty components until the component at Idx
         // reaches the target position Pos.  For example, pc-a -> -pc-a when
         // moving pc to the second position.
         do {
           // Insert one empty component at Idx.
           StringRef CurrentComponent(""); // The empty component.
           for (unsigned i = Idx; i < Components.size();) {
             // Place the component at the new position, getting the component
             // that was at this position - it will be moved right.
             std::swap(CurrentComponent, Components[i]);
             // If it was placed on top of an empty component then we are done.
             if (CurrentComponent.empty())
               break;
             // Advance to the next component, skipping any fixed components.
-            while (++i < array_lengthof(Found) && Found[i])
+            while (++i < std::size(Found) && Found[i])
               ;
           }
           // The last component was pushed off the end - append it.
           if (!CurrentComponent.empty())
             Components.push_back(CurrentComponent);
 
           // Advance Idx to the component's new position.
-          while (++Idx < array_lengthof(Found) && Found[Idx])
+          while (++Idx < std::size(Found) && Found[Idx])
             ;
         } while (Idx < Pos); // Add more until the final position is reached.
       }
       assert(Pos < Components.size() && Components[Pos] == Comp &&
              "Component moved wrong!");
       Found[Pos] = true;
       break;
     }

llvm/lib/Support/Unix/Signals.inc

 static const int InfoSigs[] = {
   SIGUSR1
 #ifdef SIGINFO
   , SIGINFO
 #endif
 };
 
 static const size_t NumSigs =
-    array_lengthof(IntSigs) + array_lengthof(KillSigs) +
-    array_lengthof(InfoSigs) + 1 /* SIGPIPE */;
+    std::size(IntSigs) + std::size(KillSigs) +
+    std::size(InfoSigs) + 1 /* SIGPIPE */;
 
 
 static std::atomic<unsigned> NumRegisteredSignals = ATOMIC_VAR_INIT(0);
 static struct {
   struct sigaction SA;
   int SigNo;
 } RegisteredSignalInfo[NumSigs];
 
static void RegisterHandlers() { // Not signal-safe.
 
   // Create an alternate stack for signal handling. This is necessary for us to
   // be able to reliably handle signals due to stack overflow.
   CreateSigAltStack();
 
   enum class SignalKind { IsKill, IsInfo };
   auto registerHandler = [&](int Signal, SignalKind Kind) {
     unsigned Index = NumRegisteredSignals.load();
-    assert(Index < array_lengthof(RegisteredSignalInfo) &&
+    assert(Index < std::size(RegisteredSignalInfo) &&
            "Out of space for signal handlers!");
 
     struct sigaction NewHandler;
 
     switch (Kind) {
     case SignalKind::IsKill:
       NewHandler.sa_handler = SignalHandler;
       NewHandler.sa_flags = SA_NODEFER | SA_RESETHAND | SA_ONSTACK;

 // doesn't demangle symbols.
 void llvm::sys::PrintStackTrace(raw_ostream &OS, int Depth) {
 #if ENABLE_BACKTRACES
   static void *StackTrace[256];
   int depth = 0;
 #if defined(HAVE_BACKTRACE)
   // Use backtrace() to output a backtrace on Linux systems with glibc.
   if (!depth)
-    depth = backtrace(StackTrace, static_cast<int>(array_lengthof(StackTrace)));
+    depth = backtrace(StackTrace, static_cast<int>(std::size(StackTrace)));
 #endif
 #if defined(HAVE__UNWIND_BACKTRACE)
   // Try _Unwind_Backtrace() if backtrace() failed.
   if (!depth)
     depth = unwindBacktrace(StackTrace,
-                        static_cast<int>(array_lengthof(StackTrace)));
+                        static_cast<int>(std::size(StackTrace)));
 #endif
   if (!depth)
     return;
   // If "Depth" is not provided by the caller, use the return value of
   // backtrace() for printing a symbolized stack trace.
   if (!Depth)
     Depth = depth;
   if (printSymbolizedStackTrace(Argv0, StackTrace, Depth, OS))

llvm/lib/Support/Windows/Path.inc

static const char *const sReservedNames[] = { "nul", "con", "prn", "aux",
                                                 "lpt8", "lpt9" };
 
   // First, check to see if this is a device namespace, which always
   // starts with \\.\, since device namespaces are not legal file paths.
   if (path.startswith("\\\\.\\"))
     return true;
 
   // Then compare against the list of ancient reserved names.
-  for (size_t i = 0; i < array_lengthof(sReservedNames); ++i) {
+  for (size_t i = 0; i < std::size(sReservedNames); ++i) {
     if (path.equals_insensitive(sReservedNames[i]))
       return true;
   }
 
   // The path isn't what we consider reserved.
   return false;
 }
 

llvm/lib/Support/Windows/Signals.inc

static bool printStackTraceWithLLVMSymbolizer(llvm::raw_ostream &OS,
   static void *StackTrace[256];
   size_t Depth = 0;
   while (fStackWalk64(NativeMachineType, hProcess, hThread, &StackFrame,
                       &Context, 0, fSymFunctionTableAccess64,
                       fSymGetModuleBase64, 0)) {
     if (StackFrame.AddrFrame.Offset == 0)
       break;
     StackTrace[Depth++] = (void *)(uintptr_t)StackFrame.AddrPC.Offset;
-    if (Depth >= array_lengthof(StackTrace))
+    if (Depth >= std::size(StackTrace))
       break;
   }
 
   return printSymbolizedStackTrace(Argv0, &StackTrace[0], Depth, OS);
 }
 
 namespace {
 struct FindModuleData {

llvm/lib/Support/X86TargetParser.cpp

public:
   }
 
   constexpr bool operator[](unsigned I) const {
     uint32_t Mask = uint32_t(1) << (I % 32);
     return (Bits[I / 32] & Mask) != 0;
   }
 
   constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
-    for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
+    for (unsigned I = 0, E = std::size(Bits); I != E; ++I) {
       // GCC <6.2 crashes if this is written in a single statement.
       uint32_t NewBits = Bits[I] & RHS.Bits[I];
       Bits[I] = NewBits;
     }
     return *this;
   }
 
   constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
-    for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
+    for (unsigned I = 0, E = std::size(Bits); I != E; ++I) {
       // GCC <6.2 crashes if this is written in a single statement.
       uint32_t NewBits = Bits[I] | RHS.Bits[I];
       Bits[I] = NewBits;
     }
     return *this;
   }
 
   // gcc 5.3 miscompiles this if we try to write this using operator&=.
   constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
     FeatureBitset Result;
-    for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
+    for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
       Result.Bits[I] = Bits[I] & RHS.Bits[I];
     return Result;
   }
 
   // gcc 5.3 miscompiles this if we try to write this using operator&=.
   constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
     FeatureBitset Result;
-    for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
+    for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
       Result.Bits[I] = Bits[I] | RHS.Bits[I];
     return Result;
   }
 
   constexpr FeatureBitset operator~() const {
     FeatureBitset Result;
-    for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
+    for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
       Result.Bits[I] = ~Bits[I];
     return Result;
   }
 
   constexpr bool operator!=(const FeatureBitset &RHS) const {
-    for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
+    for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
       if (Bits[I] != RHS.Bits[I])
         return true;
     return false;
   }
 };
 
 struct ProcInfo {
   StringLiteral Name;
#ifndef NDEBUG
   // Check that priorities are set properly in the .def file. We expect that
   // "compat" features are assigned non-duplicate consecutive priorities
   // starting from zero (0, 1, ..., num_features - 1).
 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY,
   unsigned Priorities[] = {
 #include "llvm/Support/X86TargetParser.def"
       std::numeric_limits<unsigned>::max() // Need to consume last comma.
   };
-  std::array<unsigned, array_lengthof(Priorities) - 1> HelperList;
+  std::array<unsigned, std::size(Priorities) - 1> HelperList;
   std::iota(HelperList.begin(), HelperList.end(), 0);
   assert(std::is_permutation(HelperList.begin(), HelperList.end(),
                              std::begin(Priorities),
                              std::prev(std::end(Priorities))) &&
          "Priorities don't form consecutive range!");
 #endif
 
   switch (Feat) {
 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
   case X86::FEATURE_##ENUM:                                                    \
     return PRIORITY;
 #include "llvm/Support/X86TargetParser.def"
   default:
     llvm_unreachable("No Feature Priority for non-CPUSupports Features");
   }
 }

llvm/lib/Support/raw_ostream.cpp

 static raw_ostream &write_padding(raw_ostream &OS, unsigned NumChars) {
   static const char Chars[] = {C, C, C, C, C, C, C, C, C, C, C, C, C, C, C, C,
                                C, C, C, C, C, C, C, C, C, C, C, C, C, C, C, C,
                                C, C, C, C, C, C, C, C, C, C, C, C, C, C, C, C,
                                C, C, C, C, C, C, C, C, C, C, C, C, C, C, C, C,
                                C, C, C, C, C, C, C, C, C, C, C, C, C, C, C, C};
 
   // Usually the indentation is small, handle it with a fastpath.
-  if (NumChars < array_lengthof(Chars))
+  if (NumChars < std::size(Chars))
     return OS.write(Chars, NumChars);
 
   while (NumChars) {
-    unsigned NumToWrite = std::min(NumChars,
-                                   (unsigned)array_lengthof(Chars)-1);
+    unsigned NumToWrite = std::min(NumChars, (unsigned)std::size(Chars) - 1);
     OS.write(Chars, NumToWrite);
     NumChars -= NumToWrite;
   }
   return OS;
 }
 
 /// indent - Insert 'NumSpaces' spaces.
 raw_ostream &raw_ostream::indent(unsigned NumSpaces) {

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
   auto PtrVT = getPointerTy(DAG.getDataLayout());
   bool IsWin64 = Subtarget->isCallingConvWin64(MF.getFunction().getCallingConv());
 
   SmallVector<SDValue, 8> MemOps;
 
   static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
                                           AArch64::X3, AArch64::X4, AArch64::X5,
                                           AArch64::X6, AArch64::X7 };
-  unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
+  unsigned NumGPRArgRegs = std::size(GPRArgRegs);
   if (Subtarget->isWindowsArm64EC()) {
     // In the ARM64EC ABI, only x0-x3 are used to pass arguments to varargs
     // functions.
     NumGPRArgRegs = 4;
   }
   unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
 
   unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
   }
   FuncInfo->setVarArgsGPRIndex(GPRIdx);
   FuncInfo->setVarArgsGPRSize(GPRSaveSize);
 
   if (Subtarget->hasFPARMv8() && !IsWin64) {
     static const MCPhysReg FPRArgRegs[] = {
         AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
         AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
-    static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
+    static const unsigned NumFPRArgRegs = std::size(FPRArgRegs);
     unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
 
     unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
     int FPRIdx = 0;
     if (FPRSaveSize != 0) {
       FPRIdx = MFI.CreateStackObject(FPRSaveSize, Align(16), false);
 
       SDValue FIN = DAG.getFrameIndex(FPRIdx, PtrVT);

llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp

 const UnmangledFuncInfo UnmangledFuncInfo::Table[] = {
     {"__read_pipe_2", 4},
     {"__read_pipe_4", 6},
     {"__write_pipe_2", 4},
     {"__write_pipe_4", 6},
 };
 
 const unsigned UnmangledFuncInfo::TableSize =
-    array_lengthof(UnmangledFuncInfo::Table);
+    std::size(UnmangledFuncInfo::Table);
 
 static AMDGPULibFunc::Param getRetType(AMDGPULibFunc::EFuncId id,
                                        const AMDGPULibFunc::Param (&Leads)[2]) {
   AMDGPULibFunc::Param Res = Leads[0];
   // TBD - This switch may require to be extended for other intrinsics
   switch (id) {
   case AMDGPULibFunc::EI_SINCOS:
     Res.PtrKind = AMDGPULibFunc::BYVALUE;
static AMDGPULibFunc::ENamePrefix parseNamePrefix(StringRef& mangledName) {
 
   if (Pfx != AMDGPULibFunc::NOPFX)
     mangledName = P.second;
 
   return Pfx;
 }
 
 StringMap<int> ManglingRule::buildManglingRulesMap() {
-  StringMap<int> Map(array_lengthof(manglingRules));
+  StringMap<int> Map(std::size(manglingRules));
   int Id = 0;
   for (auto Rule : manglingRules)
     Map.insert({Rule.Name, Id++});
   return Map;
 }
 
 bool AMDGPUMangledLibFunc::parseUnmangledName(StringRef FullName) {
   static const StringMap<int> manglingRulesMap =

llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp

 unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) {
   static const uint16_t SubRegFromChannelTable[] = {
     R600::sub0, R600::sub1, R600::sub2, R600::sub3,
     R600::sub4, R600::sub5, R600::sub6, R600::sub7,
     R600::sub8, R600::sub9, R600::sub10, R600::sub11,
     R600::sub12, R600::sub13, R600::sub14, R600::sub15
   };
 
-  assert(Channel < array_lengthof(SubRegFromChannelTable));
+  assert(Channel < std::size(SubRegFromChannelTable));
   return SubRegFromChannelTable[Channel];
 }
 
 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
 
   const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
   const R600InstrInfo *TII = ST.getInstrInfo();

llvm/lib/Target/ARC/ARCISelLowering.cpp

SDValue ARCTargetLowering::LowerCallArguments(
 
   // 1b. CopyFromReg vararg registers.
   if (IsVarArg) {
     // Argument registers
     static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3,
                                         ARC::R4, ARC::R5, ARC::R6, ARC::R7};
     auto *AFI = MF.getInfo<ARCFunctionInfo>();
     unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);
-    if (FirstVAReg < array_lengthof(ArgRegs)) {
+    if (FirstVAReg < std::size(ArgRegs)) {
       int Offset = 0;
       // Save remaining registers, storing higher register numbers at a higher
       // address
-      // There are (array_lengthof(ArgRegs) - FirstVAReg) registers which
+      // There are (std::size(ArgRegs) - FirstVAReg) registers which
       // need to be saved.
-      int VarFI =
-          MFI.CreateFixedObject((array_lengthof(ArgRegs) - FirstVAReg) * 4,
+      int VarFI = MFI.CreateFixedObject((std::size(ArgRegs) - FirstVAReg) * 4,
                                         CCInfo.getNextStackOffset(), true);
       AFI->setVarArgsFrameIndex(VarFI);
       SDValue FIN = DAG.getFrameIndex(VarFI, MVT::i32);
-      for (unsigned i = FirstVAReg; i < array_lengthof(ArgRegs); i++) {
+      for (unsigned i = FirstVAReg; i < std::size(ArgRegs); i++) {
         // Move argument from phys reg -> virt reg
         unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass);
         RegInfo.addLiveIn(ArgRegs[i], VReg);
         SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
         CFRegNode.push_back(Val.getValue(Val->getNumValues() - 1));
         SDValue VAObj = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
                                     DAG.getConstant(Offset, dl, MVT::i32));
         // Move argument from virt reg -> stack

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

static const ARM_MLxEntry ARM_MLxTable[] = {
   { ARM::VMLSslfd,    ARM::VMULslfd,    ARM::VSUBfd,     false,  true  },
   { ARM::VMLAslfq,    ARM::VMULslfq,    ARM::VADDfq,     false,  true  },
   { ARM::VMLSslfq,    ARM::VMULslfq,    ARM::VSUBfq,     false,  true  },
 };
 
 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
   : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
     Subtarget(STI) {
-  for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
+  for (unsigned i = 0, e = std::size(ARM_MLxTable); i != e; ++i) {
     if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
       llvm_unreachable("Duplicated entries?");
     MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
     MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
   }
 }
 
 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl

llvm/lib/Target/ARM/ARMFrameLowering.cpp

bool ARMFrameLowering::assignCalleeSavedSpillSlots(
   }
 
   return false;
 }
 
 const TargetFrameLowering::SpillSlot *
 ARMFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {
   static const SpillSlot FixedSpillOffsets[] = {{ARM::FPCXTNS, -4}};
-  NumEntries = array_lengthof(FixedSpillOffsets);
+  NumEntries = std::size(FixedSpillOffsets);
   return FixedSpillOffsets;
 }
 
 MachineBasicBlock::iterator ARMFrameLowering::eliminateCallFramePseudoInstr(
     MachineFunction &MF, MachineBasicBlock &MBB,
     MachineBasicBlock::iterator I) const {
   const ARMBaseInstrInfo &TII =
       *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());

llvm/lib/Target/ARM/ARMISelLowering.cpp

for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 
     CCInfo.nextInRegsParam();
   }
   CCInfo.rewindByValRegsInfo();
 
   int lastInsIndex = -1;
   if (isVarArg && MFI.hasVAStart()) {
     unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
-    if (RegIdx != array_lengthof(GPRArgRegs))
+    if (RegIdx != std::size(GPRArgRegs))
       ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
   }
 
   unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
   AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
   auto PtrVT = getPointerTy(DAG.getDataLayout());
 
   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {

llvm/lib/Target/ARM/Thumb2SizeReduction.cpp

 } // end anonymous namespace
 
 INITIALIZE_PASS(Thumb2SizeReduce, DEBUG_TYPE, THUMB2_SIZE_REDUCE_NAME, false,
                 false)
 
 Thumb2SizeReduce::Thumb2SizeReduce(std::function<bool(const Function &)> Ftor)
     : MachineFunctionPass(ID), PredicateFtor(std::move(Ftor)) {
   OptimizeSize = MinimizeSize = false;
-  for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
+  for (unsigned i = 0, e = std::size(ReduceTable); i != e; ++i) {
     unsigned FromOpc = ReduceTable[i].WideOpc;
     if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
       llvm_unreachable("Duplicated entries?");
   }
 }
 
 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
   for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)

llvm/lib/Target/AVR/AVRISelLowering.cpp

static const MCPhysReg RegList16AVR[] = {
     AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
     AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
     AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
     AVR::R11R10, AVR::R10R9,  AVR::R9R8};
 static const MCPhysReg RegList16Tiny[] = {AVR::R26R25, AVR::R25R24,
                                           AVR::R24R23, AVR::R23R22,
                                           AVR::R22R21, AVR::R21R20};
 
-static_assert(array_lengthof(RegList8AVR) == array_lengthof(RegList16AVR),
+static_assert(std::size(RegList8AVR) == std::size(RegList16AVR),
               "8-bit and 16-bit register arrays must be of equal length");
-static_assert(array_lengthof(RegList8Tiny) == array_lengthof(RegList16Tiny),
+static_assert(std::size(RegList8Tiny) == std::size(RegList16Tiny),
               "8-bit and 16-bit register arrays must be of equal length");
 
 /// Analyze incoming and outgoing function arguments. We need custom C++ code
 /// to handle special constraints in the ABI.
 /// In addition, all pieces of a certain argument have to be passed either
 /// using registers or the stack but never mixing both.
 template <typename ArgT>
 static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI,
                              const Function *F, const DataLayout *TD,
                              const SmallVectorImpl<ArgT> &Args,
                              SmallVectorImpl<CCValAssign> &ArgLocs,
                              CCState &CCInfo, bool Tiny) {
   // Choose the proper register list for argument passing according to the ABI.
   ArrayRef<MCPhysReg> RegList8;
   ArrayRef<MCPhysReg> RegList16;
   if (Tiny) {
-    RegList8 = makeArrayRef(RegList8Tiny, array_lengthof(RegList8Tiny));
-    RegList16 = makeArrayRef(RegList16Tiny, array_lengthof(RegList16Tiny));
+    RegList8 = makeArrayRef(RegList8Tiny, std::size(RegList8Tiny));
+    RegList16 = makeArrayRef(RegList16Tiny, std::size(RegList16Tiny));
   } else {
-    RegList8 = makeArrayRef(RegList8AVR, array_lengthof(RegList8AVR));
-    RegList16 = makeArrayRef(RegList16AVR, array_lengthof(RegList16AVR));
+    RegList8 = makeArrayRef(RegList8AVR, std::size(RegList8AVR));
+    RegList16 = makeArrayRef(RegList16AVR, std::size(RegList16AVR));
   }
 
   unsigned NumArgs = Args.size();
   // This is the index of the last used register, in RegList*.
   // -1 means R26 (R26 is never actually used in CC).
   int RegLastIdx = -1;
   // Once a value is passed to the stack it will always be used
   bool UseStack = false;
static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args,
   // CanLowerReturn() guarantees this assertion.
   assert(TotalBytes <= 8 &&
          "return values greater than 8 bytes cannot be lowered");
 
   // Choose the proper register list for argument passing according to the ABI.
   ArrayRef<MCPhysReg> RegList8;
   ArrayRef<MCPhysReg> RegList16;
   if (Tiny) {
-    RegList8 = makeArrayRef(RegList8Tiny, array_lengthof(RegList8Tiny));
-    RegList16 = makeArrayRef(RegList16Tiny, array_lengthof(RegList16Tiny));
+    RegList8 = makeArrayRef(RegList8Tiny, std::size(RegList8Tiny));
+    RegList16 = makeArrayRef(RegList16Tiny, std::size(RegList16Tiny));
   } else {
-    RegList8 = makeArrayRef(RegList8AVR, array_lengthof(RegList8AVR));
-    RegList16 = makeArrayRef(RegList16AVR, array_lengthof(RegList16AVR));
+    RegList8 = makeArrayRef(RegList8AVR, std::size(RegList8AVR));
+    RegList16 = makeArrayRef(RegList16AVR, std::size(RegList16AVR));
   }
 
   // GCC-ABI says that the size is rounded up to the next even number,
   // but actually once it is more than 4 it will always round up to 8.
   if (TotalBytes > 4) {
     TotalBytes = 8;
   } else {
     TotalBytes = alignTo(TotalBytes, 2);

llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp

static const MCPhysReg CtrlRegDecoderTable[] = {
     /*  8 */  USR,        PC,         UGP,        GP,
     /* 12 */  CS0,        CS1,        UPCYCLELO,  UPCYCLEHI,
     /* 16 */  FRAMELIMIT, FRAMEKEY,   PKTCOUNTLO, PKTCOUNTHI,
     /* 20 */  0,          0,          0,          0,
     /* 24 */  0,          0,          0,          0,
     /* 28 */  0,          0,          UTIMERLO,   UTIMERHI
   };
 
-  if (RegNo >= array_lengthof(CtrlRegDecoderTable))
+  if (RegNo >= std::size(CtrlRegDecoderTable))
     return MCDisassembler::Fail;
 
   static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
   if (CtrlRegDecoderTable[RegNo] == NoRegister)
     return MCDisassembler::Fail;
 
   unsigned Register = CtrlRegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
static const MCPhysReg CtrlReg64DecoderTable[] = {
     /*  8 */  C9_8,       0,          C11_10,     0,
     /* 12 */  CS,         0,          UPCYCLE,    0,
     /* 16 */  C17_16,     0,          PKTCOUNT,   0,
     /* 20 */  0,          0,          0,          0,
     /* 24 */  0,          0,          0,          0,
     /* 28 */  0,          0,          UTIMER,     0
   };
 
-  if (RegNo >= array_lengthof(CtrlReg64DecoderTable))
+  if (RegNo >= std::size(CtrlReg64DecoderTable))
     return MCDisassembler::Fail;
 
   static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
   if (CtrlReg64DecoderTable[RegNo] == NoRegister)
     return MCDisassembler::Fail;
 
   unsigned Register = CtrlReg64DecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
static const MCPhysReg GuestRegDecoderTable[] = {
     /*  8 */ G8,        G9,         G10,        G11,
     /* 12 */ G12,       G13,        G14,        G15,
     /* 16 */ GPMUCNT4,  GPMUCNT5,   GPMUCNT6,   GPMUCNT7,
     /* 20 */ G20,       G21,        G22,        G23,
     /* 24 */ GPCYCLELO, GPCYCLEHI,  GPMUCNT0,   GPMUCNT1,
     /* 28 */ GPMUCNT2,  GPMUCNT3,   G30,        G31
   };
 
-  if (RegNo >= array_lengthof(GuestRegDecoderTable))
+  if (RegNo >= std::size(GuestRegDecoderTable))
     return MCDisassembler::Fail;
   if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
     return MCDisassembler::Fail;
 
   unsigned Register = GuestRegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
static const MCPhysReg GuestReg64DecoderTable[] = {
     /*  8 */ G9_8,      0,          G11_10,     0,
     /* 12 */ G13_12,    0,          G15_14,     0,
     /* 16 */ G17_16,    0,          G19_18,     0,
     /* 20 */ G21_20,    0,          G23_22,     0,
     /* 24 */ G25_24,    0,          G27_26,     0,
     /* 28 */ G29_28,    0,          G31_30,     0
   };
 
-  if (RegNo >= array_lengthof(GuestReg64DecoderTable))
+  if (RegNo >= std::size(GuestReg64DecoderTable))
     return MCDisassembler::Fail;
   if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
     return MCDisassembler::Fail;
 
   unsigned Register = GuestReg64DecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }

llvm/lib/Target/Hexagon/HexagonFrameLowering.h

const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries)
     static const SpillSlot Offsets[] = {
       { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 },
       { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 },
       { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 },
       { Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 },
       { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 },
       { Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 }
     };
-    NumEntries = array_lengthof(Offsets);
+    NumEntries = std::size(Offsets);
     return Offsets;
   }
 
   bool assignCalleeSavedSpillSlots(MachineFunction &MF,
       const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
       const override;
 
   bool needsAligna(const MachineFunction &MF) const;

llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp

bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI,
   if (MI->getDesc().isCall())
     return !TII->doesNotReturn(*MI);
 
   // Check if the instruction defines a hardware loop register.
   using namespace Hexagon;
 
   static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 };
   static const unsigned Regs1[]  = { LC1, SA1 };
-  auto CheckRegs = IsInnerHWLoop ? makeArrayRef(Regs01, array_lengthof(Regs01))
-                                 : makeArrayRef(Regs1, array_lengthof(Regs1));
+  auto CheckRegs = IsInnerHWLoop ? makeArrayRef(Regs01, std::size(Regs01))
+                                 : makeArrayRef(Regs1, std::size(Regs1));
   for (unsigned R : CheckRegs)
     if (MI->modifiesRegister(R, TRI))
       return true;
 
   return false;
 }
 
 /// Return true if the loop contains an instruction that inhibits

llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp

bool HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(LoadSDNode *N) {
   // is the location from which LD (or N) is loading.
   if (C->getNumOperands() < 4 || Loc.getNode() != C->getOperand(3).getNode())
     return false;
 
   if (MachineSDNode *L = LoadInstrForLoadIntrinsic(C)) {
     SDNode *S = StoreInstrForLoadIntrinsic(L, C);
     SDValue F[] = { SDValue(N,0), SDValue(N,1), SDValue(C,0), SDValue(C,1) };
     SDValue T[] = { SDValue(L,0), SDValue(S,0), SDValue(L,1), SDValue(S,0) };
-    ReplaceUses(F, T, array_lengthof(T));
+    ReplaceUses(F, T, std::size(T));
     // This transformation will leave the intrinsic dead. If it remains in
     // the DAG, the selection code will see it again, but without the load,
     // and it will generate a store that is normally required for it.
     CurDAG->RemoveDeadNode(C);
     return true;
   }
   return false;
 }

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

 
 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
                        CCValAssign::LocInfo &LocInfo,
                        ISD::ArgFlagsTy &ArgFlags, CCState &State) {
   static const MCPhysReg ArgRegs[] = {
     Hexagon::R0, Hexagon::R1, Hexagon::R2,
     Hexagon::R3, Hexagon::R4, Hexagon::R5
   };
-  const unsigned NumArgRegs = array_lengthof(ArgRegs);
+  const unsigned NumArgRegs = std::size(ArgRegs);
   unsigned RegNum = State.getFirstUnallocated(ArgRegs);
 
   // RegNum is an index into ArgRegs: skip a register if RegNum is odd.
   if (RegNum != NumArgRegs && RegNum % 2 == 1)
     State.AllocateReg(ArgRegs[RegNum]);
 
   // Always return false here, as this function only makes sure that the first
   // unallocated register has an even register number and does not actually

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp

if (VarKind == MCSymbolRefExpr::VK_None) {
         FixupKind = Hexagon::fixup_Hexagon_27_REG;
       } else {
         // Look for GP-relative fixups.
         unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
         static const Hexagon::Fixups GPRelFixups[] = {
           Hexagon::fixup_Hexagon_GPREL16_0, Hexagon::fixup_Hexagon_GPREL16_1,
           Hexagon::fixup_Hexagon_GPREL16_2, Hexagon::fixup_Hexagon_GPREL16_3
         };
-        assert(Shift < array_lengthof(GPRelFixups));
+        assert(Shift < std::size(GPRelFixups));
         auto UsesGP = [] (const MCInstrDesc &D) {
           for (const MCPhysReg *U = D.getImplicitUses(); U && *U; ++U)
             if (*U == Hexagon::GP)
               return true;
           return false;
         };
         if (UsesGP(MCID))
           FixupKind = GPRelFixups[Shift];

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

case LoongArchABI::ABI_LP64F:
     break;
   case LoongArchABI::ABI_ILP32D:
   case LoongArchABI::ABI_LP64D:
     UseGPRForFloat = !IsFixed;
     break;
   }
 
   // FPR32 and FPR64 alias each other.
-  if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s))
+  if (State.getFirstUnallocated(ArgFPR32s) == std::size(ArgFPR32s))
     UseGPRForFloat = true;
 
   if (UseGPRForFloat && ValVT == MVT::f32) {
     LocVT = GRLenVT;
     LocInfo = CCValAssign::BCvt;
   } else if (UseGPRForFloat && GRLen == 64 && ValVT == MVT::f64) {
     LocVT = MVT::i64;
     LocInfo = CCValAssign::BCvt;
   } else if (UseGPRForFloat && GRLen == 32 && ValVT == MVT::f64) {
     // TODO: Handle passing f64 on LA32 with D feature.
     report_fatal_error("Passing f64 with GPR on LA32 is undefined");
   }
 
   // If this is a variadic argument, the LoongArch calling convention requires
   // that it is assigned an 'even' or 'aligned' register if it has (2*GRLen)/8
   // byte alignment. An aligned register should be used regardless of whether
   // the original argument was split during legalisation or not. The argument
   // will not be passed by registers if the original type is larger than
   // 2*GRLen, so the register alignment rule does not apply.
   unsigned TwoGRLenInBytes = (2 * GRLen) / 8;
   if (!IsFixed && ArgFlags.getNonZeroOrigAlign() == TwoGRLenInBytes &&
       DL.getTypeAllocSize(OrigTy) == TwoGRLenInBytes) {
     unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
     // Skip 'odd' register if necessary.
-    if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1)
+    if (RegIdx != std::size(ArgGPRs) && RegIdx % 2 == 1)
       State.AllocateReg(ArgGPRs);
   }
 
   SmallVectorImpl<CCValAssign> &PendingLocs = State.getPendingLocs();
   SmallVectorImpl<ISD::ArgFlagsTy> &PendingArgFlags =
       State.getPendingArgFlags();
 
   assert(PendingLocs.size() == PendingArgFlags.size() &&

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp

const static MCFixupKindInfo Infos[] = {
       {"fixup_loongarch_abs64_hi12", 10, 12, 0},
       {"fixup_loongarch_tls_le_hi20", 5, 20, 0},
       {"fixup_loongarch_tls_le_lo12", 10, 12, 0},
       {"fixup_loongarch_tls_le64_lo20", 5, 20, 0},
       {"fixup_loongarch_tls_le64_hi12", 10, 12, 0},
       // TODO: Add more fixup kinds.
   };
 
-  static_assert((array_lengthof(Infos)) == LoongArch::NumTargetFixupKinds,
+  static_assert((std::size(Infos)) == LoongArch::NumTargetFixupKinds,
                 "Not all fixup kinds added to Infos array");
 
   // Fixup kinds from .reloc directive are like R_LARCH_NONE. They
   // do not require any extra processing.
   if (Kind >= FirstLiteralRelocationKind)
     return MCAsmBackend::getFixupKindInfo(FK_NONE);
 
   if (Kind < FirstTargetFixupKind)

llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp

const static MCFixupKindInfo Infos[MSP430::NumTargetFixupKinds] = {
       {"fixup_16_pcrel",      0, 16, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_16_byte",       0, 16, 0},
       {"fixup_16_pcrel_byte", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_2x_pcrel",      0, 10, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_rl_pcrel",      0, 16, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_8",             0,  8, 0},
       {"fixup_sym_diff",      0, 32, 0},
     };
-    static_assert((array_lengthof(Infos)) == MSP430::NumTargetFixupKinds,
+    static_assert((std::size(Infos)) == MSP430::NumTargetFixupKinds,
                   "Not all fixup kinds added to Infos array");
-  
     if (Kind < FirstTargetFixupKind)
       return MCAsmBackend::getFixupKindInfo(Kind);
   
     return Infos[Kind - FirstTargetFixupKind];
   }
 
   bool writeNopData(raw_ostream &OS, uint64_t Count,
                     const MCSubtargetInfo *STI) const override;

llvm/lib/Target/MSP430/MSP430ISelLowering.cpp

 /// have to be passed either using registers or the stack but never mixing both.
 template<typename ArgT>
 static void AnalyzeArguments(CCState &State,
                              SmallVectorImpl<CCValAssign> &ArgLocs,
                              const SmallVectorImpl<ArgT> &Args) {
   static const MCPhysReg CRegList[] = {
     MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
   };
-  static const unsigned CNbRegs = array_lengthof(CRegList);
+  static const unsigned CNbRegs = std::size(CRegList);
   static const MCPhysReg BuiltinRegList[] = {
     MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
     MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
   };
-  static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList);
+  static const unsigned BuiltinNbRegs = std::size(BuiltinRegList);
 
   ArrayRef<MCPhysReg> RegList;
   unsigned NbRegs;
 
   bool Builtin = (State.getCallingConv() == CallingConv::MSP430_BUILTIN);
   if (Builtin) {
     RegList = BuiltinRegList;
     NbRegs = BuiltinNbRegs;

llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

const static MCFixupKindInfo LittleEndianInfos[] = {
     { "fixup_MICROMIPS_GOTTPREL",        0,     16,   0 },
     { "fixup_MICROMIPS_TLS_TPREL_HI16",  0,     16,   0 },
     { "fixup_MICROMIPS_TLS_TPREL_LO16",  0,     16,   0 },
     { "fixup_Mips_SUB",                  0,     64,   0 },
     { "fixup_MICROMIPS_SUB",             0,     64,   0 },
     { "fixup_Mips_JALR",                 0,     32,   0 },
     { "fixup_MICROMIPS_JALR",            0,     32,   0 }
   };
-  static_assert(array_lengthof(LittleEndianInfos) == Mips::NumTargetFixupKinds,
+  static_assert(std::size(LittleEndianInfos) == Mips::NumTargetFixupKinds,
                 "Not all MIPS little endian fixup kinds added!");
 
   const static MCFixupKindInfo BigEndianInfos[] = {
     // This table *must* be in same the order of fixup_* kinds in
     // MipsFixupKinds.h.
     //
     // name                    offset  bits  flags
     { "fixup_Mips_16",          16,     16,   0 },
const static MCFixupKindInfo BigEndianInfos[] = {
     { "fixup_MICROMIPS_GOTTPREL",        16,     16,   0 },
     { "fixup_MICROMIPS_TLS_TPREL_HI16",  16,     16,   0 },
     { "fixup_MICROMIPS_TLS_TPREL_LO16",  16,     16,   0 },
     { "fixup_Mips_SUB",                   0,     64,   0 },
     { "fixup_MICROMIPS_SUB",              0,     64,   0 },
     { "fixup_Mips_JALR",                  0,     32,   0 },
     { "fixup_MICROMIPS_JALR",             0,     32,   0 }
   };
-  static_assert(array_lengthof(BigEndianInfos) == Mips::NumTargetFixupKinds,
+  static_assert(std::size(BigEndianInfos) == Mips::NumTargetFixupKinds,
                 "Not all MIPS big endian fixup kinds added!");
 
   if (Kind >= FirstLiteralRelocationKind)
     return MCAsmBackend::getFixupKindInfo(FK_NONE);
   if (Kind < FirstTargetFixupKind)
     return MCAsmBackend::getFixupKindInfo(Kind);
 
   assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&

llvm/lib/Target/Mips/Mips16ISelLowering.cpp

 bool Mips16TargetLowering::isEligibleForTailCallOptimization(
     const CCState &CCInfo, unsigned NextStackOffset,
     const MipsFunctionInfo &FI) const {
   // No tail call optimization for mips16.
   return false;
 }
 
 void Mips16TargetLowering::setMips16HardFloatLibCalls() {
-  for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) {
+  for (unsigned I = 0; I != std::size(HardFloatLibCalls); ++I) {
     assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) &&
            "Array not sorted!");
     if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL)
       setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name);
   }
 }
 
 //

llvm/lib/Target/PowerPC/PPCCallingConv.cpp

static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
                                               MVT &LocVT,
                                               CCValAssign::LocInfo &LocInfo,
                                               ISD::ArgFlagsTy &ArgFlags,
                                               CCState &State) {
   static const MCPhysReg ArgRegs[] = {
     PPC::R3, PPC::R4, PPC::R5, PPC::R6,
     PPC::R7, PPC::R8, PPC::R9, PPC::R10,
   };
-  const unsigned NumArgRegs = array_lengthof(ArgRegs);
+  const unsigned NumArgRegs = std::size(ArgRegs);
 
   unsigned RegNum = State.getFirstUnallocated(ArgRegs);
 
   // Skip one register if the first unallocated register has an even register
   // number and there are still argument registers available which have not been
   // allocated yet. RegNum is actually an index into ArgRegs, which means we
   // need to skip a register if RegNum is odd.
   if (RegNum != NumArgRegs && RegNum % 2 == 1) {
     State.AllocateReg(ArgRegs[RegNum]);
   }
 
   // Always return false here, as this function only makes sure that the first
   // unallocated register has an odd register number and does not actually
   // allocate a register for the current argument.
   return false;
 }
 
 static bool CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(
     unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo,
     ISD::ArgFlagsTy &ArgFlags, CCState &State) {
   static const MCPhysReg ArgRegs[] = {
     PPC::R3, PPC::R4, PPC::R5, PPC::R6,
     PPC::R7, PPC::R8, PPC::R9, PPC::R10,
   };
-  const unsigned NumArgRegs = array_lengthof(ArgRegs);
+  const unsigned NumArgRegs = std::size(ArgRegs);
 
   unsigned RegNum = State.getFirstUnallocated(ArgRegs);
   int RegsLeft = NumArgRegs - RegNum;
 
   // Skip if there is not enough registers left for long double type (4 gpr regs
   // in soft float mode) and put long double argument on the stack.
   if (RegNum != NumArgRegs && RegsLeft < 4) {
     for (int i = 0; i < RegsLeft; i++) {
static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
                                                 CCValAssign::LocInfo &LocInfo,
                                                 ISD::ArgFlagsTy &ArgFlags,
                                                 CCState &State) {
   static const MCPhysReg ArgRegs[] = {
     PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
     PPC::F8
   };
 
-  const unsigned NumArgRegs = array_lengthof(ArgRegs);
+  const unsigned NumArgRegs = std::size(ArgRegs);
 
   unsigned RegNum = State.getFirstUnallocated(ArgRegs);
 
   // If there is only one Floating-point register left we need to put both f64
   // values of a split ppc_fp128 value on the stack.
   if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
     State.AllocateReg(ArgRegs[RegNum]);
   }

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

static const SpillSlot AIXOffsets32[] = {CALLEE_SAVED_FPRS,
                                            // Add AIX's extra CSR.
                                            {PPC::R13, -76},
                                            CALLEE_SAVED_VRS};
 
   static const SpillSlot AIXOffsets64[] = {
       CALLEE_SAVED_FPRS, CALLEE_SAVED_GPRS64, CALLEE_SAVED_VRS};
 
   if (Subtarget.is64BitELFABI()) {
-    NumEntries = array_lengthof(ELFOffsets64);
+    NumEntries = std::size(ELFOffsets64);
     return ELFOffsets64;
   }
 
   if (Subtarget.is32BitELFABI()) {
-    NumEntries = array_lengthof(ELFOffsets32);
+    NumEntries = std::size(ELFOffsets32);
     return ELFOffsets32;
   }
 
   assert(Subtarget.isAIXABI() && "Unexpected ABI.");
 
   if (Subtarget.isPPC64()) {
-    NumEntries = array_lengthof(AIXOffsets64);
+    NumEntries = std::size(AIXOffsets64);
     return AIXOffsets64;
   }
 
-  NumEntries = array_lengthof(AIXOffsets32);
+  NumEntries = std::size(AIXOffsets32);
   return AIXOffsets32;
 }
 
 static bool spillsCR(const MachineFunction &MF) {
   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
   return FuncInfo->isCRSpilled();
 }
 

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
 
   // If the function takes variable number of arguments, make a frame index for
   // the start of the first vararg value... for expansion of llvm.va_start.
   if (isVarArg) {
     static const MCPhysReg GPArgRegs[] = {
       PPC::R3, PPC::R4, PPC::R5, PPC::R6,
       PPC::R7, PPC::R8, PPC::R9, PPC::R10,
     };
-    const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
+    const unsigned NumGPArgRegs = std::size(GPArgRegs);
 
     static const MCPhysReg FPArgRegs[] = {
       PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
       PPC::F8
     };
-    unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
+    unsigned NumFPArgRegs = std::size(FPArgRegs);
 
     if (useSoftFloat() || hasSPE())
        NumFPArgRegs = 0;
 
     FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
     FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
 
     // Make room for NumGPArgRegs and NumFPArgRegs.
static const MCPhysReg GPR[] = {
     PPC::X3, PPC::X4, PPC::X5, PPC::X6,
     PPC::X7, PPC::X8, PPC::X9, PPC::X10,
   };
   static const MCPhysReg VR[] = {
     PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
     PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
   };
 
-  const unsigned Num_GPR_Regs = array_lengthof(GPR);
+  const unsigned Num_GPR_Regs = std::size(GPR);
   const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
-  const unsigned Num_VR_Regs  = array_lengthof(VR);
+  const unsigned Num_VR_Regs = std::size(VR);
 
   // Do a first pass over the arguments to determine whether the ABI
   // guarantees that our caller has allocated the parameter save area
   // on its stack frame.  In the ELFv1 ABI, this is always the case;
   // in the ELFv2 ABI, it is true if this is a vararg function or if
   // any parameter is located in a stack slot.
 
   bool HasParameterArea = !isELFv2ABI || isVarArg;
static const MCPhysReg GPR[] = {
     PPC::X3, PPC::X4, PPC::X5, PPC::X6,
     PPC::X7, PPC::X8, PPC::X9, PPC::X10,
   };
   static const MCPhysReg VR[] = {
     PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
     PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
   };
 
-  const unsigned NumGPRs = array_lengthof(GPR);
+  const unsigned NumGPRs = std::size(GPR);
   const unsigned NumFPRs = 13;
-  const unsigned NumVRs = array_lengthof(VR);
+  const unsigned NumVRs = std::size(VR);
   const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
 
   unsigned NumBytes = LinkageSize;
   unsigned AvailableFPRs = NumFPRs;
   unsigned AvailableVRs = NumVRs;
 
   for (const ISD::OutputArg& Param : Outs) {
     if (Param.Flags.isNest()) continue;
static const MCPhysReg GPR[] = {
     PPC::X3, PPC::X4, PPC::X5, PPC::X6,
     PPC::X7, PPC::X8, PPC::X9, PPC::X10,
   };
   static const MCPhysReg VR[] = {
     PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
     PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
   };
 
-  const unsigned NumGPRs = array_lengthof(GPR);
+  const unsigned NumGPRs = std::size(GPR);
   const unsigned NumFPRs = useSoftFloat() ? 0 : 13;
-  const unsigned NumVRs  = array_lengthof(VR);
+  const unsigned NumVRs = std::size(VR);
 
   // On ELFv2, we can avoid allocating the parameter area if all the arguments
   // can be passed to the callee in registers.
   // For the fast calling convention, there is another check below.
   // Note: We should keep consistent with LowerFormalArguments_64SVR4()
   bool HasParameterArea = !isELFv2ABI || CFlags.IsVarArg || IsFastCall;
   if (!HasParameterArea) {
     unsigned ParamAreaSize = NumGPRs * PtrByteSize;
FuncInfo->setVarArgsFrameIndex(
         MFI.CreateFixedObject(PtrByteSize, CCInfo.getNextStackOffset(), true));
     SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
 
     static const MCPhysReg GPR_32[] = {PPC::R3, PPC::R4, PPC::R5, PPC::R6,
                                        PPC::R7, PPC::R8, PPC::R9, PPC::R10};
 
     static const MCPhysReg GPR_64[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6,
                                        PPC::X7, PPC::X8, PPC::X9, PPC::X10};
-    const unsigned NumGPArgRegs = array_lengthof(IsPPC64 ? GPR_64 : GPR_32);
+    const unsigned NumGPArgRegs = std::size(IsPPC64 ? GPR_64 : GPR_32);
 
     // The fixed integer arguments of a variadic function are stored to the
     // VarArgsFrameIndex on the stack so that they may be loaded by
     // dereferencing the result of va_next.
     for (unsigned GPRIndex =
              (CCInfo.getNextStackOffset() - LinkageSize) / PtrByteSize;
          GPRIndex < NumGPArgRegs; ++GPRIndex) {
 
SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
   }
 
   // Check to see if this is a wide variety of vsplti*, binop self cases.
   static const signed char SplatCsts[] = {
     -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
     -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
   };
 
-  for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
+  for (unsigned idx = 0; idx < std::size(SplatCsts); ++idx) {
     // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
     // cases which are ambiguous (e.g. formation of 0x8000_0000).  'vsplti -1'
     int i = SplatCsts[idx];
 
     // Figure out what shift amount will be used by altivec if shifted by i in
     // this splat size.
     unsigned TypeShiftAmt = i & (SplatBitSize-1);
 

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

static const uint16_t FMAOpIdxInfo[][6] = {
     {PPC::XVMADDADP, PPC::XVADDDP, PPC::XVMULDP, 1, 2, PPC::XVSUBDP},
     {PPC::XVMADDASP, PPC::XVADDSP, PPC::XVMULSP, 1, 2, PPC::XVSUBSP},
     {PPC::FMADD, PPC::FADD, PPC::FMUL, 3, 1, PPC::FSUB},
     {PPC::FMADDS, PPC::FADDS, PPC::FMULS, 3, 1, PPC::FSUBS}};
 
 // Check if an opcode is a FMA instruction. If it is, return the index in array
 // FMAOpIdxInfo. Otherwise, return -1.
 int16_t PPCInstrInfo::getFMAOpIdxInfo(unsigned Opcode) const {
-  for (unsigned I = 0; I < array_lengthof(FMAOpIdxInfo); I++)
+  for (unsigned I = 0; I < std::size(FMAOpIdxInfo); I++)
     if (FMAOpIdxInfo[I][InfoArrayIdxFMAInst] == Opcode)
       return I;
   return -1;
 }
 
 // On PowerPC target, we have two kinds of patterns related to FMA:
 // 1: Improve ILP.
 // Try to reassociate FMA chains like below:
bool PPCInstrInfo::ClobbersPredicate(MachineInstr &MI,
   // predicate-defining instructions.
 
   const TargetRegisterClass *RCs[] =
     { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
       &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
 
   bool Found = false;
   for (const MachineOperand &MO : MI.operands()) {
-    for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
+    for (unsigned c = 0; c < std::size(RCs) && !Found; ++c) {
       const TargetRegisterClass *RC = RCs[c];
       if (MO.isReg()) {
         if (MO.isDef() && RC->contains(MO.getReg())) {
           Pred.push_back(MO);
           Found = true;
         }
       } else if (MO.isRegMask()) {
         for (MCPhysReg R : *RC)

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

const static MCFixupKindInfo Infos[] = {
       {"fixup_riscv_sub_32", 0, 32, 0},
 
       {"fixup_riscv_add_64", 0, 64, 0},
       {"fixup_riscv_sub_64", 0, 64, 0},
 
       {"fixup_riscv_set_6b", 2, 6, 0},
       {"fixup_riscv_sub_6b", 2, 6, 0},
   };
-  static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds,
+  static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds,
                 "Not all fixup kinds added to Infos array");
 
   // Fixup kinds from .reloc directive are like R_RISCV_NONE. They
   // do not require any extra processing.
   if (Kind >= FirstLiteralRelocationKind)
     return MCAsmBackend::getFixupKindInfo(FK_NONE);
 
   if (Kind < FirstTargetFixupKind)

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
   case RISCVABI::ABI_ILP32D:
   case RISCVABI::ABI_LP64D:
     UseGPRForF16_F32 = !IsFixed;
     UseGPRForF64 = !IsFixed;
     break;
   }
 
   // FPR16, FPR32, and FPR64 alias each other.
-  if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s)) {
+  if (State.getFirstUnallocated(ArgFPR32s) == std::size(ArgFPR32s)) {
     UseGPRForF16_F32 = true;
     UseGPRForF64 = true;
   }
 
   // From this point on, rely on UseGPRForF16_F32, UseGPRForF64 and
   // similar local variables rather than directly checking against the target
   // ABI.
 
static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
   // legalisation or not. The argument will not be passed by registers if the
   // original type is larger than 2*XLEN, so the register alignment rule does
   // not apply.
   unsigned TwoXLenInBytes = (2 * XLen) / 8;
   if (!IsFixed && ArgFlags.getNonZeroOrigAlign() == TwoXLenInBytes &&
       DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) {
     unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
     // Skip 'odd' register if necessary.
-    if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1)
+    if (RegIdx != std::size(ArgGPRs) && RegIdx % 2 == 1)
       State.AllocateReg(ArgGPRs);
   }
 
   SmallVectorImpl<CCValAssign> &PendingLocs = State.getPendingLocs();
   SmallVectorImpl<ISD::ArgFlagsTy> &PendingArgFlags =
       State.getPendingArgFlags();
 
   assert(PendingLocs.size() == PendingArgFlags.size() &&

llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

if (RegNo > 31)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
                                               const MCDisassembler *Decoder) {
-  if (RegNo >= array_lengthof(PRRegDecoderTable))
+  if (RegNo >= std::size(PRRegDecoderTable))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
                                                const MCDisassembler *Decoder) {

llvm/lib/Target/VE/VEFrameLowering.h

public:
   const SpillSlot *
   getCalleeSavedSpillSlots(unsigned &NumEntries) const override {
     static const SpillSlot Offsets[] = {
         {VE::SX17, 40},  {VE::SX18, 48},  {VE::SX19, 56},  {VE::SX20, 64},
         {VE::SX21, 72},  {VE::SX22, 80},  {VE::SX23, 88},  {VE::SX24, 96},
         {VE::SX25, 104}, {VE::SX26, 112}, {VE::SX27, 120}, {VE::SX28, 128},
         {VE::SX29, 136}, {VE::SX30, 144}, {VE::SX31, 152}, {VE::SX32, 160},
         {VE::SX33, 168}};
-    NumEntries = array_lengthof(Offsets);
+    NumEntries = std::size(Offsets);
     return Offsets;
   }
 
 protected:
   const VESubtarget &STI;
 
 private:
   // Returns true if MF is a leaf procedure.

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

else if (X86Op->isMem()) {
       MemOp = X86Op;
       assert(MemOp->Mem.Size == 0 && "Memory size always 0 under ATT syntax");
       // Have we found an unqualified memory operand,
       // break. IA allows only one memory operand.
       break;
     }
   }
 
-  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) {
+  for (unsigned I = 0, E = std::size(Match); I != E; ++I) {
     Tmp.back() = Suffixes[I];
     if (MemOp && HasVectorReg)
       MemOp->Mem.Size = MemSize[I];
     Match[I] = Match_MnemonicFail;
     if (MemOp || !HasVectorReg) {
       Match[I] =
           MatchInstruction(Operands, Inst, ErrorInfoIgnore, MissingFeatures,
                            MatchingInlineAsm, isParsingIntelSyntax());
bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
 
   // Otherwise, the match failed, try to produce a decent error message.
 
   // If we had multiple suffix matches, then identify this as an ambiguous
   // match.
   if (NumSuccessfulMatches > 1) {
     char MatchChars[4];
     unsigned NumMatches = 0;
-    for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I)
+    for (unsigned I = 0, E = std::size(Match); I != E; ++I)
       if (Match[I] == Match_Success)
         MatchChars[NumMatches++] = Suffixes[I];
 
     SmallString<126> Msg;
     raw_svector_ostream OS(Msg);
     OS << "ambiguous instructions require an explicit suffix (could be ";
     for (unsigned i = 0; i != NumMatches; ++i) {
       if (i != 0)

llvm/lib/Target/X86/X86ISelLowering.cpp

static int canLowerByDroppingElements(ArrayRef<int> Mask, bool MatchEven,
 
   for (int i = 0, e = Mask.size(); i < e; ++i) {
     // Ignore undef lanes, we'll optimistically collapse them to the pattern we
     // want.
     if (Mask[i] < 0)
       continue;
 
     bool IsAnyViable = false;
-    for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
+    for (unsigned j = 0; j != std::size(ViableForN); ++j)
       if (ViableForN[j]) {
         uint64_t N = j + 1;
 
         // The shuffle mask must be equal to (i * 2^N) % M.
         if ((uint64_t)(Mask[i] - Offset) == (((uint64_t)i << N) & ModMask))
           IsAnyViable = true;
         else
           ViableForN[j] = false;
       }
     // Early exit if we exhaust the possible powers of two.
     if (!IsAnyViable)
       break;
   }
 
-  for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
+  for (unsigned j = 0; j != std::size(ViableForN); ++j)
     if (ViableForN[j])
       return j + 1;
 
   // Return 0 as there is no viable power of two.
   return 0;
 }
 
 // X86 has dedicated pack instructions that can handle specific truncation

llvm/lib/Target/XCore/XCoreISelLowering.cpp

#endif
   // 1b. CopyFromReg vararg registers.
   if (isVarArg) {
     // Argument registers
     static const MCPhysReg ArgRegs[] = {
       XCore::R0, XCore::R1, XCore::R2, XCore::R3
     };
     XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
     unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);
-    if (FirstVAReg < array_lengthof(ArgRegs)) {
+    if (FirstVAReg < std::size(ArgRegs)) {
       int offset = 0;
       // Save remaining registers, storing higher register numbers at a higher
       // address
-      for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
+      for (int i = std::size(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
         // Create a stack slot
         int FI = MFI.CreateFixedObject(4, offset, true);
         if (i == (int)FirstVAReg) {
           XFI->setVarArgsFrameIndex(FI);
         }
         offset -= StackSlotSize;
         SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
         // Move argument from phys reg -> virt reg

llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp

if (StartIdx + 1 != SimpVect.size()) {
       // Pop all addends being folded and push the resulting folded addend.
       SimpVect.resize(StartIdx);
       if (!R.isZero()) {
         SimpVect.push_back(&R);
       }
     }
   }
 
-  assert((NextTmpIdx <= array_lengthof(TmpResult) + 1) &&
-         "out-of-bound access");
+  assert((NextTmpIdx <= std::size(TmpResult) + 1) && "out-of-bound access");
 
   Value *Result;
   if (!SimpVect.empty())
     Result = createNaryFAdd(SimpVect, InstrQuota);
   else {
     // The addition is folded to 0.0.
     Result = ConstantFP::get(Instr->getType(), 0.0);
   }

llvm/lib/Transforms/Utils/MetaRenamer.cpp

int rand() {
     return (unsigned int)(next / 65536) % 32768;
   }
 };
 
 struct Renamer {
   Renamer(unsigned int seed) { prng.srand(seed); }
 
   const char *newName() {
-    return metaNames[prng.rand() % array_lengthof(metaNames)];
+    return metaNames[prng.rand() % std::size(metaNames)];
   }
 
   PRNG prng;
 };
 
 static void
 parseExcludedPrefixes(StringRef PrefixesStr,
                       SmallVectorImpl<StringRef> &ExcludedPrefixes) {

llvm/tools/llvm-objdump/COFFDump.cpp

static const char *DirName[COFF::NUM_DATA_DIRECTORIES + 1] = {
       "Load Configuration Directory",
       "Bound Import Directory",
       "Import Address Table Directory",
       "Delay Import Directory",
       "CLR Runtime Header",
       "Reserved",
   };
   outs() << "\nThe Data Directory\n";
-  for (uint32_t I = 0; I != array_lengthof(DirName); ++I) {
+  for (uint32_t I = 0; I != std::size(DirName); ++I) {
     uint32_t Addr = 0, Size = 0;
     if (const data_directory *Data = Obj.getDataDirectory(I)) {
       Addr = Data->RelativeVirtualAddress;
       Size = Data->Size;
     }
     outs() << format("Entry %x ", I) << formatAddr(Addr)
            << format(" %08x %s\n", uint32_t(Size), DirName[I]);
   }

llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp

 
 void Decoder::decodeOpcodes(ArrayRef<uint8_t> Opcodes, unsigned Offset,
                             bool Prologue) {
   assert((!Prologue || Offset == 0) && "prologue should always use offset 0");
   const RingEntry* DecodeRing = isAArch64 ? Ring64 : Ring;
   bool Terminated = false;
   for (unsigned OI = Offset, OE = Opcodes.size(); !Terminated && OI < OE; ) {
     for (unsigned DI = 0;; ++DI) {
-      if ((isAArch64 && (DI >= array_lengthof(Ring64))) ||
-          (!isAArch64 && (DI >= array_lengthof(Ring)))) {
+      if ((isAArch64 && (DI >= std::size(Ring64))) ||
+          (!isAArch64 && (DI >= std::size(Ring)))) {
         SW.startLine() << format("0x%02x                ; Bad opcode!\n",
                                  Opcodes.data()[OI]);
         ++OI;
         break;
       }
 
       if ((Opcodes[OI] & DecodeRing[DI].Mask) == DecodeRing[DI].Value) {
         if (OI + DecodeRing[DI].Length > OE) {

llvm/tools/llvm-readobj/ELFDumper.cpp

template <typename ELFT> static GNUAbiTag getGNUAbiTag(ArrayRef<uint8_t> Desc) {
 
   if (Words.size() < 4)
     return {"", "", /*IsValid=*/false};
 
   static const char *OSNames[] = {
       "Linux", "Hurd", "Solaris", "FreeBSD", "NetBSD", "Syllable", "NaCl",
   };
   StringRef OSName = "Unknown";
-  if (Words[0] < array_lengthof(OSNames))
+  if (Words[0] < std::size(OSNames))
     OSName = OSNames[Words[0]];
   uint32_t Major = Words[1], Minor = Words[2], Patch = Words[3];
   std::string str;
   raw_string_ostream ABI(str);
   ABI << Major << "." << Minor << "." << Patch;
   return {std::string(OSName), ABI.str(), /*IsValid=*/true};
 }
 

llvm/unittests/ADT/APFloatTest.cpp

uint64_t NaNPayloads[] = {
       0xDEADBEEF,
       uint64_t(-2),
       uint64_t(1) << PayloadBits,       // overflow bit
       uint64_t(1) << (PayloadBits - 1), // signaling bit
       uint64_t(1) << (PayloadBits - 2)  // highest possible bit
   };
 
   // Convert payload integer to decimal string representation.
-  std::string NaNPayloadDecStrings[array_lengthof(NaNPayloads)];
-  for (size_t I = 0; I < array_lengthof(NaNPayloads); ++I)
+  std::string NaNPayloadDecStrings[std::size(NaNPayloads)];
+  for (size_t I = 0; I < std::size(NaNPayloads); ++I)
     NaNPayloadDecStrings[I] = utostr(NaNPayloads[I]);
 
   // Convert payload integer to hexadecimal string representation.
-  std::string NaNPayloadHexStrings[array_lengthof(NaNPayloads)];
-  for (size_t I = 0; I < array_lengthof(NaNPayloads); ++I)
+  std::string NaNPayloadHexStrings[std::size(NaNPayloads)];
+  for (size_t I = 0; I < std::size(NaNPayloads); ++I)
     NaNPayloadHexStrings[I] = "0x" + utohexstr(NaNPayloads[I]);
 
   // Fix payloads to expected result.
   for (uint64_t &Payload : NaNPayloads)
     Payload &= PayloadMask;
 
   // Signaling NaN must have a non-zero payload. In case a zero payload is
   // requested, a default arbitrary payload is set instead. Save this payload
   // for testing.
   const uint64_t SNaNDefaultPayload =
       APFloat::getSNaN(Sem).bitcastToAPInt().getZExtValue() & PayloadMask;
 
   // Negative sign prefix (or none - for positive).
   const char Signs[] = {0, '-'};
 
   // "Signaling" prefix (or none - for "Quiet").
   const char NaNTypes[] = {0, 's', 'S'};
 
   const StringRef NaNStrings[] = {"nan", "NaN"};
   for (StringRef NaNStr : NaNStrings)
     for (char TypeChar : NaNTypes) {
       bool Signaling = (TypeChar == 's' || TypeChar == 'S');
 
-      for (size_t J = 0; J < array_lengthof(NaNPayloads); ++J) {
+      for (size_t J = 0; J < std::size(NaNPayloads); ++J) {
         uint64_t Payload = (Signaling && !NaNPayloads[J]) ? SNaNDefaultPayload
                                                           : NaNPayloads[J];
         std::string &PayloadDec = NaNPayloadDecStrings[J];
         std::string &PayloadHex = NaNPayloadHexStrings[J];
 
         for (char SignChar : Signs) {
           bool Negative = (SignChar == '-');
 
struct {
     { MSmallestNormalized, PLargestValue, "0x1.fffffep+127", APFloat::opInexact, APFloat::fcNormal },
     { MSmallestNormalized, MLargestValue, "-0x1.fffffep+127", APFloat::opInexact, APFloat::fcNormal },
     { MSmallestNormalized, PSmallestValue, "-0x1.fffffcp-127", APFloat::opOK, APFloat::fcNormal },
     { MSmallestNormalized, MSmallestValue, "-0x1.000002p-126", APFloat::opOK, APFloat::fcNormal },
     { MSmallestNormalized, PSmallestNormalized, "0x0p+0", APFloat::opOK, APFloat::fcZero },
     { MSmallestNormalized, MSmallestNormalized, "-0x1p-125", APFloat::opOK, APFloat::fcNormal }
   };
 
-  for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) {
+  for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) {
     APFloat x(SpecialCaseTests[i].x);
     APFloat y(SpecialCaseTests[i].y);
     APFloat::opStatus status = x.add(y, APFloat::rmNearestTiesToEven);
 
     APFloat result(APFloat::IEEEsingle(), SpecialCaseTests[i].result);
 
     EXPECT_TRUE(result.bitwiseIsEqual(x));
     EXPECT_EQ(SpecialCaseTests[i].status, (int)status);
struct {
     { MSmallestNormalized, PLargestValue, "-0x1.fffffep+127", APFloat::opInexact, APFloat::fcNormal },
     { MSmallestNormalized, MLargestValue, "0x1.fffffep+127", APFloat::opInexact, APFloat::fcNormal },
     { MSmallestNormalized, PSmallestValue, "-0x1.000002p-126", APFloat::opOK, APFloat::fcNormal },
     { MSmallestNormalized, MSmallestValue, "-0x1.fffffcp-127", APFloat::opOK, APFloat::fcNormal },
     { MSmallestNormalized, PSmallestNormalized, "-0x1p-125", APFloat::opOK, APFloat::fcNormal },
     { MSmallestNormalized, MSmallestNormalized, "0x0p+0", APFloat::opOK, APFloat::fcZero }
   };
 
-  for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) {
+  for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) {
     APFloat x(SpecialCaseTests[i].x);
     APFloat y(SpecialCaseTests[i].y);
     APFloat::opStatus status = x.subtract(y, APFloat::rmNearestTiesToEven);
 
     APFloat result(APFloat::IEEEsingle(), SpecialCaseTests[i].result);
 
     EXPECT_TRUE(result.bitwiseIsEqual(x));
     EXPECT_EQ(SpecialCaseTests[i].status, (int)status);
struct {
     {MinQuad, NMinQuad, "-0x0.0000000000000000000000000001p-16382",
      UnderflowStatus, APFloat::fcNormal, APFloat::rmTowardNegative},
     {MinQuad, NMinQuad, "-0", UnderflowStatus, APFloat::fcZero,
      APFloat::rmTowardZero},
     {MinQuad, NMinQuad, "-0", UnderflowStatus, APFloat::fcZero,
      APFloat::rmNearestTiesToAway},
   };
 
-  for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) {
+  for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) {
     APFloat x(SpecialCaseTests[i].x);
     APFloat y(SpecialCaseTests[i].y);
     APFloat::opStatus status = x.multiply(y, SpecialCaseTests[i].roundingMode);
 
     APFloat result(x.getSemantics(), SpecialCaseTests[i].result);
 
     EXPECT_TRUE(result.bitwiseIsEqual(x));
     EXPECT_EQ(SpecialCaseTests[i].status, (int)status);
struct {
     {NMinQuad, MaxQuad, "-0x0.0000000000000000000000000001p-16382",
      UnderflowStatus, APFloat::fcNormal, APFloat::rmTowardNegative},
     {NMinQuad, MaxQuad, "-0", UnderflowStatus, APFloat::fcZero,
      APFloat::rmTowardZero},
     {NMinQuad, MaxQuad, "-0", UnderflowStatus, APFloat::fcZero,
      APFloat::rmNearestTiesToAway},
   };
 
-  for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) {
+  for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) {
     APFloat x(SpecialCaseTests[i].x);
     APFloat y(SpecialCaseTests[i].y);
     APFloat::opStatus status = x.divide(y, SpecialCaseTests[i].roundingMode);
 
     APFloat result(x.getSemantics(), SpecialCaseTests[i].result);
 
     EXPECT_TRUE(result.bitwiseIsEqual(x));
     EXPECT_EQ(SpecialCaseTests[i].status, (int)status);
struct {
     { MVal6, PVal4, "-0x1p+0", APFloat::opOK, APFloat::fcNormal },
     { MVal6, MVal4, "-0x1p+0", APFloat::opOK, APFloat::fcNormal },
     { MVal6, PVal5, "0.5", APFloat::opOK, APFloat::fcNormal },
     { MVal6, MVal5, "0.5", APFloat::opOK, APFloat::fcNormal },
     { MVal6, PVal6, "-0x0p+0", APFloat::opOK, APFloat::fcZero },
     { MVal6, MVal6, "-0x0p+0", APFloat::opOK, APFloat::fcZero },
   };
 
-  for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) {
+  for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) {
     APFloat x(SpecialCaseTests[i].x);
     APFloat y(SpecialCaseTests[i].y);
     APFloat::opStatus status = x.remainder(y);
 
     APFloat result(x.getSemantics(), SpecialCaseTests[i].result);
 
     EXPECT_TRUE(result.bitwiseIsEqual(x));
     EXPECT_EQ(SpecialCaseTests[i].status, (int)status);

llvm/unittests/ADT/StringRefTest.cpp

struct SignedPair {
   };
 
 TEST(StringRefTest, getAsInteger) {
   uint8_t U8;
   uint16_t U16;
   uint32_t U32;
   uint64_t U64;
 
-  for (size_t i = 0; i < array_lengthof(Unsigned); ++i) {
+  for (size_t i = 0; i < std::size(Unsigned); ++i) {
     bool U8Success = StringRef(Unsigned[i].Str).getAsInteger(0, U8);
     if (static_cast<uint8_t>(Unsigned[i].Expected) == Unsigned[i].Expected) {
       ASSERT_FALSE(U8Success);
       EXPECT_EQ(U8, Unsigned[i].Expected);
     } else {
       ASSERT_TRUE(U8Success);
     }
     bool U16Success = StringRef(Unsigned[i].Str).getAsInteger(0, U16);
for (size_t i = 0; i < std::size(Unsigned); ++i) {
     EXPECT_EQ(U64, Unsigned[i].Expected);
   }
 
   int8_t S8;
   int16_t S16;
   int32_t S32;
   int64_t S64;
 
-  for (size_t i = 0; i < array_lengthof(Signed); ++i) {
+  for (size_t i = 0; i < std::size(Signed); ++i) {
     bool S8Success = StringRef(Signed[i].Str).getAsInteger(0, S8);
     if (static_cast<int8_t>(Signed[i].Expected) == Signed[i].Expected) {
       ASSERT_FALSE(S8Success);
       EXPECT_EQ(S8, Signed[i].Expected);
     } else {
       ASSERT_TRUE(S8Success);
     }
     bool S16Success = StringRef(Signed[i].Str).getAsInteger(0, S16);
static const char* BadStrings[] = {
   , "-123"                  // negative unsigned value
   , "0x"
   , "0b"
 };
 
 
 TEST(StringRefTest, getAsUnsignedIntegerBadStrings) {
   unsigned long long U64;
-  for (size_t i = 0; i < array_lengthof(BadStrings); ++i) {
+  for (size_t i = 0; i < std::size(BadStrings); ++i) {
     bool IsBadNumber = StringRef(BadStrings[i]).getAsInteger(0, U64);
     ASSERT_TRUE(IsBadNumber);
   }
 }
 
 struct ConsumeUnsignedPair {
   const char *Str;
   uint64_t Expected;
const char *Leftover;
     {"-0b101010-1", -42, "-1"}};
 
 TEST(StringRefTest, consumeIntegerUnsigned) {
   uint8_t U8;
   uint16_t U16;
   uint32_t U32;
   uint64_t U64;
 
-  for (size_t i = 0; i < array_lengthof(ConsumeUnsigned); ++i) {
+  for (size_t i = 0; i < std::size(ConsumeUnsigned); ++i) {
     StringRef Str = ConsumeUnsigned[i].Str;
     bool U8Success = Str.consumeInteger(0, U8);
     if (static_cast<uint8_t>(ConsumeUnsigned[i].Expected) ==
         ConsumeUnsigned[i].Expected) {
       ASSERT_FALSE(U8Success);
       EXPECT_EQ(U8, ConsumeUnsigned[i].Expected);
       EXPECT_EQ(Str, ConsumeUnsigned[i].Leftover);
     } else {

 }
 
 TEST(StringRefTest, consumeIntegerSigned) {
   int8_t S8;
   int16_t S16;
   int32_t S32;
   int64_t S64;
 
-  for (size_t i = 0; i < array_lengthof(ConsumeSigned); ++i) {
+  for (size_t i = 0; i < std::size(ConsumeSigned); ++i) {
     StringRef Str = ConsumeSigned[i].Str;
     bool S8Success = Str.consumeInteger(0, S8);
     if (static_cast<int8_t>(ConsumeSigned[i].Expected) ==
         ConsumeSigned[i].Expected) {
       ASSERT_FALSE(S8Success);
       EXPECT_EQ(S8, ConsumeSigned[i].Expected);
       EXPECT_EQ(Str, ConsumeSigned[i].Leftover);
     } else {

 static const char *join_input[] = { "a", "b", "c" };
 static const char join_result1[] = "a";
 static const char join_result2[] = "a:b:c";
 static const char join_result3[] = "a::b::c";
 
 TEST(StringRefTest, joinStrings) {
   std::vector<StringRef> v1;
   std::vector<std::string> v2;
-  for (size_t i = 0; i < array_lengthof(join_input); ++i) {
+  for (size_t i = 0; i < std::size(join_input); ++i) {
     v1.push_back(join_input[i]);
     v2.push_back(join_input[i]);
   }
 
   bool v1_join1 = join(v1.begin(), v1.begin() + 1, ":") == join_result1;
   EXPECT_TRUE(v1_join1);
   bool v1_join2 = join(v1.begin(), v1.end(), ":") == join_result2;
   EXPECT_TRUE(v1_join2);

llvm/unittests/ADT/TinyPtrVectorTest.cpp

protected:
 
   VectorT V;
   VectorT V2;
 
   ValueT TestValues[1024];
   std::vector<PtrT> TestPtrs;
 
   TinyPtrVectorTest() {
-    for (size_t i = 0, e = array_lengthof(TestValues); i != e; ++i)
+    for (size_t i = 0, e = std::size(TestValues); i != e; ++i)
       TestPtrs.push_back(PtrT(&TestValues[i]));
 
     std::shuffle(TestPtrs.begin(), TestPtrs.end(), std::mt19937{});
   }
 
   PtrT makePtr(ValueT *V) { return PtrT(V); }
 
   ArrayRef<PtrT> testArray(size_t N) {

llvm/unittests/ProfileData/CoverageMappingTest.cpp

for (size_t I = 0; I < N; ++I) {
     ASSERT_EQ(Input.Regions[I].startLoc(), Output.Regions[I].startLoc());
     ASSERT_EQ(Input.Regions[I].endLoc(), Output.Regions[I].endLoc());
     ASSERT_EQ(Input.Regions[I].Kind, Output.Regions[I].Kind);
   }
 }
 
 TEST_P(CoverageMappingTest, correct_deserialize_for_more_than_two_files) {
   const char *FileNames[] = {"bar", "baz", "foo"};
-  static const unsigned N = array_lengthof(FileNames);
+  static const unsigned N = std::size(FileNames);
 
   startFunction("func", 0x1234);
   for (unsigned I = 0; I < N; ++I)
     // Use LineStart to hold the index of the file name
     // in order to preserve that information during possible sorting of CMRs.
     addCMR(Counter::getCounter(0), FileNames[I], I, 1, I, 1);
 
   writeAndReadCoverageRegions();

 }
 
 static const auto Err = [](Error E) { FAIL(); };
 
 TEST_P(CoverageMappingTest, load_coverage_for_more_than_two_files) {
   ProfileWriter.addRecord({"func", 0x1234, {0}}, Err);
 
   const char *FileNames[] = {"bar", "baz", "foo"};
-  static const unsigned N = array_lengthof(FileNames);
+  static const unsigned N = std::size(FileNames);
 
   startFunction("func", 0x1234);
   for (unsigned I = 0; I < N; ++I)
     // Use LineStart to hold the index of the file name
     // in order to preserve that information during possible sorting of CMRs.
     addCMR(Counter::getCounter(0), FileNames[I], I, 1, I, 1);
 
   EXPECT_THAT_ERROR(loadCoverageMapping(), Succeeded());

llvm/unittests/Support/BinaryStreamTest.cpp

private:
   // So reads from the beginning actually come from the middle.
   MutableArrayRef<uint8_t> Data;
   uint32_t PartitionIndex = 0;
   endianness Endian;
   BumpPtrAllocator Allocator;
 };
 
 constexpr endianness Endians[] = {big, little, native};
-constexpr uint32_t NumEndians = llvm::array_lengthof(Endians);
+constexpr uint32_t NumEndians = std::size(Endians);
 constexpr uint32_t NumStreams = 2 * NumEndians;
 
 class BinaryStreamTest : public testing::Test {
 
 public:
   BinaryStreamTest() {}
 
   void SetUp() override {

llvm/unittests/Support/CSKYTargetParserTest.cpp

const char *ArchExt[][4] = {
       {"3e3r2", "no3e3r2", "+3e3r2", "-3e3r2"},
       {"3e3r3", "no3e3r3", "+3e3r3", "-3e3r3"},
       {"3e7", "no3e7", "+3e7", "-3e7"},
       {"mp1e2", "nomp1e2", "+mp1e2", "-mp1e2"},
       {"7e10", "no7e10", "+7e10", "-7e10"},
       {"10e60", "no10e60", "+10e60", "-10e60"},
   };
 
-  for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
+  for (unsigned i = 0; i < std::size(ArchExt); i++) {
     EXPECT_EQ(StringRef(ArchExt[i][2]), CSKY::getArchExtFeature(ArchExt[i][0]));
     EXPECT_EQ(StringRef(ArchExt[i][3]), CSKY::getArchExtFeature(ArchExt[i][1]));
   }
 }
 
 } // namespace

llvm/unittests/Support/CommandLineTest.cpp

TEST(CommandLineTest, AliasesWithArguments) {
   static const size_t ARGC = 3;
   const char *const Inputs[][ARGC] = {
     { "-tool", "-actual=x", "-extra" },
     { "-tool", "-actual", "x" },
     { "-tool", "-alias=x", "-extra" },
     { "-tool", "-alias", "x" }
   };
 
-  for (size_t i = 0, e = array_lengthof(Inputs); i < e; ++i) {
+  for (size_t i = 0, e = std::size(Inputs); i < e; ++i) {
     StackOption<std::string> Actual("actual");
     StackOption<bool> Extra("extra");
     StackOption<std::string> Input(cl::Positional);
 
     cl::alias Alias("alias", llvm::cl::aliasopt(Actual));
 
     cl::ParseCommandLineOptions(ARGC, Inputs[i]);
     EXPECT_EQ("x", Actual);
void testAliasRequired(int argc, const char *const *argv) {
   EXPECT_EQ(1, Option.getNumOccurrences());
 
   Alias.removeArgument();
 }
 
 TEST(CommandLineTest, AliasRequired) {
   const char *opts1[] = { "-tool", "-option=x" };
   const char *opts2[] = { "-tool", "-o", "x" };
-  testAliasRequired(array_lengthof(opts1), opts1);
-  testAliasRequired(array_lengthof(opts2), opts2);
+  testAliasRequired(std::size(opts1), opts1);
+  testAliasRequired(std::size(opts2), opts2);
 }
 
 TEST(CommandLineTest, HideUnrelatedOptions) {
   StackOption<int> TestOption1("hide-option-1");
   StackOption<int> TestOption2("hide-option-2", cl::cat(TestCategory));
 
   cl::HideUnrelatedOptions(TestCategory);
 
TEST(CommandLineTest, HideUnrelatedOptionsMulti) {
   ASSERT_TRUE(Map.count("help") == (size_t)0 ||
               cl::NotHidden == Map["help"]->getOptionHiddenFlag())
       << "Hid default option that should be visable.";
 }
 
 TEST(CommandLineTest, SetMultiValues) {
   StackOption<int> Option("option");
   const char *args[] = {"prog", "-option=1", "-option=2"};
-  EXPECT_TRUE(cl::ParseCommandLineOptions(array_lengthof(args), args,
-                                          StringRef(), &llvm::nulls()));
+  EXPECT_TRUE(cl::ParseCommandLineOptions(std::size(args), args, StringRef(),
+                                          &llvm::nulls()));
   EXPECT_EQ(Option, 2);
 }
 
 TEST(CommandLineTest, SetValueInSubcategories) {
   cl::ResetCommandLineParser();
 
   StackSubCommand SC1("sc1", "First subcommand");
   StackSubCommand SC2("sc2", "Second subcommand");
#endif
   SmallVector<const char *, 2> Argv = {"clang", "@eols.rsp"};
   BumpPtrAllocator A;
   StringSaver Saver(A);
   ASSERT_TRUE(cl::ExpandResponseFiles(Saver, cl::TokenizeWindowsCommandLine,
                                       Argv, true, true, false,
                                       /*CurrentDir=*/StringRef(TestRoot), FS));
   const char *Expected[] = {"clang", "-Xclang", "-Wno-whatever", nullptr,
                             "input.cpp"};
-  ASSERT_EQ(array_lengthof(Expected), Argv.size());
-  for (size_t I = 0, E = array_lengthof(Expected); I < E; ++I) {
+  ASSERT_EQ(std::size(Expected), Argv.size());
+  for (size_t I = 0, E = std::size(Expected); I < E; ++I) {
     if (Expected[I] == nullptr) {
       ASSERT_EQ(Argv[I], nullptr);
     } else {
       ASSERT_STREQ(Expected[I], Argv[I]);
     }
   }
 }
 

llvm/unittests/Support/FormatVariadicTest.cpp

const char *Header =
       "-7}|{9,10}|{10,16}|{11,17}|{12,6}|{13,4}";
   const char *Line =
       "{0,6}|{1,8:X}|{2,=10}|{3,=10:5}|{4,=13}|{5,7:3}|{6,7:P2}|{7,"
       "10:X8}|{8,-7:N}|{9,10:E4}|{10,16:N}|{11,17:D}|{12,6}|{13,"
       "4:X}";
 
   std::string S;
   llvm::raw_string_ostream Stream(S);
-  Stream << formatv(Intro, std::tuple_size<Tuple>::value,
-                    llvm::array_lengthof(Ts))
+  Stream << formatv(Intro, std::tuple_size<Tuple>::value, std::size(Ts))
          << "\n";
   Stream << formatv(Header, "Char", "HexInt", "Str", "Ref", "std::str",
                     "double", "float", "pointer", "comma", "exp", "bigint",
                     "bigint2", "limit", "byte")
          << "\n";
   for (auto &Item : Ts) {
     Stream << std::apply(format_tuple(Line), Item) << "\n";
   }

llvm/unittests/Support/TargetParserTest.cpp

const char *ArchExt[][4] = {{"crc", "nocrc", "+crc", "-crc"},
                               {"iwmmxt2", "noiwmmxt2", nullptr, nullptr},
                               {"maverick", "maverick", nullptr, nullptr},
                               {"xscale", "noxscale", nullptr, nullptr},
                               {"sb", "nosb", "+sb", "-sb"},
                               {"i8mm", "noi8mm", "+i8mm", "-i8mm"},
                               {"mve", "nomve", "+mve", "-mve"},
                               {"mve.fp", "nomve.fp", "+mve.fp", "-mve.fp"}};
 
-  for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
+  for (unsigned i = 0; i < std::size(ArchExt); i++) {
     EXPECT_EQ(StringRef(ArchExt[i][2]), ARM::getArchExtFeature(ArchExt[i][0]));
     EXPECT_EQ(StringRef(ArchExt[i][3]), ARM::getArchExtFeature(ArchExt[i][1]));
   }
 }
 
 static bool
 testArchExtDependency(const char *ArchExt,
                       const std::initializer_list<const char *> &Expected) {
TEST(TargetParserTest, ARMArchExtDependencies) {
   EXPECT_TRUE(testArchExtDependency("mve.fp", {"+mve.fp", "+mve", "+dsp"}));
   EXPECT_TRUE(testArchExtDependency("nodsp", {"-dsp", "-mve", "-mve.fp"}));
   EXPECT_TRUE(testArchExtDependency("nomve", {"-mve", "-mve.fp"}));
 }
 
 TEST(TargetParserTest, ARMparseHWDiv) {
   const char *hwdiv[] = {"thumb", "arm", "arm,thumb", "thumb,arm"};
 
-  for (unsigned i = 0; i < array_lengthof(hwdiv); i++)
+  for (unsigned i = 0; i < std::size(hwdiv); i++)
     EXPECT_NE(ARM::AEK_INVALID, ARM::parseHWDiv((StringRef)hwdiv[i]));
 }
 
 TEST(TargetParserTest, ARMparseArchEndianAndISA) {
   const char *Arch[] = {
       "v2",        "v2a",    "v3",    "v3m",    "v4",       "v4t",
       "v5",        "v5t",    "v5e",   "v5te",   "v5tej",    "v6",
       "v6j",       "v6k",    "v6hl",  "v6t2",   "v6kz",     "v6z",
       "v6zk",      "v6-m",   "v6m",   "v6sm",   "v6s-m",    "v7-a",
       "v7",        "v7a",    "v7ve",  "v7hl",   "v7l",      "v7-r",
       "v7r",       "v7-m",   "v7m",   "v7k",    "v7s",      "v7e-m",
       "v7em",      "v8-a",   "v8",    "v8a",    "v8l",      "v8.1-a",
       "v8.1a",     "v8.2-a", "v8.2a", "v8.3-a", "v8.3a",    "v8.4-a",
       "v8.4a",     "v8.5-a", "v8.5a", "v8.6-a", "v8.6a",    "v8.7-a",
       "v8.7a",     "v8.8-a", "v8.8a", "v8-r",   "v8m.base", "v8m.main",
       "v8.1m.main"};
 
-  for (unsigned i = 0; i < array_lengthof(Arch); i++) {
+  for (unsigned i = 0; i < std::size(Arch); i++) {
     std::string arm_1 = "armeb" + (std::string)(Arch[i]);
     std::string arm_2 = "arm" + (std::string)(Arch[i]) + "eb";
     std::string arm_3 = "arm" + (std::string)(Arch[i]);
     std::string thumb_1 = "thumbeb" + (std::string)(Arch[i]);
     std::string thumb_2 = "thumb" + (std::string)(Arch[i]) + "eb";
     std::string thumb_3 = "thumb" + (std::string)(Arch[i]);
 
     EXPECT_EQ(ARM::EndianKind::BIG, ARM::parseArchEndian(arm_1));
TEST(TargetParserTest, ARMparseArchEndianAndISA) {
   EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("aarch64_be"));
   EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("arm64"));
   EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("arm64_be"));
   EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("arm64_32"));
   EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("aarch64_32"));
 }
 
 TEST(TargetParserTest, ARMparseArchProfile) {
-  for (unsigned i = 0; i < array_lengthof(ARMArch); i++) {
+  for (unsigned i = 0; i < std::size(ARMArch); i++) {
     switch (ARM::parseArch(ARMArch[i])) {
     case ARM::ArchKind::ARMV6M:
     case ARM::ArchKind::ARMV7M:
     case ARM::ArchKind::ARMV7EM:
     case ARM::ArchKind::ARMV8MMainline:
     case ARM::ArchKind::ARMV8MBaseline:
     case ARM::ArchKind::ARMV8_1MMainline:
       EXPECT_EQ(ARM::ProfileKind::M, ARM::parseArchProfile(ARMArch[i]));
for (unsigned i = 0; i < std::size(ARMArch); i++) {
     default:
       EXPECT_EQ(ARM::ProfileKind::INVALID, ARM::parseArchProfile(ARMArch[i]));
       break;
     }
   }
 }
 
 TEST(TargetParserTest, ARMparseArchVersion) {
-  for (unsigned i = 0; i < array_lengthof(ARMArch); i++)
+  for (unsigned i = 0; i < std::size(ARMArch); i++)
     if (((std::string)ARMArch[i]).substr(0, 4) == "armv")
       EXPECT_EQ((ARMArch[i][4] - 48u), ARM::parseArchVersion(ARMArch[i]));
     else
       EXPECT_EQ(5u, ARM::parseArchVersion(ARMArch[i]));
 }
 
 class AArch64CPUTestFixture
     : public ::testing::TestWithParam<ARMCPUTestParams> {};
const char *ArchExt[][4] = {
       {"sme", "nosme", "+sme", "-sme"},
       {"sme-f64", "nosme-f64", "+sme-f64", "-sme-f64"},
       {"sme-i64", "nosme-i64", "+sme-i64", "-sme-i64"},
       {"hbc", "nohbc", "+hbc", "-hbc"},
       {"mops", "nomops", "+mops", "-mops"},
       {"pmuv3", "nopmuv3", "+perfmon", "-perfmon"},
   };
 
-  for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
+  for (unsigned i = 0; i < std::size(ArchExt); i++) {
     EXPECT_EQ(StringRef(ArchExt[i][2]),
               AArch64::getArchExtFeature(ArchExt[i][0]));
     EXPECT_EQ(StringRef(ArchExt[i][3]),
               AArch64::getArchExtFeature(ArchExt[i][1]));
   }
 }
 
 } // namespace

llvm/utils/KillTheDoctor/KillTheDoctor.cpp

static std::error_code GetFileNameFromHandle(HANDLE FileHandle,
 
   // Create a file mapping to get the file name.
   MappedViewOfFileScopedHandle MappedFile(
     ::MapViewOfFile(FileMapping, FILE_MAP_READ, 0, 0, 1));
 
   if (!MappedFile)
     return windows_error(::GetLastError());
 
-  Success = ::GetMappedFileNameA(::GetCurrentProcess(),
-                                MappedFile,
-                                Filename,
-                                array_lengthof(Filename) - 1);
+  Success = ::GetMappedFileNameA(::GetCurrentProcess(), MappedFile, Filename,
+                                 std::size(Filename) - 1);
 
   if (!Success)
     return windows_error(::GetLastError());
   else {
     Name = Filename;
     return std::error_code();
   }
 }
static std::string FindProgram(const std::string &Program,
 
   for (pathext_t::iterator i = pathext.begin(), e = pathext.end(); i != e; ++i){
     SmallString<5> ext;
     for (std::size_t ii = 0, e = i->size(); ii != e; ++ii)
       ext.push_back(::tolower((*i)[ii]));
     LPCSTR Extension = NULL;
     if (ext.size() && ext[0] == '.')
       Extension = ext.c_str();
-    DWORD length = ::SearchPathA(NULL,
-                                 Program.c_str(),
-                                 Extension,
-                                 array_lengthof(PathName),
-                                 PathName,
-                                 NULL);
+    DWORD length = ::SearchPathA(NULL, Program.c_str(), Extension,
+                                 std::size(PathName), PathName, NULL);
     if (length == 0)
       ec = windows_error(::GetLastError());
-    else if (length > array_lengthof(PathName)) {
+    else if (length > std::size(PathName)) {
       // This may have been the file, return with error.
       ec = windows_error(ERROR_BUFFER_OVERFLOW);
       break;
     } else {
       // We found the path! Return it.
       ec = std::error_code();
       break;
     }

llvm/utils/TableGen/AsmWriterEmitter.cpp

void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
   O.indent(2) << "  }\n";
   O.indent(2) << "} sortCheckVar(OpToPatterns);\n";
   O << "#endif\n\n";
 
   O.indent(2) << "AliasMatchingData M {\n";
   O.indent(2) << "  makeArrayRef(OpToPatterns),\n";
   O.indent(2) << "  makeArrayRef(Patterns),\n";
   O.indent(2) << "  makeArrayRef(Conds),\n";
-  O.indent(2) << "  StringRef(AsmStrings, array_lengthof(AsmStrings)),\n";
+  O.indent(2) << "  StringRef(AsmStrings, std::size(AsmStrings)),\n";
   if (MCOpPredicates.empty())
     O.indent(2) << "  nullptr,\n";
   else
     O.indent(2) << "  &" << Target.getName() << ClassName << "ValidateMCOperand,\n";
   O.indent(2) << "};\n";
 
   O.indent(2) << "const char *AsmString = matchAliasPatterns(MI, "
               << (PassSubtarget ? "&STI" : "nullptr") << ", M);\n";

llvm/utils/TableGen/CodeGenTarget.cpp

 }
 
 static const char *FixedInstrs[] = {
 #define HANDLE_TARGET_OPCODE(OPC) #OPC,
 #include "llvm/Support/TargetOpcodes.def"
     nullptr};
 
 unsigned CodeGenTarget::getNumFixedInstructions() {
-  return array_lengthof(FixedInstrs) - 1;
+  return std::size(FixedInstrs) - 1;
 }
 
 /// Return all of the instructions defined by the target, ordered by
 /// their enum value.
 void CodeGenTarget::ComputeInstrsByEnum() const {
   const auto &Insts = getInstructions();
   for (const char *const *p = FixedInstrs; *p; ++p) {
     const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);

llvm/utils/TableGen/RegisterInfoEmitter.cpp

for (unsigned I = 0, E = maxLength; I != E; ++I) {
         OS << ";\n";
       }
 
       // We have to store the size in a const global, it's used in multiple
       // places.
       OS << "extern const unsigned " << Namespace
          << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2LSize";
       if (!isCtor)
-        OS << " = array_lengthof(" << Namespace
+        OS << " = std::size(" << Namespace
            << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2L);\n\n";
       else
         OS << ";\n\n";
     }
   }
 
   for (auto &RE : Regs) {
     Record *Reg = RE.TheDef;
for (unsigned i = 0, e = maxLength; i != e; ++i) {
         OS << ";\n";
       }
 
       // We have to store the size in a const global, it's used in multiple
       // places.
       OS << "extern const unsigned " << Namespace
          << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
       if (!isCtor)
-        OS << " = array_lengthof(" << Namespace
+        OS << " = std::size(" << Namespace
            << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n";
       else
         OS << ";\n\n";
     }
   }
 }
 
 void RegisterInfoEmitter::EmitRegMapping(

llvm/utils/TableGen/X86DisassemblerTables.cpp

switch (dt) {
     default:
       llvm_unreachable("Unknown decision type");
     MODRMTYPES
   };
 #undef ENUM_ENTRY
 }
 
 DisassemblerTables::DisassemblerTables() {
-  for (unsigned i = 0; i < llvm::array_lengthof(Tables); i++)
+  for (unsigned i = 0; i < std::size(Tables); i++)
     Tables[i] = std::make_unique<ContextDecision>();
 
   HasConflicts = false;
 }
 
 DisassemblerTables::~DisassemblerTables() {
 }