Distinguish between different forms of "address-taken" MachineBasicBlocks

[efriedma]

Summary

There are two different senses in which a block can be "address-taken". There can be a BlockAddress involved, which means we need to map the IR-level value to some specific block of machine code. Or there can be constructs inside a function which involve using the address of a basic block to implement certain kinds of control flow.

Mixing these together causes a problem: if target-specific passes are marking random blocks "address-taken", if we have a BlockAddress, we can't actually tell which MachineBasicBlock corresponds to the BlockAddress.

So split this into two separate bits: one for BlockAddress, and one for the machine-specific bits. And try to clarify when, exactly, it's appropriate to use the new setMBBLabelUsed().

Discovered while trying to sort out related stuff on D102817.

[craig.topper]

llvm/include/llvm/CodeGen/MachineBasicBlock.h

246

Did clang-format format this differently than setMBBLabelUsed()? It's not over 80 columns on one line is it?

[efriedma]

Fix formatting

[kparzysz]

The IR spec states that the value of blockaddress can only be used in an indirect branch/call, or in a comparison against null. The latter seems to fall under the "address materialized somewhere" that you mention in the referenced review. Is the motivation behind BlockAddressTarget to identify blocks that are targets of indirect branches? Otherwise, it's not clear to me why blockaddress(bb) == null is any different from storing the address of bb in an exception table, for example.

[efriedma]

The problem that I spotted that led me to actually submitting this patch is the use of hasAddressTaken() in AsmPrinter::emitBasicBlockStart. It's ambiguous: in general, there could be mulitple "address-taken" MachineBasicBlocks that map to a given BasicBlock. (Maybe there's some other way to disambiguate, but this seems like the simplest.)

There are other reasons it might make sense to have this separation, anyway: we have robust support for "orphaned" blockaddresses (which don't actually map to any MachineBasicBlock), but for target-specific uses of setHasAddressTaken(), we probably end up with a use-after-free. So some places in the code generator might want to check for a "target-specific" address-taken, but not uses of blockaddress.

[kparzysz]

I'm not questioning the splitting, I'm just wondering if the terminology could be more self-explanatory. In AsmPrinter there is a check that an address-taken block must actually be present, but that's a hard requirement really only when there is a branch to it. So I was thinking that maybe "isIndirectBranchTarget" could be a better name, but I wasn't sure if it captured the intent.

[efriedma]

The way things currently work, the significant thing is whether the block is actually referred to by a blockaddress constant. isel doesn't actually check whether the block is the target of an indirectbr. So the naming reflects the current behavior; we treat the block as "address-taken" based on whether there's a blockaddress.

Given the LangRef rules, blocks that have an blockaddress pointing at them are generally also the target of an indirectbr, but we don't actually enforce that anywhere.

The LangRef rule is written the way it is to avoid promising anything about the way blockaddress constants are lowered. For example, if a block is unreachable, we can replace the associated blockaddress constant with a constant "1". Or on some targets like wasm, we convert indirectbrs to switches because we can't jump to arbitrary addresses. (We could implement an optimization to explicitly eliminate blockaddresses that refer to blocks that don't have an indirectbr predecessor... but it's not really important, so nobody has.)

[tentzen]

How about AddressTaken_Internal and AddressTaken_External?

the _Internal is used for blockAddress-constant, jump table, etc where it's targeted by IR internal user code domain.
the latter indicates that the address is taken and can be targeted externally by Runtime (EH case), OS or even HW (like the retpoline case).

Or AddressTaken_User and AddressTaken_System that refer to user mode and system mode.

[arsenm]

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

3482–3486

I don't like this hard requirement on the IR. CodeGen passes should try to avoid depending on the block being present (In particular llvm-reduce is now stripping out IR block references).

llvm/test/tools/llvm-reduce/mir/preserve-block-info.mir

11

Probably should add another case and check for the second flavor

[efriedma]

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

3482–3486

I'm not sure what alternative you're suggesting here. There's a contract based on the BasicBlock: we emit a symbol here, and uses of the BlockAddress constant refer to it. To emit the correct symbol we need the BasicBlock. If we skip emitting the symbol here, we miscompile.

[arsenm]

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

3482–3486

This needs to do something to handle the null block. Can it emit an __unnamed symbol or something like for anonymous functions? If this is going to assert on null the verifier at least has to check it

[efriedma]

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

3482–3486

If we're not concerned about emitting code that actually works, we can skip emitting the symbol. The blockaddress will point to the end of the function.

I think I'd prefer to have a verifier check; I'll look into adding that.

[efriedma]

Add verifier check

[efriedma]

Make the verifier check more strict, to match the asmprinter.

Alternatively, I guess we could drop both of the hasAddressTaken() assertions in AsmPrinter, but ensuring people don't use the wrong APIs seems more important than the resulting consequences for testcase reduction.

[efriedma]

In D124697#3498401, @tentzen wrote:

How about AddressTaken_Internal and AddressTaken_External?

the _Internal is used for blockAddress-constant, jump table, etc where it's targeted by IR internal user code domain.
the latter indicates that the address is taken and can be targeted externally by Runtime (EH case), OS or even HW (like the retpoline case).

Or AddressTaken_User and AddressTaken_System that refer to user mode and system mode.

This isn't really the distinction I'm trying making here. The distinction here is between LLVM IR uses of blockaddress (for indirectbr), and MachineFunction uses of MachineBasicBlock labels (for retpoline etc.). Jump tables would fall into the latter category, except that we have explicit code to update jump tables in the places where it would matter.

[tentzen]

This isn't really the distinction I'm trying making here. The distinction here is between LLVM IR uses of blockaddress (for indirectbr), and MachineFunction uses of MachineBasicBlock labels (for retpoline etc.). Jump tables would fall into the latter category, except that we have explicit code to update jump tables in the places where it would matter.

OK. How about IRBlockAddressTaken and MachineBlockAddressTaken. I think having "AddressTaken" explicitly spelled out here can avoid future confusions.

[efriedma]

Updated names according to suggestion from @tentzen

[arsenm]

llvm/include/llvm/CodeGen/MachineBasicBlock.h

152

If you're going to depend on the underlying IR block, you don't really need another field inside MachineBasicBlock. You can just query directly from the IR

[efriedma]

llvm/include/llvm/CodeGen/MachineBasicBlock.h

152

In general, there are multiple MachineBasicBlocks which correspond to a single IR BasicBlock; when we split a block for whatever reason, getBasicBlock() is the same for both halves. We need to know which one is the jump destination.

[arsenm]

llvm/include/llvm/CodeGen/MachineBasicBlock.h

152

Does it actually make sense to preserve the IR block if the block is split? Is the IR block used for anything else? Maybe for block splitting the second half of the block shouldn't have the IR link

[efriedma]

llvm/include/llvm/CodeGen/MachineBasicBlock.h

152

It might be possible to mess with the value stored as getBasicBlock(); as far as I can tell, the result is mostly used for debug prints and as an argument to CreateMachineBasicBlock(). It is used for a few other (possibly dubious) things: to get MD_loop/MD_make_implicit metadata, to get debug locations, to get the LandingPadInst for a landing pad. Nothing we couldn't handle some other way, I think.

If we want to go in that direction, though, I might as well just replace bool IRBlockAddressTaken with BasicBlock *IRBlockAddress", and avoid the dependency on getBasicBlock() altogether.

[efriedma]

llvm/include/llvm/CodeGen/MachineBasicBlock.h

152

@arsenm Ping

[asmith]

@arsenm @efriedma we'll update the SEH patch with this change if it's ready?

[efriedma]

I was hoping to hear back from @arsenm about the review comment, but I think this is ready otherwise.

[arsenm]

llvm/include/llvm/CodeGen/MachineBasicBlock.h

152

Right, that's what I was suggesting. Just go through the IR block. I suspect the IR block is misleading in the split case anyway

[efriedma]

For ir-block-address-taken basic blocks, don't depend on MachineBasicBlock::getBasicBlock(); store the corresponding BasicBlock separately. This ensures it stays isolated from any future cleanups related to getBasicBlock(). (The MIR ir-block-address-taken now takes a basic block argument.)

[efriedma]

@arsenm Ping

[arsenm]

llvm/include/llvm/CodeGen/MachineBasicBlock.h

152

I meant go from the underlying IR block that's already there, not introduce a second reference. Blocks split from the end of of the block would not have an IR block reference

[efriedma]

llvm/include/llvm/CodeGen/MachineBasicBlock.h

152

Directly hacking at getBasicBlock() would be basically impossible to land in a single patch. There are a bunch of places that use getBasicBlock(); we'd need to ensure that every existing use of getBasicBlock() doesn't depend on the existing splitting behavior. We'd need to land a patch similar to this, then audit/modify various users of getBasicBlock(), then hack at the code that creates MBBs.

I agree that the concept of the "corresponding IR block" is a bit fuzzy for a random basic block once you've started to run MachineFunction optimizations. But I'm not sure changing the rule for splitting BBs is helpful; we do a bunch of work to change the rules, and the result is that it's still fuzzy. I mean, knowing the BB tied to the initial MBB is useful specifically if you want some IR element tied to the beginning of the block, like a blockaddress or landingpad. But not so useful if you want to query the terminator the IR block used, like some other places do.

[efriedma]

@arsenm ping

[efriedma]

@arsenm ping

[arsenm]

LGTM. I agree it's more work to drop the second block but would leave less clutter

llvm/include/llvm/CodeGen/MachineBasicBlock.h

private:
   /// Maximum amount of bytes that can be added to align the basic block. If the
   /// alignment cannot be reached in this many bytes, no bytes are emitted.
   /// Zero to represent no maximum.
   unsigned MaxBytesForAlignment = 0;
 
   /// Indicate that this basic block is entered via an exception handler.
   bool IsEHPad = false;
 
-  /// Indicate that this basic block is potentially the target of an indirect
-  /// branch.
-  bool AddressTaken = false;
+  /// Indicate that this MachineBasicBlock is referenced somewhere other than
+  /// as predecessor/successor, a terminator MachineInstr, or a jump table.
+  bool MBBLabelUsed = false;
+
+  /// Indicate that this basic block is the MachineBasicBlock which corresponds
+  /// to an IR-level "blockaddress" constant.
+  bool BlockAddressTarget = false;
 
   /// Indicate that this basic block needs its symbol be emitted regardless of
   /// whether the flow just falls-through to it.
   bool LabelMustBeEmitted = false;
 
   /// Indicate that this basic block is the entry block of an EH scope, i.e.,
   /// the block that used to have a catchpad or cleanuppad instruction in the
   /// LLVM IR.
public:
   }
 
   /// Return the name of the corresponding LLVM basic block, or an empty string.
   StringRef getName() const;
 
   /// Return a formatted string to identify this block and its parent function.
   std::string getFullName() const;
 
-  /// Test whether this block is potentially the target of an indirect branch.
-  bool hasAddressTaken() const { return AddressTaken; }
-
-  /// Set this block to reflect that it potentially is the target of an indirect
-  /// branch.
-  void setHasAddressTaken() { AddressTaken = true; }
+  /// Test whether this block is used as as something other than the target
+  /// of a terminator, exception-handling target, or jump table. This is
+  /// either the result of an IR-level "blockaddress", or some form
+  /// of target-specific branch lowering.
+  bool hasAddressTaken() const { return MBBLabelUsed || BlockAddressTarget; }
+
+  /// Test whether this block is used as something other than the target of a
+  /// terminator, exception-handling target, jump table, or IR blockaddress.
+  /// For example, its address might be loaded into a register, or
+  /// stored in some branch table that isn't part of MachineJumpTableInfo.
+  bool isMBBLabelUsed() const { return MBBLabelUsed; }
+
+  /// Test whether this block is the target of an IR BlockAddress.  (There can
+  /// more than one MBB associated with an IR BB where the address is taken.)
+  bool isBlockAddressTarget() const { return BlockAddressTarget; }
+
+  /// Set this block to indicate that its address is used as something other
+  /// than the target of a terminator, exception-handling target, jump table,
+  /// or IR-level "blockaddress".
+  void setMBBLabelUsed() { MBBLabelUsed = true; }
+
+  /// Set this block to reflect that it corresponds to an IR-level basic block
+  /// with a BlockAddress.
+  void setIsBlockAddressTarget() { BlockAddressTarget = true; }
 
   /// Test whether this block must have its label emitted.
   bool hasLabelMustBeEmitted() const { return LabelMustBeEmitted; }
 
   /// Set this block to reflect that, regardless how we flow to it, we need
   /// its label be emitted.
   void setLabelMustBeEmitted() { LabelMustBeEmitted = true; }
 

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

if (MBB.isBeginSection() && !MBB.isEntryBlock()) {
     CurrentSectionBeginSym = MBB.getSymbol();
   }
 
   // If the block has its address taken, emit any labels that were used to
   // reference the block.  It is possible that there is more than one label
   // here, because multiple LLVM BB's may have been RAUW'd to this block after
   // the references were generated.
   const BasicBlock *BB = MBB.getBasicBlock();
-  if (MBB.hasAddressTaken()) {
+  if (MBB.isBlockAddressTarget()) {
     if (isVerbose())
       OutStreamer->AddComment("Block address taken");
 
-    // MBBs can have their address taken as part of CodeGen without having
-    // their corresponding BB's address taken in IR
-    if (BB && BB->hasAddressTaken())
-      for (MCSymbol *Sym : getAddrLabelSymbolToEmit(BB))
-        OutStreamer->emitLabel(Sym);
+    assert(BB && BB->hasAddressTaken() && "Missing BB");
+  } else if (isVerbose() && MBB.isMBBLabelUsed()) {
+    OutStreamer->AddComment("Block address taken");
   }
 
   // Print some verbose block comments.
   if (isVerbose()) {
     if (BB) {
       if (BB->hasName()) {
         BB->printAsOperand(OutStreamer->GetCommentOS(),
                            /*PrintType=*/false, BB->getModule());

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
   // Create all blocks, in IR order, to preserve the layout.
   for (const BasicBlock &BB: F) {
     auto *&MBB = BBToMBB[&BB];
 
     MBB = MF->CreateMachineBasicBlock(&BB);
     MF->push_back(MBB);
 
     if (BB.hasAddressTaken())
-      MBB->setHasAddressTaken();
+      MBB->setIsBlockAddressTarget();
 
     if (!HasMustTailInVarArgFn)
       HasMustTailInVarArgFn = checkForMustTailInVarArgFn(IsVarArg, BB);
   }
 
   MF->getFrameInfo().setHasMustTailInVarArgFunc(HasMustTailInVarArgFn);
 
   // Make our arguments/constants entry block fallthrough to the IR entry block.

llvm/lib/CodeGen/MIRParser/MILexer.h

enum TokenKind {
     kw_addrspace,
     kw_stack,
     kw_got,
     kw_jump_table,
     kw_constant_pool,
     kw_call_entry,
     kw_custom,
     kw_liveout,
-    kw_address_taken,
     kw_landing_pad,
     kw_inlineasm_br_indirect_target,
     kw_ehfunclet_entry,
     kw_liveins,
     kw_successors,
     kw_floatpred,
     kw_intpred,
     kw_shufflemask,
     kw_pre_instr_symbol,
     kw_post_instr_symbol,
     kw_heap_alloc_marker,
     kw_bbsections,
     kw_unknown_size,
     kw_unknown_address,
+    kw_blockaddress_target,
+    kw_mbb_label_used,
 
     // Metadata types.
     kw_distinct,
 
     // Named metadata keywords
     md_tbaa,
     md_alias_scope,
     md_noalias,

llvm/lib/CodeGen/MIRParser/MILexer.cpp

return StringSwitch<MIToken::TokenKind>(Identifier)
       .Case("addrspace", MIToken::kw_addrspace)
       .Case("stack", MIToken::kw_stack)
       .Case("got", MIToken::kw_got)
       .Case("jump-table", MIToken::kw_jump_table)
       .Case("constant-pool", MIToken::kw_constant_pool)
       .Case("call-entry", MIToken::kw_call_entry)
       .Case("custom", MIToken::kw_custom)
       .Case("liveout", MIToken::kw_liveout)
-      .Case("address-taken", MIToken::kw_address_taken)
       .Case("landing-pad", MIToken::kw_landing_pad)
       .Case("inlineasm-br-indirect-target",
             MIToken::kw_inlineasm_br_indirect_target)
       .Case("ehfunclet-entry", MIToken::kw_ehfunclet_entry)
       .Case("liveins", MIToken::kw_liveins)
       .Case("successors", MIToken::kw_successors)
       .Case("floatpred", MIToken::kw_floatpred)
       .Case("intpred", MIToken::kw_intpred)
       .Case("shufflemask", MIToken::kw_shufflemask)
       .Case("pre-instr-symbol", MIToken::kw_pre_instr_symbol)
       .Case("post-instr-symbol", MIToken::kw_post_instr_symbol)
       .Case("heap-alloc-marker", MIToken::kw_heap_alloc_marker)
       .Case("bbsections", MIToken::kw_bbsections)
       .Case("unknown-size", MIToken::kw_unknown_size)
       .Case("unknown-address", MIToken::kw_unknown_address)
       .Case("distinct", MIToken::kw_distinct)
+      .Case("blockaddress-target", MIToken::kw_blockaddress_target)
+      .Case("mbb-label-used", MIToken::kw_mbb_label_used)
       .Default(MIToken::Identifier);
 }
 
 static Cursor maybeLexIdentifier(Cursor C, MIToken &Token) {
   if (!isalpha(C.peek()) && C.peek() != '_')
     return None;
   auto Range = C;
   while (isIdentifierChar(C.peek()))

llvm/lib/CodeGen/MIRParser/MIParser.cpp

bool MIParser::parseBasicBlockDefinition(
     DenseMap<unsigned, MachineBasicBlock *> &MBBSlots) {
   assert(Token.is(MIToken::MachineBasicBlockLabel));
   unsigned ID = 0;
   if (getUnsigned(ID))
     return true;
   auto Loc = Token.location();
   auto Name = Token.stringValue();
   lex();
-  bool HasAddressTaken = false;
+  bool MBBLabelUsed = false;
+  bool IsBlockAddressTarget = false;
   bool IsLandingPad = false;
   bool IsInlineAsmBrIndirectTarget = false;
   bool IsEHFuncletEntry = false;
   Optional<MBBSectionID> SectionID;
   uint64_t Alignment = 0;
   BasicBlock *BB = nullptr;
   if (consumeIfPresent(MIToken::lparen)) {
     do {
       // TODO: Report an error when multiple same attributes are specified.
       switch (Token.kind()) {
-      case MIToken::kw_address_taken:
-        HasAddressTaken = true;
+      case MIToken::kw_mbb_label_used:
+        MBBLabelUsed = true;
+        lex();
+        break;
+      case MIToken::kw_blockaddress_target:
+        IsBlockAddressTarget = true;
         lex();
         break;
       case MIToken::kw_landing_pad:
         IsLandingPad = true;
         lex();
         break;
       case MIToken::kw_inlineasm_br_indirect_target:
         IsInlineAsmBrIndirectTarget = true;
         lex();
         break;
       case MIToken::kw_ehfunclet_entry:
         IsEHFuncletEntry = true;
         lex();
         break;
       case MIToken::kw_align:
         if (parseAlignment(Alignment))
           return true;
         break;
       case MIToken::IRBlock:
+      case MIToken::NamedIRBlock:
         // TODO: Report an error when both name and ir block are specified.
         if (parseIRBlock(BB, MF.getFunction()))
           return true;
         lex();
         break;
       case MIToken::kw_bbsections:
         if (parseSectionID(SectionID))
           return true;
bool MIParser::parseBasicBlockDefinition(
   auto *MBB = MF.CreateMachineBasicBlock(BB);
   MF.insert(MF.end(), MBB);
   bool WasInserted = MBBSlots.insert(std::make_pair(ID, MBB)).second;
   if (!WasInserted)
     return error(Loc, Twine("redefinition of machine basic block with id #") +
                           Twine(ID));
   if (Alignment)
     MBB->setAlignment(Align(Alignment));
-  if (HasAddressTaken)
-    MBB->setHasAddressTaken();
+  if (MBBLabelUsed)
+    MBB->setMBBLabelUsed();
+  if (IsBlockAddressTarget)
+    MBB->setIsBlockAddressTarget();
   MBB->setIsEHPad(IsLandingPad);
   MBB->setIsInlineAsmBrIndirectTarget(IsInlineAsmBrIndirectTarget);
   MBB->setIsEHFuncletEntry(IsEHFuncletEntry);
   if (SectionID.hasValue()) {
     MBB->setSectionID(SectionID.getValue());
     MF.setBBSectionsType(BasicBlockSection::List);
   }
   return false;

llvm/lib/CodeGen/MachineBasicBlock.cpp

if (const auto *bb = getBasicBlock()) {
           os << "<ir-block badref>";
         else
           os << (Twine("%ir-block.") + Twine(slot)).str();
       }
     }
   }
 
   if (printNameFlags & PrintNameAttributes) {
-    if (hasAddressTaken()) {
+    if (isMBBLabelUsed()) {
       os << (hasAttributes ? ", " : " (");
-      os << "address-taken";
+      os << "mbb-label-used";
+      hasAttributes = true;
+    }
+    if (isBlockAddressTarget()) {
+      os << (hasAttributes ? ", " : " (");
+      os << "blockaddress-target";
       hasAttributes = true;
     }
     if (isEHPad()) {
       os << (hasAttributes ? ", " : " (");
       os << "landing-pad";
       hasAttributes = true;
     }
     if (isInlineAsmBrIndirectTarget()) {

llvm/lib/CodeGen/MachineVerifier.cpp

for (const auto &LI : MBB->liveins()) {
       if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
           MBB->getIterator() != MBB->getParent()->begin()) {
         report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
         report_context(LI.PhysReg);
       }
     }
   }
 
+  if (MBB->isBlockAddressTarget() && !MBB->getBasicBlock())
+    report("blockaddresstarget block is missing associated basic block.", MBB);
+
   // Count the number of landing pad successors.
   SmallPtrSet<const MachineBasicBlock*, 4> LandingPadSuccs;
   for (const auto *succ : MBB->successors()) {
     if (succ->isEHPad())
       LandingPadSuccs.insert(succ);
     if (!FunctionBlocks.count(succ))
       report("MBB has successor that isn't part of the function.", MBB);
     if (!MBBInfoMap[succ].Preds.count(MBB)) {

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

for (const BasicBlock &BB : *Fn) {
     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(&BB);
     MBBMap[&BB] = MBB;
     MF->push_back(MBB);
 
     // Transfer the address-taken flag. This is necessary because there could
     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
     // the first one should be marked.
     if (BB.hasAddressTaken())
-      MBB->setHasAddressTaken();
+      MBB->setIsBlockAddressTarget();
 
     // Mark landing pad blocks.
     if (BB.isEHPad())
       MBB->setIsEHPad();
 
     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
     // appropriate.
     for (const PHINode &PN : BB.phis()) {

llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp

if (!TII->isValidOffset(LOOP_i, CountImm, TRI)) {
         .addImm(CountImm);
       BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r))
         .addMBB(LoopStart).addReg(CountReg);
     } else
       BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_i))
         .addMBB(LoopStart).addImm(CountImm);
   }
 
-  // Make sure the loop start always has a reference in the CFG.  We need
-  // to create a BlockAddress operand to get this mechanism to work both the
-  // MachineBasicBlock and BasicBlock objects need the flag set.
-  LoopStart->setHasAddressTaken();
-  // This line is needed to set the hasAddressTaken flag on the BasicBlock
-  // object.
-  BlockAddress::get(const_cast<BasicBlock *>(LoopStart->getBasicBlock()));
+  // Make sure the loop start always has a reference in the CFG.
+  LoopStart->setMBBLabelUsed();
 
   // Replace the loop branch with an endloop instruction.
   DebugLoc LastIDL = LastI->getDebugLoc();
   BuildMI(*LastMBB, LastI, LastIDL, TII->get(ENDLOOP)).addMBB(LoopStart);
 
   // The loop ends with either:
   //  - a conditional branch followed by an unconditional branch, or
   //  - a conditional branch to the loop start.

llvm/lib/Target/VE/VEISelLowering.cpp

VETargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
 
   MachineBasicBlock *ThisMBB = MBB;
   MachineBasicBlock *MainMBB = MF->CreateMachineBasicBlock(BB);
   MachineBasicBlock *SinkMBB = MF->CreateMachineBasicBlock(BB);
   MachineBasicBlock *RestoreMBB = MF->CreateMachineBasicBlock(BB);
   MF->insert(I, MainMBB);
   MF->insert(I, SinkMBB);
   MF->push_back(RestoreMBB);
-  RestoreMBB->setHasAddressTaken();
+  RestoreMBB->setMBBLabelUsed();
 
   // Transfer the remainder of BB and its successor edges to SinkMBB.
   SinkMBB->splice(SinkMBB->begin(), MBB,
                   std::next(MachineBasicBlock::iterator(MI)), MBB->end());
   SinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
 
   // ThisMBB:
   Register LabelReg =

llvm/lib/Target/X86/X86FrameLowering.cpp

void X86FrameLowering::emitCatchRetReturnValue(MachineBasicBlock &MBB,
   } else {
     // MOV32ri $CatchRetTarget, %eax
     BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
         .addMBB(CatchRetTarget);
   }
 
   // Record that we've taken the address of CatchRetTarget and no longer just
   // reference it in a terminator.
-  CatchRetTarget->setHasAddressTaken();
+  CatchRetTarget->setMBBLabelUsed();
 }
 
 bool X86FrameLowering::restoreCalleeSavedRegisters(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
     MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;
 

llvm/lib/Target/X86/X86ISelLowering.cpp

X86TargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
 
   MachineBasicBlock *thisMBB = MBB;
   MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
   MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
   MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
   MF->insert(I, mainMBB);
   MF->insert(I, sinkMBB);
   MF->push_back(restoreMBB);
-  restoreMBB->setHasAddressTaken();
+  restoreMBB->setMBBLabelUsed();
 
   MachineInstrBuilder MIB;
 
   // Transfer the remainder of BB and its successor edges to sinkMBB.
   sinkMBB->splice(sinkMBB->begin(), MBB,
                   std::next(MachineBasicBlock::iterator(MI)), MBB->end());
   sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
 

llvm/lib/Target/X86/X86IndirectThunks.cpp

void RetpolineThunkInserter::populateThunk(MachineFunction &MF) {
   // processors, the PAUSE instruction is (essentially) a nop, so we also use an
   // LFENCE instruction which they have advised will stop speculation as well
   // with minimal resource utilization. We still end the capture with a jump to
   // form an infinite loop to fully guarantee that no matter what implementation
   // of the x86 ISA, speculating this code path never escapes.
   BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::PAUSE));
   BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::LFENCE));
   BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::JMP_1)).addMBB(CaptureSpec);
-  CaptureSpec->setHasAddressTaken();
+  CaptureSpec->setMBBLabelUsed();
   CaptureSpec->addSuccessor(CaptureSpec);
 
   CallTarget->addLiveIn(ThunkReg);
-  CallTarget->setHasAddressTaken();
+  CallTarget->setMBBLabelUsed();
   CallTarget->setAlignment(Align(16));
 
   // Insert return address clobber
   const unsigned MovOpc = Is64Bit ? X86::MOV64mr : X86::MOV32mr;
   const Register SPReg = Is64Bit ? X86::RSP : X86::ESP;
   addRegOffset(BuildMI(CallTarget, DebugLoc(), TII->get(MovOpc)), SPReg, false,
                0)
       .addReg(ThunkReg);

llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp

for (MachineBasicBlock &MBB : MF) {
     // branch back to itself. We can do this here because at this point, every
     // predecessor of this block has an available value. This is basically just
     // automating the construction of a PHI node for this target.
     Register TargetReg = TargetAddrSSA.GetValueInMiddleOfBlock(&MBB);
 
     // Insert a comparison of the incoming target register with this block's
     // address. This also requires us to mark the block as having its address
     // taken explicitly.
-    MBB.setHasAddressTaken();
+    MBB.setMBBLabelUsed();
     auto InsertPt = MBB.SkipPHIsLabelsAndDebug(MBB.begin());
     if (MF.getTarget().getCodeModel() == CodeModel::Small &&
         !Subtarget->isPositionIndependent()) {
       // Check directly against a relocated immediate when we can.
       auto CheckI = BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::CMP64ri32))
                         .addReg(TargetReg, RegState::Kill)
                         .addMBB(&MBB);
       ++NumInstsInserted;

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

 ; CHECK: body:
 ;
 ; ABI/constant lowering and IR-level entry basic block.
 ; CHECK: bb.{{[0-9]+.[a-zA-Z0-9.]+}}:
 ; Make sure we have one successor
 ; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+]](0x80000000)
 ;
 ; Check basic block L1 has 2 successors: BBL1 and BBL2
-; CHECK: [[BB_L1]].{{[a-zA-Z0-9.]+}} (address-taken):
+; CHECK: [[BB_L1]].{{[a-zA-Z0-9.]+}} (blockaddress-target):
 ; CHECK-NEXT: successors: %[[BB_L1]](0x40000000),
 ; CHECK:                  %[[BB_L2:bb.[0-9]+]](0x40000000)
 ; CHECK: G_BRINDIRECT %{{[0-9]+}}(p0)
 ;
 ; Check basic block L2 is the return basic block
-; CHECK: [[BB_L2]].{{[a-zA-Z0-9.]+}} (address-taken):
+; CHECK: [[BB_L2]].{{[a-zA-Z0-9.]+}} (blockaddress-target):
 ; CHECK-NEXT: RET_ReallyLR
 
 @indirectbr.L = internal unnamed_addr constant [3 x i8*] [i8* blockaddress(@indirectbr, %L1), i8* blockaddress(@indirectbr, %L2), i8* null], align 8
 
 define void @indirectbr() {
 entry:
   br label %L1
 L1:                                               ; preds = %entry, %L1

llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir

 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   ; CHECK-LABEL: name: test_blockaddress
   ; CHECK: bb.0 (%ir-block.0):
-  ; CHECK:   [[BLOCK_ADDR:%[0-9]+]]:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
-  ; CHECK:   [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @addr
-  ; CHECK:   [[ADD_LOW:%[0-9]+]]:_(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @addr
-  ; CHECK:   G_STORE [[BLOCK_ADDR]](p0), [[ADD_LOW]](p0) :: (store (p0) into @addr)
-  ; CHECK:   G_BRINDIRECT [[BLOCK_ADDR]](p0)
-  ; CHECK: bb.1.block (address-taken):
-  ; CHECK:   RET_ReallyLR
+  ; CHECK-NEXT:   [[BLOCK_ADDR:%[0-9]+]]:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
+  ; CHECK-NEXT:   [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @addr
+  ; CHECK-NEXT:   [[ADD_LOW:%[0-9]+]]:_(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @addr
+  ; CHECK-NEXT:   G_STORE [[BLOCK_ADDR]](p0), [[ADD_LOW]](p0) :: (store (p0) into @addr)
+  ; CHECK-NEXT:   G_BRINDIRECT [[BLOCK_ADDR]](p0)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.block (blockaddress-target):
+  ; CHECK-NEXT:   RET_ReallyLR
   bb.1 (%ir-block.0):
     %0:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
     %1:_(p0) = G_GLOBAL_VALUE @addr
     G_STORE %0(p0), %1(p0) :: (store (p0) into @addr)
     G_BRINDIRECT %0(p0)
 
-  bb.2.block (address-taken):
+  bb.2.block (blockaddress-target):
     RET_ReallyLR
 
 ...
 

llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir

 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 body:             |
   ; CHECK-LABEL: name: test_blockaddress
   ; CHECK: bb.0 (%ir-block.0):
-  ; CHECK:   [[MOVaddrBA:%[0-9]+]]:gpr64common = MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block)
-  ; CHECK:   [[MOVaddr:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @addr, target-flags(aarch64-pageoff, aarch64-nc) @addr
-  ; CHECK:   [[COPY:%[0-9]+]]:gpr64 = COPY [[MOVaddrBA]]
-  ; CHECK:   STRXui [[COPY]], [[MOVaddr]], 0 :: (store (p0) into @addr)
-  ; CHECK:   BR [[MOVaddrBA]]
-  ; CHECK: bb.1.block (address-taken):
+  ; CHECK-NEXT:   [[MOVaddrBA:%[0-9]+]]:gpr64common = MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block)
+  ; CHECK-NEXT:   [[MOVaddr:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @addr, target-flags(aarch64-pageoff, aarch64-nc) @addr
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64 = COPY [[MOVaddrBA]]
+  ; CHECK-NEXT:   STRXui [[COPY]], [[MOVaddr]], 0 :: (store (p0) into @addr)
+  ; CHECK-NEXT:   BR [[MOVaddrBA]]
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.block (blockaddress-target):
   ; LARGE-LABEL: name: test_blockaddress
   ; LARGE: bb.0 (%ir-block.0):
-  ; LARGE:   [[MOVZXi:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 0
-  ; LARGE:   [[MOVKXi:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi]], target-flags(aarch64-g1, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 16
-  ; LARGE:   [[MOVKXi1:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi]], target-flags(aarch64-g2, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 32
-  ; LARGE:   [[MOVKXi2:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi1]], target-flags(aarch64-g3) blockaddress(@test_blockaddress, %ir-block.block), 48
-  ; LARGE:   [[MOVZXi1:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) @addr, 0
-  ; LARGE:   [[MOVKXi3:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi1]], target-flags(aarch64-g1, aarch64-nc) @addr, 16
-  ; LARGE:   [[MOVKXi4:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi3]], target-flags(aarch64-g2, aarch64-nc) @addr, 32
-  ; LARGE:   [[MOVKXi5:%[0-9]+]]:gpr64common = MOVKXi [[MOVKXi4]], target-flags(aarch64-g3) @addr, 48
-  ; LARGE:   STRXui [[MOVKXi2]], [[MOVKXi5]], 0 :: (store (p0) into @addr)
-  ; LARGE:   BR [[MOVKXi2]]
-  ; LARGE: bb.1.block (address-taken):
+  ; LARGE-NEXT:   [[MOVZXi:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 0
+  ; LARGE-NEXT:   [[MOVKXi:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi]], target-flags(aarch64-g1, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 16
+  ; LARGE-NEXT:   [[MOVKXi1:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi]], target-flags(aarch64-g2, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 32
+  ; LARGE-NEXT:   [[MOVKXi2:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi1]], target-flags(aarch64-g3) blockaddress(@test_blockaddress, %ir-block.block), 48
+  ; LARGE-NEXT:   [[MOVZXi1:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) @addr, 0
+  ; LARGE-NEXT:   [[MOVKXi3:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi1]], target-flags(aarch64-g1, aarch64-nc) @addr, 16
+  ; LARGE-NEXT:   [[MOVKXi4:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi3]], target-flags(aarch64-g2, aarch64-nc) @addr, 32
+  ; LARGE-NEXT:   [[MOVKXi5:%[0-9]+]]:gpr64common = MOVKXi [[MOVKXi4]], target-flags(aarch64-g3) @addr, 48
+  ; LARGE-NEXT:   STRXui [[MOVKXi2]], [[MOVKXi5]], 0 :: (store (p0) into @addr)
+  ; LARGE-NEXT:   BR [[MOVKXi2]]
+  ; LARGE-NEXT: {{  $}}
+  ; LARGE-NEXT: bb.1.block (blockaddress-target):
   bb.1 (%ir-block.0):
     %0:gpr(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
     %1:gpr(p0) = G_GLOBAL_VALUE @addr
     G_STORE %0(p0), %1(p0) :: (store (p0) into @addr)
     G_BRINDIRECT %0(p0)
 
-  bb.2.block (address-taken):
+  bb.2.block (blockaddress-target):
     RET_ReallyLR
 
 ...

llvm/test/CodeGen/AArch64/branch-target-enforcement.mir

body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: simple_external
     ; CHECK: HINT 34
     ; CHECK: RET
     $w0 = ORRWrs $wzr, $wzr, 0
     RET undef $lr, implicit killed $w0
 
 ---
-# Internal function, not address-taken in this module, however the compiler
+# Internal function, not blockaddress-target in this module, however the compiler
 # cannot 100% ensure that later parts of the toolchain won't add indirect
 # jumps. E.g. a linker adding a thunk to extend the range of a direct jump.
 # Therefore, even this case needs a BTI.
 name:            simple_internal
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: simple_internal
     ; CHECK: HINT 34
bb.0.entry:
     ; CHECK-NEXT: HINT 34
     ; CHECK: BR killed renamable $x9
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
 
     renamable $x8 = ADRP target-flags(aarch64-page) @label_address.addr
     renamable $x9 = LDRXui renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @label_address.addr :: (dereferenceable load (s64) from @label_address.addr)
     BR killed renamable $x9
 
-  bb.1.return (address-taken):
-    ; CHECK: bb.1.return (address-taken):
+  bb.1.return (blockaddress-target):
+    ; CHECK: bb.1.return (blockaddress-target):
     ; CHECK-NEXT: HINT 36
     liveins: $x8
 
     $x9 = ADRP target-flags(aarch64-page) blockaddress(@label_address, %ir-block.lab2)
     renamable $w0 = ORRWri $wzr, 0
     renamable $x9 = ADDXri killed $x9, target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@label_address, %ir-block.lab2), 0
     STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @label_address.addr :: (store (s64) into @label_address.addr)
     RET undef $lr, implicit killed $w0
 
-  bb.2.lab2 (address-taken):
-    ; CHECK: bb.2.lab2 (address-taken):
+  bb.2.lab2 (blockaddress-target):
+    ; CHECK: bb.2.lab2 (blockaddress-target):
     ; CHECK-NEXT: HINT 36
     liveins: $x8
 
     $x9 = ADRP target-flags(aarch64-page) blockaddress(@label_address, %ir-block.return)
     renamable $w0 = ORRWri $wzr, 1984
     renamable $x9 = ADDXri killed $x9, target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@label_address, %ir-block.return), 0
     STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @label_address.addr :: (store (s64) into @label_address.addr)
     RET undef $lr, implicit killed $w0
 
 ---
 # Function takes address of the entry block, so the entry block needs a BTI JC.
 name:            label_address_entry
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
       stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 body:             |
-  bb.0.entry (address-taken):
+  bb.0.entry (blockaddress-target):
     ; CHECK-LABEL: label_address_entry
-    ; CHECK: bb.0.entry (address-taken):
+    ; CHECK: bb.0.entry (blockaddress-target):
     ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
     ; CHECK-NEXT: {{  }}
     ; CHECK-NEXT: HINT 38
     ; CHECK: BR killed renamable $x9
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
 
     renamable $x8 = ADRP target-flags(aarch64-page) @label_address.addr
     renamable $x9 = LDRXui renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @label_address.addr :: (dereferenceable load (s64) from @label_address.addr)
     BR killed renamable $x9
 
-  bb.1.return (address-taken):
-    ; CHECK: bb.1.return (address-taken):
+  bb.1.return (blockaddress-target):
+    ; CHECK: bb.1.return (blockaddress-target):
     ; CHECK-NEXT: HINT 36
     liveins: $x8
     frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
     frame-setup CFI_INSTRUCTION negate_ra_sign_state
     early-clobber $sp = frame-setup STRXpre killed $lr, $sp, -16 :: (store (s64) into %stack.0)
     INLINEASM &"", 1, 12, implicit-def dead early-clobber $lr
     $x9 = ADRP target-flags(aarch64-page) blockaddress(@label_address, %ir-block.entry)
     renamable $w0 = ORRWri $wzr, 0

llvm/test/CodeGen/AArch64/speculation-hardening-sls.mir

bb.0.entry:
     renamable $x8 = ADDXri $x8, target-flags(aarch64-pageoff, aarch64-nc) @ptr_aa, 0
     renamable $x8 = LDRXroW killed renamable $x8, killed renamable $w2, 1, 1
     BRAA killed renamable $x8, $sp
   ; CHECK:       braa x8, sp
   ; ISBDSB-NEXT: dsb sy
   ; ISBDSB-NEXT: isb
   ; SB-NEXT:     {{ sb$}}
 
-  bb.1.l2 (address-taken):
+  bb.1.l2 (blockaddress-target):
     renamable $w0 = MOVZWi 1, 0
     RET undef $lr, implicit $w0
 
-  bb.2.return (address-taken):
+  bb.2.return (blockaddress-target):
     $w0 = ORRWrs $wzr, $wzr, 0
     RET undef $lr, implicit $w0
 ...
 ---
 name:            br_aaz
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: br_aaz:
   bb.0.entry:
     successors: %bb.2, %bb.1
     liveins: $w2
     $x8 = ADRP target-flags(aarch64-page) @ptr_aaz
     renamable $x8 = ADDXri $x8, target-flags(aarch64-pageoff, aarch64-nc) @ptr_aaz, 0
     renamable $x8 = LDRXroW killed renamable $x8, killed renamable $w2, 1, 1
     BRAAZ killed renamable $x8
   ; CHECK:       braaz x8
   ; ISBDSB-NEXT: dsb sy
   ; ISBDSB-NEXT: isb
   ; SB-NEXT:     {{ sb$}}
 
-  bb.1.l2 (address-taken):
+  bb.1.l2 (blockaddress-target):
     renamable $w0 = MOVZWi 1, 0
     RET undef $lr, implicit $w0
 
-  bb.2.return (address-taken):
+  bb.2.return (blockaddress-target):
     $w0 = ORRWrs $wzr, $wzr, 0
     RET undef $lr, implicit $w0
 ...
 ---
 name:            br_ab
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: br_ab:
   bb.0.entry:
     successors: %bb.2, %bb.1
     liveins: $w2
     $x8 = ADRP target-flags(aarch64-page) @ptr_ab
     renamable $x8 = ADDXri $x8, target-flags(aarch64-pageoff, aarch64-nc) @ptr_ab, 0
     renamable $x8 = LDRXroW killed renamable $x8, killed renamable $w2, 1, 1
     BRAA killed renamable $x8, $sp
   ; CHECK:       braa x8, sp
   ; ISBDSB-NEXT: dsb sy
   ; ISBDSB-NEXT: isb
   ; SB-NEXT:     {{ sb$}}
 
-  bb.1.l2 (address-taken):
+  bb.1.l2 (blockaddress-target):
     renamable $w0 = MOVZWi 1, 0
     RET undef $lr, implicit $w0
 
-  bb.2.return (address-taken):
+  bb.2.return (blockaddress-target):
     $w0 = ORRWrs $wzr, $wzr, 0
     RET undef $lr, implicit $w0
 ...
 ---
 name:            br_abz
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: br_abz:
   bb.0.entry:
     successors: %bb.2, %bb.1
     liveins: $w2
     $x8 = ADRP target-flags(aarch64-page) @ptr_abz
     renamable $x8 = ADDXri $x8, target-flags(aarch64-pageoff, aarch64-nc) @ptr_abz, 0
     renamable $x8 = LDRXroW killed renamable $x8, killed renamable $w2, 1, 1
     BRAAZ killed renamable $x8
   ; CHECK:       braaz x8
   ; ISBDSB-NEXT: dsb sy
   ; ISBDSB-NEXT: isb
   ; SB-NEXT:     {{ sb$}}
 
-  bb.1.l2 (address-taken):
+  bb.1.l2 (blockaddress-target):
     renamable $w0 = MOVZWi 1, 0
     RET undef $lr, implicit $w0
 
-  bb.2.return (address-taken):
+  bb.2.return (blockaddress-target):
     $w0 = ORRWrs $wzr, $wzr, 0
     RET undef $lr, implicit $w0
 ...

llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir

 ...
 ---
 name:            fn1
 alignment:       2
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: fn1
   ; CHECK: bb.0:
-  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
-  ; CHECK:   liveins: $r0, $r1, $r2, $r4, $lr
-  ; CHECK:   $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $lr
-  ; CHECK:   t2CMPri killed renamable $r2, 34, 14 /* CC::al */, $noreg, implicit-def $cpsr
-  ; CHECK:   $r0 = t2MOVi 2, 1 /* CC::ne */, $cpsr, $noreg
-  ; CHECK:   $r0 = t2MOVi 3, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed $r0
-  ; CHECK:   tBL 14 /* CC::al */, $noreg, @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def dead $r0
-  ; CHECK:   t2CMPri $sp, 34, 14 /* CC::al */, $noreg, implicit-def $cpsr
-  ; CHECK:   t2Bcc %bb.2, 1 /* CC::ne */, $cpsr
-  ; CHECK:   t2Bcc %bb.2, 2 /* CC::hs */, killed $cpsr
-  ; CHECK:   t2B %bb.1, 14 /* CC::al */, $noreg
-  ; CHECK: bb.1:
-  ; CHECK:   INLINEASM &"", 1
-  ; CHECK:   $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
-  ; CHECK: bb.2.l_yes (address-taken):
-  ; CHECK:   $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $r0, $r1, $r2, $r4, $lr
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $lr
+  ; CHECK-NEXT:   t2CMPri killed renamable $r2, 34, 14 /* CC::al */, $noreg, implicit-def $cpsr
+  ; CHECK-NEXT:   $r0 = t2MOVi 2, 1 /* CC::ne */, $cpsr, $noreg
+  ; CHECK-NEXT:   $r0 = t2MOVi 3, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed $r0
+  ; CHECK-NEXT:   tBL 14 /* CC::al */, $noreg, @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def dead $r0
+  ; CHECK-NEXT:   t2CMPri $sp, 34, 14 /* CC::al */, $noreg, implicit-def $cpsr
+  ; CHECK-NEXT:   t2Bcc %bb.2, 1 /* CC::ne */, $cpsr
+  ; CHECK-NEXT:   t2Bcc %bb.2, 2 /* CC::hs */, killed $cpsr
+  ; CHECK-NEXT:   t2B %bb.1, 14 /* CC::al */, $noreg
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */
+  ; CHECK-NEXT:   $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.l_yes (blockaddress-target):
+  ; CHECK-NEXT:   $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $r0, $r1, $r2, $r4, $lr
 
     $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $lr
     t2CMPri killed renamable $r2, 34, 14, $noreg, implicit-def $cpsr
     t2Bcc %bb.2, 1, killed $cpsr
 
bb.2:
     t2Bcc %bb.4, 1, $cpsr
     t2Bcc %bb.4, 2, killed $cpsr
     t2B %bb.3, 14, $noreg
 
   bb.3:
     INLINEASM &"", 1
     $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc
 
-  bb.4.l_yes (address-taken):
+  bb.4.l_yes (blockaddress-target):
     $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc
 
 ...

llvm/test/CodeGen/ARM/ifcvt-size.mir

bb.3.if.else:
     liveins: $r1, $r2
 
     renamable $r0 = tLDRi killed renamable $r1, 0, 14, $noreg
     renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg
     renamable $r0 = t2LDRSHi12 killed renamable $r0, 0, 14, $noreg
     INLINEASM_BR &"b ${0:l}", 1, 13, blockaddress(@fn9, %ir-block.lab1)
     tBX_RET 14, $noreg, implicit $r2
     
-  bb.5.lab1 (address-taken):
+  bb.5.lab1 (blockaddress-target):
     liveins: $r0
 
     renamable $r0, dead $cpsr = nsw tADDi8 killed renamable $r0, 5, 14, $noreg
     tBX_RET 14, $noreg, implicit $r0
 ...

llvm/test/CodeGen/Hexagon/bank-conflict.mir

bb.0:
     successors: %bb.1(0x80000000)
     liveins: $r0:0x00000001
 
     $r3 = A2_tfrsi 0
     $r2 = A2_tfrsi -121502345
     $r4 = A2_tfrsi 10
     J2_loop0r %bb.1, killed $r0, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
 
-  bb.1 (address-taken):
+  bb.1 (mbb-label-used):
     successors: %bb.2(0x80000000)
     liveins: $lc0:0x00000004, $r2:0x00000001, $r3:0x00000001, $r4:0x00000001, $sa0:0x00000004
 
     $r5 = M2_mpysip $r3, 1824
     $r7 = L2_loadrigp @g2, implicit $gp :: (dereferenceable load (s32) from @g2)
     $r8 = L2_loadrigp @g3, implicit killed $gp :: (dereferenceable load (s32) from @g3, align 8)
     $r6 = A2_tfr $r5
     $r7 = A2_and killed $r8, killed $r7

llvm/test/CodeGen/Hexagon/hwloop-redef-imm.mir

 # RUN: llc -march=hexagon -run-pass hwloops %s -o - | FileCheck %s
 
 # Normally, if the registers holding the induction variable's bounds
 # are redefined inside of the loop's body, the loop cannot be converted
 # to a hardware loop. However, if the redefining instruction is actually
 # loading an immediate value into the register, this conversion is both
 # possible and legal (since the immediate itself will be used in the
 # loop setup in the preheader).
 
 # CHECK:  [[R0:%[0-9]+]]:intregs = A2_tfrsi 1920
 # CHECK:  J2_loop0r %bb.1, [[R0]]
 #
-# CHECK: bb.1.b1 (address-taken):
+# CHECK: bb.1.b1 (mbb-label-used):
 # CHECK:   ENDLOOP0 %bb.1
 
 
 --- |
   define void @fred() {
   b0:
     br label %b1
   b1:

llvm/test/CodeGen/Hexagon/loop_correctness.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=hexagon -O3 -hexagon-instsimplify=0 < %s | FileCheck %s
 
 define void @f0(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
 ; CHECK-LABEL: f0:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     loop0(.LBB0_1,#3)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp0: // Block address taken
-; CHECK-NEXT:  .LBB0_1: // %b2
+; CHECK-NEXT:  .LBB0_1: // Block address taken
+; CHECK-NEXT:    // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     nop
 ; CHECK-NEXT:     nop
 ; CHECK-NEXT:    } :endloop0
 ; CHECK-NEXT:  // %bb.2: // %b3
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     jumpr r31

 
 define void @f1(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
 ; CHECK-LABEL: f1:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     loop0(.LBB1_1,#2)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp1: // Block address taken
-; CHECK-NEXT:  .LBB1_1: // %b2
+; CHECK-NEXT:  .LBB1_1: // Block address taken
+; CHECK-NEXT:    // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     nop
 ; CHECK-NEXT:     nop
 ; CHECK-NEXT:    } :endloop0
 ; CHECK-NEXT:  // %bb.2: // %b3
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     jumpr r31

 
 define void @f2(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
 ; CHECK-LABEL: f2:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     loop0(.LBB2_1,#1)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp2: // Block address taken
-; CHECK-NEXT:  .LBB2_1: // %b2
+; CHECK-NEXT:  .LBB2_1: // Block address taken
+; CHECK-NEXT:    // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     nop
 ; CHECK-NEXT:     nop
 ; CHECK-NEXT:    } :endloop0
 ; CHECK-NEXT:  // %bb.2: // %b3
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     jumpr r31

 
 define void @f3(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
 ; CHECK-LABEL: f3:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     loop0(.LBB3_1,#4)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp3: // Block address taken
-; CHECK-NEXT:  .LBB3_1: // %b2
+; CHECK-NEXT:  .LBB3_1: // Block address taken
+; CHECK-NEXT:    // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     nop
 ; CHECK-NEXT:     nop
 ; CHECK-NEXT:    } :endloop0
 ; CHECK-NEXT:  // %bb.2: // %b3
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     jumpr r31

 
 define void @f4(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
 ; CHECK-LABEL: f4:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     loop0(.LBB4_1,#2)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp4: // Block address taken
-; CHECK-NEXT:  .LBB4_1: // %b2
+; CHECK-NEXT:  .LBB4_1: // Block address taken
+; CHECK-NEXT:    // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     nop
 ; CHECK-NEXT:     nop
 ; CHECK-NEXT:    } :endloop0
 ; CHECK-NEXT:  // %bb.2: // %b3
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     jumpr r31

 
 define void @f5(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
 ; CHECK-LABEL: f5:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     loop0(.LBB5_1,#2)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp5: // Block address taken
-; CHECK-NEXT:  .LBB5_1: // %b2
+; CHECK-NEXT:  .LBB5_1: // Block address taken
+; CHECK-NEXT:    // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     nop
 ; CHECK-NEXT:     nop
 ; CHECK-NEXT:    } :endloop0
 ; CHECK-NEXT:  // %bb.2: // %b3
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     jumpr r31

llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir

body:             |
 
   bb.2.b2.preheader:
     successors: %bb.3(0x80000000)
 
     %10:intregs = IMPLICIT_DEF
     %14:intregs = COPY %10
     J2_loop0r %bb.3, %14, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
 
-  bb.3.b2 (address-taken):
+  bb.3.b2 (mbb-label-used):
     successors: %bb.3(0x7c000000), %bb.4(0x04000000)
 
     %1:intregs = PHI %7, %bb.2, %5, %bb.3, post-instr-symbol <mcsymbol Stage-3_Cycle-0>
     %2:intregs = PHI %10, %bb.2, %4, %bb.3, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
     %3:intregs = PHI %6, %bb.2, %2, %bb.3, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
     %11:intregs = S2_addasl_rrri %7, %3, 1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
     %12:intregs = L2_loadruh_io %11, -4, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (load (s16) from %ir.cgep2, !tbaa !0)
     %5:intregs = S2_storerh_pi %1, -2, %12, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (store (s16) into %ir.lsr.iv, !tbaa !0)
     %4:intregs = nsw A2_addi %2, -1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
     ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
     J2_jump %bb.4, implicit-def dead $pc
 
   bb.4.b3:
     PS_jmpret $r31, implicit-def dead $pc
 
 ...

llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir

bb.1:
 
     %0:intregs = A2_addi %14, -2
     %1:intregs = A2_addi %12, 10
     %2:intregs = A2_addi %13, 4
     %17:intregs = A2_tfrsi 0
     %23:intregs = COPY %0
     J2_loop0r %bb.2, %23, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
 
-  bb.2 (address-taken):
+  bb.2 (mbb-label-used):
     successors: %bb.3, %bb.2
 
     %3:intregs = PHI %2, %bb.1, %10, %bb.2
     %4:intregs = PHI %1, %bb.1, %9, %bb.2
     %6:intregs = PHI %17, %bb.1, %7, %bb.2
     %18:intregs, %10:intregs = L2_loadrh_pi %3, 2 :: (load (s16) from %ir.lsr.iv7)
     %19:intregs = L2_loadrh_io %4, -8 :: (load (s16) from %ir.cgep10)
     %20:intregs = A2_addi %18, 10

llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir

 body:             |
   bb.0:
     successors: %bb.1
 
     %10:intregs = IMPLICIT_DEF
     %11:intregs = IMPLICIT_DEF
     J2_loop0i %bb.1, 6, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
 
-  bb.1 (address-taken):
+  bb.1 (mbb-label-used):
     successors: %bb.1, %bb.2
 
     %0:intregs = PHI %11, %bb.0, %6, %bb.1
     %2:intregs = PHI %10, %bb.0, %4, %bb.1
     %3:intregs = PHI %10, %bb.0, %2, %bb.1
     %4:intregs = L2_loadri_io %0, -8 :: (load (s32) from %ir.cgep)
     %12:intregs = A2_subsat %3, %4, implicit-def dead $usr_ovf
     S2_storeri_io %0, 0, %12 :: (store (s32) into %ir.lsr.iv1)
     %6:intregs = A2_addi %0, -4
     ENDLOOP0 %bb.1, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
     J2_jump %bb.2, implicit-def dead $pc
 
   bb.2:
 
 ...

llvm/test/CodeGen/MIR/Generic/basic-blocks.mir

 name:            foo
 body: |
   bb.0.entry:
 ...
 ---
 # CHECK-LABEL: name: bar
 # CHECK: body:
 # CHECK-NEXT: bb.0.start (align 4):
-# CHECK:      bb.1 (address-taken):
+# CHECK:      bb.1 (mbb-label-used):
 name:            bar
 body: |
   bb.0.start (align 4):
-  bb.1 (address-taken):
+  bb.1 (mbb-label-used):
 ...
 ---
 # CHECK-LABEL: name: test
 # CHECK: body:
-# CHECK-NEXT: bb.0.start (address-taken, align 4):
-# CHECK:      bb.1 (address-taken, align 4):
+# CHECK-NEXT: bb.0.start (mbb-label-used, align 4):
+# CHECK:      bb.1 (mbb-label-used, align 4):
 name:            test
 body: |
-  bb.0.start (align 4, address-taken):
-  bb.1 (address-taken, align 4):
+  bb.0.start (align 4, mbb-label-used):
+  bb.1 (mbb-label-used, align 4):
 ...

llvm/test/CodeGen/MIR/X86/block-address-operands.mir

 body: |
   bb.0.entry:
     successors: %bb.1.block
   ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test, %ir-block.block), $noreg
     $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.block), _
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1.block (address-taken):
+  bb.1.block (blockaddress-target):
     RET64
 ...
 ---
 name:            test2
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     successors: %bb.1
   ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test2, %ir-block."quoted block"), $noreg
     $rax = LEA64r $rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1 (address-taken):
+  bb.1 (%ir-block."quoted block", blockaddress-target):
     RET64
 ...
 ---
 name:            slot_in_other_function
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $rdi
body: |
   bb.0.entry:
     successors: %bb.1
   ; CHECK-LABEL: name: test3
   ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test3, %ir-block.0), $noreg
     $rax = LEA64r $rip, 1, _, blockaddress(@test3, %ir-block.0), _
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1 (address-taken):
+  bb.1 (%ir-block.0, blockaddress-target):
     RET64
 ...
 ---
 name:            test4
 body: |
   bb.0.entry:
     successors: %bb.1.block
   ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test, %ir-block.block) + 2, $noreg
     $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1.block (address-taken):
+  bb.1.block (blockaddress-target):
     RET64
 ...

llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+#
 
 --- |
 
   @addr = global i8* null
 
   define void @test() {
   entry:
     store volatile i8* blockaddress(@test, %block), i8** @addr

 body: |
   bb.0.entry:
     successors: %bb.1.block
     ; CHECK: [[@LINE+1]]:51: expected an IR block reference
     $rax = LEA64r $rip, 1, _, blockaddress(@test, _), _
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1.block (address-taken):
+  bb.1.block (blockaddress-target):
     RET64
 ...

llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir

 body: |
   bb.0.entry:
     successors: %bb.1.block
     ; CHECK: [[@LINE+1]]:44: expected an IR function reference
     $rax = LEA64r $rip, 1, _, blockaddress(@addr, %ir-block.block), _
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1.block (address-taken):
+  bb.1.block (blockaddress-target):
     RET64
 ...

llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir

 body: |
   bb.0.entry:
     successors: %bb.1.block
     ; CHECK: [[@LINE+1]]:44: expected a global value
     $rax = LEA64r $rip, 1, _, blockaddress(0, %ir-block.block), _
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1.block (address-taken):
+  bb.1.block (blockaddress-target):
     RET64
 ...

llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir

 body: |
   bb.0.entry:
     successors: %bb.1.block
     ; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block."block "'
     $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block."block "), _
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1.block (address-taken):
+  bb.1.block (blockaddress-target):
     RET64
 ...

llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir

 body: |
   bb.0.entry:
     successors: %bb.1
     ; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block.1'
     $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.1), _
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1 (address-taken):
+  bb.1 (blockaddress-target):
     RET64
 ...

llvm/test/CodeGen/X86/callbr-asm-kill.mir

body:             |
   ; CHECK: bb.0.entry:
   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
   ; CHECK-NEXT:   liveins: $rdi, $rsi
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr64 = COPY killed $rsi
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr64 = COPY killed $rdi
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr64 = COPY killed [[COPY1]]
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT: bb.1.loop (address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT: bb.1.loop (blockaddress-target, inlineasm-br-indirect-target):
   ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gr64 = COPY killed [[COPY2]]
   ; CHECK-NEXT:   [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.mem)
   ; CHECK-NEXT:   ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
   ; CHECK-NEXT:   $rdi = COPY killed [[COPY3]]
   ; CHECK-NEXT:   CALL64pcrel32 target-flags(x86-plt) @foo, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp
   ; CHECK-NEXT:   ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
   ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gr64 = COPY [[MOV64rm]]
   ; CHECK-NEXT:   INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 196654 /* mem:m */, killed [[MOV64rm]], 1, $noreg, 0, $noreg, 13 /* imm */, blockaddress(@test1, %ir-block.loop)
   ; CHECK-NEXT:   JMP_1 %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2.end:
   ; CHECK-NEXT:   RET 0
   bb.0.entry:
     liveins: $rdi, $rsi
 
     %3:gr64 = COPY killed $rsi
     %2:gr64 = COPY killed $rdi
 
-  bb.1.loop (address-taken, inlineasm-br-indirect-target):
+  bb.1.loop (blockaddress-target, inlineasm-br-indirect-target):
     successors: %bb.2(0x80000000), %bb.1(0x00000000)
 
     %0:gr64 = PHI %2, %bb.0, %1, %bb.1
     %1:gr64 = MOV64rm %3, 1, $noreg, 0, $noreg :: (load (s64) from %ir.mem)
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     $rdi = COPY killed %0
     CALL64pcrel32 target-flags(x86-plt) @foo, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 196654 /* mem:m */, %1, 1, $noreg, 0, $noreg, 13 /* imm */, blockaddress(@test1, %ir-block.loop)
     JMP_1 %bb.2
 
   bb.2.end:
     RET 0
 
 ...

llvm/test/CodeGen/X86/callbr-asm-outputs-pred-succ.ll

 ; The fallthrough is a block containing a second INLINEASM_BR. Check it has two successors,
 ; and the the probability for fallthrough is 100%.
 ; CHECK: bb.1 (%ir-block.4):
 ; CHECK-NEXT: predecessors: %bb.0
 ; CHECK-NEXT: successors: %bb.3(0x80000000), %bb.2(0x00000000); %bb.3(100.00%), %bb.2(0.00%)
 
 ; Check the second INLINEASM_BR target block is preceded by the block with the
 ; second INLINEASM_BR.
-; CHECK: bb.2 (%ir-block.7, address-taken, inlineasm-br-indirect-target):
+; CHECK: bb.2 (%ir-block.7, blockaddress-target, inlineasm-br-indirect-target):
 ; CHECK-NEXT: predecessors: %bb.1
 
 ; Check the first INLINEASM_BR target block is predecessed by the block with
 ; the first INLINEASM_BR.
-; CHECK: bb.4 (%ir-block.11, address-taken, inlineasm-br-indirect-target):
+; CHECK: bb.4 (%ir-block.11, blockaddress-target, inlineasm-br-indirect-target):
 ; CHECK-NEXT: predecessors: %bb.0
 
 @.str = private unnamed_addr constant [26 x i8] c"inline asm#1 returned %d\0A\00", align 1
 @.str.2 = private unnamed_addr constant [26 x i8] c"inline asm#2 returned %d\0A\00", align 1
 @str = private unnamed_addr constant [30 x i8] c"inline asm#1 caused exception\00", align 1
 @str.4 = private unnamed_addr constant [30 x i8] c"inline asm#2 caused exception\00", align 1
 
 ; Function Attrs: nounwind uwtable

llvm/test/CodeGen/X86/tail-dup-asm-goto.ll

 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -mtriple=x86_64-linux -stop-after=early-tailduplication < %s | FileCheck %s
 
 ; Ensure that we don't duplicate a block with an "INLINEASM_BR" instruction
 ; during code gen.
 declare dso_local void @foo()
 
 define i8* @test1(i8** %arg1, i8* %arg2) {
   ; CHECK-LABEL: name: test1
   ; CHECK: bb.0.bb:
-  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
-  ; CHECK:   liveins: $rdi, $rsi
-  ; CHECK:   [[COPY:%[0-9]+]]:gr64 = COPY $rsi
-  ; CHECK:   [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
-  ; CHECK:   [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.arg1)
-  ; CHECK:   [[SUB64rr:%[0-9]+]]:gr64 = SUB64rr [[MOV64rm]], [[COPY]], implicit-def $eflags
-  ; CHECK:   JCC_1 %bb.2, 4, implicit $eflags
-  ; CHECK:   JMP_1 %bb.1
-  ; CHECK: bb.1.bb100:
-  ; CHECK:   successors: %bb.3(0x80000000)
-  ; CHECK:   MOV64mi32 [[COPY1]], 1, $noreg, 0, $noreg, 0 :: (store (s64) into %ir.arg1)
-  ; CHECK:   JMP_1 %bb.3
-  ; CHECK: bb.2.bb106:
-  ; CHECK:   successors: %bb.3(0x80000000)
-  ; CHECK:   ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
-  ; CHECK:   CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp
-  ; CHECK:   ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
-  ; CHECK: bb.3.bb110:
-  ; CHECK:   successors: %bb.5(0x80000000), %bb.4(0x00000000)
-  ; CHECK:   [[PHI:%[0-9]+]]:gr64 = PHI [[COPY]], %bb.2, [[MOV64rm]], %bb.1
-  ; CHECK:   INLINEASM_BR &"#$0 $1 $2", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 42, 13 /* imm */, 0, 13 /* imm */, blockaddress(@test1, %ir-block.bb17.i.i.i), 12 /* clobber */, implicit-def early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def early-clobber $eflags
-  ; CHECK:   JMP_1 %bb.5
-  ; CHECK: bb.4.bb17.i.i.i (address-taken, inlineasm-br-indirect-target):
-  ; CHECK:   successors: %bb.5(0x80000000)
-  ; CHECK: bb.5.kmem_cache_has_cpu_partial.exit:
-  ; CHECK:   $rax = COPY [[PHI]]
-  ; CHECK:   RET 0, $rax
+  ; CHECK-NEXT:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK-NEXT:   liveins: $rdi, $rsi
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr64 = COPY $rsi
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+  ; CHECK-NEXT:   [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.arg1)
+  ; CHECK-NEXT:   [[SUB64rr:%[0-9]+]]:gr64 = SUB64rr [[MOV64rm]], [[COPY]], implicit-def $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.2, 4, implicit $eflags
+  ; CHECK-NEXT:   JMP_1 %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.bb100:
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   MOV64mi32 [[COPY1]], 1, $noreg, 0, $noreg, 0 :: (store (s64) into %ir.arg1)
+  ; CHECK-NEXT:   JMP_1 %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.bb106:
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+  ; CHECK-NEXT:   CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp
+  ; CHECK-NEXT:   ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.bb110:
+  ; CHECK-NEXT:   successors: %bb.5(0x80000000), %bb.4(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gr64 = PHI [[COPY]], %bb.2, [[MOV64rm]], %bb.1
+  ; CHECK-NEXT:   INLINEASM_BR &"#$0 $1 $2", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 42, 13 /* imm */, 0, 13 /* imm */, blockaddress(@test1, %ir-block.bb17.i.i.i), 12 /* clobber */, implicit-def early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def early-clobber $eflags
+  ; CHECK-NEXT:   JMP_1 %bb.5
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4.bb17.i.i.i (blockaddress-target, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.5(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.5.kmem_cache_has_cpu_partial.exit:
+  ; CHECK-NEXT:   $rax = COPY [[PHI]]
+  ; CHECK-NEXT:   RET 0, $rax
 bb:
   %i28.i = load i8*, i8** %arg1, align 8
   %if = icmp ne i8* %i28.i, %arg2
   br i1 %if, label %bb100, label %bb106
 
 bb100:                                            ; preds = %bb
   store i8* null, i8** %arg1, align 8
   br label %bb110

llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir

body:             |
   bb.5.if.end6:
     successors: %bb.6(0x00000001), %bb.8(0x7fffffff)
     liveins: $r8b
 
     MOV32mi $rbp, 1, $noreg, -12, $noreg, 0 :: (store (s32) into %stack.0)
     TEST8rr killed renamable $r8b, renamable $r8b, implicit-def $eflags
     JCC_1 %bb.6, 5, implicit $eflags
 
-  bb.8.return (address-taken):
+  bb.8.return (mbb-label-used):
     $eax = MOV32rm $rbp, 1, $noreg, -12, $noreg :: (load (s32) from %stack.0)
     SEH_Epilogue
     $rsp = frame-destroy ADD64ri8 $rsp, 48, implicit-def dead $eflags
     $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp
     RET64 $eax
 
   bb.1.if.then:
     successors: %bb.2(0x7ffff800), %bb.7(0x00000800)

llvm/test/tools/llvm-reduce/mir/preserve-block-info.mir

 # REQUIRES: amdgpu-registered-target
 # RUN: llvm-reduce -simplify-mir --delta-passes=instructions -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
 # RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
 
 # CHECK-INTERESTINGNESS: V_MOV_B32
 
 
 # RESULT: bb.0.entry:
 # RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 
-# RESULT: bb.1 (address-taken, align 8):
+# RESULT: bb.1 (blockaddress-target, align 8):
 # RESULT: bb.2 (landing-pad, align 16):
 # RESULT: bb.3 (inlineasm-br-indirect-target):
 # RESULT: bb.4 (ehfunclet-entry):
 # RESULT: bb.5 (bbsections 1):
 # RESULT: bb.6 (bbsections 2):
 # RESULT: bb.7 (bbsections 3):
 # RESULT: bb.8:
 # RESULT-NEXT: successors: %bb.9(0x66666666), %bb.10(0x1999999a)

 hasWinCFI:       true
 failsVerification: true
 tracksDebugUserValues: true
 body:             |
   bb.0.entry:
     S_NOP 0
     %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 
-  bb.1 (address-taken, align 8):
+  bb.1 (blockaddress-target, align 8):
 
   bb.2 (landing-pad, align 16):
 
   bb.3 (inlineasm-br-indirect-target):
 
   bb.4 (ehfunclet-entry):
 
   bb.5 (bbsections 1):

llvm/tools/llvm-reduce/ReducerWorkItem.cpp

static std::unique_ptr<MachineFunction> cloneMF(MachineFunction *SrcMF,
   auto *DstMRI = &DstMF->getRegInfo();
 
   // Clone blocks.
   for (MachineBasicBlock &SrcMBB : *SrcMF) {
     MachineBasicBlock *DstMBB =
         DstMF->CreateMachineBasicBlock(SrcMBB.getBasicBlock());
     Src2DstMBB[&SrcMBB] = DstMBB;
 
-    if (SrcMBB.hasAddressTaken())
-      DstMBB->setHasAddressTaken();
+    if (SrcMBB.isBlockAddressTarget())
+      DstMBB->setIsBlockAddressTarget();
+    if (SrcMBB.isMBBLabelUsed())
+      DstMBB->setMBBLabelUsed();
 
     // FIXME: This is not serialized
     if (SrcMBB.hasLabelMustBeEmitted())
       DstMBB->setLabelMustBeEmitted();
 
     DstMBB->setAlignment(SrcMBB.getAlignment());
 
     // FIXME: This is not serialized