[NFC][MachineFunction] Rename APIs to conform to coding style

[mtrofin]

Summary

Function names should start with lowercase, so renamed accordingly.

[jrtc27]

Is this really worth it? It's churn for downstreams, and has little gain given this is a drop in the ocean for old code style. The LLVM Coding Standards also say:

[...] we explicitly do not want patches that do large-scale reformatting of existing code. On the other hand, it is reasonable to rename the methods of a class if you’re about to change it in some other way. Please commit such changes separately to make code review easier.

so, unless you're planning large-scale refactoring of the APIs (which seems unlikely), that reads to me as "don't".

[mtrofin]

In D115217#3175465, @jrtc27 wrote:

Is this really worth it? It's churn for downstreams, and has little gain given this is a drop in the ocean for old code style. The LLVM Coding Standards also say:

[...] we explicitly do not want patches that do large-scale reformatting of existing code. On the other hand, it is reasonable to rename the methods of a class if you’re about to change it in some other way. Please commit such changes separately to make code review easier.

so, unless you're planning large-scale refactoring of the APIs (which seems unlikely), that reads to me as "don't".

It was *very* easy to do (straight-forward, automated refactoring), so I figured I'd put it up see what people think. I wasn't aware of the explicit pushback against large-scale refactorings (thanks for pointing that out!). I can definitely piecemeal it.

Unless I'm missing something, I'm not sure how to think about the downstream aspect, nor the relative amount of old/new code styles. I could see those arguments raised vis-a-vis any API refactoring patch, and IIRC, we've generally been doing API cleanups.

[foad]

In D115217#3175465, @jrtc27 wrote:

Is this really worth it? It's churn for downstreams, and has little gain given this is a drop in the ocean for old code style. The LLVM Coding Standards also say:

Just to put the opposite point of view, I'm quite happy with refactoring patches like this, even though I also have to deal with downstream merge conflicts.

It would be a bit easier to resolve any conflicts if you could say exactly how you made these changes -- hopefully the answer is something simple like "I just ran git clang-format"!

llvm/include/llvm/CodeGen/MachineFunction.h

public:
   }
 
   /// Should we be emitting segmented stack stuff for the function
   bool shouldSplitStack() const;
 
   /// getNumBlockIDs - Return the number of MBB ID's allocated.
   unsigned getNumBlockIDs() const { return (unsigned)MBBNumbering.size(); }
 
-  /// RenumberBlocks - This discards all of the MachineBasicBlock numbers and
+  /// renumberBlocks - This discards all of the MachineBasicBlock numbers and
   /// recomputes them.  This guarantees that the MBB numbers are sequential,
   /// dense, and match the ordering of the blocks within the function.  If a
   /// specific MachineBasicBlock is specified, only that block and those after
   /// it are renumbered.
-  void RenumberBlocks(MachineBasicBlock *MBBFrom = nullptr);
+  void renumberBlocks(MachineBasicBlock *MBBFrom = nullptr);
 
   /// print - Print out the MachineFunction in a format suitable for debugging
   /// to the specified stream.
   void print(raw_ostream &OS, const SlotIndexes* = nullptr) const;
 
   /// viewCFG - This function is meant for use from the debugger.  You can just
   /// say 'call F->viewCFG()' and a ghostview window should pop up from the
   /// program, displaying the CFG of the current function with the code for each
public:
   /// removeFromMBBNumbering - Remove the specific machine basic block from our
   /// tracker, this is only really to be used by the MachineBasicBlock
   /// implementation.
   void removeFromMBBNumbering(unsigned N) {
     assert(N < MBBNumbering.size() && "Illegal basic block #");
     MBBNumbering[N] = nullptr;
   }
 
-  /// CreateMachineInstr - Allocate a new MachineInstr. Use this instead
+  /// createMachineInstr - Allocate a new MachineInstr. Use this instead
   /// of `new MachineInstr'.
-  MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL,
+  MachineInstr *createMachineInstr(const MCInstrDesc &MCID, DebugLoc DL,
                                    bool NoImplicit = false);
 
   /// Create a new MachineInstr which is a copy of \p Orig, identical in all
   /// ways except the instruction has no parent, prev, or next. Bundling flags
   /// are reset.
   ///
   /// Note: Clones a single instruction, not whole instruction bundles.
   /// Does not perform target specific adjustments; consider using
   /// TargetInstrInfo::duplicate() instead.
-  MachineInstr *CloneMachineInstr(const MachineInstr *Orig);
+  MachineInstr *cloneMachineInstr(const MachineInstr *Orig);
 
   /// Clones instruction or the whole instruction bundle \p Orig and insert
   /// into \p MBB before \p InsertBefore.
   ///
   /// Note: Does not perform target specific adjustments; consider using
   /// TargetInstrInfo::duplicate() intead.
-  MachineInstr &CloneMachineInstrBundle(MachineBasicBlock &MBB,
-      MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig);
+  MachineInstr &
+  cloneMachineInstrBundle(MachineBasicBlock &MBB,
+                          MachineBasicBlock::iterator InsertBefore,
+                          const MachineInstr &Orig);
 
-  /// DeleteMachineInstr - Delete the given MachineInstr.
-  void DeleteMachineInstr(MachineInstr *MI);
+  /// deleteMachineInstr - Delete the given MachineInstr.
+  void deleteMachineInstr(MachineInstr *MI);
 
-  /// CreateMachineBasicBlock - Allocate a new MachineBasicBlock. Use this
+  /// createMachineBasicBlock - Allocate a new MachineBasicBlock. Use this
   /// instead of `new MachineBasicBlock'.
-  MachineBasicBlock *CreateMachineBasicBlock(const BasicBlock *bb = nullptr);
+  MachineBasicBlock *createMachineBasicBlock(const BasicBlock *bb = nullptr);
 
-  /// DeleteMachineBasicBlock - Delete the given MachineBasicBlock.
-  void DeleteMachineBasicBlock(MachineBasicBlock *MBB);
+  /// deleteMachineBasicBlock - Delete the given MachineBasicBlock.
+  void deleteMachineBasicBlock(MachineBasicBlock *MBB);
 
   /// getMachineMemOperand - Allocate a new MachineMemOperand.
   /// MachineMemOperands are owned by the MachineFunction and need not be
   /// explicitly deallocated.
   MachineMemOperand *getMachineMemOperand(
       MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s,
       Align base_alignment, const AAMDNodes &AAInfo = AAMDNodes(),
       const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,

llvm/include/llvm/CodeGen/MachineInstr.h

private:
 
   void
   dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
             SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
 
 public:
   MachineInstr(const MachineInstr &) = delete;
   MachineInstr &operator=(const MachineInstr &) = delete;
-  // Use MachineFunction::DeleteMachineInstr() instead.
+  // Use MachineFunction::deleteMachineInstr() instead.
   ~MachineInstr() = delete;
 
   const MachineBasicBlock* getParent() const { return Parent; }
   MachineBasicBlock* getParent() { return Parent; }
 
   /// Move the instruction before \p MovePos.
   void moveBefore(MachineInstr *MovePos);
 

llvm/include/llvm/CodeGen/MachineInstrBuilder.h

bool constrainAllUses(const TargetInstrInfo &TII,
                         const RegisterBankInfo &RBI) const {
     return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
   }
 };
 
 /// Builder interface. Specify how to create the initial instruction itself.
 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
                                    const MCInstrDesc &MCID) {
-  return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
+  return MachineInstrBuilder(MF, MF.createMachineInstr(MCID, DL));
 }
 
 /// This version of the builder sets up the first operand as a
 /// destination virtual register.
 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
                                    const MCInstrDesc &MCID, Register DestReg) {
-  return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
-           .addReg(DestReg, RegState::Define);
+  return MachineInstrBuilder(MF, MF.createMachineInstr(MCID, DL))
 }
 
 /// This version of the builder inserts the newly-built instruction before
 /// the given position in the given MachineBasicBlock, and sets up the first
 /// operand as a destination virtual register.
 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                    MachineBasicBlock::iterator I,
                                    const DebugLoc &DL, const MCInstrDesc &MCID,
                                    Register DestReg) {
   MachineFunction &MF = *BB.getParent();
-  MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
+  MachineInstr *MI = MF.createMachineInstr(MCID, DL);
   BB.insert(I, MI);
   return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
 }
 
 /// This version of the builder inserts the newly-built instruction before
 /// the given position in the given MachineBasicBlock, and sets up the first
 /// operand as a destination virtual register.
 ///
 /// If \c I is inside a bundle, then the newly inserted \a MachineInstr is
 /// added to the same bundle.
 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                    MachineBasicBlock::instr_iterator I,
                                    const DebugLoc &DL, const MCInstrDesc &MCID,
                                    Register DestReg) {
   MachineFunction &MF = *BB.getParent();
-  MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
+  MachineInstr *MI = MF.createMachineInstr(MCID, DL);
   BB.insert(I, MI);
   return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
 }
 
 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
                                    const DebugLoc &DL, const MCInstrDesc &MCID,
                                    Register DestReg) {
   // Calling the overload for instr_iterator is always correct.  However, the

 /// This version of the builder inserts the newly-built instruction before the
 /// given position in the given MachineBasicBlock, and does NOT take a
 /// destination register.
 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                    MachineBasicBlock::iterator I,
                                    const DebugLoc &DL,
                                    const MCInstrDesc &MCID) {
   MachineFunction &MF = *BB.getParent();
-  MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
+  MachineInstr *MI = MF.createMachineInstr(MCID, DL);
   BB.insert(I, MI);
   return MachineInstrBuilder(MF, MI);
 }
 
 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                    MachineBasicBlock::instr_iterator I,
                                    const DebugLoc &DL,
                                    const MCInstrDesc &MCID) {
   MachineFunction &MF = *BB.getParent();
-  MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
+  MachineInstr *MI = MF.createMachineInstr(MCID, DL);
   BB.insert(I, MI);
   return MachineInstrBuilder(MF, MI);
 }
 
 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
                                    const DebugLoc &DL,
                                    const MCInstrDesc &MCID) {
   // Calling the overload for instr_iterator is always correct.  However, the

llvm/lib/CodeGen/BasicBlockSections.cpp

bool BasicBlockSections::runOnMachineFunction(MachineFunction &MF) {
   if (BBSectionsType == BasicBlockSection::List &&
       hasInstrProfHashMismatch(MF))
     return true;
 
   // Renumber blocks before sorting them for basic block sections.  This is
   // useful during sorting, basic blocks in the same section will retain the
   // default order.  This renumbering should also be done for basic block
   // labels to match the profiles with the correct blocks.
-  MF.RenumberBlocks();
+  MF.renumberBlocks();
 
   if (BBSectionsType == BasicBlockSection::Labels) {
     MF.setBBSectionsType(BBSectionsType);
     return true;
   }
 
   std::vector<Optional<BBClusterInfo>> FuncBBClusterInfo;
   if (BBSectionsType == BasicBlockSection::List &&

llvm/lib/CodeGen/BranchFolding.cpp

MachineBasicBlock *BranchFolder::SplitMBBAt(MachineBasicBlock &CurMBB,
                                             const BasicBlock *BB) {
   if (!TII->isLegalToSplitMBBAt(CurMBB, BBI1))
     return nullptr;
 
   MachineFunction &MF = *CurMBB.getParent();
 
   // Create the fall-through block.
   MachineFunction::iterator MBBI = CurMBB.getIterator();
-  MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(BB);
+  MachineBasicBlock *NewMBB = MF.createMachineBasicBlock(BB);
   CurMBB.getParent()->insert(++MBBI, NewMBB);
 
   // Move all the successors of this block to the specified block.
   NewMBB->transferSuccessors(&CurMBB);
 
   // Add an edge from CurMBB to NewMBB for the fall-through.
   CurMBB.addSuccessor(NewMBB);
 

 //===----------------------------------------------------------------------===//
 //  Branch Optimization
 //===----------------------------------------------------------------------===//
 
 bool BranchFolder::OptimizeBranches(MachineFunction &MF) {
   bool MadeChange = false;
 
   // Make sure blocks are numbered in order
-  MF.RenumberBlocks();
+  MF.renumberBlocks();
   // Renumbering blocks alters EH scope membership, recalculate it.
   EHScopeMembership = getEHScopeMembership(MF);
 
   for (MachineBasicBlock &MBB :
        llvm::make_early_inc_range(llvm::drop_begin(MF))) {
     MadeChange |= OptimizeBlock(&MBB);
 
     // If it is dead, remove it.

llvm/lib/CodeGen/BranchRelaxation.cpp

for (auto &MBB :
 
     PrevNum = Num;
   }
 }
 
 /// Insert a new empty basic block and insert it after \BB
 MachineBasicBlock *BranchRelaxation::createNewBlockAfter(MachineBasicBlock &BB) {
   // Create a new MBB for the code after the OrigBB.
-  MachineBasicBlock *NewBB =
-      MF->CreateMachineBasicBlock(BB.getBasicBlock());
+  MachineBasicBlock *NewBB = MF->createMachineBasicBlock(BB.getBasicBlock());
   MF->insert(++BB.getIterator(), NewBB);
 
   // Insert an entry into BlockInfo to align it properly with the block numbers.
   BlockInfo.insert(BlockInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
 
   return NewBB;
 }
 
 /// Split the basic block containing MI into two blocks, which are joined by
 /// an unconditional branch.  Update data structures and renumber blocks to
 /// account for this change and returns the newly created block.
 MachineBasicBlock *BranchRelaxation::splitBlockBeforeInstr(MachineInstr &MI,
                                                            MachineBasicBlock *DestBB) {
   MachineBasicBlock *OrigBB = MI.getParent();
 
   // Create a new MBB for the code after the OrigBB.
   MachineBasicBlock *NewBB =
-      MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
+      MF->createMachineBasicBlock(OrigBB->getBasicBlock());
   MF->insert(++OrigBB->getIterator(), NewBB);
 
   // Splice the instructions starting with MI over to NewBB.
   NewBB->splice(NewBB->end(), OrigBB, MI.getIterator(), OrigBB->end());
 
   // Add an unconditional branch from OrigBB to NewBB.
   // Note the new unconditional branch is not being recorded.
   // There doesn't seem to be meaningful DebugInfo available; this doesn't
bool BranchRelaxation::runOnMachineFunction(MachineFunction &mf) {
   TII = ST.getInstrInfo();
 
   TRI = ST.getRegisterInfo();
   if (TRI->trackLivenessAfterRegAlloc(*MF))
     RS.reset(new RegScavenger());
 
   // Renumber all of the machine basic blocks in the function, guaranteeing that
   // the numbers agree with the position of the block in the function.
-  MF->RenumberBlocks();
+  MF->renumberBlocks();
 
   // Do the initial scan of the function, building up information about the
   // sizes of each block.
   scanFunction();
 
   LLVM_DEBUG(dbgs() << "  Basic blocks before relaxation\n"; dumpBBs(););
 
   bool MadeChange = false;

llvm/lib/CodeGen/CodeGenCommonISel.cpp

 MachineBasicBlock *
 StackProtectorDescriptor::addSuccessorMBB(
     const BasicBlock *BB, MachineBasicBlock *ParentMBB, bool IsLikely,
     MachineBasicBlock *SuccMBB) {
   // If SuccBB has not been created yet, create it.
   if (!SuccMBB) {
     MachineFunction *MF = ParentMBB->getParent();
     MachineFunction::iterator BBI(ParentMBB);
-    SuccMBB = MF->CreateMachineBasicBlock(BB);
+    SuccMBB = MF->createMachineBasicBlock(BB);
     MF->insert(++BBI, SuccMBB);
   }
   // Add it as a successor of ParentMBB.
   ParentMBB->addSuccessor(
       SuccMBB, BranchProbabilityInfo::getBranchProbStackProtector(IsLikely));
   return SuccMBB;
 }
 

llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp

for (auto Reg : RegsToReload) {
       }
     }
   }
 
   // Re-write statepoint machine instruction to replace caller saved operands
   // with indirect memory location (frame index).
   MachineInstr *rewriteStatepoint() {
     MachineInstr *NewMI =
-        MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
+        MF.createMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
     MachineInstrBuilder MIB(MF, NewMI);
 
     unsigned NumOps = MI.getNumOperands();
 
     // New indices for the remaining defs.
     SmallVector<unsigned, 8> NewIndices;
     unsigned NumDefs = MI.getNumDefs();
     for (unsigned I = 0; I < NumDefs; ++I) {

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

if (!BOpIsInOrAndTree || BOp->getParent() != CurBB->getBasicBlock() ||
     emitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB, TProb, FProb,
                                  InvertCond);
     return;
   }
 
   //  Create TmpBB after CurBB.
   MachineFunction::iterator BBI(CurBB);
   MachineBasicBlock *TmpBB =
-      MF->CreateMachineBasicBlock(CurBB->getBasicBlock());
+      MF->createMachineBasicBlock(CurBB->getBasicBlock());
   CurBB->getParent()->insert(++BBI, TmpBB);
 
   if (Opc == Instruction::Or) {
     // Codegen X | Y as:
     // BB1:
     //   jmp_if_X TBB
     //   jmp TmpBB
     // TmpBB:
for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
     bool FallthroughUnreachable = false;
     MachineBasicBlock *Fallthrough;
     if (I == W.LastCluster) {
       // For the last cluster, fall through to the default destination.
       Fallthrough = DefaultMBB;
       FallthroughUnreachable = isa<UnreachableInst>(
           DefaultMBB->getBasicBlock()->getFirstNonPHIOrDbg());
     } else {
-      Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
+      Fallthrough = CurMF->createMachineBasicBlock(CurMBB->getBasicBlock());
       CurMF->insert(BBI, Fallthrough);
     }
     UnhandledProbs -= I->Prob;
 
     switch (I->Kind) {
     case CC_BitTests: {
       if (!lowerBitTestWorkItem(W, SwitchMBB, CurMBB, DefaultMBB, MIB, BBI,
                                 DefaultProb, UnhandledProbs, I, Fallthrough,
if (!DL->isLittleEndian() && !CLI->enableBigEndian()) {
     R << "unable to translate in big endian mode";
     reportTranslationError(*MF, *TPC, *ORE, R);
   }
 
   // Release the per-function state when we return, whether we succeeded or not.
   auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });
 
   // Setup a separate basic-block for the arguments and constants
-  MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *EntryBB = MF->createMachineBasicBlock();
   MF->push_back(EntryBB);
   EntryBuilder->setMBB(*EntryBB);
 
   DebugLoc DbgLoc = F.getEntryBlock().getFirstNonPHI()->getDebugLoc();
   SwiftError.setFunction(CurMF);
   SwiftError.createEntriesInEntryBlock(DbgLoc);
 
   bool IsVarArg = F.isVarArg();
   bool HasMustTailInVarArgFn = false;
 
   // Create all blocks, in IR order, to preserve the layout.
   for (const BasicBlock &BB: F) {
     auto *&MBB = BBToMBB[&BB];
 
-    MBB = MF->CreateMachineBasicBlock(&BB);
+    MBB = MF->createMachineBasicBlock(&BB);
     MF->push_back(MBB);
 
     if (BB.hasAddressTaken())
       MBB->setHasAddressTaken();
 
     if (!HasMustTailInVarArgFn)
       HasMustTailInVarArgFn = checkForMustTailInVarArgFn(IsVarArg, BB);
   }
#endif
   // Update the live-in information for the new entry block.
   for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
     NewEntryBB.addLiveIn(LiveIn);
   NewEntryBB.sortUniqueLiveIns();
 
   // Get rid of the now empty basic block.
   EntryBB->removeSuccessor(&NewEntryBB);
   MF->remove(EntryBB);
-  MF->DeleteMachineBasicBlock(EntryBB);
+  MF->deleteMachineBasicBlock(EntryBB);
 
   assert(&MF->front() == &NewEntryBB &&
          "New entry wasn't next in the list of basic block!");
 
   // Initialize stack protector information.
   StackProtector &SP = getAnalysis<StackProtector>();
   SP.copyToMachineFrameInfo(MF->getFrameInfo());
 
   return false;
 }

llvm/lib/CodeGen/GlobalISel/Localizer.cpp

for (MachineOperand &MOUse :
         continue;
 
       LLVM_DEBUG(dbgs() << "Fixing non-local use\n");
       Changed = true;
       auto MBBAndReg = std::make_pair(InsertMBB, Reg);
       auto NewVRegIt = MBBWithLocalDef.find(MBBAndReg);
       if (NewVRegIt == MBBWithLocalDef.end()) {
         // Create the localized instruction.
-        MachineInstr *LocalizedMI = MF.CloneMachineInstr(&MI);
+        MachineInstr *LocalizedMI = MF.cloneMachineInstr(&MI);
         LocalizedInstrs.insert(LocalizedMI);
         MachineInstr &UseMI = *MOUse.getParent();
         if (MRI->hasOneUse(Reg) && !UseMI.isPHI())
           InsertMBB->insert(InsertMBB->SkipPHIsAndLabels(UseMI), LocalizedMI);
         else
           InsertMBB->insert(InsertMBB->SkipPHIsAndLabels(InsertMBB->begin()),
                             LocalizedMI);
 

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

std::unique_ptr<MachineInstr *[]> NewInstrs(
       new MachineInstr *[RepairPt.getNumInsertPoints()]);
   bool IsFirst = true;
   unsigned Idx = 0;
   for (const std::unique_ptr<InsertPoint> &InsertPt : RepairPt) {
     MachineInstr *CurMI;
     if (IsFirst)
       CurMI = MI;
     else
-      CurMI = MIRBuilder.getMF().CloneMachineInstr(MI);
+      CurMI = MIRBuilder.getMF().cloneMachineInstr(MI);
     InsertPt->insert(*CurMI);
     NewInstrs[Idx++] = CurMI;
     IsFirst = false;
   }
   // TODO:
   // Legalize NewInstrs if need be.
   return true;
 }

llvm/lib/CodeGen/IfConversion.cpp

LLVM_DEBUG(dbgs() << "\nIfcvt: function (" << ++FnNum << ") \'"
                     << MF.getName() << "\'");
 
   if (FnNum < IfCvtFnStart || (IfCvtFnStop != -1 && FnNum > IfCvtFnStop)) {
     LLVM_DEBUG(dbgs() << " skipped\n");
     return false;
   }
   LLVM_DEBUG(dbgs() << "\n");
 
-  MF.RenumberBlocks();
+  MF.renumberBlocks();
   BBAnalysis.resize(MF.getNumBlockIDs());
 
   std::vector<std::unique_ptr<IfcvtToken>> Tokens;
   MadeChange = false;
   unsigned NumIfCvts = NumSimple + NumSimpleFalse + NumTriangle +
     NumTriangleRev + NumTriangleFalse + NumTriangleFRev + NumDiamonds;
   while (IfCvtLimit == -1 || (int)NumIfCvts < IfCvtLimit) {
     // Do an initial analysis for each basic block and find all the potential
void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
   MachineFunction &MF = *ToBBI.BB->getParent();
 
   MachineBasicBlock &FromMBB = *FromBBI.BB;
   for (MachineInstr &I : FromMBB) {
     // Do not copy the end of the block branches.
     if (IgnoreBr && I.isBranch())
       break;
 
-    MachineInstr *MI = MF.CloneMachineInstr(&I);
+    MachineInstr *MI = MF.cloneMachineInstr(&I);
     // Make a copy of the call site info.
     if (I.isCandidateForCallSiteEntry())
       MF.copyCallSiteInfo(&I, MI);
 
     ToBBI.BB->insert(ToBBI.BB->end(), MI);
     ToBBI.NonPredSize++;
     unsigned ExtraPredCost = TII->getPredicationCost(I);
     unsigned NumCycles = SchedModel.computeInstrLatency(&I, false);

llvm/lib/CodeGen/MIRParser/MIParser.cpp

bool MIParser::parseBasicBlockDefinition(
   if (!Name.empty()) {
     BB = dyn_cast_or_null<BasicBlock>(
         MF.getFunction().getValueSymbolTable()->lookup(Name));
     if (!BB)
       return error(Loc, Twine("basic block '") + Name +
                             "' is not defined in the function '" +
                             MF.getName() + "'");
   }
-  auto *MBB = MF.CreateMachineBasicBlock(BB);
+  auto *MBB = MF.createMachineBasicBlock(BB);
   MF.insert(MF.end(), MBB);
   bool WasInserted = MBBSlots.insert(std::make_pair(ID, MBB)).second;
   if (!WasInserted)
     return error(Loc, Twine("redefinition of machine basic block with id #") +
                           Twine(ID));
   if (Alignment)
     MBB->setAlignment(Align(Alignment));
   if (HasAddressTaken)
bool MIParser::parse(MachineInstr *&MI) {
   const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
   if (!MCID.isVariadic()) {
     // FIXME: Move the implicit operand verification to the machine verifier.
     if (verifyImplicitOperands(Operands, MCID))
       return true;
   }
 
   // TODO: Check for extraneous machine operands.
-  MI = MF.CreateMachineInstr(MCID, DebugLocation, /*NoImplicit=*/true);
+  MI = MF.createMachineInstr(MCID, DebugLocation, /*NoImplicit=*/true);
   MI->setFlags(Flags);
   for (const auto &Operand : Operands)
     MI->addOperand(MF, Operand.Operand);
   if (assignRegisterTies(*MI, Operands))
     return true;
   if (PreInstrSymbol)
     MI->setPreInstrSymbol(MF, PreInstrSymbol);
   if (PostInstrSymbol)

llvm/lib/CodeGen/MIRSampleProfile.cpp

bool MIRProfileLoaderPass::runOnMachineFunction(MachineFunction &MF) {
   LLVM_DEBUG(dbgs() << "MIRProfileLoader pass working on Func: "
                     << MF.getFunction().getName() << "\n");
   MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
   MIRSampleLoader->setInitVals(
       &getAnalysis<MachineDominatorTree>(),
       &getAnalysis<MachinePostDominatorTree>(), &getAnalysis<MachineLoopInfo>(),
       MBFI, &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE());
 
-  MF.RenumberBlocks();
+  MF.renumberBlocks();
   if (ViewBFIBefore && ViewBlockLayoutWithBFI != GVDT_None &&
       (ViewBlockFreqFuncName.empty() ||
        MF.getFunction().getName().equals(ViewBlockFreqFuncName))) {
     MBFI->view("MIR_Prof_loader_b." + MF.getName(), false);
   }
 
   bool Changed = MIRSampleLoader->runOnFunction(MF);
   if (Changed)

llvm/lib/CodeGen/MachineBasicBlock.cpp

void ilist_traits<MachineInstr>::transferNodesFromList(ilist_traits &FromList,
   // If splicing between two blocks within the same function, just update the
   // parent pointers.
   for (; First != Last; ++First)
     First->setParent(Parent);
 }
 
 void ilist_traits<MachineInstr>::deleteNode(MachineInstr *MI) {
   assert(!MI->getParent() && "MI is still in a block!");
-  Parent->getParent()->DeleteMachineInstr(MI);
+  Parent->getParent()->deleteMachineInstr(MI);
 }
 
 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() {
   instr_iterator I = instr_begin(), E = instr_end();
   while (I != E && I->isPHI())
     ++I;
   assert((I == E || !I->isInsideBundle()) &&
          "First non-phi MI cannot be inside a bundle!");
if (UpdateLiveIns) {
     // new block.
     MachineBasicBlock::iterator Prev(&MI);
     LiveRegs.init(*MF->getSubtarget().getRegisterInfo());
     LiveRegs.addLiveOuts(*this);
     for (auto I = rbegin(), E = Prev.getReverse(); I != E; ++I)
       LiveRegs.stepBackward(*I);
   }
 
-  MachineBasicBlock *SplitBB = MF->CreateMachineBasicBlock(getBasicBlock());
+  MachineBasicBlock *SplitBB = MF->createMachineBasicBlock(getBasicBlock());
 
   MF->insert(++MachineFunction::iterator(this), SplitBB);
   SplitBB->splice(SplitBB->begin(), this, SplitPoint, end());
 
   SplitBB->transferSuccessorsAndUpdatePHIs(this);
   addSuccessor(SplitBB);
 
   if (UpdateLiveIns)
MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
     std::vector<SparseBitVector<>> *LiveInSets) {
   if (!canSplitCriticalEdge(Succ))
     return nullptr;
 
   MachineFunction *MF = getParent();
   MachineBasicBlock *PrevFallthrough = getNextNode();
   DebugLoc DL;  // FIXME: this is nowhere
 
-  MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *NMBB = MF->createMachineBasicBlock();
   MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
   LLVM_DEBUG(dbgs() << "Splitting critical edge: " << printMBBReference(*this)
                     << " -- " << printMBBReference(*NMBB) << " -- "
                     << printMBBReference(*Succ) << '\n');
 
   LiveIntervals *LIS = P.getAnalysisIfAvailable<LiveIntervals>();
   SlotIndexes *Indexes = P.getAnalysisIfAvailable<SlotIndexes>();
   if (LIS)

llvm/lib/CodeGen/MachineCombiner.cpp

for (auto P : Patterns) {
           // Eagerly stop after the first pattern fires.
           Changed = true;
           break;
         }
         // Cleanup instructions of the alternative code sequence. There is no
         // use for them.
         MachineFunction *MF = MBB->getParent();
         for (auto *InstrPtr : InsInstrs)
-          MF->DeleteMachineInstr(InstrPtr);
+          MF->deleteMachineInstr(InstrPtr);
       }
       InstrIdxForVirtReg.clear();
     }
   }
 
   if (Changed && IncrementalUpdate)
     Traces->invalidate(MBB);
   return Changed;

llvm/lib/CodeGen/MachineFunction.cpp

 //===----------------------------------------------------------------------===//
 // MachineFunction implementation
 //===----------------------------------------------------------------------===//
 
 // Out-of-line virtual method.
 MachineFunctionInfo::~MachineFunctionInfo() = default;
 
 void ilist_alloc_traits<MachineBasicBlock>::deleteNode(MachineBasicBlock *MBB) {
-  MBB->getParent()->DeleteMachineBasicBlock(MBB);
+  MBB->getParent()->deleteMachineBasicBlock(MBB);
 }
 
 static inline unsigned getFnStackAlignment(const TargetSubtargetInfo *STI,
                                            const Function &F) {
   if (auto MA = F.getFnStackAlign())
     return MA->value();
   return STI->getFrameLowering()->getStackAlign().value();
 }
MachineFunction::addFrameInst(const MCCFIInstruction &Inst) {
   FrameInstructions.push_back(Inst);
   return FrameInstructions.size() - 1;
 }
 
 /// This discards all of the MachineBasicBlock numbers and recomputes them.
 /// This guarantees that the MBB numbers are sequential, dense, and match the
 /// ordering of the blocks within the function.  If a specific MachineBasicBlock
 /// is specified, only that block and those after it are renumbered.
-void MachineFunction::RenumberBlocks(MachineBasicBlock *MBB) {
+void MachineFunction::renumberBlocks(MachineBasicBlock *MBB) {
   if (empty()) { MBBNumbering.clear(); return; }
   MachineFunction::iterator MBBI, E = end();
   if (MBB == nullptr)
     MBBI = begin();
   else
     MBBI = MBB->getIterator();
 
   // Figure out the block number this should have.
for (auto MBBI = std::next(begin()), E = end(); MBBI != E; ++MBBI) {
     MBBI->setIsBeginSection();
     std::prev(MBBI)->setIsEndSection();
     CurrentSectionID = MBBI->getSectionID();
   }
   back().setIsEndSection();
 }
 
 /// Allocate a new MachineInstr. Use this instead of `new MachineInstr'.
-MachineInstr *MachineFunction::CreateMachineInstr(const MCInstrDesc &MCID,
+MachineInstr *MachineFunction::createMachineInstr(const MCInstrDesc &MCID,
                                                   DebugLoc DL,
                                                   bool NoImplicit) {
   return new (InstructionRecycler.Allocate<MachineInstr>(Allocator))
       MachineInstr(*this, MCID, std::move(DL), NoImplicit);
 }
 
 /// Create a new MachineInstr which is a copy of the 'Orig' instruction,
 /// identical in all ways except the instruction has no parent, prev, or next.
-MachineInstr *
-MachineFunction::CloneMachineInstr(const MachineInstr *Orig) {
+MachineInstr *MachineFunction::cloneMachineInstr(const MachineInstr *Orig) {
   return new (InstructionRecycler.Allocate<MachineInstr>(Allocator))
              MachineInstr(*this, *Orig);
 }
 
-MachineInstr &MachineFunction::CloneMachineInstrBundle(MachineBasicBlock &MBB,
-    MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) {
+MachineInstr &MachineFunction::cloneMachineInstrBundle(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
+    const MachineInstr &Orig) {
   MachineInstr *FirstClone = nullptr;
   MachineBasicBlock::const_instr_iterator I = Orig.getIterator();
   while (true) {
-    MachineInstr *Cloned = CloneMachineInstr(&*I);
+    MachineInstr *Cloned = cloneMachineInstr(&*I);
     MBB.insert(InsertBefore, Cloned);
     if (FirstClone == nullptr) {
       FirstClone = Cloned;
     } else {
       Cloned->bundleWithPred();
     }
 
     if (!I->isBundledWithSucc())
       break;
     ++I;
   }
   // Copy over call site info to the cloned instruction if needed. If Orig is in
   // a bundle, copyCallSiteInfo takes care of finding the call instruction in
   // the bundle.
   if (Orig.shouldUpdateCallSiteInfo())
     copyCallSiteInfo(&Orig, FirstClone);
   return *FirstClone;
 }
 
 /// Delete the given MachineInstr.
 ///
 /// This function also serves as the MachineInstr destructor - the real
 /// ~MachineInstr() destructor must be empty.
-void
-MachineFunction::DeleteMachineInstr(MachineInstr *MI) {
+void MachineFunction::deleteMachineInstr(MachineInstr *MI) {
   // Verify that a call site info is at valid state. This assertion should
   // be triggered during the implementation of support for the
   // call site info of a new architecture. If the assertion is triggered,
   // back trace will tell where to insert a call to updateCallSiteInfo().
   assert((!MI->isCandidateForCallSiteEntry() ||
           CallSitesInfo.find(MI) == CallSitesInfo.end()) &&
          "Call site info was not updated!");
   // Strip it for parts. The operand array and the MI object itself are
   // independently recyclable.
   if (MI->Operands)
     deallocateOperandArray(MI->CapOperands, MI->Operands);
   // Don't call ~MachineInstr() which must be trivial anyway because
   // ~MachineFunction drops whole lists of MachineInstrs wihout calling their
   // destructors.
   InstructionRecycler.Deallocate(Allocator, MI);
 }
 
 /// Allocate a new MachineBasicBlock. Use this instead of
 /// `new MachineBasicBlock'.
 MachineBasicBlock *
-MachineFunction::CreateMachineBasicBlock(const BasicBlock *bb) {
+MachineFunction::createMachineBasicBlock(const BasicBlock *bb) {
   return new (BasicBlockRecycler.Allocate<MachineBasicBlock>(Allocator))
              MachineBasicBlock(*this, bb);
 }
 
 /// Delete the given MachineBasicBlock.
-void
-MachineFunction::DeleteMachineBasicBlock(MachineBasicBlock *MBB) {
+void MachineFunction::deleteMachineBasicBlock(MachineBasicBlock *MBB) {
   assert(MBB->getParent() == this && "MBB parent mismatch!");
   // Clean up any references to MBB in jump tables before deleting it.
   if (JumpTableInfo)
     JumpTableInfo->RemoveMBBFromJumpTables(MBB);
   MBB->~MachineBasicBlock();
   BasicBlockRecycler.Deallocate(Allocator, MBB);
 }
 

llvm/lib/CodeGen/MachineFunctionSplitter.cpp

if (SectionPrefix.hasValue() &&
        SectionPrefix.getValue().equals("unknown"))) {
     return false;
   }
 
   // Renumbering blocks here preserves the order of the blocks as
   // sortBasicBlocksAndUpdateBranches uses the numeric identifier to sort
   // blocks. Preserving the order of blocks is essential to retaining decisions
   // made by prior passes such as MachineBlockPlacement.
-  MF.RenumberBlocks();
+  MF.renumberBlocks();
   MF.setBBSectionsType(BasicBlockSection::Preset);
   auto *MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
   auto *PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
 
   SmallVector<MachineBasicBlock *, 2> LandingPads;
   for (auto &MBB : MF) {
     if (MBB.isEntryBlock())
       continue;

llvm/lib/CodeGen/MachineLoopUtils.cpp

MachineBasicBlock *llvm::PeelSingleBlockLoop(LoopPeelDirection Direction,
   MachineFunction &MF = *Loop->getParent();
   MachineBasicBlock *Preheader = *Loop->pred_begin();
   if (Preheader == Loop)
     Preheader = *std::next(Loop->pred_begin());
   MachineBasicBlock *Exit = *Loop->succ_begin();
   if (Exit == Loop)
     Exit = *std::next(Loop->succ_begin());
 
-  MachineBasicBlock *NewBB = MF.CreateMachineBasicBlock(Loop->getBasicBlock());
+  MachineBasicBlock *NewBB = MF.createMachineBasicBlock(Loop->getBasicBlock());
   if (Direction == LPD_Front)
     MF.insert(Loop->getIterator(), NewBB);
   else
     MF.insert(std::next(Loop->getIterator()), NewBB);
 
   DenseMap<Register, Register> Remaps;
   auto InsertPt = NewBB->end();
   for (MachineInstr &MI : *Loop) {
-    MachineInstr *NewMI = MF.CloneMachineInstr(&MI);
+    MachineInstr *NewMI = MF.cloneMachineInstr(&MI);
     NewBB->insert(InsertPt, NewMI);
     for (MachineOperand &MO : NewMI->defs()) {
       Register OrigR = MO.getReg();
       if (OrigR.isPhysical())
         continue;
       Register &R = Remaps[OrigR];
       R = MRI.createVirtualRegister(MRI.getRegClass(OrigR));
       MO.setReg(R);

llvm/lib/CodeGen/MachineOutliner.cpp

MachineFunction *MachineOutliner::createOutlinedFunction(
   TII.mergeOutliningCandidateAttributes(*F, OF.Candidates);
 
   BasicBlock *EntryBB = BasicBlock::Create(C, "entry", F);
   IRBuilder<> Builder(EntryBB);
   Builder.CreateRetVoid();
 
   MachineModuleInfo &MMI = getAnalysis<MachineModuleInfoWrapperPass>().getMMI();
   MachineFunction &MF = MMI.getOrCreateMachineFunction(*F);
-  MachineBasicBlock &MBB = *MF.CreateMachineBasicBlock();
+  MachineBasicBlock &MBB = *MF.createMachineBasicBlock();
 
   // Insert the new function into the module.
   MF.insert(MF.begin(), &MBB);
 
   MachineFunction *OriginalMF = FirstCand.front()->getMF();
   const std::vector<MCCFIInstruction> &Instrs =
       OriginalMF->getFrameInstructions();
   for (auto I = FirstCand.front(), E = std::next(FirstCand.back()); I != E;
        ++I) {
     if (I->isDebugInstr())
       continue;
-    MachineInstr *NewMI = MF.CloneMachineInstr(&*I);
+    MachineInstr *NewMI = MF.cloneMachineInstr(&*I);
     if (I->isCFIInstruction()) {
       unsigned CFIIndex = NewMI->getOperand(0).getCFIIndex();
       MCCFIInstruction CFI = Instrs[CFIIndex];
       (void)MF.addFrameInst(CFI);
     }
     NewMI->dropMemRefs(MF);
 
     // Don't keep debug information for outlined instructions.

llvm/lib/CodeGen/MachinePipeliner.cpp

if (ExperimentalCodeGen && NewInstrChanges.empty()) {
     MSE.cleanup();
   }
   ++NumPipelined;
 }
 
 /// Clean up after the software pipeliner runs.
 void SwingSchedulerDAG::finishBlock() {
   for (auto &KV : NewMIs)
-    MF.DeleteMachineInstr(KV.second);
+    MF.deleteMachineInstr(KV.second);
   NewMIs.clear();
 
   // Call the superclass.
   ScheduleDAGInstrs::finishBlock();
 }
 
 /// Return the register values for  the operands of a Phi instruction.
 /// This function assume the instruction is a Phi.
bool SwingSchedulerDAG::canUseLastOffsetValue(MachineInstr *MI,
   unsigned BasePos1 = 0, OffsetPos1 = 0;
   if (!TII->getBaseAndOffsetPosition(*PrevDef, BasePos1, OffsetPos1))
     return false;
 
   // Make sure that the instructions do not access the same memory location in
   // the next iteration.
   int64_t LoadOffset = MI->getOperand(OffsetPosLd).getImm();
   int64_t StoreOffset = PrevDef->getOperand(OffsetPos1).getImm();
-  MachineInstr *NewMI = MF.CloneMachineInstr(MI);
+  MachineInstr *NewMI = MF.cloneMachineInstr(MI);
   NewMI->getOperand(OffsetPosLd).setImm(LoadOffset + StoreOffset);
   bool Disjoint = TII->areMemAccessesTriviallyDisjoint(*NewMI, *PrevDef);
-  MF.DeleteMachineInstr(NewMI);
+  MF.deleteMachineInstr(NewMI);
   if (!Disjoint)
     return false;
 
   // Set the return value once we determine that we return true.
   BasePos = BasePosLd;
   OffsetPos = OffsetPosLd;
   NewBase = PrevReg;
   Offset = StoreOffset;
if (!TII->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos))
       return;
     Register BaseReg = MI->getOperand(BasePos).getReg();
     MachineInstr *LoopDef = findDefInLoop(BaseReg);
     int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef));
     int DefCycleNum = Schedule.cycleScheduled(getSUnit(LoopDef));
     int BaseStageNum = Schedule.stageScheduled(SU);
     int BaseCycleNum = Schedule.cycleScheduled(SU);
     if (BaseStageNum < DefStageNum) {
-      MachineInstr *NewMI = MF.CloneMachineInstr(MI);
+      MachineInstr *NewMI = MF.cloneMachineInstr(MI);
       int OffsetDiff = DefStageNum - BaseStageNum;
       if (DefCycleNum < BaseCycleNum) {
         NewMI->getOperand(BasePos).setReg(RegAndOffset.first);
         if (OffsetDiff > 0)
           --OffsetDiff;
       }
       int64_t NewOffset =
           MI->getOperand(OffsetPos).getImm() + RegAndOffset.second * OffsetDiff;
for (unsigned i = 0, e = MI->getNumOperands(); i < e; ++i) {
         // Check that the instruction appears in the InstrChanges structure,
         // which contains instructions that can have the offset updated.
         DenseMap<SUnit *, std::pair<unsigned, int64_t>>::iterator It =
           InstrChanges.find(SU);
         if (It != InstrChanges.end()) {
           unsigned BasePos, OffsetPos;
           // Update the base register and adjust the offset.
           if (TII->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos)) {
-            MachineInstr *NewMI = MF.CloneMachineInstr(MI);
+            MachineInstr *NewMI = MF.cloneMachineInstr(MI);
             NewMI->getOperand(BasePos).setReg(NewBaseReg);
             int64_t NewOffset =
                 MI->getOperand(OffsetPos).getImm() - It->second.second;
             NewMI->getOperand(OffsetPos).setImm(NewOffset);
             SU->setInstr(NewMI);
             MISUnitMap[NewMI] = SU;
             NewMIs[MI] = NewMI;
           }

llvm/lib/CodeGen/MachineSink.cpp

SuccToSinkTo.splice(InsertPos, ParentBlock, MI,
                       ++MachineBasicBlock::iterator(MI));
 
   // Sink a copy of debug users to the insert position. Mark the original
   // DBG_VALUE location as 'undef', indicating that any earlier variable
   // location should be terminated as we've optimised away the value at this
   // point.
   for (auto DbgValueToSink : DbgValuesToSink) {
     MachineInstr *DbgMI = DbgValueToSink.first;
-    MachineInstr *NewDbgMI = DbgMI->getMF()->CloneMachineInstr(DbgMI);
+    MachineInstr *NewDbgMI = DbgMI->getMF()->cloneMachineInstr(DbgMI);
     SuccToSinkTo.insert(InsertPos, NewDbgMI);
 
     bool PropagatedAllSunkOps = true;
     for (unsigned Reg : DbgValueToSink.second) {
       if (DbgMI->hasDebugOperandForReg(Reg)) {
         if (!attemptDebugCopyProp(MI, *DbgMI, Reg)) {
           PropagatedAllSunkOps = false;
           break;

llvm/lib/CodeGen/ModuloSchedule.cpp

void ModuloScheduleExpander::expand() {
   generatePipelinedLoop();
 }
 
 void ModuloScheduleExpander::generatePipelinedLoop() {
   LoopInfo = TII->analyzeLoopForPipelining(BB);
   assert(LoopInfo && "Must be able to analyze loop!");
 
   // Create a new basic block for the kernel and add it to the CFG.
-  MachineBasicBlock *KernelBB = MF.CreateMachineBasicBlock(BB->getBasicBlock());
+  MachineBasicBlock *KernelBB = MF.createMachineBasicBlock(BB->getBasicBlock());
 
   unsigned MaxStageCount = Schedule.getNumStages() - 1;
 
   // Remember the registers that are used in different stages. The index is
   // the iteration, or stage, that the instruction is scheduled in.  This is
   // a map between register names in the original block and the names created
   // in each stage of the pipelined loop.
   ValueMapTy *VRMap = new ValueMapTy[(MaxStageCount + 1) * 2];
for (MachineInstr *CI : Schedule.getInstructions()) {
     updateInstruction(NewMI, false, MaxStageCount, StageNum, VRMap);
     KernelBB->push_back(NewMI);
     InstrMap[NewMI] = CI;
   }
 
   // Copy any terminator instructions to the new kernel, and update
   // names as needed.
   for (MachineInstr &MI : BB->terminators()) {
-    MachineInstr *NewMI = MF.CloneMachineInstr(&MI);
+    MachineInstr *NewMI = MF.cloneMachineInstr(&MI);
     updateInstruction(NewMI, false, MaxStageCount, 0, VRMap);
     KernelBB->push_back(NewMI);
     InstrMap[NewMI] = &MI;
   }
 
   NewKernel = KernelBB;
   KernelBB->transferSuccessors(BB);
   KernelBB->replaceSuccessor(BB, KernelBB);
void ModuloScheduleExpander::generateProlog(unsigned LastStage,
   InstrMapTy InstrMap;
 
   // Generate a basic block for each stage, not including the last stage,
   // which will be generated in the kernel. Each basic block may contain
   // instructions from multiple stages/iterations.
   for (unsigned i = 0; i < LastStage; ++i) {
     // Create and insert the prolog basic block prior to the original loop
     // basic block.  The original loop is removed later.
-    MachineBasicBlock *NewBB = MF.CreateMachineBasicBlock(BB->getBasicBlock());
+    MachineBasicBlock *NewBB = MF.createMachineBasicBlock(BB->getBasicBlock());
     PrologBBs.push_back(NewBB);
     MF.insert(BB->getIterator(), NewBB);
     NewBB->transferSuccessors(PredBB);
     PredBB->addSuccessor(NewBB);
     PredBB = NewBB;
 
     // Generate instructions for each appropriate stage. Process instructions
     // in original program order.
void ModuloScheduleExpander::generateEpilog(unsigned LastStage,
   MachineBasicBlock *EpilogStart = LoopExitBB;
   InstrMapTy InstrMap;
 
   // Generate a basic block for each stage, not including the last stage,
   // which was generated for the kernel.  Each basic block may contain
   // instructions from multiple stages/iterations.
   int EpilogStage = LastStage + 1;
   for (unsigned i = LastStage; i >= 1; --i, ++EpilogStage) {
-    MachineBasicBlock *NewBB = MF.CreateMachineBasicBlock();
+    MachineBasicBlock *NewBB = MF.createMachineBasicBlock();
     EpilogBBs.push_back(NewBB);
     MF.insert(BB->getIterator(), NewBB);
 
     PredBB->replaceSuccessor(LoopExitBB, NewBB);
     NewBB->addSuccessor(LoopExitBB);
 
     if (EpilogStart == LoopExitBB)
       EpilogStart = NewBB;
void ModuloScheduleExpander::updateMemOperands(MachineInstr &NewMI,
   NewMI.setMemRefs(MF, NewMMOs);
 }
 
 /// Clone the instruction for the new pipelined loop and update the
 /// memory operands, if needed.
 MachineInstr *ModuloScheduleExpander::cloneInstr(MachineInstr *OldMI,
                                                  unsigned CurStageNum,
                                                  unsigned InstStageNum) {
-  MachineInstr *NewMI = MF.CloneMachineInstr(OldMI);
+  MachineInstr *NewMI = MF.cloneMachineInstr(OldMI);
   // Check for tied operands in inline asm instructions. This should be handled
   // elsewhere, but I'm not sure of the best solution.
   if (OldMI->isInlineAsm())
     for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
       const auto &MO = OldMI->getOperand(i);
       if (MO.isReg() && MO.isUse())
         break;
       unsigned UseIdx;
       if (OldMI->isRegTiedToUseOperand(i, &UseIdx))
         NewMI->tieOperands(i, UseIdx);
     }
   updateMemOperands(*NewMI, *OldMI, CurStageNum - InstStageNum);
   return NewMI;
 }
 
 /// Clone the instruction for the new pipelined loop. If needed, this
 /// function updates the instruction using the values saved in the
 /// InstrChanges structure.
 MachineInstr *ModuloScheduleExpander::cloneAndChangeInstr(
     MachineInstr *OldMI, unsigned CurStageNum, unsigned InstStageNum) {
-  MachineInstr *NewMI = MF.CloneMachineInstr(OldMI);
+  MachineInstr *NewMI = MF.cloneMachineInstr(OldMI);
   auto It = InstrChanges.find(OldMI);
   if (It != InstrChanges.end()) {
     std::pair<unsigned, int64_t> RegAndOffset = It->second;
     unsigned BasePos, OffsetPos;
     if (!TII->getBaseAndOffsetPosition(*OldMI, BasePos, OffsetPos))
       return nullptr;
     int64_t NewOffset = OldMI->getOperand(OffsetPos).getImm();
     MachineInstr *LoopDef = findDefInLoop(RegAndOffset.first);
for (MachineInstr &MI : DestBB->phis()) {
     }
   }
   for (auto *P : PhiToDelete)
     P->eraseFromParent();
   InsertPt = DestBB->getFirstNonPHI();
   // Helper to clone Phi instructions into the destination block. We clone Phi
   // greedily to avoid combinatorial explosion of Phi instructions.
   auto clonePhi = [&](MachineInstr *Phi) {
-    MachineInstr *NewMI = MF.CloneMachineInstr(Phi);
+    MachineInstr *NewMI = MF.cloneMachineInstr(Phi);
     DestBB->insert(InsertPt, NewMI);
     Register OrigR = Phi->getOperand(0).getReg();
     Register R = MRI.createVirtualRegister(MRI.getRegClass(OrigR));
     NewMI->getOperand(0).setReg(R);
     NewMI->getOperand(1).setReg(OrigR);
     NewMI->getOperand(2).setMBB(*DestBB->pred_begin());
     Remaps[OrigR] = R;
     CanonicalMIs[NewMI] = CanonicalMIs[Phi];

 }
 
 MachineBasicBlock *PeelingModuloScheduleExpander::CreateLCSSAExitingBlock() {
   MachineFunction &MF = *BB->getParent();
   MachineBasicBlock *Exit = *BB->succ_begin();
   if (Exit == BB)
     Exit = *std::next(BB->succ_begin());
 
-  MachineBasicBlock *NewBB = MF.CreateMachineBasicBlock(BB->getBasicBlock());
+  MachineBasicBlock *NewBB = MF.createMachineBasicBlock(BB->getBasicBlock());
   MF.insert(std::next(BB->getIterator()), NewBB);
 
   // Clone all phis in BB into NewBB and rewrite.
   for (MachineInstr &MI : BB->phis()) {
     auto RC = MRI.getRegClass(MI.getOperand(0).getReg());
     Register OldR = MI.getOperand(3).getReg();
     Register R = MRI.createVirtualRegister(RC);
     SmallVector<MachineInstr *, 4> Uses;

llvm/lib/CodeGen/PHIElimination.cpp

if (MRI->use_nodbg_empty(DefReg)) {
       DefMI->eraseFromParent();
     }
   }
 
   // Clean up the lowered PHI instructions.
   for (auto &I : LoweredPHIs) {
     if (LIS)
       LIS->RemoveMachineInstrFromMaps(*I.first);
-    MF.DeleteMachineInstr(I.first);
+    MF.deleteMachineInstr(I.first);
   }
 
   // TODO: we should use the incremental DomTree updater here.
   if (Changed)
     if (auto *MDT = getAnalysisIfAvailable<MachineDominatorTree>())
       MDT->getBase().recalculate(MF);
 
   LoweredPHIs.clear();
if (LIS) {
       }
     }
   }
 
   // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
   if (reusedIncoming || !IncomingReg) {
     if (LIS)
       LIS->RemoveMachineInstrFromMaps(*MPhi);
-    MF.DeleteMachineInstr(MPhi);
+    MF.deleteMachineInstr(MPhi);
   }
 }
 
 /// analyzePHINodes - Gather information about the PHI nodes in here. In
 /// particular, we want to map the number of uses of a virtual register which is
 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
 /// used later to determine when the vreg is killed in the BB.
 void PHIElimination::analyzePHINodes(const MachineFunction& MF) {

llvm/lib/CodeGen/RegAllocFast.cpp

for (auto MISpilledOperands : SpilledOperandsMap) {
     (void)NewDV;
     LLVM_DEBUG(dbgs() << "Inserting debug info due to spill:\n" << *NewDV);
 
     if (LiveOut) {
       // We need to insert a DBG_VALUE at the end of the block if the spill slot
       // is live out, but there is another use of the value after the
       // spill. This will allow LiveDebugValues to see the correct live out
       // value to propagate to the successors.
-      MachineInstr *ClonedDV = MBB->getParent()->CloneMachineInstr(NewDV);
+      MachineInstr *ClonedDV = MBB->getParent()->cloneMachineInstr(NewDV);
       MBB->insert(FirstTerm, ClonedDV);
       LLVM_DEBUG(dbgs() << "Cloning debug info due to live out spill\n");
     }
 
     // Rewrite unassigned dbg_values to use the stack slot.
     // TODO We can potentially do this for list debug values as well if we know
     // how the dbg_values are getting unassigned.
     if (DBG.isNonListDebugValue()) {

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

if (BB.isEHPad()) {
         assert(&*BB.begin() == PadInst &&
                "WinEHPrepare failed to remove PHIs from imaginary BBs");
         continue;
       }
       if (isa<FuncletPadInst>(PadInst))
         assert(&*BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs");
     }
 
-    MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(&BB);
+    MachineBasicBlock *MBB = mf.createMachineBasicBlock(&BB);
     MBBMap[&BB] = MBB;
     MF->push_back(MBB);
 
     // Transfer the address-taken flag. This is necessary because there could
     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
     // the first one should be marked.
     if (BB.hasAddressTaken())
       MBB->setHasAddressTaken();

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

if (!BOpIsInOrAndTree || BOp->getParent() != CurBB->getBasicBlock() ||
     EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
                                  TProb, FProb, InvertCond);
     return;
   }
 
   //  Create TmpBB after CurBB.
   MachineFunction::iterator BBI(CurBB);
   MachineFunction &MF = DAG.getMachineFunction();
-  MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
+  MachineBasicBlock *TmpBB = MF.createMachineBasicBlock(CurBB->getBasicBlock());
   CurBB->getParent()->insert(++BBI, TmpBB);
 
   if (Opc == Instruction::Or) {
     // Codegen X | Y as:
     // BB1:
     //   jmp_if_X TBB
     //   jmp TmpBB
     // TmpBB:
for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
     bool FallthroughUnreachable = false;
     MachineBasicBlock *Fallthrough;
     if (I == W.LastCluster) {
       // For the last cluster, fall through to the default destination.
       Fallthrough = DefaultMBB;
       FallthroughUnreachable = isa<UnreachableInst>(
           DefaultMBB->getBasicBlock()->getFirstNonPHIOrDbg());
     } else {
-      Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
+      Fallthrough = CurMF->createMachineBasicBlock(CurMBB->getBasicBlock());
       CurMF->insert(BBI, Fallthrough);
       // Put Cond in a virtual register to make it available from the new blocks.
       ExportFromCurrentBlock(Cond);
     }
     UnhandledProbs -= I->Prob;
 
     switch (I->Kind) {
       case CC_JumpTable: {
void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
   // we can branch to its destination directly if it's squeezed exactly in
   // between the known lower bound and Pivot - 1.
   MachineBasicBlock *LeftMBB;
   if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
       FirstLeft->Low == W.GE &&
       (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
     LeftMBB = FirstLeft->MBB;
   } else {
-    LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
+    LeftMBB = FuncInfo.MF->createMachineBasicBlock(W.MBB->getBasicBlock());
     FuncInfo.MF->insert(BBI, LeftMBB);
     WorkList.push_back(
         {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultProb / 2});
     // Put Cond in a virtual register to make it available from the new blocks.
     ExportFromCurrentBlock(Cond);
   }
 
   // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
   // single cluster, RHS.Low == Pivot, and we can branch to its destination
   // directly if RHS.High equals the current upper bound.
   MachineBasicBlock *RightMBB;
   if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
       W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
     RightMBB = FirstRight->MBB;
   } else {
-    RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
+    RightMBB = FuncInfo.MF->createMachineBasicBlock(W.MBB->getBasicBlock());
     FuncInfo.MF->insert(BBI, RightMBB);
     WorkList.push_back(
         {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultProb / 2});
     // Put Cond in a virtual register to make it available from the new blocks.
     ExportFromCurrentBlock(Cond);
   }
 
   // Create the CaseBlock record that will be used to lower the branch.
MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster(
 
   LLVM_DEBUG(dbgs() << "Peeled one top case in switch stmt, prob: "
                     << TopCaseProb << "\n");
 
   // Record the MBB for the peeled switch statement.
   MachineFunction::iterator BBI(SwitchMBB);
   ++BBI;
   MachineBasicBlock *PeeledSwitchMBB =
-      FuncInfo.MF->CreateMachineBasicBlock(SwitchMBB->getBasicBlock());
+      FuncInfo.MF->createMachineBasicBlock(SwitchMBB->getBasicBlock());
   FuncInfo.MF->insert(BBI, PeeledSwitchMBB);
 
   ExportFromCurrentBlock(SI.getCondition());
   auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex;
   SwitchWorkListItem W = {SwitchMBB, PeeledCaseIt, PeeledCaseIt,
                           nullptr,   nullptr,      TopCaseProb.getCompl()};
   lowerWorkItem(W, SI.getCondition(), SwitchMBB, PeeledSwitchMBB);
 

llvm/lib/CodeGen/SwitchLoweringUtils.cpp

if (TLI->isSuitableForBitTests(NumDests, NumCmps,
     // Clusters[First..Last] should be lowered as bit tests instead.
     return false;
   }
 
   // Create the MBB that will load from and jump through the table.
   // Note: We create it here, but it's not inserted into the function yet.
   MachineFunction *CurMF = FuncInfo.MF;
   MachineBasicBlock *JumpTableMBB =
-      CurMF->CreateMachineBasicBlock(SI->getParent());
+      CurMF->createMachineBasicBlock(SI->getParent());
 
   // Add successors. Note: use table order for determinism.
   SmallPtrSet<MachineBasicBlock *, 8> Done;
   for (MachineBasicBlock *Succ : Table) {
     if (Done.count(Succ))
       continue;
     addSuccessorWithProb(JumpTableMBB, Succ, JTProbs[Succ]);
     Done.insert(Succ);
if (a.ExtraProb != b.ExtraProb)
       return a.ExtraProb > b.ExtraProb;
     if (a.Bits != b.Bits)
       return a.Bits > b.Bits;
     return a.Mask < b.Mask;
   });
 
   for (auto &CB : CBV) {
     MachineBasicBlock *BitTestBB =
-        FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
+        FuncInfo.MF->createMachineBasicBlock(SI->getParent());
     BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraProb));
   }
   BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
                             SI->getCondition(), -1U, MVT::Other, false,
                             ContiguousRange, nullptr, nullptr, std::move(BTI),
                             TotalProb);
 
   BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,

llvm/lib/CodeGen/TargetInstrInfo.cpp

if (HasDef && Reg0 == Reg1 &&
     Reg0 = Reg1;
     SubReg0 = SubReg1;
   }
 
   MachineInstr *CommutedMI = nullptr;
   if (NewMI) {
     // Create a new instruction.
     MachineFunction &MF = *MI.getMF();
-    CommutedMI = MF.CloneMachineInstr(&MI);
+    CommutedMI = MF.cloneMachineInstr(&MI);
   } else {
     CommutedMI = &MI;
   }
 
   if (HasDef) {
     CommutedMI->getOperand(0).setReg(Reg0);
     CommutedMI->getOperand(0).setSubReg(SubReg0);
   }
bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
   return true;
 }
 
 void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
                                     MachineBasicBlock::iterator I,
                                     Register DestReg, unsigned SubIdx,
                                     const MachineInstr &Orig,
                                     const TargetRegisterInfo &TRI) const {
-  MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
+  MachineInstr *MI = MBB.getParent()->cloneMachineInstr(&Orig);
   MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
   MBB.insert(I, MI);
 }
 
 bool TargetInstrInfo::produceSameValue(const MachineInstr &MI0,
                                        const MachineInstr &MI1,
                                        const MachineRegisterInfo *MRI) const {
   return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
 }
 
 MachineInstr &TargetInstrInfo::duplicate(MachineBasicBlock &MBB,
     MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const {
   assert(!Orig.isNotDuplicable() && "Instruction cannot be duplicated");
   MachineFunction &MF = *MBB.getParent();
-  return MF.CloneMachineInstrBundle(MBB, InsertBefore, Orig);
+  return MF.cloneMachineInstrBundle(MBB, InsertBefore, Orig);
 }
 
 // If the COPY instruction in MI can be folded to a stack operation, return
 // the register class to use.
 static const TargetRegisterClass *canFoldCopy(const MachineInstr &MI,
                                               unsigned FoldIdx) {
   assert(MI.isCopy() && "MI must be a COPY instruction");
   if (MI.getNumOperands() != 2)
for (unsigned Op : Ops) {
     } else if (Op < StartIdx) {
       return nullptr;
     }
     if (MI.getOperand(Op).isTied())
       return nullptr;
   }
 
   MachineInstr *NewMI =
-      MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
+      MF.createMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
   MachineInstrBuilder MIB(MF, NewMI);
 
   // No need to fold return, the meta data, and function arguments
   for (unsigned i = 0; i < StartIdx; ++i)
     if (i != DefToFoldIdx)
       MIB.add(MI.getOperand(i));
 
   for (unsigned i = StartIdx, e = MI.getNumOperands(); i < e; ++i) {

llvm/lib/CodeGen/UnreachableBlockElim.cpp

while (phi != BB->end() && phi->isPHI()) {
         }
         continue;
       }
 
       ++phi;
     }
   }
 
-  F.RenumberBlocks();
+  F.renumberBlocks();
 
   return (!DeadBlocks.empty() || ModifiedPHI);
 }

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

bool AArch64ExpandPseudo::expandCMP_SWAP(
   // Duplicating undef operands into 2 instructions does not guarantee the same
   // value on both; However undef should be replaced by xzr anyway.
   assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
   Register AddrReg = MI.getOperand(2).getReg();
   Register DesiredReg = MI.getOperand(3).getReg();
   Register NewReg = MI.getOperand(4).getReg();
 
   MachineFunction *MF = MBB.getParent();
-  auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+  auto LoadCmpBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto StoreBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto DoneBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
 
   MF->insert(++MBB.getIterator(), LoadCmpBB);
   MF->insert(++LoadCmpBB->getIterator(), StoreBB);
   MF->insert(++StoreBB->getIterator(), DoneBB);
 
   // .Lloadcmp:
   //     mov wStatus, 0
   //     ldaxr xDest, [xAddr]
case AArch64::CMP_SWAP_128:
     LdxpOp = AArch64::LDAXPX;
     StxpOp = AArch64::STLXPX;
     break;
   default:
     llvm_unreachable("Unexpected opcode");
   }
 
   MachineFunction *MF = MBB.getParent();
-  auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto FailBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+  auto LoadCmpBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto StoreBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto FailBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto DoneBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
 
   MF->insert(++MBB.getIterator(), LoadCmpBB);
   MF->insert(++LoadCmpBB->getIterator(), StoreBB);
   MF->insert(++StoreBB->getIterator(), FailBB);
   MF->insert(++FailBB->getIterator(), DoneBB);
 
   // .Lloadcmp:
   //     ldaxp xDestLo, xDestHi, [xAddr]
BuildMI(MBB, MBBI, DL, TII->get(OpCode1), AddressReg)
         .addImm(1);
     Size -= 16;
   }
   MachineBasicBlock::iterator I =
       BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVi64imm), SizeReg)
           .addImm(Size);
   expandMOVImm(MBB, I, 64);
 
-  auto LoopBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+  auto LoopBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto DoneBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
 
   MF->insert(++MBB.getIterator(), LoopBB);
   MF->insert(++LoopBB->getIterator(), DoneBB);
 
   BuildMI(LoopBB, DL, TII->get(OpCode2))
       .addDef(AddressReg)
       .addReg(AddressReg)
       .addReg(AddressReg)
case AArch64::ORRXrr: {
     case AArch64::EORXrr:      Opcode = AArch64::EORXrs; break;
     case AArch64::ORNWrr:      Opcode = AArch64::ORNWrs; break;
     case AArch64::ORNXrr:      Opcode = AArch64::ORNXrs; break;
     case AArch64::ORRWrr:      Opcode = AArch64::ORRWrs; break;
     case AArch64::ORRXrr:      Opcode = AArch64::ORRXrs; break;
     }
     MachineFunction &MF = *MBB.getParent();
     // Try to create new inst without implicit operands added.
-    MachineInstr *NewMI = MF.CreateMachineInstr(
+    MachineInstr *NewMI = MF.createMachineInstr(
         TII->get(Opcode), MI.getDebugLoc(), /*NoImplicit=*/true);
     MBB.insert(MBBI, NewMI);
     MachineInstrBuilder MIB1(MF, NewMI);
     MIB1.addReg(MI.getOperand(0).getReg(), RegState::Define)
         .add(MI.getOperand(1))
         .add(MI.getOperand(2))
         .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
     transferImpOps(MI, MIB1, MIB1);

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

AArch64TargetLowering::EmitF128CSEL(MachineInstr &MI,
   MachineFunction::iterator It = ++MBB->getIterator();
 
   Register DestReg = MI.getOperand(0).getReg();
   Register IfTrueReg = MI.getOperand(1).getReg();
   Register IfFalseReg = MI.getOperand(2).getReg();
   unsigned CondCode = MI.getOperand(3).getImm();
   bool NZCVKilled = MI.getOperand(4).isKill();
 
-  MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *TrueBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *EndBB = MF->createMachineBasicBlock(LLVM_BB);
   MF->insert(It, TrueBB);
   MF->insert(It, EndBB);
 
   // Transfer rest of current basic-block to EndBB
   EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
                 MBB->end());
   EndBB->transferSuccessorsAndUpdatePHIs(MBB);
 

llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp

static MachineFunction &createFrameHelperMachineFunction(Module *M,
   MF.getRegInfo().freezeReservedRegs(MF);
 
   // Create entry block.
   BasicBlock *EntryBB = BasicBlock::Create(C, "entry", F);
   IRBuilder<> Builder(EntryBB);
   Builder.CreateRetVoid();
 
   // Insert the new block into the function.
-  MachineBasicBlock *MBB = MF.CreateMachineBasicBlock();
+  MachineBasicBlock *MBB = MF.createMachineBasicBlock();
   MF.insert(MF.begin(), MBB);
 
   return MF;
 }
 
 /// Emit a store-pair instruction for frame-setup.
 static void emitStore(MachineFunction &MF, MachineBasicBlock &MBB,
                       MachineBasicBlock::iterator Pos,

llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp

AMDGPUMachineCFGStructurizer::createLinearizedExitBlock(RegionMRT *Region) {
   auto Exit = Region->getSucc();
 
   // If the exit is the end of the function, we just use the existing
   MachineFunction *MF = Region->getEntry()->getParent();
   if (Exit == nullptr && hasOneExitNode(*MF)) {
     return &(*(--(Region->getEntry()->getParent()->end())));
   }
 
-  MachineBasicBlock *LastMerge = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *LastMerge = MF->createMachineBasicBlock();
   if (Exit == nullptr) {
     MachineFunction::iterator ExitIter = MF->end();
     MF->insert(ExitIter, LastMerge);
   } else {
     MachineFunction::iterator ExitIter = Exit->getIterator();
     MF->insert(ExitIter, LastMerge);
     LastMerge->addSuccessor(Exit);
     insertUnconditionalBranch(LastMerge, Exit);
static void removeExternalCFGEdges(MachineBasicBlock *StartMBB,
   }
 }
 
 MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfBlock(
     MachineBasicBlock *MergeBB, MachineBasicBlock *CodeBBStart,
     MachineBasicBlock *CodeBBEnd, MachineBasicBlock *SelectBB, unsigned IfReg,
     bool InheritPreds) {
   MachineFunction *MF = MergeBB->getParent();
-  MachineBasicBlock *IfBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *IfBB = MF->createMachineBasicBlock();
 
   if (InheritPreds) {
     for (MachineBasicBlock *Pred : CodeBBStart->predecessors())
       if (Pred != CodeBBEnd)
         Pred->addSuccessor(IfBB);
   }
 
   removeExternalCFGEdges(CodeBBStart, CodeBBEnd);

 // Split the exit block so that we can insert a end control flow
 MachineBasicBlock *
 AMDGPUMachineCFGStructurizer::splitExit(LinearizedRegion *LRegion) {
   auto MRTRegion = LRegion->getRegionMRT();
   auto Exit = LRegion->getExit();
   auto MF = Exit->getParent();
   auto Succ = MRTRegion->getSucc();
 
-  auto NewExit = MF->CreateMachineBasicBlock();
+  auto NewExit = MF->createMachineBasicBlock();
   auto AfterExitIter = Exit->getIterator();
   AfterExitIter++;
   MF->insert(AfterExitIter, NewExit);
   Exit->removeSuccessor(Succ);
   Exit->addSuccessor(NewExit);
   NewExit->addSuccessor(Succ);
   insertUnconditionalBranch(NewExit, Succ);
   LRegion->addMBB(NewExit);
AMDGPUMachineCFGStructurizer::splitExit(LinearizedRegion *LRegion) {
 
   return NewExit;
 }
 
 static MachineBasicBlock *split(MachineBasicBlock::iterator I) {
   // Create the fall-through block.
   MachineBasicBlock *MBB = (*I).getParent();
   MachineFunction *MF = MBB->getParent();
-  MachineBasicBlock *SuccMBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *SuccMBB = MF->createMachineBasicBlock();
   auto MBBIter = ++(MBB->getIterator());
   MF->insert(MBBIter, SuccMBB);
   SuccMBB->transferSuccessorsAndUpdatePHIs(MBB);
   MBB->addSuccessor(SuccMBB);
 
   // Splice the code over.
   SuccMBB->splice(SuccMBB->end(), MBB, I, MBB->end());
 

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

#endif
   B.buildInstr(TargetOpcode::IMPLICIT_DEF)
     .addDef(InitSaveExecReg);
 
   Register PhiExec = MRI.createVirtualRegister(WaveRC);
   Register NewExec = MRI.createVirtualRegister(WaveRC);
 
   // To insert the loop we need to split the block. Move everything before this
   // point to a new block, and insert a new empty block before this instruction.
-  MachineBasicBlock *LoopBB = MF->CreateMachineBasicBlock();
-  MachineBasicBlock *RemainderBB = MF->CreateMachineBasicBlock();
-  MachineBasicBlock *RestoreExecBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *LoopBB = MF->createMachineBasicBlock();
+  MachineBasicBlock *RemainderBB = MF->createMachineBasicBlock();
+  MachineBasicBlock *RestoreExecBB = MF->createMachineBasicBlock();
   MachineFunction::iterator MBBI(MBB);
   ++MBBI;
   MF->insert(MBBI, LoopBB);
   MF->insert(MBBI, RestoreExecBB);
   MF->insert(MBBI, RemainderBB);
 
   LoopBB->addSuccessor(RestoreExecBB);
   LoopBB->addSuccessor(LoopBB);

llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp

if (I->getOpcode() == R600::PRED_X) {
       }
     }
   }
 }
 
 void AMDGPUCFGStructurizer::insertInstrEnd(MachineBasicBlock *MBB,
                                            int NewOpcode, const DebugLoc &DL) {
   MachineInstr *MI =
-      MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL);
+      MBB->getParent()->createMachineInstr(TII->get(NewOpcode), DL);
   MBB->push_back(MI);
   //assume the instruction doesn't take any reg operand ...
   SHOWNEWINSTR(MI);
 }
 
 MachineInstr *AMDGPUCFGStructurizer::insertInstrBefore(MachineBasicBlock *MBB,
                                                        int NewOpcode,
                                                        const DebugLoc &DL) {
   MachineInstr *MI =
-      MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL);
+      MBB->getParent()->createMachineInstr(TII->get(NewOpcode), DL);
   if (!MBB->empty())
     MBB->insert(MBB->begin(), MI);
   else
     MBB->push_back(MI);
   SHOWNEWINSTR(MI);
   return MI;
 }
 
 MachineInstr *AMDGPUCFGStructurizer::insertInstrBefore(
     MachineBasicBlock::iterator I, int NewOpcode) {
   MachineInstr *OldMI = &(*I);
   MachineBasicBlock *MBB = OldMI->getParent();
   MachineInstr *NewMBB =
-      MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DebugLoc());
+      MBB->getParent()->createMachineInstr(TII->get(NewOpcode), DebugLoc());
   MBB->insert(I, NewMBB);
   //assume the instruction doesn't take any reg operand ...
   SHOWNEWINSTR(NewMBB);
   return NewMBB;
 }
 
 void AMDGPUCFGStructurizer::insertCondBranchBefore(
     MachineBasicBlock::iterator I, int NewOpcode, const DebugLoc &DL) {
   MachineInstr *OldMI = &(*I);
   MachineBasicBlock *MBB = OldMI->getParent();
   MachineFunction *MF = MBB->getParent();
-  MachineInstr *NewMI = MF->CreateMachineInstr(TII->get(NewOpcode), DL);
+  MachineInstr *NewMI = MF->createMachineInstr(TII->get(NewOpcode), DL);
   MBB->insert(I, NewMI);
   MachineInstrBuilder MIB(*MF, NewMI);
   MIB.addReg(OldMI->getOperand(1).getReg(), false);
   SHOWNEWINSTR(NewMI);
   //erase later oldInstr->eraseFromParent();
 }
 
 void AMDGPUCFGStructurizer::insertCondBranchBefore(
     MachineBasicBlock *blk, MachineBasicBlock::iterator I, int NewOpcode,
     int RegNum, const DebugLoc &DL) {
   MachineFunction *MF = blk->getParent();
-  MachineInstr *NewInstr = MF->CreateMachineInstr(TII->get(NewOpcode), DL);
+  MachineInstr *NewInstr = MF->createMachineInstr(TII->get(NewOpcode), DL);
   //insert before
   blk->insert(I, NewInstr);
   MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false);
   SHOWNEWINSTR(NewInstr);
 }
 
 int AMDGPUCFGStructurizer::getBranchNzeroOpcode(int OldOpcode) {
   switch(OldOpcode) {

 void AMDGPUCFGStructurizer::cloneSuccessorList(MachineBasicBlock *DstMBB,
     MachineBasicBlock *SrcMBB) {
   for (MachineBasicBlock *Succ : SrcMBB->successors())
     DstMBB->addSuccessor(Succ);  // *iter's predecessor is also taken care of
 }
 
 MachineBasicBlock *AMDGPUCFGStructurizer::clone(MachineBasicBlock *MBB) {
   MachineFunction *Func = MBB->getParent();
-  MachineBasicBlock *NewMBB = Func->CreateMachineBasicBlock();
+  MachineBasicBlock *NewMBB = Func->createMachineBasicBlock();
   Func->push_back(NewMBB);  //insert to function
   for (const MachineInstr &It : *MBB)
-    NewMBB->push_back(Func->CloneMachineInstr(&It));
+    NewMBB->push_back(Func->cloneMachineInstr(&It));
   return NewMBB;
 }
 
 void AMDGPUCFGStructurizer::replaceInstrUseOfBlockWith(
     MachineBasicBlock *SrcMBB, MachineBasicBlock *OldMBB,
     MachineBasicBlock *NewBlk) {
   MachineInstr *BranchMI = getLoopendBlockBranchInstr(SrcMBB);
   if (BranchMI && isCondBranch(BranchMI) &&
AMDGPUCFGStructurizer::normalizeInfiniteLoopExit(MachineLoop* LoopRep) {
 
   if (!LoopHeader || !LoopLatch)
     return nullptr;
   MachineInstr *BranchMI = getLoopendBlockBranchInstr(LoopLatch);
   // Is LoopRep an infinite loop ?
   if (!BranchMI || !isUncondBranch(BranchMI))
     return nullptr;
 
-  MachineBasicBlock *DummyExitBlk = FuncRep->CreateMachineBasicBlock();
+  MachineBasicBlock *DummyExitBlk = FuncRep->createMachineBasicBlock();
   FuncRep->push_back(DummyExitBlk);  //insert to function
   SHOWNEWBLK(DummyExitBlk, "DummyExitBlock to normalize infiniteLoop: ");
   LLVM_DEBUG(dbgs() << "Old branch instr: " << *BranchMI << "\n";);
   LLVMContext &Ctx = LoopHeader->getParent()->getFunction().getContext();
   Ctx.emitError("Extra register needed to handle CFG");
   return nullptr;
 }
 
void AMDGPUCFGStructurizer::removeRedundantConditionalBranch(
   LLVM_DEBUG(dbgs() << "Removing unneeded cond branch instr: " << *BranchMI);
   BranchMI->eraseFromParent();
   SHOWNEWBLK(MBB1, "Removing redundant successor");
   MBB->removeSuccessor(MBB1, true);
 }
 
 void AMDGPUCFGStructurizer::addDummyExitBlock(
     SmallVectorImpl<MachineBasicBlock*> &RetMBB) {
-  MachineBasicBlock *DummyExitBlk = FuncRep->CreateMachineBasicBlock();
+  MachineBasicBlock *DummyExitBlk = FuncRep->createMachineBasicBlock();
   FuncRep->push_back(DummyExitBlk);  //insert to function
   insertInstrEnd(DummyExitBlk, R600::RETURN);
 
   for (MachineBasicBlock *MBB : RetMBB) {
     if (MachineInstr *MI = getReturnInstr(MBB))
       MI->eraseFromParent();
     MBB->addSuccessor(DummyExitBlk);
     LLVM_DEBUG(dbgs() << "Add dummyExitBlock to BB" << MBB->getNumber()

llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

if (Use == Src0) {
       if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,
                                         OldOpndValue, CombBCZ, IsShrinkable)) {
         DPPMIs.push_back(DPPInst);
         Rollback = false;
       }
     } else {
       assert(Use == Src1 && OrigMI.isCommutable()); // by check [1]
       auto *BB = OrigMI.getParent();
-      auto *NewMI = BB->getParent()->CloneMachineInstr(&OrigMI);
+      auto *NewMI = BB->getParent()->cloneMachineInstr(&OrigMI);
       BB->insert(OrigMI, NewMI);
       if (TII->commuteInstruction(*NewMI)) {
         LLVM_DEBUG(dbgs() << "  commuted:  " << *NewMI);
         if (auto *DPPInst =
                 createDPPInst(*NewMI, MovMI, CombOldVGPR, OldOpndValue, CombBCZ,
                               IsShrinkable)) {
           DPPMIs.push_back(DPPInst);
           Rollback = false;

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

 /// \returns { LoopBody, Remainder }
 static std::pair<MachineBasicBlock *, MachineBasicBlock *>
 splitBlockForLoop(MachineInstr &MI, MachineBasicBlock &MBB, bool InstInLoop) {
   MachineFunction *MF = MBB.getParent();
   MachineBasicBlock::iterator I(&MI);
 
   // To insert the loop we need to split the block. Move everything after this
   // point to a new block, and insert a new empty block between the two.
-  MachineBasicBlock *LoopBB = MF->CreateMachineBasicBlock();
-  MachineBasicBlock *RemainderBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *LoopBB = MF->createMachineBasicBlock();
+  MachineBasicBlock *RemainderBB = MF->createMachineBasicBlock();
   MachineFunction::iterator MBBI(MBB);
   ++MBBI;
 
   MF->insert(MBBI, LoopBB);
   MF->insert(MBBI, RemainderBB);
 
   LoopBB->addSuccessor(LoopBB);
   LoopBB->addSuccessor(RemainderBB);
loadM0FromVGPR(const SIInstrInfo *TII, MachineBasicBlock &MBB, MachineInstr &MI,
   std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, MBB, false);
 
   const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
 
   auto InsPt = emitLoadM0FromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, *Idx,
                                       InitResultReg, DstReg, PhiReg, TmpExec,
                                       Offset, UseGPRIdxMode, SGPRIdxReg);
 
-  MachineBasicBlock* LandingPad = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *LandingPad = MF->createMachineBasicBlock();
   MachineFunction::iterator MBBI(LoopBB);
   ++MBBI;
   MF->insert(MBBI, LandingPad);
   LoopBB->removeSuccessor(RemainderBB);
   LandingPad->addSuccessor(RemainderBB);
   LoopBB->addSuccessor(LandingPad);
   MachineBasicBlock::iterator First = LandingPad->begin();
   BuildMI(*LandingPad, First, DL, TII->get(MovExecOpc), Exec)

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

for (auto &MO : I->uses()) {
       if (MO.isReg() && MO.isUse()) {
         MRI.clearKillFlags(MO.getReg());
       }
     }
   }
 
   // To insert the loop we need to split the block. Move everything after this
   // point to a new block, and insert a new empty block between the two.
-  MachineBasicBlock *LoopBB = MF.CreateMachineBasicBlock();
-  MachineBasicBlock *RemainderBB = MF.CreateMachineBasicBlock();
+  MachineBasicBlock *LoopBB = MF.createMachineBasicBlock();
+  MachineBasicBlock *RemainderBB = MF.createMachineBasicBlock();
   MachineFunction::iterator MBBI(MBB);
   ++MBBI;
 
   MF.insert(MBBI, LoopBB);
   MF.insert(MBBI, RemainderBB);
 
   LoopBB->addSuccessor(LoopBB);
   LoopBB->addSuccessor(RemainderBB);

llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp

for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
       default:
         break;
       }
     }
   }
 
   // Lower any early exit branches first
   if (!EarlyTermInstrs.empty()) {
-    MachineBasicBlock *EarlyExitBlock = MF.CreateMachineBasicBlock();
+    MachineBasicBlock *EarlyExitBlock = MF.createMachineBasicBlock();
     DebugLoc DL;
 
     MF.insert(MF.end(), EarlyExitBlock);
     BuildMI(*EarlyExitBlock, EarlyExitBlock->end(), DL, TII->get(MovOpc),
             ExecReg)
         .addImm(0);
     generateEndPgm(*EarlyExitBlock, EarlyExitBlock->end(), DL, TII, MF);
 
bool SILateBranchLowering::runOnMachineFunction(MachineFunction &MF) {
   // Now check return to epilog instructions occur at function end
   if (!EpilogInstrs.empty()) {
     MachineBasicBlock *EmptyMBBAtEnd = nullptr;
     assert(!MF.getInfo<SIMachineFunctionInfo>()->returnsVoid());
 
     // If there are multiple returns to epilog then all will
     // become jumps to new empty end block.
     if (EpilogInstrs.size() > 1) {
-      EmptyMBBAtEnd = MF.CreateMachineBasicBlock();
+      EmptyMBBAtEnd = MF.createMachineBasicBlock();
       MF.insert(MF.end(), EmptyMBBAtEnd);
     }
 
     for (auto MI : EpilogInstrs) {
       auto MBB = MI->getParent();
       if (MBB == &MF.back() && MI == &MBB->back())
         continue;
 
       // SI_RETURN_TO_EPILOG is not the last instruction.
       // Jump to empty block at function end.
       if (!EmptyMBBAtEnd) {
-        EmptyMBBAtEnd = MF.CreateMachineBasicBlock();
+        EmptyMBBAtEnd = MF.createMachineBasicBlock();
         MF.insert(MF.end(), EmptyMBBAtEnd);
       }
 
       MBB->addSuccessor(EmptyMBBAtEnd);
       MDT->getBase().insertEdge(MBB, EmptyMBBAtEnd);
       BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(AMDGPU::S_BRANCH))
           .addMBB(EmptyMBBAtEnd);
       MI->eraseFromParent();
       MadeChange = true;
     }
 
     EpilogInstrs.clear();
   }
 
   return MadeChange;
 }

llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp

 }
 
 bool SIPreEmitPeephole::runOnMachineFunction(MachineFunction &MF) {
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   TII = ST.getInstrInfo();
   TRI = &TII->getRegisterInfo();
   bool Changed = false;
 
-  MF.RenumberBlocks();
+  MF.renumberBlocks();
 
   for (MachineBasicBlock &MBB : MF) {
     MachineBasicBlock::iterator TermI = MBB.getFirstTerminator();
     // Check first terminator for branches to optimize
     if (TermI != MBB.end()) {
       MachineInstr &MI = *TermI;
       switch (MI.getOpcode()) {
       case AMDGPU::S_CBRANCH_VCCZ:

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

 void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator I,
                                      Register DestReg, unsigned SubIdx,
                                      const MachineInstr &Orig,
                                      const TargetRegisterInfo &TRI) const {
   unsigned Opcode = Orig.getOpcode();
   switch (Opcode) {
   default: {
-    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
+    MachineInstr *MI = MBB.getParent()->cloneMachineInstr(&Orig);
     MI->substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
     MBB.insert(I, MI);
     break;
   }
   case ARM::tLDRpci_pic:
   case ARM::t2LDRpci_pic: {
     MachineFunction &MF = *MBB.getParent();
     unsigned CPI = Orig.getOperand(1).getIndex();

llvm/lib/Target/ARM/ARMBlockPlacement.cpp

bool ARMBlockPlacement::revertWhileToDoLoop(MachineInstr *WLS) {
   assert(Br->getOperand(1).getImm() == 14);
 
   // Clear the kill flags, as the cmp/bcc will no longer kill any operands.
   WLS->getOperand(1).setIsKill(false);
   if (WLS->getOpcode() == ARM::t2WhileLoopStartTP)
     WLS->getOperand(2).setIsKill(false);
 
   // Create the new block
-  MachineBasicBlock *NewBlock = Preheader->getParent()->CreateMachineBasicBlock(
+  MachineBasicBlock *NewBlock = Preheader->getParent()->createMachineBasicBlock(
       Preheader->getBasicBlock());
   Preheader->getParent()->insert(++Preheader->getIterator(), NewBlock);
   // Move the Br to it
   Br->removeFromParent();
   NewBlock->insert(NewBlock->end(), Br);
   // And setup the successors correctly.
   Preheader->replaceSuccessor(Br->getOperand(0).getMBB(), NewBlock);
   NewBlock->addSuccessor(Br->getOperand(0).getMBB());
bool ARMBlockPlacement::revertWhileToDoLoop(MachineInstr *WLS) {
   LLVM_DEBUG(dbgs() << DEBUG_PREFIX
                     << "Reverting While Loop to Do Loop: " << *WLS << "\n");
 
   RevertWhileLoopStartLR(WLS, TII, ARM::t2Bcc, true);
 
   LivePhysRegs LiveRegs;
   computeAndAddLiveIns(LiveRegs, *NewBlock);
 
-  Preheader->getParent()->RenumberBlocks();
+  Preheader->getParent()->renumberBlocks();
   BBUtils->computeAllBlockSizes();
   BBUtils->adjustBBOffsetsAfter(Preheader);
 
   return true;
 }
 
 /// Checks if loop has a backwards branching WLS, and if possible, fixes it.
 /// This requires checking the predecessor (ie. preheader or it's predecessor)
if (skipFunction(MF.getFunction()))
     return false;
   const ARMSubtarget &ST = static_cast<const ARMSubtarget &>(MF.getSubtarget());
   if (!ST.hasLOB())
     return false;
   LLVM_DEBUG(dbgs() << DEBUG_PREFIX << "Running on " << MF.getName() << "\n");
   MLI = &getAnalysis<MachineLoopInfo>();
   TII = static_cast<const ARMBaseInstrInfo *>(ST.getInstrInfo());
   BBUtils = std::unique_ptr<ARMBasicBlockUtils>(new ARMBasicBlockUtils(MF));
-  MF.RenumberBlocks();
+  MF.renumberBlocks();
   BBUtils->computeAllBlockSizes();
   BBUtils->adjustBBOffsetsAfter(&MF.front());
   bool Changed = false;
   RevertedWhileLoops.clear();
 
   // Find loops with a backwards branching WLS and fix if possible.
   for (auto *ML : *MLI)
     Changed |= processPostOrderLoops(ML);
if (BBPrevious->isSuccessor(BB))
     FixFallthrough(BBPrevious, BB);
   // Fix fall through from the destination BB to the one that used to before it.
   if (BeforePrev->isSuccessor(Before))
     FixFallthrough(BeforePrev, Before);
   // Fix fall through from the moved BB to the one that used to follow.
   if (BBNext && BB->isSuccessor(BBNext))
     FixFallthrough(BB, BBNext);
 
-  F->RenumberBlocks();
+  F->renumberBlocks();
   BBUtils->computeAllBlockSizes();
   BBUtils->adjustBBOffsetsAfter(BB);
 }

llvm/lib/Target/ARM/ARMConstantIslandPass.cpp

bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
   bool GenerateTBB = isThumb2 || (isThumb1 && SynthesizeThumb1TBB);
   // TBB generation code in this constant island pass has not been adapted to
   // deal with speculation barriers.
   if (STI->hardenSlsRetBr())
     GenerateTBB = false;
 
   // Renumber all of the machine basic blocks in the function, guaranteeing that
   // the numbers agree with the position of the block in the function.
-  MF->RenumberBlocks();
+  MF->renumberBlocks();
 
   // Try to reorder and otherwise adjust the block layout to make good use
   // of the TB[BH] instructions.
   bool MadeChange = false;
   if (GenerateTBB && AdjustJumpTableBlocks) {
     scanFunctionJumpTables();
     MadeChange |= reorderThumb2JumpTables();
     // Data is out of date, so clear it. It'll be re-computed later.
     T2JumpTables.clear();
     // Blocks may have shifted around. Keep the numbering up to date.
-    MF->RenumberBlocks();
+    MF->renumberBlocks();
   }
 
   // Align any non-fallthrough blocks
   MadeChange |= AlignBlocks(MF, STI);
 
   // Perform the initial placement of the constant pool entries.  To start with,
   // we put them all at the end of the function.
   std::vector<MachineInstr*> CPEMIs;
bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
   return MadeChange;
 }
 
 /// Perform the initial placement of the regular constant pool entries.
 /// To start with, we put them all at the end of the function.
 void
 ARMConstantIslands::doInitialConstPlacement(std::vector<MachineInstr*> &CPEMIs) {
   // Create the basic block to hold the CPE's.
-  MachineBasicBlock *BB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *BB = MF->createMachineBasicBlock();
   MF->push_back(BB);
 
   // MachineConstantPool measures alignment in bytes.
   const Align MaxAlign = MCP->getConstantPoolAlign();
   const unsigned MaxLogAlign = Log2(MaxAlign);
 
   // Mark the basic block as required by the const-pool.
   BB->setAlignment(MaxAlign);
case ARM::t2TBH_JT:
       break;
     }
 
     unsigned NumOps = MI->getDesc().getNumOperands();
     MachineOperand JTOp =
       MI->getOperand(NumOps - (MI->isPredicable() ? 2 : 1));
     unsigned JTI = JTOp.getIndex();
     unsigned Size = JT[JTI].MBBs.size() * sizeof(uint32_t);
-    MachineBasicBlock *JumpTableBB = MF->CreateMachineBasicBlock();
+    MachineBasicBlock *JumpTableBB = MF->createMachineBasicBlock();
     MF->insert(std::next(MachineFunction::iterator(MBB)), JumpTableBB);
     MachineInstr *CPEMI = BuildMI(*JumpTableBB, JumpTableBB->begin(),
                                   DebugLoc(), TII->get(JTOpcode))
                               .addImm(i++)
                               .addJumpTableIndex(JTI)
                               .addImm(Size);
     CPEMIs.push_back(CPEMI);
     CPEntries.emplace_back(1, CPEntry(CPEMI, JTI));
     JumpTableEntryIndices.insert(std::make_pair(JTI, CPEntries.size() - 1));
     if (!LastCorrectlyNumberedBB)
       LastCorrectlyNumberedBB = &MBB;
   }
 
   // If we did anything then we need to renumber the subsequent blocks.
   if (LastCorrectlyNumberedBB)
-    MF->RenumberBlocks(LastCorrectlyNumberedBB);
+    MF->renumberBlocks(LastCorrectlyNumberedBB);
 }
 
 /// BBHasFallthrough - Return true if the specified basic block can fallthrough
 /// into the block immediately after it.
 bool ARMConstantIslands::BBHasFallthrough(MachineBasicBlock *MBB) {
   // Get the next machine basic block in the function.
   MachineFunction::iterator MBBI = MBB->getIterator();
   // Can't fall off end of function.
static bool CompareMBBNumbers(const MachineBasicBlock *LHS,
   return LHS->getNumber() < RHS->getNumber();
 }
 
 /// updateForInsertedWaterBlock - When a block is newly inserted into the
 /// machine function, it upsets all of the block numbers.  Renumber the blocks
 /// and update the arrays that parallel this numbering.
 void ARMConstantIslands::updateForInsertedWaterBlock(MachineBasicBlock *NewBB) {
   // Renumber the MBB's to keep them consecutive.
-  NewBB->getParent()->RenumberBlocks(NewBB);
+  NewBB->getParent()->renumberBlocks(NewBB);
 
   // Insert an entry into BBInfo to align it properly with the (newly
   // renumbered) block numbers.
   BBUtils->insert(NewBB->getNumber(), BasicBlockInfo());
 
   // Next, update WaterList.  Specifically, we need to add NewMBB as having
   // available water after it.
   water_iterator IP = llvm::lower_bound(WaterList, NewBB, CompareMBBNumbers);
MachineBasicBlock *ARMConstantIslands::splitBlockBeforeInstr(MachineInstr *MI) {
   LivePhysRegs LRs(*MF->getSubtarget().getRegisterInfo());
   LRs.addLiveOuts(*OrigBB);
   auto LivenessEnd = ++MachineBasicBlock::iterator(MI).getReverse();
   for (MachineInstr &LiveMI : make_range(OrigBB->rbegin(), LivenessEnd))
     LRs.stepBackward(LiveMI);
 
   // Create a new MBB for the code after the OrigBB.
   MachineBasicBlock *NewBB =
-    MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
+      MF->createMachineBasicBlock(OrigBB->getBasicBlock());
   MachineFunction::iterator MBBI = ++OrigBB->getIterator();
   MF->insert(MBBI, NewBB);
 
   // Splice the instructions starting with MI over to NewBB.
   NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
 
   // Add an unconditional branch from OrigBB to NewBB.
   // Note the new unconditional branch is not being recorded.
MachineBasicBlock *ARMConstantIslands::splitBlockBeforeInstr(MachineInstr *MI) {
   MachineRegisterInfo &MRI = MF->getRegInfo();
   for (MCPhysReg L : LRs)
     if (!MRI.isReserved(L))
       NewBB->addLiveIn(L);
 
   // Update internal data structures to account for the newly inserted MBB.
   // This is almost the same as updateForInsertedWaterBlock, except that
   // the Water goes after OrigBB, not NewBB.
-  MF->RenumberBlocks(NewBB);
+  MF->renumberBlocks(NewBB);
 
   // Insert an entry into BBInfo to align it properly with the (newly
   // renumbered) block numbers.
   BBUtils->insert(NewBB->getNumber(), BasicBlockInfo());
 
   // Next, update WaterList.  Specifically, we need to add OrigMBB as having
   // available water after it (but not if it's already there, which happens
   // when splitting before a conditional branch that is followed by an
bool ARMConstantIslands::handleConstantPoolUser(unsigned CPUserIndex,
   if (result==1) return false;
   else if (result==2) return true;
 
   // No existing clone of this CPE is within range.
   // We will be generating a new clone.  Get a UID for it.
   unsigned ID = AFI->createPICLabelUId();
 
   // Look for water where we can place this CPE.
-  MachineBasicBlock *NewIsland = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *NewIsland = MF->createMachineBasicBlock();
   MachineBasicBlock *NewMBB;
   water_iterator IP;
   if (findAvailableWater(U, UserOffset, IP, CloserWater)) {
     LLVM_DEBUG(dbgs() << "Found water in range\n");
     MachineBasicBlock *WaterBB = *IP;
 
     // If the original WaterList entry was "new water" on this iteration,
     // propagate that to the new island.  This is just keeping NewWaterList
MachineBasicBlock *ARMConstantIslands::adjustJTTargetBlockForward(
   // has to have an analyzable terminator for us to move this one. Be paranoid
   // and make sure we're not trying to move the entry block of the function.
   if (!B && Cond.empty() && BB != &MF->front() &&
       !TII->analyzeBranch(*OldPrior, TBB, FBB, CondPrior)) {
     BB->moveAfter(JTBB);
     OldPrior->updateTerminator(BB);
     BB->updateTerminator(OldNext != MF->end() ? &*OldNext : nullptr);
     // Update numbering to account for the block being moved.
-    MF->RenumberBlocks();
+    MF->renumberBlocks();
     ++NumJTMoved;
     return nullptr;
   }
 
   // Create a new MBB for the code after the jump BB.
-  MachineBasicBlock *NewBB =
-    MF->CreateMachineBasicBlock(JTBB->getBasicBlock());
+  MachineBasicBlock *NewBB = MF->createMachineBasicBlock(JTBB->getBasicBlock());
   MachineFunction::iterator MBBI = ++JTBB->getIterator();
   MF->insert(MBBI, NewBB);
 
   // Copy live-in information to new block.
   for (const MachineBasicBlock::RegisterMaskPair &RegMaskPair : BB->liveins())
     NewBB->addLiveIn(RegMaskPair);
 
   // Add an unconditional branch from NewBB to BB.
   // There doesn't seem to be meaningful DebugInfo available; this doesn't
   // correspond directly to anything in the source.
   if (isThumb2)
     BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B))
         .addMBB(BB)
         .add(predOps(ARMCC::AL));
   else
     BuildMI(NewBB, DebugLoc(), TII->get(ARM::tB))
         .addMBB(BB)
         .add(predOps(ARMCC::AL));
 
   // Update internal data structures to account for the newly inserted MBB.
-  MF->RenumberBlocks(NewBB);
+  MF->renumberBlocks(NewBB);
 
   // Update the CFG.
   NewBB->addSuccessor(BB);
   JTBB->replaceSuccessor(BB, NewBB);
 
   if (MF->getInfo<ARMFunctionInfo>()->branchTargetEnforcement())
     fixupBTI(JTI, *BB, *NewBB);
 

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

ARMExpandPseudo::CMSEClearFPRegsV8(MachineBasicBlock &MBB,
   // If optimising for minimum size, clear FP registers unconditionally.
   // Otherwise, check the CONTROL.SFPA (Secure Floating-Point Active) bit and
   // don't clear them if they belong to the non-secure state.
   MachineBasicBlock *ClearBB, *DoneBB;
   if (STI->hasMinSize()) {
     ClearBB = DoneBB = &MBB;
   } else {
     MachineFunction *MF = MBB.getParent();
-    ClearBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-    DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+    ClearBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+    DoneBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
 
     MF->insert(++MBB.getIterator(), ClearBB);
     MF->insert(++ClearBB->getIterator(), DoneBB);
 
     DoneBB->splice(DoneBB->end(), &MBB, MBBI, MBB.end());
     DoneBB->transferSuccessors(&MBB);
     MBB.addSuccessor(ClearBB);
     MBB.addSuccessor(DoneBB);
assert(STI->hasV8MBaselineOps() &&
            "CMP_SWAP not expected to be custom expanded for Thumb1");
     assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) &&
            "ARMv8-M.baseline does not have t2UXTB/t2UXTH");
     assert((UxtOp == 0 || ARM::tGPRRegClass.contains(DesiredReg)) &&
            "DesiredReg used for UXT op must be tGPR");
   }
 
   MachineFunction *MF = MBB.getParent();
-  auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+  auto LoadCmpBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto StoreBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto DoneBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
 
   MF->insert(++MBB.getIterator(), LoadCmpBB);
   MF->insert(++LoadCmpBB->getIterator(), StoreBB);
   MF->insert(++StoreBB->getIterator(), DoneBB);
 
   if (UxtOp) {
     MachineInstrBuilder MIB =
         BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg)
bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
   New.setIsKill(false);
 
   Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
   Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
   Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);
   Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);
 
   MachineFunction *MF = MBB.getParent();
-  auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+  auto LoadCmpBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto StoreBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto DoneBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
 
   MF->insert(++MBB.getIterator(), LoadCmpBB);
   MF->insert(++LoadCmpBB->getIterator(), StoreBB);
   MF->insert(++StoreBB->getIterator(), DoneBB);
 
   // .Lloadcmp:
   //     ldrexd rDestLo, rDestHi, [rAddr]
   //     cmp rDestLo, rDesiredLo

llvm/lib/Target/ARM/ARMFrameLowering.cpp

void ARMFrameLowering::adjustForSegmentedStacks(
   }
 
   // Use R4 and R5 as scratch registers.
   // We save R4 and R5 before use and restore them before leaving the function.
   unsigned ScratchReg0 = ARM::R4;
   unsigned ScratchReg1 = ARM::R5;
   uint64_t AlignedStackSize;
 
-  MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock();
-  MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock();
-  MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock();
-  MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock();
-  MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock();
+  MachineBasicBlock *PrevStackMBB = MF.createMachineBasicBlock();
+  MachineBasicBlock *PostStackMBB = MF.createMachineBasicBlock();
+  MachineBasicBlock *AllocMBB = MF.createMachineBasicBlock();
+  MachineBasicBlock *GetMBB = MF.createMachineBasicBlock();
+  MachineBasicBlock *McrMBB = MF.createMachineBasicBlock();
 
   // Grab everything that reaches PrologueMBB to update there liveness as well.
   SmallPtrSet<MachineBasicBlock *, 8> BeforePrologueRegion;
   SmallVector<MachineBasicBlock *, 2> WalkList;
   WalkList.push_back(&PrologueMBB);
 
   do {
     MachineBasicBlock *CurMBB = WalkList.pop_back_val();

llvm/lib/Target/ARM/ARMISelLowering.cpp

void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
   // Create the jump table and associated information.
   MachineJumpTableInfo *JTI =
     MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
   unsigned MJTI = JTI->createJumpTableIndex(LPadList);
 
   // Create the MBBs for the dispatch code.
 
   // Shove the dispatch's address into the return slot in the function context.
-  MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *DispatchBB = MF->createMachineBasicBlock();
   DispatchBB->setIsEHPad();
 
-  MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *TrapBB = MF->createMachineBasicBlock();
   unsigned trap_opcode;
   if (Subtarget->isThumb())
     trap_opcode = ARM::tTRAP;
   else
     trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
 
   BuildMI(TrapBB, dl, TII->get(trap_opcode));
   DispatchBB->addSuccessor(TrapBB);
 
-  MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *DispContBB = MF->createMachineBasicBlock();
   DispatchBB->addSuccessor(DispContBB);
 
   // Insert and MBBs.
   MF->insert(MF->end(), DispatchBB);
   MF->insert(MF->end(), DispContBB);
   MF->insert(MF->end(), TrapBB);
 
   // Insert code into the entry block that creates and registers the function
ARMTargetLowering::EmitStructByval(MachineInstr &MI,
   //   [destLoop] = STR_POST(scratch, destPhi, UnitSize)
   //   subs varLoop, varPhi, #UnitSize
   //   bne loopMBB
   //   fallthrough --> exitMBB
   // exitMBB:
   //   epilogue to handle left-over bytes
   //   [scratch, srcOut] = LDRB_POST(srcLoop, 1)
   //   [destOut] = STRB_POST(scratch, destLoop, 1)
-  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *loopMBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *exitMBB = MF->createMachineBasicBlock(LLVM_BB);
   MF->insert(It, loopMBB);
   MF->insert(It, exitMBB);
 
   // Transfer the remainder of BB and its successor edges to exitMBB.
   exitMBB->splice(exitMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
 

 
 MachineBasicBlock *
 ARMTargetLowering::EmitLowered__dbzchk(MachineInstr &MI,
                                        MachineBasicBlock *MBB) const {
   DebugLoc DL = MI.getDebugLoc();
   MachineFunction *MF = MBB->getParent();
   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
 
-  MachineBasicBlock *ContBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *ContBB = MF->createMachineBasicBlock();
   MF->insert(++MBB->getIterator(), ContBB);
   ContBB->splice(ContBB->begin(), MBB,
                  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
   ContBB->transferSuccessorsAndUpdatePHIs(MBB);
   MBB->addSuccessor(ContBB);
 
-  MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *TrapBB = MF->createMachineBasicBlock();
   BuildMI(TrapBB, DL, TII->get(ARM::t__brkdiv0));
   MF->push_back(TrapBB);
   MBB->addSuccessor(TrapBB);
 
   BuildMI(*MBB, MI, DL, TII->get(ARM::tCMPi8))
       .addReg(MI.getOperand(0).getReg())
       .addImm(0)
       .add(predOps(ARMCC::AL));
case ARM::MVE_MEMSETLOOPINST: {
     MachineRegisterInfo &MRI = MF->getRegInfo();
 
     Register OpDestReg = MI.getOperand(0).getReg();
     Register OpSrcReg = MI.getOperand(1).getReg();
     Register OpSizeReg = MI.getOperand(2).getReg();
 
     // Allocate the required MBBs and add to parent function.
     MachineBasicBlock *TpEntry = BB;
-    MachineBasicBlock *TpLoopBody = MF->CreateMachineBasicBlock();
+    MachineBasicBlock *TpLoopBody = MF->createMachineBasicBlock();
     MachineBasicBlock *TpExit;
 
     MF->push_back(TpLoopBody);
 
     // If any instructions are present in the current block after
     // MVE_MEMCPYLOOPINST or MVE_MEMSETLOOPINST, split the current block and
     // move the instructions into the newly created exit block. If there are no
     // instructions add an explicit branch to the FallThrough block and then
case ARM::tMOVCCr_pseudo: {
     //  thisMBB:
     //  ...
     //   TrueVal = ...
     //   cmpTY ccX, r1, r2
     //   bCC copy1MBB
     //   fallthrough --> copy0MBB
     MachineBasicBlock *thisMBB  = BB;
     MachineFunction *F = BB->getParent();
-    MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *copy0MBB = F->createMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *sinkMBB = F->createMachineBasicBlock(LLVM_BB);
     F->insert(It, copy0MBB);
     F->insert(It, sinkMBB);
 
     // Check whether CPSR is live past the tMOVCCr_pseudo.
     const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
     if (!MI.killsRegister(ARM::CPSR) &&
         !checkAndUpdateCPSRKill(MI, thisMBB, TRI)) {
       copy0MBB->addLiveIn(ARM::CPSR);
case ARM::t2ABS: {
     // into
     //     V2 = MOVS V0
     //     BCC                      (branch to SinkBB if V0 >= 0)
     //     RSBBB: V3 = RSBri V2, 0  (compute ABS if V2 < 0)
     //     SinkBB: V1 = PHI(V2, V3)
     const BasicBlock *LLVM_BB = BB->getBasicBlock();
     MachineFunction::iterator BBI = ++BB->getIterator();
     MachineFunction *Fn = BB->getParent();
-    MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *SinkBB  = Fn->CreateMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *RSBBB = Fn->createMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *SinkBB = Fn->createMachineBasicBlock(LLVM_BB);
     Fn->insert(BBI, RSBBB);
     Fn->insert(BBI, SinkBB);
 
     Register ABSSrcReg = MI.getOperand(1).getReg();
     Register ABSDstReg = MI.getOperand(0).getReg();
     bool ABSSrcKIll = MI.getOperand(1).isKill();
     bool isThumb2 = Subtarget->isThumb2();
     MachineRegisterInfo &MRI = Fn->getRegInfo();

llvm/lib/Target/ARM/Thumb1FrameLowering.cpp

for (unsigned i = CSI.size(); i != 0; --i) {
     MIB.addReg(Reg, getDefRegState(true));
     NeedsPop = true;
   }
 
   // It's illegal to emit pop instruction without operands.
   if (NeedsPop)
     MBB.insert(MI, &*MIB);
   else
-    MF.DeleteMachineInstr(MIB);
+    MF.deleteMachineInstr(MIB);
 
   return true;
 }

llvm/lib/Target/AVR/AVRISelLowering.cpp

MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
 
   MachineFunction::iterator I;
   for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I)
     ;
   if (I != F->end())
     ++I;
 
   // Create loop block.
-  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *LoopBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *CheckBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *RemBB = F->createMachineBasicBlock(LLVM_BB);
 
   F->insert(I, LoopBB);
   F->insert(I, CheckBB);
   F->insert(I, RemBB);
 
   // Update machine-CFG edges by transferring all successors of the current
   // block to the block containing instructions after shift.
   RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
 
   // If the current basic block falls through to another basic block,
   // we must insert an unconditional branch to the fallthrough destination
   // if we are to insert basic blocks at the prior fallthrough point.
   if (FallThrough != nullptr) {
     BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
   }
 
-  MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *trueMBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *falseMBB = MF->createMachineBasicBlock(LLVM_BB);
 
   MachineFunction::iterator I;
   for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I)
     ;
   if (I != MF->end())
     ++I;
   MF->insert(I, trueMBB);
   MF->insert(I, falseMBB);

llvm/lib/Target/BPF/BPFISelLowering.cpp

#endif
 
   // ThisMBB:
   // ...
   //  TrueVal = ...
   //  jmp_XX r1, r2 goto Copy1MBB
   //  fallthrough --> Copy0MBB
   MachineBasicBlock *ThisMBB = BB;
   MachineFunction *F = BB->getParent();
-  MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *Copy0MBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *Copy1MBB = F->createMachineBasicBlock(LLVM_BB);
 
   F->insert(I, Copy0MBB);
   F->insert(I, Copy1MBB);
   // Update machine-CFG edges by transferring all successors of the current
   // block to the new block which will contain the Phi node for the select.
   Copy1MBB->splice(Copy1MBB->begin(), BB,
                    std::next(MachineBasicBlock::iterator(MI)), BB->end());
   Copy1MBB->transferSuccessorsAndUpdatePHIs(BB);

llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp

if (TII->analyzeBranch(*ExitingBlock, TB, FB, Tmp1, false))
     return nullptr;
 
   for (MachineBasicBlock *PB : Preds) {
     bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp1, false);
     if (NotAnalyzed)
       return nullptr;
   }
 
-  MachineBasicBlock *NewPH = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *NewPH = MF->createMachineBasicBlock();
   MF->insert(Header->getIterator(), NewPH);
 
   if (Header->pred_size() > 2) {
     // Ensure that the header has only two predecessors: the preheader and
     // the loop latch.  Any additional predecessors of the header should
     // join at the newly created preheader. Inspect all PHI nodes from the
     // header and create appropriate corresponding PHI nodes in the preheader.
 
     for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
          I != E && I->isPHI(); ++I) {
       MachineInstr *PN = &*I;
 
       const MCInstrDesc &PD = TII->get(TargetOpcode::PHI);
-      MachineInstr *NewPN = MF->CreateMachineInstr(PD, DL);
+      MachineInstr *NewPN = MF->createMachineInstr(PD, DL);
       NewPH->insert(NewPH->end(), NewPN);
 
       Register PR = PN->getOperand(0).getReg();
       const TargetRegisterClass *RC = MRI->getRegClass(PR);
       Register NewPR = MRI->createVirtualRegister(RC);
       NewPN->addOperand(MachineOperand::CreateReg(NewPR, true));
 
       // Copy all non-latch operands of a header's PHI node to the newly

llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp

if (TII->mayBeNewStore(*MI)) {
       // Make sure the register to be stored is defined by an instruction in the
       // packet.
       MachineOperand &MO = MI->getOperand(MI->getNumOperands() - 1);
       if (!MO.isReg() || RegDefs.count(MO.getReg()) == 0)
         return Hazard;
       // The .new store version uses different resources so check if it
       // causes a hazard.
       MachineFunction *MF = MI->getParent()->getParent();
-      MachineInstr *NewMI =
-        MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
-                               MI->getDebugLoc());
+      MachineInstr *NewMI = MF->createMachineInstr(
+          TII->get(TII->getDotNewOp(*MI)), MI->getDebugLoc());
       if (Resources->canReserveResources(*NewMI))
         RetVal = NoHazard;
       LLVM_DEBUG(dbgs() << "*** Try .new version? " << (RetVal == NoHazard)
                         << "\n");
-      MF->DeleteMachineInstr(NewMI);
+      MF->deleteMachineInstr(NewMI);
     }
     return RetVal;
   }
 
   if (SU == UsesDotCur && DotCurPNum != (int)PacketNum) {
     LLVM_DEBUG(dbgs() << "*** .cur Hazard in cycle " << PacketNum << ", "
                       << *MI);
     return Hazard;
void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) {
   if (TII->isZeroCost(MI->getOpcode()))
     return;
 
   if (!Resources->canReserveResources(*MI)) {
     // It must be a .new store since other instructions must be able to be
     // reserved at this point.
     assert(TII->mayBeNewStore(*MI) && "Expecting .new store");
     MachineFunction *MF = MI->getParent()->getParent();
-    MachineInstr *NewMI =
-        MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
-                               MI->getDebugLoc());
+    MachineInstr *NewMI = MF->createMachineInstr(
+        TII->get(TII->getDotNewOp(*MI)), MI->getDebugLoc());
     assert(Resources->canReserveResources(*NewMI));
     Resources->reserveResources(*NewMI);
-    MF->DeleteMachineInstr(NewMI);
+    MF->deleteMachineInstr(NewMI);
   }
   else
     Resources->reserveResources(*MI);
   LLVM_DEBUG(dbgs() << " Add instruction " << *MI);
 
   // When scheduling a dot cur instruction, check if there is an instruction
   // that can use the dot cur in the same packet. If so, we'll attempt to
   // schedule it before other instructions. We only do this if the load has a

llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

 
 bool HexagonPacketizerList::canReserveResourcesForConstExt() {
   return tryAllocateResourcesForConstExt(false);
 }
 
 // Allocate resources (i.e. 4 bytes) for constant extender. If succeeded,
 // return true, otherwise, return false.
 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(bool Reserve) {
-  auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
+  auto *ExtMI = MF.createMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
   bool Avail = ResourceTracker->canReserveResources(*ExtMI);
   if (Reserve && Avail)
     ResourceTracker->reserveResources(*ExtMI);
-  MF.DeleteMachineInstr(ExtMI);
+  MF.deleteMachineInstr(ExtMI);
   return Avail;
 }
 
 bool HexagonPacketizerList::isCallDependent(const MachineInstr &MI,
       SDep::Kind DepType, unsigned DepReg) {
   // Check for LR dependence.
   if (DepReg == HRI->getRARegister())
     return true;
bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr &MI,
 
   if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
     return false;
 
   // Create a dot new machine instruction to see if resources can be
   // allocated. If not, bail out now.
   int NewOpcode = HII->getDotNewOp(MI);
   const MCInstrDesc &D = HII->get(NewOpcode);
-  MachineInstr *NewMI = MF.CreateMachineInstr(D, DebugLoc());
+  MachineInstr *NewMI = MF.createMachineInstr(D, DebugLoc());
   bool ResourcesAvailable = ResourceTracker->canReserveResources(*NewMI);
-  MF.DeleteMachineInstr(NewMI);
+  MF.deleteMachineInstr(NewMI);
   if (!ResourcesAvailable)
     return false;
 
   // New Value Store only. New Value Jump generated as a separate pass.
   if (!canPromoteToNewValue(MI, PacketSU, DepReg, MII))
     return false;
 
   return true;

llvm/lib/Target/MSP430/MSP430BranchSelector.cpp

static bool isInRage(int DistanceInBytes) {
   return isInt<10>(Words);
 }
 
 /// Measure each basic block, fill the BlockOffsets, and return the size of
 /// the function, starting with BB
 unsigned MSP430BSel::measureFunction(OffsetVector &BlockOffsets,
                                      MachineBasicBlock *FromBB) {
   // Give the blocks of the function a dense, in-order, numbering.
-  MF->RenumberBlocks(FromBB);
+  MF->renumberBlocks(FromBB);
 
   MachineFunction::iterator Begin;
   if (FromBB == nullptr) {
     Begin = MF->begin();
   } else {
     Begin = FromBB->getIterator();
   }
 
for (auto MI = MBB->begin(), EE = MBB->end(); MI != EE; ++MI) {
       // If JCC is not the last instruction we need to split the MBB.
       if (MI->getOpcode() == MSP430::JCC && std::next(MI) != EE) {
 
         LLVM_DEBUG(dbgs() << "  Found a basic block that needs to be split, "
                           << printMBBReference(*MBB) << "\n");
 
         // Create a new basic block.
         MachineBasicBlock *NewBB =
-            MF->CreateMachineBasicBlock(MBB->getBasicBlock());
+            MF->createMachineBasicBlock(MBB->getBasicBlock());
         MF->insert(std::next(MBB), NewBB);
 
         // Splice the instructions following MI over to the NewBB.
         NewBB->splice(NewBB->end(), &*MBB, std::next(MI), MBB->end());
 
         // Update the successor lists.
         for (MachineBasicBlock *Succ : MBB->successors()) {
           if (Succ == DestBB) {

llvm/lib/Target/MSP430/MSP430ISelLowering.cpp

case MSP430::Rrcl16: {
     return BB;
   }
   }
 
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
   MachineFunction::iterator I = ++BB->getIterator();
 
   // Create loop block
-  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *LoopBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *RemBB = F->createMachineBasicBlock(LLVM_BB);
 
   F->insert(I, LoopBB);
   F->insert(I, RemBB);
 
   // Update machine-CFG edges by transferring all successors of the current
   // block to the block containing instructions after shift.
   RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
                 BB->end());
MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   //  thisMBB:
   //  ...
   //   TrueVal = ...
   //   cmpTY ccX, r1, r2
   //   jCC copy1MBB
   //   fallthrough --> copy0MBB
   MachineBasicBlock *thisMBB = BB;
   MachineFunction *F = BB->getParent();
-  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *copy0MBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *copy1MBB = F->createMachineBasicBlock(LLVM_BB);
   F->insert(I, copy0MBB);
   F->insert(I, copy1MBB);
   // Update machine-CFG edges by transferring all successors of the current
   // block to the new block which will contain the Phi node for the select.
   copy1MBB->splice(copy1MBB->begin(), BB,
                    std::next(MachineBasicBlock::iterator(MI)), BB->end());
   copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
   // Next, add the true and fallthrough blocks as its successors.

llvm/lib/Target/Mips/Mips16ISelLowering.cpp

Mips16TargetLowering::emitSel16(unsigned Opc, MachineInstr &MI,
   //  thisMBB:
   //  ...
   //   TrueVal = ...
   //   setcc r1, r2, r3
   //   bNE   r1, r0, copy1MBB
   //   fallthrough --> copy0MBB
   MachineBasicBlock *thisMBB  = BB;
   MachineFunction *F = BB->getParent();
-  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *copy0MBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *sinkMBB = F->createMachineBasicBlock(LLVM_BB);
   F->insert(It, copy0MBB);
   F->insert(It, sinkMBB);
 
   // Transfer the remainder of BB and its successor edges to sinkMBB.
   sinkMBB->splice(sinkMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
 
Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI,
   //  thisMBB:
   //  ...
   //   TrueVal = ...
   //   setcc r1, r2, r3
   //   bNE   r1, r0, copy1MBB
   //   fallthrough --> copy0MBB
   MachineBasicBlock *thisMBB  = BB;
   MachineFunction *F = BB->getParent();
-  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *copy0MBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *sinkMBB = F->createMachineBasicBlock(LLVM_BB);
   F->insert(It, copy0MBB);
   F->insert(It, sinkMBB);
 
   // Transfer the remainder of BB and its successor edges to sinkMBB.
   sinkMBB->splice(sinkMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
 
Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2,
   //  thisMBB:
   //  ...
   //   TrueVal = ...
   //   setcc r1, r2, r3
   //   bNE   r1, r0, copy1MBB
   //   fallthrough --> copy0MBB
   MachineBasicBlock *thisMBB  = BB;
   MachineFunction *F = BB->getParent();
-  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *copy0MBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *sinkMBB = F->createMachineBasicBlock(LLVM_BB);
   F->insert(It, copy0MBB);
   F->insert(It, sinkMBB);
 
   // Transfer the remainder of BB and its successor edges to sinkMBB.
   sinkMBB->splice(sinkMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
 

llvm/lib/Target/Mips/MipsBranchExpansion.cpp

void MipsBranchExpansion::splitMBB(MachineBasicBlock *MBB) {
   if ((FirstBr == End) ||
       (!FirstBr->isConditionalBranch() && !FirstBr->isUnconditionalBranch()))
     return;
 
   assert(!FirstBr->isIndirectBranch() && "Unexpected indirect branch found.");
 
   // Create a new MBB. Move instructions in MBB to the newly created MBB.
   MachineBasicBlock *NewMBB =
-      MFp->CreateMachineBasicBlock(MBB->getBasicBlock());
+      MFp->createMachineBasicBlock(MBB->getBasicBlock());
 
   // Insert NewMBB and fix control flow.
   MachineBasicBlock *Tgt = getTargetMBB(*FirstBr);
   NewMBB->transferSuccessors(MBB);
   if (Tgt != getTargetMBB(*LastBr))
     NewMBB->removeSuccessor(Tgt, true);
   MBB->addSuccessor(NewMBB);
   MBB->addSuccessor(Tgt);
   MFp->insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
 
   NewMBB->splice(NewMBB->end(), MBB, LastBr.getReverse(), MBB->end());
 }
 
 // Fill MBBInfos.
 void MipsBranchExpansion::initMBBInfo() {
   // Split the MBBs if they have two branches. Each basic block should have at
   // most one branch after this loop is executed.
   for (auto &MBB : *MFp)
     splitMBB(&MBB);
 
-  MFp->RenumberBlocks();
+  MFp->renumberBlocks();
   MBBInfos.clear();
   MBBInfos.resize(MFp->size());
 
   for (unsigned I = 0, E = MBBInfos.size(); I < E; ++I) {
     MachineBasicBlock *MBB = MFp->getBlockNumbered(I);
 
     // Compute size of MBB.
     for (MachineBasicBlock::instr_iterator MI = MBB->instr_begin();

 // wrong code if branches whose allowed offsets are [-128, -126, ..., 126]
 // are present.
 void MipsBranchExpansion::expandToLongBranch(MBBInfo &I) {
   MachineBasicBlock::iterator Pos;
   MachineBasicBlock *MBB = I.Br->getParent(), *TgtMBB = getTargetMBB(*I.Br);
   DebugLoc DL = I.Br->getDebugLoc();
   const BasicBlock *BB = MBB->getBasicBlock();
   MachineFunction::iterator FallThroughMBB = ++MachineFunction::iterator(MBB);
-  MachineBasicBlock *LongBrMBB = MFp->CreateMachineBasicBlock(BB);
+  MachineBasicBlock *LongBrMBB = MFp->createMachineBasicBlock(BB);
 
   MFp->insert(FallThroughMBB, LongBrMBB);
   MBB->replaceSuccessor(TgtMBB, LongBrMBB);
 
   if (IsPIC) {
-    MachineBasicBlock *BalTgtMBB = MFp->CreateMachineBasicBlock(BB);
+    MachineBasicBlock *BalTgtMBB = MFp->createMachineBasicBlock(BB);
     MFp->insert(FallThroughMBB, BalTgtMBB);
     LongBrMBB->addSuccessor(BalTgtMBB);
     BalTgtMBB->addSuccessor(TgtMBB);
 
     // We must select between the MIPS32r6/MIPS64r6 BALC (which is a normal
     // instruction) and the pre-MIPS32r6/MIPS64r6 definition (which is an
     // pseudo-instruction wrapping BGEZAL).
     const unsigned BalOp =
for (I = MBBInfos.begin(); I != E; ++I) {
       if (!I->Br)
         continue;
 
       expandToLongBranch(*I);
       ++LongBranches;
       EverMadeChange = MadeChange = true;
     }
 
-    MFp->RenumberBlocks();
+    MFp->renumberBlocks();
   }
 
   return EverMadeChange;
 }
 
 bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) {
   const TargetMachine &TM = MF.getTarget();
   IsPIC = TM.isPositionIndependent();

llvm/lib/Target/Mips/MipsConstantIslandPass.cpp

bool MipsConstantIslands::runOnMachineFunction(MachineFunction &mf) {
   if (!PrescannedForConstants) prescanForConstants();
 
   HasFarJump = false;
   // This pass invalidates liveness information when it splits basic blocks.
   MF->getRegInfo().invalidateLiveness();
 
   // Renumber all of the machine basic blocks in the function, guaranteeing that
   // the numbers agree with the position of the block in the function.
-  MF->RenumberBlocks();
+  MF->renumberBlocks();
 
   bool MadeChange = false;
 
   // Perform the initial placement of the constant pool entries.  To start with,
   // we put them all at the end of the function.
   std::vector<MachineInstr*> CPEMIs;
   if (!MCP->isEmpty())
     doInitialPlacement(CPEMIs);
bool MipsConstantIslands::runOnMachineFunction(MachineFunction &mf) {
   return MadeChange;
 }
 
 /// doInitialPlacement - Perform the initial placement of the constant pool
 /// entries.  To start with, we put them all at the end of the function.
 void
 MipsConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) {
   // Create the basic block to hold the CPE's.
-  MachineBasicBlock *BB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *BB = MF->createMachineBasicBlock();
   MF->push_back(BB);
 
   // MachineConstantPool measures alignment in bytes. We measure in log2(bytes).
   const Align MaxAlign = MCP->getConstantPoolAlign();
 
   // Mark the basic block as required by the const-pool.
   // If AlignConstantIslands isn't set, use 4-byte alignment for everything.
   BB->setAlignment(AlignConstantIslands ? MaxAlign : Align(4));

 }
 
 /// updateForInsertedWaterBlock - When a block is newly inserted into the
 /// machine function, it upsets all of the block numbers.  Renumber the blocks
 /// and update the arrays that parallel this numbering.
 void MipsConstantIslands::updateForInsertedWaterBlock
   (MachineBasicBlock *NewBB) {
   // Renumber the MBB's to keep them consecutive.
-  NewBB->getParent()->RenumberBlocks(NewBB);
+  NewBB->getParent()->renumberBlocks(NewBB);
 
   // Insert an entry into BBInfo to align it properly with the (newly
   // renumbered) block numbers.
   BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
 
   // Next, update WaterList.  Specifically, we need to add NewMBB as having
   // available water after it.
   water_iterator IP = llvm::lower_bound(WaterList, NewBB, CompareMBBNumbers);
   WaterList.insert(IP, NewBB);
 }
 
 unsigned MipsConstantIslands::getUserOffset(CPUser &U) const {
   return getOffsetOf(U.MI);
 }
 
 /// Split the basic block containing MI into two blocks, which are joined by
 /// an unconditional branch.  Update data structures and renumber blocks to
 /// account for this change and returns the newly created block.
 MachineBasicBlock *
 MipsConstantIslands::splitBlockBeforeInstr(MachineInstr &MI) {
   MachineBasicBlock *OrigBB = MI.getParent();
 
   // Create a new MBB for the code after the OrigBB.
   MachineBasicBlock *NewBB =
-    MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
+      MF->createMachineBasicBlock(OrigBB->getBasicBlock());
   MachineFunction::iterator MBBI = ++OrigBB->getIterator();
   MF->insert(MBBI, NewBB);
 
   // Splice the instructions starting with MI over to NewBB.
   NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
 
   // Add an unconditional branch from OrigBB to NewBB.
   // Note the new unconditional branch is not being recorded.
   // There doesn't seem to be meaningful DebugInfo available; this doesn't
   // correspond to anything in the source.
   BuildMI(OrigBB, DebugLoc(), TII->get(Mips::Bimm16)).addMBB(NewBB);
   ++NumSplit;
 
   // Update the CFG.  All succs of OrigBB are now succs of NewBB.
   NewBB->transferSuccessors(OrigBB);
 
   // OrigBB branches to NewBB.
   OrigBB->addSuccessor(NewBB);
 
   // Update internal data structures to account for the newly inserted MBB.
   // This is almost the same as updateForInsertedWaterBlock, except that
   // the Water goes after OrigBB, not NewBB.
-  MF->RenumberBlocks(NewBB);
+  MF->renumberBlocks(NewBB);
 
   // Insert an entry into BBInfo to align it properly with the (newly
   // renumbered) block numbers.
   BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
 
   // Next, update WaterList.  Specifically, we need to add OrigMBB as having
   // available water after it (but not if it's already there, which happens
   // when splitting before a conditional branch that is followed by an
bool MipsConstantIslands::handleConstantPoolUser(unsigned CPUserIndex) {
 
   // See if the current entry is within range, or there is a clone of it
   // in range.
   int result = findInRangeCPEntry(U, UserOffset);
   if (result==1) return false;
   else if (result==2) return true;
 
   // Look for water where we can place this CPE.
-  MachineBasicBlock *NewIsland = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *NewIsland = MF->createMachineBasicBlock();
   MachineBasicBlock *NewMBB;
   water_iterator IP;
   if (findAvailableWater(U, UserOffset, IP)) {
     LLVM_DEBUG(dbgs() << "Found water in range\n");
     MachineBasicBlock *WaterBB = *IP;
 
     // If the original WaterList entry was "new water" on this iteration,
     // propagate that to the new island.  This is just keeping NewWaterList

llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp

INITIALIZE_PASS(MipsDelaySlotFiller, DEBUG_TYPE,
                 "Fill delay slot for MIPS", false, false)
 
 /// This function inserts clones of Filler into predecessor blocks.
 static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) {
   MachineFunction *MF = Filler->getParent()->getParent();
 
   for (BB2BrMap::const_iterator I = BrMap.begin(); I != BrMap.end(); ++I) {
     if (I->second) {
-      MIBundleBuilder(I->second).append(MF->CloneMachineInstr(&*Filler));
+      MIBundleBuilder(I->second).append(MF->cloneMachineInstr(&*Filler));
       ++UsefulSlots;
     } else {
-      I->first->insert(I->first->end(), MF->CloneMachineInstr(&*Filler));
+      I->first->insert(I->first->end(), MF->cloneMachineInstr(&*Filler));
     }
   }
 }
 
 /// This function adds registers Filler defines to MBB's live-in register list.
 static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) {
   for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) {
     const MachineOperand &MO = Filler->getOperand(I);

llvm/lib/Target/Mips/MipsExpandPseudo.cpp

bool MipsExpandPseudo::expandAtomicCmpSwapSubword(
   Register Mask2 = I->getOperand(4).getReg();
   Register ShiftNewVal = I->getOperand(5).getReg();
   Register ShiftAmnt = I->getOperand(6).getReg();
   Register Scratch = I->getOperand(7).getReg();
   Register Scratch2 = I->getOperand(8).getReg();
 
   // insert new blocks after the current block
   const BasicBlock *LLVM_BB = BB.getBasicBlock();
-  MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *loop1MBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *loop2MBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *sinkMBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *exitMBB = MF->createMachineBasicBlock(LLVM_BB);
   MachineFunction::iterator It = ++BB.getIterator();
   MF->insert(It, loop1MBB);
   MF->insert(It, loop2MBB);
   MF->insert(It, sinkMBB);
   MF->insert(It, exitMBB);
 
   // Transfer the remainder of BB and its successor edges to exitMBB.
   exitMBB->splice(exitMBB->begin(), &BB,
bool MipsExpandPseudo::expandAtomicCmpSwap(MachineBasicBlock &BB,
   Register Dest = I->getOperand(0).getReg();
   Register Ptr = I->getOperand(1).getReg();
   Register OldVal = I->getOperand(2).getReg();
   Register NewVal = I->getOperand(3).getReg();
   Register Scratch = I->getOperand(4).getReg();
 
   // insert new blocks after the current block
   const BasicBlock *LLVM_BB = BB.getBasicBlock();
-  MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *loop1MBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *loop2MBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *exitMBB = MF->createMachineBasicBlock(LLVM_BB);
   MachineFunction::iterator It = ++BB.getIterator();
   MF->insert(It, loop1MBB);
   MF->insert(It, loop2MBB);
   MF->insert(It, exitMBB);
 
   // Transfer the remainder of BB and its successor edges to exitMBB.
   exitMBB->splice(exitMBB->begin(), &BB,
                   std::next(MachineBasicBlock::iterator(I)), BB.end());
bool MipsExpandPseudo::expandAtomicBinOpSubword(
   Register Mask = I->getOperand(3).getReg();
   Register Mask2 = I->getOperand(4).getReg();
   Register ShiftAmnt = I->getOperand(5).getReg();
   Register OldVal = I->getOperand(6).getReg();
   Register BinOpRes = I->getOperand(7).getReg();
   Register StoreVal = I->getOperand(8).getReg();
 
   const BasicBlock *LLVM_BB = BB.getBasicBlock();
-  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *loopMBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *sinkMBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *exitMBB = MF->createMachineBasicBlock(LLVM_BB);
   MachineFunction::iterator It = ++BB.getIterator();
   MF->insert(It, loopMBB);
   MF->insert(It, sinkMBB);
   MF->insert(It, exitMBB);
 
   exitMBB->splice(exitMBB->begin(), &BB, std::next(I), BB.end());
   exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
 
bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
   case Mips::ATOMIC_LOAD_MAX_I64_POSTRA:
     IsMax = true;
     break;
   default:
     llvm_unreachable("Unknown pseudo atomic!");
   }
 
   const BasicBlock *LLVM_BB = BB.getBasicBlock();
-  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *loopMBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *exitMBB = MF->createMachineBasicBlock(LLVM_BB);
   MachineFunction::iterator It = ++BB.getIterator();
   MF->insert(It, loopMBB);
   MF->insert(It, exitMBB);
 
   exitMBB->splice(exitMBB->begin(), &BB, std::next(I), BB.end());
   exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
 
   BB.addSuccessor(loopMBB, BranchProbability::getOne());
bool MipsExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
   STI = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
   TII = STI->getInstrInfo();
 
   bool Modified = false;
   for (MachineBasicBlock &MBB : MF)
     Modified |= expandMBB(MBB);
 
   if (Modified)
-    MF.RenumberBlocks();
+    MF.renumberBlocks();
 
   return Modified;
 }
 
 /// createMipsExpandPseudoPass - returns an instance of the pseudo instruction
 /// expansion pass.
 FunctionPass *llvm::createMipsExpandPseudoPass() {
   return new MipsExpandPseudo();
 }

llvm/lib/Target/Mips/MipsISelLowering.cpp

case Mips::ATOMIC_LOAD_UMAX_I16:
     NeedsAdditionalReg = true;
     break;
   default:
     llvm_unreachable("Unknown subword atomic pseudo for expansion!");
   }
 
   // insert new blocks after the current block
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
-  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *exitMBB = MF->createMachineBasicBlock(LLVM_BB);
   MachineFunction::iterator It = ++BB->getIterator();
   MF->insert(It, exitMBB);
 
   // Transfer the remainder of BB and its successor edges to exitMBB.
   exitMBB->splice(exitMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
 
MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
   // value isn't a problem.
   // The Dead flag is needed as the value in scratch isn't used by any other
   // instruction. Kill isn't used as Dead is more precise.
   Register Scratch = RegInfo.createVirtualRegister(RC);
   Register Scratch2 = RegInfo.createVirtualRegister(RC);
 
   // insert new blocks after the current block
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
-  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *exitMBB = MF->createMachineBasicBlock(LLVM_BB);
   MachineFunction::iterator It = ++BB->getIterator();
   MF->insert(It, exitMBB);
 
   // Transfer the remainder of BB and its successor edges to exitMBB.
   exitMBB->splice(exitMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
 
MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
   //  thisMBB:
   //  ...
   //   TrueVal = ...
   //   setcc r1, r2, r3
   //   bNE   r1, r0, copy1MBB
   //   fallthrough --> copy0MBB
   MachineBasicBlock *thisMBB  = BB;
   MachineFunction *F = BB->getParent();
-  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *copy0MBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *sinkMBB = F->createMachineBasicBlock(LLVM_BB);
   F->insert(It, copy0MBB);
   F->insert(It, sinkMBB);
 
   // Transfer the remainder of BB and its successor edges to sinkMBB.
   sinkMBB->splice(sinkMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
 
MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
   //  thisMBB:
   //  ...
   //   TrueVal = ...
   //   setcc r1, r2, r3
   //   bNE   r1, r0, copy1MBB
   //   fallthrough --> copy0MBB
   MachineBasicBlock *thisMBB = BB;
   MachineFunction *F = BB->getParent();
-  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *copy0MBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *sinkMBB = F->createMachineBasicBlock(LLVM_BB);
   F->insert(It, copy0MBB);
   F->insert(It, sinkMBB);
 
   // Transfer the remainder of BB and its successor edges to sinkMBB.
   sinkMBB->splice(sinkMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
 

llvm/lib/Target/Mips/MipsSEISelLowering.cpp

MipsSETargetLowering::emitBPOSGE32(MachineInstr &MI,
 
   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
   DebugLoc DL = MI.getDebugLoc();
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
   MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
   MachineFunction *F = BB->getParent();
-  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *FBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *TBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *Sink = F->createMachineBasicBlock(LLVM_BB);
   F->insert(It, FBB);
   F->insert(It, TBB);
   F->insert(It, Sink);
 
   // Transfer the remainder of BB and its successor edges to Sink.
   Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
                BB->end());
   Sink->transferSuccessorsAndUpdatePHIs(BB);
MachineBasicBlock *MipsSETargetLowering::emitMSACBranchPseudo(
 
   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
   DebugLoc DL = MI.getDebugLoc();
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
   MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
   MachineFunction *F = BB->getParent();
-  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *FBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *TBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *Sink = F->createMachineBasicBlock(LLVM_BB);
   F->insert(It, FBB);
   F->insert(It, TBB);
   F->insert(It, Sink);
 
   // Transfer the remainder of BB and its successor edges to Sink.
   Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
                BB->end());
   Sink->transferSuccessorsAndUpdatePHIs(BB);

llvm/lib/Target/PowerPC/PPCBranchSelector.cpp

int PPCBSel::computeBranchSize(MachineFunction &Fn,
 
   return BranchSize;
 }
 
 bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
   const PPCInstrInfo *TII =
       static_cast<const PPCInstrInfo *>(Fn.getSubtarget().getInstrInfo());
   // Give the blocks of the function a dense, in-order, numbering.
-  Fn.RenumberBlocks();
+  Fn.renumberBlocks();
   BlockSizes.resize(Fn.getNumBlockIDs());
   FirstImpreciseBlock = -1;
 
   // Measure each MBB and compute a size for the entire function.
   unsigned FuncSize = ComputeBlockSizes(Fn);
 
   // If the entire function is smaller than the displacement of a branch field,
   // we know we don't need to shrink any branches in this function.  This is a

llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp

bool processBlock(MachineBasicBlock &ReturnMBB) {
         for (MachineBasicBlock::iterator J = Pred->getLastNonDebugInstr();;) {
           if (J == Pred->end())
             break;
 
           if (J->getOpcode() == PPC::B) {
             if (J->getOperand(0).getMBB() == &ReturnMBB) {
               // This is an unconditional branch to the return. Replace the
               // branch with a blr.
-              MachineInstr *MI = ReturnMBB.getParent()->CloneMachineInstr(&*I);
+              MachineInstr *MI = ReturnMBB.getParent()->cloneMachineInstr(&*I);
               Pred->insert(J, MI);
 
               MachineBasicBlock::iterator K = J--;
               K->eraseFromParent();
               BlockChanged = true;
               ++NumBLR;
               continue;
             }
           } else if (J->getOpcode() == PPC::BCC) {
             if (J->getOperand(2).getMBB() == &ReturnMBB) {
               // This is a conditional branch to the return. Replace the branch
               // with a bclr.
-              MachineInstr *MI = ReturnMBB.getParent()->CloneMachineInstr(&*I);
+              MachineInstr *MI = ReturnMBB.getParent()->cloneMachineInstr(&*I);
               MI->setDesc(TII->get(PPC::BCCLR));
               MachineInstrBuilder(*ReturnMBB.getParent(), MI)
                   .add(J->getOperand(0))
                   .add(J->getOperand(1));
               Pred->insert(J, MI);
 
               MachineBasicBlock::iterator K = J--;
               K->eraseFromParent();
               BlockChanged = true;
               ++NumBCLR;
               continue;
             }
           } else if (J->getOpcode() == PPC::BC || J->getOpcode() == PPC::BCn) {
             if (J->getOperand(1).getMBB() == &ReturnMBB) {
               // This is a conditional branch to the return. Replace the branch
               // with a bclr.
-              MachineInstr *MI = ReturnMBB.getParent()->CloneMachineInstr(&*I);
+              MachineInstr *MI = ReturnMBB.getParent()->cloneMachineInstr(&*I);
               MI->setDesc(
                   TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn));
               MachineInstrBuilder(*ReturnMBB.getParent(), MI)
                   .add(J->getOperand(0));
               Pred->insert(J, MI);
 
               MachineBasicBlock::iterator K = J--;
               K->eraseFromParent();

llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp

for (MachineBasicBlock::iterator MBBI = MBB.begin(), MBBE = MBB.end();
          MBBI != MBBE;) {
       MachineInstr &MI = *MBBI;
       MachineBasicBlock::iterator NMBBI = std::next(MBBI);
       Changed |= expandMI(MBB, MI, NMBBI);
       MBBI = NMBBI;
     }
   }
   if (Changed)
-    MF.RenumberBlocks();
+    MF.renumberBlocks();
   return Changed;
 }
 
 bool PPCExpandAtomicPseudo::expandMI(MachineBasicBlock &MBB, MachineInstr &MI,
                                      MachineBasicBlock::iterator &NMBBI) {
   switch (MI.getOpcode()) {
   case PPC::ATOMIC_SWAP_I128:
   case PPC::ATOMIC_LOAD_ADD_I128:
bool PPCExpandAtomicPseudo::expandAtomicRMW128(
     MachineBasicBlock::iterator &NMBBI) {
   const MCInstrDesc &LL = TII->get(PPC::LQARX);
   const MCInstrDesc &SC = TII->get(PPC::STQCX);
   DebugLoc DL = MI.getDebugLoc();
   MachineFunction *MF = MBB.getParent();
   const BasicBlock *BB = MBB.getBasicBlock();
   // Create layout of control flow.
   MachineFunction::iterator MFI = ++MBB.getIterator();
-  MachineBasicBlock *LoopMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *ExitMBB = MF->CreateMachineBasicBlock(BB);
+  MachineBasicBlock *LoopMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *ExitMBB = MF->createMachineBasicBlock(BB);
   MF->insert(MFI, LoopMBB);
   MF->insert(MFI, ExitMBB);
   ExitMBB->splice(ExitMBB->begin(), &MBB, std::next(MI.getIterator()),
                   MBB.end());
   ExitMBB->transferSuccessorsAndUpdatePHIs(&MBB);
   MBB.addSuccessor(LoopMBB);
 
   // For non-min/max operations, control flow is kinda like:
bool PPCExpandAtomicPseudo::expandAtomicCmpSwap128(
   //   stqcx new ptr
   //   bne 0, loop
   //   b exit
   // fail:
   //   stqcx old ptr
   // exit:
   //   ....
   MachineFunction::iterator MFI = ++MBB.getIterator();
-  MachineBasicBlock *LoopCmpMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *CmpSuccMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *CmpFailMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *ExitMBB = MF->CreateMachineBasicBlock(BB);
+  MachineBasicBlock *LoopCmpMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *CmpSuccMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *CmpFailMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *ExitMBB = MF->createMachineBasicBlock(BB);
   MF->insert(MFI, LoopCmpMBB);
   MF->insert(MFI, CmpSuccMBB);
   MF->insert(MFI, CmpFailMBB);
   MF->insert(MFI, ExitMBB);
   ExitMBB->splice(ExitMBB->begin(), &MBB, std::next(MI.getIterator()),
                   MBB.end());
   ExitMBB->transferSuccessorsAndUpdatePHIs(&MBB);
   MBB.addSuccessor(LoopCmpMBB);

llvm/lib/Target/PowerPC/PPCExpandISEL.cpp

void PPCExpandISEL::reorganizeBlockLayout(BlockISELList &BIL,
   MachineBasicBlock *Successor = nullptr;
   const BasicBlock *LLVM_BB = MBB->getBasicBlock();
   MachineBasicBlock::iterator MBBI = (*BIL.back());
   NewSuccessor = (MBBI != MBB->getLastNonDebugInstr() || !MBB->canFallThrough())
                      // Another BB is needed to move the instructions that
                      // follow this ISEL.  If the ISEL is the last instruction
                      // in a block that can't fall through, we also need a block
                      // to branch to.
-                     ? MF->CreateMachineBasicBlock(LLVM_BB)
+                     ? MF->createMachineBasicBlock(LLVM_BB)
                      : nullptr;
 
   MachineFunction::iterator It = MBB->getIterator();
   ++It; // Point to the successor block of MBB.
 
   // If NewSuccessor is NULL then the last ISEL in this group is the last
   // non-debug instruction in this block. Find the fall-through successor
   // of this block to use when updating the CFG below.
   if (!NewSuccessor) {
     for (auto &Succ : MBB->successors()) {
       if (MBB->isLayoutSuccessor(Succ)) {
         Successor = Succ;
         break;
       }
     }
   } else
     Successor = NewSuccessor;
 
   // The FalseBlock and TrueBlock are inserted after the MBB block but before
   // its successor.
   // Note this need to be done *after* the above setting the Successor code.
   if (IsFalseBlockRequired) {
-    FalseBlock = MF->CreateMachineBasicBlock(LLVM_BB);
+    FalseBlock = MF->createMachineBasicBlock(LLVM_BB);
     MF->insert(It, FalseBlock);
   }
 
   if (IsTrueBlockRequired) {
-    TrueBlock = MF->CreateMachineBasicBlock(LLVM_BB);
+    TrueBlock = MF->createMachineBasicBlock(LLVM_BB);
     MF->insert(It, TrueBlock);
   }
 
   if (NewSuccessor) {
     MF->insert(It, NewSuccessor);
 
     // Transfer the rest of this block into the new successor block.
     NewSuccessor->splice(NewSuccessor->end(), MBB,

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

auto probeRealignedStack = [&](MachineBasicBlock &MBB,
     // bb.1:
     //   stdu <backchain>, <negprobesize>(r1)
     //   sub $scratchreg, $scratchreg, negprobesize
     //   cmpdi $scratchreg, <negprobesize>
     //   blt bb.1
     // bb.2:
     //   stdux <backchain>, r1, $scratchreg
     MachineFunction::iterator MBBInsertPoint = std::next(MBB.getIterator());
-    MachineBasicBlock *ProbeLoopBodyMBB = MF.CreateMachineBasicBlock(ProbedBB);
+    MachineBasicBlock *ProbeLoopBodyMBB = MF.createMachineBasicBlock(ProbedBB);
     MF.insert(MBBInsertPoint, ProbeLoopBodyMBB);
-    MachineBasicBlock *ProbeExitMBB = MF.CreateMachineBasicBlock(ProbedBB);
+    MachineBasicBlock *ProbeExitMBB = MF.createMachineBasicBlock(ProbedBB);
     MF.insert(MBBInsertPoint, ProbeExitMBB);
     // bb.2
     {
       Register BackChainPointer = HasRedZone ? BPReg : TempReg;
       allocateAndProbe(*ProbeExitMBB, ProbeExitMBB->end(), 0, ScratchReg, false,
                        BackChainPointer);
       if (HasRedZone)
         // PROBED_STACKALLOC_64 assumes Operand(1) stores the old sp, copy BPReg
if (NumBlocks < 3) {
       MaterializeImm(*CurrentMBB, {MI}, NumBlocks, ScratchReg);
       BuildMI(*CurrentMBB, {MI}, DL, TII.get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR))
           .addReg(ScratchReg, RegState::Kill);
       if (!UseDForm)
         MaterializeImm(*CurrentMBB, {MI}, NegProbeSize, ScratchReg);
       // Create MBBs of the loop.
       MachineFunction::iterator MBBInsertPoint =
           std::next(CurrentMBB->getIterator());
-      MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(ProbedBB);
+      MachineBasicBlock *LoopMBB = MF.createMachineBasicBlock(ProbedBB);
       MF.insert(MBBInsertPoint, LoopMBB);
-      MachineBasicBlock *ExitMBB = MF.CreateMachineBasicBlock(ProbedBB);
+      MachineBasicBlock *ExitMBB = MF.createMachineBasicBlock(ProbedBB);
       MF.insert(MBBInsertPoint, ExitMBB);
       // Synthesize the loop body.
       allocateAndProbe(*LoopMBB, LoopMBB->end(), NegProbeSize, ScratchReg,
                        UseDForm, FPReg);
       BuildMI(LoopMBB, DL, TII.get(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ))
           .addMBB(LoopMBB);
       LoopMBB->addSuccessor(ExitMBB);
       LoopMBB->addSuccessor(LoopMBB);

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
   MachineFunction::iterator It = ++BB->getIterator();
 
   Register dest = MI.getOperand(0).getReg();
   Register ptrA = MI.getOperand(1).getReg();
   Register ptrB = MI.getOperand(2).getReg();
   Register incr = MI.getOperand(3).getReg();
   DebugLoc dl = MI.getDebugLoc();
 
-  MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *loopMBB = F->createMachineBasicBlock(LLVM_BB);
   MachineBasicBlock *loop2MBB =
-    CmpOpcode ? F->CreateMachineBasicBlock(LLVM_BB) : nullptr;
-  MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
+      CmpOpcode ? F->createMachineBasicBlock(LLVM_BB) : nullptr;
+  MachineBasicBlock *exitMBB = F->createMachineBasicBlock(LLVM_BB);
   F->insert(It, loopMBB);
   if (CmpOpcode)
     F->insert(It, loop2MBB);
   F->insert(It, exitMBB);
   exitMBB->splice(exitMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
 
MachineBasicBlock *PPCTargetLowering::EmitPartwordAtomicBinary(
 
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
   MachineFunction::iterator It = ++BB->getIterator();
 
   Register dest = MI.getOperand(0).getReg();
   Register ptrA = MI.getOperand(1).getReg();
   Register ptrB = MI.getOperand(2).getReg();
 
-  MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *loopMBB = F->createMachineBasicBlock(LLVM_BB);
   MachineBasicBlock *loop2MBB =
-      CmpOpcode ? F->CreateMachineBasicBlock(LLVM_BB) : nullptr;
-  MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
+      CmpOpcode ? F->createMachineBasicBlock(LLVM_BB) : nullptr;
+  MachineBasicBlock *exitMBB = F->createMachineBasicBlock(LLVM_BB);
   F->insert(It, loopMBB);
   if (CmpOpcode)
     F->insert(It, loop2MBB);
   F->insert(It, exitMBB);
   exitMBB->splice(exitMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
 
PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
   //  buf[LabelOffset] = LR
   //  v_main = 0
   //
   // sinkMBB:
   //  v = phi(main, restore)
   //
 
   MachineBasicBlock *thisMBB = MBB;
-  MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
+  MachineBasicBlock *mainMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *sinkMBB = MF->createMachineBasicBlock(BB);
   MF->insert(I, mainMBB);
   MF->insert(I, sinkMBB);
 
   MachineInstrBuilder MIB;
 
   // Transfer the remainder of BB and its successor edges to sinkMBB.
   sinkMBB->splice(sinkMBB->begin(), MBB,
                   std::next(MachineBasicBlock::iterator(MI)), MBB->end());
PPCTargetLowering::emitProbedAlloca(MachineInstr &MI,
   //                     |
   //       +---------+   |
   //       | TailMBB +<--+
   //       +---------+
   // In MBB, calculate previous frame pointer and final stack pointer.
   // In TestMBB, test if sp is equal to final stack pointer, if so, jump to
   // TailMBB. In BlockMBB, update the sp atomically and jump back to TestMBB.
   // TailMBB is spliced via \p MI.
-  MachineBasicBlock *TestMBB = MF->CreateMachineBasicBlock(ProbedBB);
-  MachineBasicBlock *TailMBB = MF->CreateMachineBasicBlock(ProbedBB);
-  MachineBasicBlock *BlockMBB = MF->CreateMachineBasicBlock(ProbedBB);
+  MachineBasicBlock *TestMBB = MF->createMachineBasicBlock(ProbedBB);
+  MachineBasicBlock *TailMBB = MF->createMachineBasicBlock(ProbedBB);
+  MachineBasicBlock *BlockMBB = MF->createMachineBasicBlock(ProbedBB);
 
   MachineFunction::iterator MBBIter = ++MBB->getIterator();
   MF->insert(MBBIter, TestMBB);
   MF->insert(MBBIter, BlockMBB);
   MF->insert(MBBIter, TailMBB);
 
   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
if (MI.getOpcode() == PPC::SELECT_CC_I4 ||
 
     //  thisMBB:
     //  ...
     //   TrueVal = ...
     //   cmpTY ccX, r1, r2
     //   bCC copy1MBB
     //   fallthrough --> copy0MBB
     MachineBasicBlock *thisMBB = BB;
-    MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *copy0MBB = F->createMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *sinkMBB = F->createMachineBasicBlock(LLVM_BB);
     DebugLoc dl = MI.getDebugLoc();
     F->insert(It, copy0MBB);
     F->insert(It, sinkMBB);
 
     // Transfer the remainder of BB and its successor edges to sinkMBB.
     sinkMBB->splice(sinkMBB->begin(), BB,
                     std::next(MachineBasicBlock::iterator(MI)), BB->end());
     sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
if (MI.getOpcode() == PPC::SELECT_CC_I4 ||
     // readLoop:
     // mfspr Rx,TBU # load from TBU
     // mfspr Ry,TB  # load from TB
     // mfspr Rz,TBU # load from TBU
     // cmpw crX,Rx,Rz # check if 'old'='new'
     // bne readLoop   # branch if they're not equal
     // ...
 
-    MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *readMBB = F->createMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *sinkMBB = F->createMachineBasicBlock(LLVM_BB);
     DebugLoc dl = MI.getDebugLoc();
     F->insert(It, readMBB);
     F->insert(It, sinkMBB);
 
     // Transfer the remainder of BB and its successor edges to sinkMBB.
     sinkMBB->splice(sinkMBB->begin(), BB,
                     std::next(MachineBasicBlock::iterator(MI)), BB->end());
     sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
     }
     Register dest = MI.getOperand(0).getReg();
     Register ptrA = MI.getOperand(1).getReg();
     Register ptrB = MI.getOperand(2).getReg();
     Register oldval = MI.getOperand(3).getReg();
     Register newval = MI.getOperand(4).getReg();
     DebugLoc dl = MI.getDebugLoc();
 
-    MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *loop1MBB = F->createMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *loop2MBB = F->createMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *midMBB = F->createMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *exitMBB = F->createMachineBasicBlock(LLVM_BB);
     F->insert(It, loop1MBB);
     F->insert(It, loop2MBB);
     F->insert(It, midMBB);
     F->insert(It, exitMBB);
     exitMBB->splice(exitMBB->begin(), BB,
                     std::next(MachineBasicBlock::iterator(MI)), BB->end());
     exitMBB->transferSuccessorsAndUpdatePHIs(BB);
 
else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
 
     Register dest = MI.getOperand(0).getReg();
     Register ptrA = MI.getOperand(1).getReg();
     Register ptrB = MI.getOperand(2).getReg();
     Register oldval = MI.getOperand(3).getReg();
     Register newval = MI.getOperand(4).getReg();
     DebugLoc dl = MI.getDebugLoc();
 
-    MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *loop1MBB = F->createMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *loop2MBB = F->createMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *midMBB = F->createMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *exitMBB = F->createMachineBasicBlock(LLVM_BB);
     F->insert(It, loop1MBB);
     F->insert(It, loop2MBB);
     F->insert(It, midMBB);
     F->insert(It, exitMBB);
     exitMBB->splice(exitMBB->begin(), BB,
                     std::next(MachineBasicBlock::iterator(MI)), BB->end());
     exitMBB->transferSuccessorsAndUpdatePHIs(BB);
 

llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp

if (BSI.BranchToFallThrough) {
       ProbOrigFallThrough = ProbOrigTarget.getCompl();
     }
   }
 
   // Create a new basic block.
   MachineBasicBlock::iterator InsertPoint = BSI.SplitBefore;
   const BasicBlock *LLVM_BB = ThisMBB->getBasicBlock();
   MachineFunction::iterator It = ThisMBB->getIterator();
-  MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *NewMBB = MF->createMachineBasicBlock(LLVM_BB);
   MF->insert(++It, NewMBB);
 
   // Move everything after SplitBefore into the new block.
   NewMBB->splice(NewMBB->end(), ThisMBB, InsertPoint, ThisMBB->end());
   NewMBB->transferSuccessors(ThisMBB);
   if (!ProbOrigTarget.isUnknown()) {
     auto MBBI = find(NewMBB->successors(), OrigTarget);
     NewMBB->setSuccProbability(MBBI, ProbOrigTarget);

llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp

 bool RISCVExpandAtomicPseudo::expandAtomicBinOp(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
     AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
     MachineBasicBlock::iterator &NextMBBI) {
   MachineInstr &MI = *MBBI;
   DebugLoc DL = MI.getDebugLoc();
 
   MachineFunction *MF = MBB.getParent();
-  auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+  auto LoopMBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto DoneMBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
 
   // Insert new MBBs.
   MF->insert(++MBB.getIterator(), LoopMBB);
   MF->insert(++LoopMBB->getIterator(), DoneMBB);
 
   // Set up successors and transfer remaining instructions to DoneMBB.
   LoopMBB->addSuccessor(LoopMBB);
   LoopMBB->addSuccessor(DoneMBB);
bool RISCVExpandAtomicPseudo::expandAtomicMinMaxOp(
     MachineBasicBlock::iterator &NextMBBI) {
   assert(IsMasked == true &&
          "Should only need to expand masked atomic max/min");
   assert(Width == 32 && "Should never need to expand masked 64-bit operations");
 
   MachineInstr &MI = *MBBI;
   DebugLoc DL = MI.getDebugLoc();
   MachineFunction *MF = MBB.getParent();
-  auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+  auto LoopHeadMBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto LoopIfBodyMBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto LoopTailMBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto DoneMBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
 
   // Insert new MBBs.
   MF->insert(++MBB.getIterator(), LoopHeadMBB);
   MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB);
   MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB);
   MF->insert(++LoopTailMBB->getIterator(), DoneMBB);
 
   // Set up successors and transfer remaining instructions to DoneMBB.

 }
 
 bool RISCVExpandAtomicPseudo::expandAtomicCmpXchg(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool IsMasked,
     int Width, MachineBasicBlock::iterator &NextMBBI) {
   MachineInstr &MI = *MBBI;
   DebugLoc DL = MI.getDebugLoc();
   MachineFunction *MF = MBB.getParent();
-  auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+  auto LoopHeadMBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto LoopTailMBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
+  auto DoneMBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
 
   // Insert new MBBs.
   MF->insert(++MBB.getIterator(), LoopHeadMBB);
   MF->insert(++LoopHeadMBB->getIterator(), LoopTailMBB);
   MF->insert(++LoopTailMBB->getIterator(), DoneMBB);
 
   // Set up successors and transfer remaining instructions to DoneMBB.
   LoopHeadMBB->addSuccessor(LoopTailMBB);

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

bool RISCVExpandPseudo::expandAuipcInstPair(
     unsigned SecondOpcode) {
   MachineFunction *MF = MBB.getParent();
   MachineInstr &MI = *MBBI;
   DebugLoc DL = MI.getDebugLoc();
 
   Register DestReg = MI.getOperand(0).getReg();
   const MachineOperand &Symbol = MI.getOperand(1);
 
-  MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
+  MachineBasicBlock *NewMBB = MF->createMachineBasicBlock(MBB.getBasicBlock());
 
   // Tell AsmPrinter that we unconditionally want the symbol of this label to be
   // emitted.
   NewMBB->setLabelMustBeEmitted();
 
   MF->insert(++MBB.getIterator(), NewMBB);
 
   BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg)

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static MachineBasicBlock *emitReadCycleWidePseudo(MachineInstr &MI,
   // rdcycleh x4 # load high word of cycle
   // bne x3, x4, read # check if high word reads match, otherwise try again
   // ...
 
   MachineFunction &MF = *BB->getParent();
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
   MachineFunction::iterator It = ++BB->getIterator();
 
-  MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *LoopMBB = MF.createMachineBasicBlock(LLVM_BB);
   MF.insert(It, LoopMBB);
 
-  MachineBasicBlock *DoneMBB = MF.CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *DoneMBB = MF.createMachineBasicBlock(LLVM_BB);
   MF.insert(It, DoneMBB);
 
   // Transfer the remainder of BB and its successor edges to DoneMBB.
   DoneMBB->splice(DoneMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   DoneMBB->transferSuccessorsAndUpdatePHIs(BB);
 
   BB->addSuccessor(LoopMBB);
static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
 
   const RISCVInstrInfo &TII = *Subtarget.getInstrInfo();
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
   DebugLoc DL = MI.getDebugLoc();
   MachineFunction::iterator I = ++BB->getIterator();
 
   MachineBasicBlock *HeadMBB = BB;
   MachineFunction *F = BB->getParent();
-  MachineBasicBlock *TailMBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *TailMBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *IfFalseMBB = F->createMachineBasicBlock(LLVM_BB);
 
   F->insert(I, IfFalseMBB);
   F->insert(I, TailMBB);
 
   // Transfer debug instructions associated with the selects to TailMBB.
   for (MachineInstr *DebugInstr : SelectDebugValues) {
     TailMBB->push_back(DebugInstr->removeFromParent());
   }

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

#define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP)                           \
   CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF64)
 
 MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
                                                      bool NewMI,
                                                      unsigned OpIdx1,
                                                      unsigned OpIdx2) const {
   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
     if (NewMI)
-      return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
+      return *MI.getParent()->getParent()->cloneMachineInstr(&MI);
     return MI;
   };
 
   switch (MI.getOpcode()) {
   case CASE_VFMA_SPLATS(FMACC):
   case CASE_VFMA_SPLATS(FMADD):
   case CASE_VFMA_SPLATS(FMSAC):
   case CASE_VFMA_SPLATS(FMSUB):

llvm/lib/Target/Sparc/SparcISelLowering.cpp

SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
   //     |  IfFalseMBB
   //     | /
   //    SinkMBB
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
   MachineFunction::iterator It = ++BB->getIterator();
 
   MachineBasicBlock *ThisMBB = BB;
   MachineFunction *F = BB->getParent();
-  MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *IfFalseMBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *SinkMBB = F->createMachineBasicBlock(LLVM_BB);
   F->insert(It, IfFalseMBB);
   F->insert(It, SinkMBB);
 
   // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
   SinkMBB->splice(SinkMBB->begin(), ThisMBB,
                   std::next(MachineBasicBlock::iterator(MI)), ThisMBB->end());
   SinkMBB->transferSuccessorsAndUpdatePHIs(ThisMBB);
 

llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

 // each having the opcode given by NewOpcode.
 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
                                  unsigned NewOpcode) const {
   MachineBasicBlock *MBB = MI->getParent();
   MachineFunction &MF = *MBB->getParent();
 
   // Get two load or store instructions.  Use the original instruction for one
   // of them (arbitrarily the second here) and create a clone for the other.
-  MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
+  MachineInstr *EarlierMI = MF.cloneMachineInstr(&*MI);
   MBB->insert(MI, EarlierMI);
 
   // Set up the two 64-bit registers and remember super reg and its flags.
   MachineOperand &HighRegOp = EarlierMI->getOperand(0);
   MachineOperand &LowRegOp = MI->getOperand(0);
   Register Reg128 = LowRegOp.getReg();
   unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
   unsigned Reg128Undef  = getUndefRegState(LowRegOp.isUndef());

 }
 
 MachineInstr *SystemZInstrInfo::commuteInstructionImpl(MachineInstr &MI,
                                                        bool NewMI,
                                                        unsigned OpIdx1,
                                                        unsigned OpIdx2) const {
   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
     if (NewMI)
-      return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
+      return *MI.getParent()->getParent()->cloneMachineInstr(&MI);
     return MI;
   };
 
   switch (MI.getOpcode()) {
   case SystemZ::SELRMux:
   case SystemZ::SELFHR:
   case SystemZ::SELR:
   case SystemZ::SELGR:
unsigned SystemZ::reverseCCMask(unsigned CCMask) {
   return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
           (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
           (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
           (CCMask & SystemZ::CCMASK_CMP_UO));
 }
 
 MachineBasicBlock *SystemZ::emitBlockAfter(MachineBasicBlock *MBB) {
   MachineFunction &MF = *MBB->getParent();
-  MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
+  MachineBasicBlock *NewMBB = MF.createMachineBasicBlock(MBB->getBasicBlock());
   MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
   return NewMBB;
 }
 
 MachineBasicBlock *SystemZ::splitBlockAfter(MachineBasicBlock::iterator MI,
                                             MachineBasicBlock *MBB) {
   MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
   NewMBB->splice(NewMBB->begin(), MBB,

llvm/lib/Target/SystemZ/SystemZLongBranch.cpp

TerminatorInfo SystemZLongBranch::describeTerminator(MachineInstr &MI) {
   }
   return Terminator;
 }
 
 // Fill MBBs and Terminators, setting the addresses on the assumption
 // that no branches need relaxation.  Return the size of the function under
 // this assumption.
 uint64_t SystemZLongBranch::initMBBInfo() {
-  MF->RenumberBlocks();
+  MF->renumberBlocks();
   unsigned NumBlocks = MF->size();
 
   MBBs.clear();
   MBBs.resize(NumBlocks);
 
   Terminators.clear();
   Terminators.reserve(NumBlocks);
 

llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp

assert(DestReg == MI.getOperand(1).getReg() &&
          "Expected destination and first source operand to be the same.");
 
   LivePhysRegs LiveRegs(TII->getRegisterInfo());
   LiveRegs.addLiveOuts(MBB);
   for (auto I = std::prev(MBB.end()); I != MBBI; --I)
     LiveRegs.stepBackward(*I);
 
   // Splice MBB at MI, moving the rest of the block into RestMBB.
-  MachineBasicBlock *RestMBB = MF.CreateMachineBasicBlock(BB);
+  MachineBasicBlock *RestMBB = MF.createMachineBasicBlock(BB);
   MF.insert(std::next(MachineFunction::iterator(MBB)), RestMBB);
   RestMBB->splice(RestMBB->begin(), &MBB, MI, MBB.end());
   RestMBB->transferSuccessors(&MBB);
   for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
     RestMBB->addLiveIn(*I);
 
   // Create a new block MoveMBB to hold the move instruction.
-  MachineBasicBlock *MoveMBB = MF.CreateMachineBasicBlock(BB);
+  MachineBasicBlock *MoveMBB = MF.createMachineBasicBlock(BB);
   MF.insert(std::next(MachineFunction::iterator(MBB)), MoveMBB);
   MoveMBB->addLiveIn(SrcReg);
   for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
     MoveMBB->addLiveIn(*I);
 
   // At the end of MBB, create a conditional branch to RestMBB if the
   // condition is false, otherwise fall through to MoveMBB.
   BuildMI(&MBB, DL, TII->get(SystemZ::BRC))

llvm/lib/Target/VE/VEISelLowering.cpp

VETargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
   //   ...
   //
   // RestoreMBB:
   //   %s17 = buf[3] = iff %s17 is used as BP
   //   v_restore = 1
   //   goto SinkMBB
 
   MachineBasicBlock *ThisMBB = MBB;
-  MachineBasicBlock *MainMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *SinkMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *RestoreMBB = MF->CreateMachineBasicBlock(BB);
+  MachineBasicBlock *MainMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *SinkMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *RestoreMBB = MF->createMachineBasicBlock(BB);
   MF->insert(I, MainMBB);
   MF->insert(I, SinkMBB);
   MF->push_back(RestoreMBB);
   RestoreMBB->setHasAddressTaken();
 
   // Transfer the remainder of BB and its successor edges to SinkMBB.
   SinkMBB->splice(SinkMBB->begin(), MBB,
                   std::next(MachineBasicBlock::iterator(MI)), MBB->end());
VETargetLowering::emitSjLjDispatchBlock(MachineInstr &MI,
   //   Call abort.
   //
   // DispContBB:
   //   %breg = address of jump table
   //   %pc = load and calculate next pc from %breg and %callsite
   //   jmp %pc
 
   // Shove the dispatch's address into the return slot in the function context.
-  MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *DispatchBB = MF->createMachineBasicBlock();
   DispatchBB->setIsEHPad(true);
 
   // Trap BB will causes trap like `assert(0)`.
-  MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *TrapBB = MF->createMachineBasicBlock();
   DispatchBB->addSuccessor(TrapBB);
 
-  MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *DispContBB = MF->createMachineBasicBlock();
   DispatchBB->addSuccessor(DispContBB);
 
   // Insert MBBs.
   MF->push_back(DispatchBB);
   MF->push_back(DispContBB);
   MF->push_back(TrapBB);
 
   // Insert code to call abort in the TrapBB.

llvm/lib/Target/VE/VEInstrInfo.cpp

bool VEInstrInfo::expandExtendStackPseudo(MachineInstr &MI) const {
   //   shm.l   %sp, 0x10(%s61)          // store new limit at addr:16
   //   monc                             // call monitor
   //   or      %s0, 0, %s62             // restore the value of %s0
   // sinkBB:
 
   // Create new MBB
   MachineBasicBlock *BB = &MBB;
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
-  MachineBasicBlock *syscallMBB = MF.CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *sinkMBB = MF.CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *syscallMBB = MF.createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *sinkMBB = MF.createMachineBasicBlock(LLVM_BB);
   MachineFunction::iterator It = ++(BB->getIterator());
   MF.insert(It, syscallMBB);
   MF.insert(It, sinkMBB);
 
   // Transfer the remainder of BB and its successor edges to sinkMBB.
   sinkMBB->splice(sinkMBB->begin(), BB,
                   std::next(std::next(MachineBasicBlock::iterator(MI))),
                   BB->end());

llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp

 /// interrupted by blocks not dominated by their header.
 /// TODO: There are many opportunities for improving the heuristics here.
 /// Explore them.
 static void sortBlocks(MachineFunction &MF, const MachineLoopInfo &MLI,
                        const WebAssemblyExceptionInfo &WEI,
                        const MachineDominatorTree &MDT) {
   // Remember original layout ordering, so we can update terminators after
   // reordering to point to the original layout successor.
-  MF.RenumberBlocks();
+  MF.renumberBlocks();
 
   // Prepare for a topological sort: Record the number of predecessors each
   // block has, ignoring loop backedges.
   SmallVector<unsigned, 16> NumPredsLeft(MF.getNumBlockIDs(), 0);
   for (MachineBasicBlock &MBB : MF) {
     unsigned N = MBB.pred_size();
     if (MachineLoop *L = MLI.getLoopFor(&MBB))
       if (L->getHeader() == &MBB)
if (!Next) {
       }
     }
     // Move the next block into place and iterate.
     Next->moveAfter(MBB);
     maybeUpdateTerminator(MBB);
     MBB = Next;
   }
   assert(Entries.empty() && "Active sort region list not finished");
-  MF.RenumberBlocks();
+  MF.renumberBlocks();
 
 #ifndef NDEBUG
   SmallSetVector<const SortRegion *, 8> OnStack;
 
   // Insert a sentinel representing the degenerate loop that starts at the
   // function entry block and includes the entire function as a "loop" that
   // executes once.
   OnStack.insert(nullptr);

llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

class WebAssemblyCFGStackify final : public MachineFunctionPass {
   // <EH pad, TRY marker> map
   DenseMap<const MachineBasicBlock *, MachineInstr *> EHPadToTry;
 
   // We need an appendix block to place 'end_loop' or 'end_try' marker when the
   // loop / exception bottom block is the last block in a function
   MachineBasicBlock *AppendixBB = nullptr;
   MachineBasicBlock *getAppendixBlock(MachineFunction &MF) {
     if (!AppendixBB) {
-      AppendixBB = MF.CreateMachineBasicBlock();
+      AppendixBB = MF.createMachineBasicBlock();
       // Give it a fake predecessor so that AsmPrinter prints its label.
       AppendixBB->addSuccessor(AppendixBB);
       MF.push_back(AppendixBB);
     }
     return AppendixBB;
   }
 
   // Before running rewriteDepthImmediates function, 'delegate' has a BB as its
   // destination operand. getFakeCallerBlock() returns a fake BB that will be
   // used for the operand when 'delegate' needs to rethrow to the caller. This
   // will be rewritten as an immediate value that is the number of block depths
   // + 1 in rewriteDepthImmediates, and this fake BB will be removed at the end
   // of the pass.
   MachineBasicBlock *FakeCallerBB = nullptr;
   MachineBasicBlock *getFakeCallerBlock(MachineFunction &MF) {
     if (!FakeCallerBB)
-      FakeCallerBB = MF.CreateMachineBasicBlock();
+      FakeCallerBB = MF.createMachineBasicBlock();
     return FakeCallerBB;
   }
 
   // Helper functions to register / unregister scope information created by
   // marker instructions.
   void registerScope(MachineInstr *Begin, MachineInstr *End);
   void registerTryScope(MachineInstr *Begin, MachineInstr *End,
                         MachineBasicBlock *EHPad);
void WebAssemblyCFGStackify::addTryDelegate(MachineInstr *RangeBegin,
   // Create the nested try instruction.
   auto TryPos = getLatestInsertPos(
       BeginBB, SmallPtrSet<const MachineInstr *, 4>(), AfterSet);
   MachineInstr *Try = BuildMI(*BeginBB, TryPos, RangeBegin->getDebugLoc(),
                               TII.get(WebAssembly::TRY))
                           .addImm(int64_t(WebAssembly::BlockType::Void));
 
   // Create a BB to insert the 'delegate' instruction.
-  MachineBasicBlock *DelegateBB = MF.CreateMachineBasicBlock();
+  MachineBasicBlock *DelegateBB = MF.createMachineBasicBlock();
   // If the destination of 'delegate' is not the caller, adds the destination to
   // the BB's successors.
   if (DelegateDest != FakeCallerBB)
     DelegateBB->addSuccessor(DelegateDest);
 
   auto SplitPos = std::next(RangeEnd->getIterator());
   if (SplitPos == EndBB->end()) {
     // If the range's end instruction is at the end of the BB, insert the new
if (PostSplit) {
       // - After:
       // pre_bb: (previous 'bb')
       //   range_end
       // delegate_bb: (new)
       //   delegate
       // post_bb: (new)
       //   other_insts
       PreBB = EndBB;
-      PostBB = MF.CreateMachineBasicBlock();
+      PostBB = MF.createMachineBasicBlock();
       MF.insert(std::next(PreBB->getIterator()), PostBB);
       MF.insert(std::next(PreBB->getIterator()), DelegateBB);
       PostBB->splice(PostBB->end(), PreBB, SplitPos, PreBB->end());
       PostBB->transferSuccessors(PreBB);
     } else {
       // - Before:
       // ehpad:
       //   range_end
       //   catch
       //   ...
       //
       // - After:
       // pre_bb: (new)
       //   range_end
       // delegate_bb: (new)
       //   delegate
       // post_bb: (previous 'ehpad')
       //   catch
       //   ...
       assert(EndBB->isEHPad());
-      PreBB = MF.CreateMachineBasicBlock();
+      PreBB = MF.createMachineBasicBlock();
       PostBB = EndBB;
       MF.insert(PostBB->getIterator(), PreBB);
       MF.insert(PostBB->getIterator(), DelegateBB);
       PreBB->splice(PreBB->end(), PostBB, PostBB->begin(), SplitPos);
       // We don't need to transfer predecessors of the EH pad to 'PreBB',
       // because an EH pad's predecessors are all through unwind edges and they
       // should still unwind to the EH pad, not PreBB.
     }
bool WebAssemblyCFGStackify::fixCatchUnwindMismatches(MachineFunction &MF) {
   }
 
   return true;
 }
 
 void WebAssemblyCFGStackify::recalculateScopeTops(MachineFunction &MF) {
   // Renumber BBs and recalculate ScopeTop info because new BBs might have been
   // created and inserted during fixing unwind mismatches.
-  MF.RenumberBlocks();
+  MF.renumberBlocks();
   ScopeTops.clear();
   ScopeTops.resize(MF.getNumBlockIDs());
   for (auto &MBB : reverse(MF)) {
     for (auto &MI : reverse(MBB)) {
       if (ScopeTops[MBB.getNumber()])
         break;
       switch (MI.getOpcode()) {
       case WebAssembly::END_BLOCK:
for (MachineInstr &MI : llvm::reverse(MBB)) {
       }
     }
   }
   assert(Stack.empty() && "Control flow should be balanced");
 }
 
 void WebAssemblyCFGStackify::cleanupFunctionData(MachineFunction &MF) {
   if (FakeCallerBB)
-    MF.DeleteMachineBasicBlock(FakeCallerBB);
+    MF.deleteMachineBasicBlock(FakeCallerBB);
   AppendixBB = FakeCallerBB = nullptr;
 }
 
 void WebAssemblyCFGStackify::releaseMemory() {
   ScopeTops.clear();
   BeginToEnd.clear();
   EndToBegin.clear();
   TryToEHPad.clear();

llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp

void WebAssemblyDebugValueManager::updateReg(unsigned Reg) {
   CurrentReg = Reg;
 }
 
 void WebAssemblyDebugValueManager::clone(MachineInstr *Insert,
                                          unsigned NewReg) {
   MachineBasicBlock *MBB = Insert->getParent();
   MachineFunction *MF = MBB->getParent();
   for (MachineInstr *DBI : reverse(DbgValues)) {
-    MachineInstr *Clone = MF->CloneMachineInstr(DBI);
+    MachineInstr *Clone = MF->cloneMachineInstr(DBI);
     for (auto &MO : Clone->getDebugOperandsForReg(CurrentReg))
       MO.setReg(NewReg);
     MBB->insert(Insert, Clone);
   }
 }
 
 void WebAssemblyDebugValueManager::replaceWithLocal(unsigned LocalId) {
   for (auto *DBI : DbgValues) {
     auto IndexType = DBI->isIndirectDebugValue()
                          ? llvm::WebAssembly::TI_LOCAL_INDIRECT
                          : llvm::WebAssembly::TI_LOCAL;
     for (auto &MO : DBI->getDebugOperandsForReg(CurrentReg))
       MO.ChangeToTargetIndex(IndexType, LocalId);
   }
 }

llvm/lib/Target/WebAssembly/WebAssemblyFixBrTableDefaults.cpp

for (auto &MI : *MBB) {
         }
         break;
       }
     }
   }
 
   if (Changed) {
     // We rewrote part of the function; recompute relevant things.
-    MF.RenumberBlocks();
+    MF.renumberBlocks();
     return true;
   }
 
   return false;
 }
 
 } // end anonymous namespace
 
 INITIALIZE_PASS(WebAssemblyFixBrTableDefaults, DEBUG_TYPE,
                 "Removes range checks and sets br_table default targets", false,
                 false)
 
 FunctionPass *llvm::createWebAssemblyFixBrTableDefaults() {
   return new WebAssemblyFixBrTableDefaults();
 }

llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp

for (auto I = SortedEntries.begin(), E = SortedEntries.end() - 1; I != E;
       auto ANum = (*I)->getNumber();
       auto BNum = (*(std::next(I)))->getNumber();
       assert(ANum != BNum);
     }
   }
 #endif
 
   // Create a dispatch block which will contain a jump table to the entries.
-  MachineBasicBlock *Dispatch = MF.CreateMachineBasicBlock();
+  MachineBasicBlock *Dispatch = MF.createMachineBasicBlock();
   MF.insert(MF.end(), Dispatch);
   Blocks.insert(Dispatch);
 
   // Add the jump table.
   const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
   MachineInstrBuilder MIB =
       BuildMI(Dispatch, DebugLoc(), TII.get(WebAssembly::BR_TABLE_I32));
 
for (auto *Entry : Pred->successors()) {
       // If there exists a layout predecessor of this entry and this predecessor
       // is not that, we rather create a routing block after that layout
       // predecessor to save a branch.
       if (auto *OtherPred = EntryToLayoutPred.lookup({Entry, PredInLoop}))
         if (OtherPred != Pred)
           continue;
 
       // This is a successor we need to rewrite.
-      MachineBasicBlock *Routing = MF.CreateMachineBasicBlock();
+      MachineBasicBlock *Routing = MF.createMachineBasicBlock();
       MF.insert(Pred->isLayoutSuccessor(Entry)
                     ? MachineFunction::iterator(Entry)
                     : MF.end(),
                 Routing);
       Blocks.insert(Routing);
 
       // Set the jump table's register of the index of the block we wish to
       // jump to, and jump to the jump table.
bool WebAssemblyFixIrreducibleControlFlow::runOnMachineFunction(
   BlockSet AllBlocks;
   for (auto &MBB : MF) {
     AllBlocks.insert(&MBB);
   }
 
   if (LLVM_UNLIKELY(processRegion(&*MF.begin(), AllBlocks, MF))) {
     // We rewrote part of the function; recompute relevant things.
     MF.getRegInfo().invalidateLiveness();
-    MF.RenumberBlocks();
+    MF.renumberBlocks();
     return true;
   }
 
   return false;
 }

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

static MachineBasicBlock *LowerFPToInt(MachineInstr &MI, DebugLoc DL,
   int64_t Limit = Int64 ? INT64_MIN : INT32_MIN;
   int64_t Substitute = IsUnsigned ? 0 : Limit;
   double CmpVal = IsUnsigned ? -(double)Limit * 2.0 : -(double)Limit;
   auto &Context = BB->getParent()->getFunction().getContext();
   Type *Ty = Float64 ? Type::getDoubleTy(Context) : Type::getFloatTy(Context);
 
   const BasicBlock *LLVMBB = BB->getBasicBlock();
   MachineFunction *F = BB->getParent();
-  MachineBasicBlock *TrueMBB = F->CreateMachineBasicBlock(LLVMBB);
-  MachineBasicBlock *FalseMBB = F->CreateMachineBasicBlock(LLVMBB);
-  MachineBasicBlock *DoneMBB = F->CreateMachineBasicBlock(LLVMBB);
+  MachineBasicBlock *TrueMBB = F->createMachineBasicBlock(LLVMBB);
+  MachineBasicBlock *FalseMBB = F->createMachineBasicBlock(LLVMBB);
+  MachineBasicBlock *DoneMBB = F->createMachineBasicBlock(LLVMBB);
 
   MachineFunction::iterator It = ++BB->getIterator();
   F->insert(It, FalseMBB);
   F->insert(It, TrueMBB);
   F->insert(It, DoneMBB);
 
   // Transfer the remainder of BB and its successor edges to DoneMBB.
   DoneMBB->splice(DoneMBB->begin(), BB, std::next(MI.getIterator()), BB->end());
LowerCallResults(MachineInstr &CallResults, DebugLoc DL, MachineBasicBlock *BB,
   } else if (IsRetCall) {
     CallOp = WebAssembly::RET_CALL;
   } else {
     CallOp = WebAssembly::CALL;
   }
 
   MachineFunction &MF = *BB->getParent();
   const MCInstrDesc &MCID = TII.get(CallOp);
-  MachineInstrBuilder MIB(MF, MF.CreateMachineInstr(MCID, DL));
+  MachineInstrBuilder MIB(MF, MF.createMachineInstr(MCID, DL));
 
   // See if we must truncate the function pointer.
   // CALL_INDIRECT takes an i32, but in wasm64 we represent function pointers
   // as 64-bit for uniformity with other pointer types.
   // See also: WebAssemblyFastISel::selectCall
   if (IsIndirect && MF.getSubtarget<WebAssemblySubtarget>().hasAddr64()) {
     Register Reg32 =
         MF.getRegInfo().createVirtualRegister(&WebAssembly::I32RegClass);

llvm/lib/Target/X86/X86CmovConversion.cpp

if (llvm::any_of(Group, [&](MachineInstr *I) {
       }))
     std::swap(CC, OppCC);
 
   MachineBasicBlock *MBB = MI.getParent();
   MachineFunction::iterator It = ++MBB->getIterator();
   MachineFunction *F = MBB->getParent();
   const BasicBlock *BB = MBB->getBasicBlock();
 
-  MachineBasicBlock *FalseMBB = F->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(BB);
+  MachineBasicBlock *FalseMBB = F->createMachineBasicBlock(BB);
+  MachineBasicBlock *SinkMBB = F->createMachineBasicBlock(BB);
   F->insert(It, FalseMBB);
   F->insert(It, SinkMBB);
 
   // If the EFLAGS register isn't dead in the terminator, then claim that it's
   // live into the sink and copy blocks.
   if (checkEFLAGSLive(LastCMOV)) {
     FalseMBB->addLiveIn(X86::EFLAGS);
     SinkMBB->addLiveIn(X86::EFLAGS);

llvm/lib/Target/X86/X86ExpandPseudo.cpp

BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11)
                           JTInst->getOperand(2 + 2 * Target).getImm())
         .addReg(0);
     BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr))
         .add(Selector)
         .addReg(X86::R11);
   };
 
   auto CreateMBB = [&]() {
-    auto *NewMBB = MF->CreateMachineBasicBlock(BB);
+    auto *NewMBB = MF->createMachineBasicBlock(BB);
     MBB->addSuccessor(NewMBB);
     if (!MBB->isLiveIn(X86::EFLAGS))
       MBB->addLiveIn(X86::EFLAGS);
     return NewMBB;
   };
 
   auto EmitCondJump = [&](unsigned CC, MachineBasicBlock *ThenMBB) {
     BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC);
for (MachineInstr &MI : EntryBlk->instrs()) {
     LiveRegs.stepForward(MI, Clobbers);
   }
 
   // Create the new basic blocks. One block contains all the XMM stores,
   // and another block is the final destination regardless of whether any
   // stores were performed.
   const BasicBlock *LLVMBlk = EntryBlk->getBasicBlock();
   MachineFunction::iterator EntryBlkIter = ++EntryBlk->getIterator();
-  MachineBasicBlock *GuardedRegsBlk = Func->CreateMachineBasicBlock(LLVMBlk);
-  MachineBasicBlock *TailBlk = Func->CreateMachineBasicBlock(LLVMBlk);
+  MachineBasicBlock *GuardedRegsBlk = Func->createMachineBasicBlock(LLVMBlk);
+  MachineBasicBlock *TailBlk = Func->createMachineBasicBlock(LLVMBlk);
   Func->insert(EntryBlkIter, GuardedRegsBlk);
   Func->insert(EntryBlkIter, TailBlk);
 
   // Transfer the remainder of EntryBlk and its successor edges to TailBlk.
   TailBlk->splice(TailBlk->begin(), EntryBlk,
                   std::next(MachineBasicBlock::iterator(VAStartPseudoInstr)),
                   EntryBlk->end());
   TailBlk->transferSuccessorsAndUpdatePHIs(EntryBlk);

llvm/lib/Target/X86/X86FlagsCopyLowering.cpp

bool IsEdgeSplit =
                            "Should only have spliced terminators!");
                     return llvm::any_of(
                         MI.operands(), [&](MachineOperand &MOp) {
                           return MOp.isMBB() && MOp.getMBB() == &UnsplitSucc;
                         });
                   }) ||
       MBB.getFallThrough() == &UnsplitSucc;
 
-  MachineBasicBlock &NewMBB = *MF.CreateMachineBasicBlock();
+  MachineBasicBlock &NewMBB = *MF.createMachineBasicBlock();
 
   // Insert the new block immediately after the current one. Any existing
   // fallthrough will be sunk into this new block anyways.
   MF.insert(std::next(MachineFunction::iterator(&MBB)), &NewMBB);
 
   // Splice the tail of instructions into the new block.
   NewMBB.splice(NewMBB.end(), &MBB, SplitI.getIterator(), MBB.end());
 

llvm/lib/Target/X86/X86FloatingPoint.cpp

void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
   }
 
   // Update stack information so that we know the destination register is now on
   // the stack.
   unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
   assert(UpdatedSlot < StackTop && Dest < 7);
   Stack[UpdatedSlot]   = Dest;
   RegMap[Dest]         = UpdatedSlot;
-  MBB->getParent()->DeleteMachineInstr(&MI); // Remove the old instruction
+  MBB->getParent()->deleteMachineInstr(&MI); // Remove the old instruction
 }
 
 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
 /// register arguments and no explicit destinations.
 ///
 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
   MachineInstr &MI = *I;
 

llvm/lib/Target/X86/X86FrameLowering.cpp

if (AlignOffset < StackProbeSize) {
       Offset -= AlignOffset;
     }
   }
 
   // Synthesize a loop
   NumFrameLoopProbe++;
   const BasicBlock *LLVM_BB = MBB.getBasicBlock();
 
-  MachineBasicBlock *testMBB = MF.CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *tailMBB = MF.CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *testMBB = MF.createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *tailMBB = MF.createMachineBasicBlock(LLVM_BB);
 
   MachineFunction::iterator MBBIter = ++MBB.getIterator();
   MF.insert(MBBIter, testMBB);
   MF.insert(MBBIter, tailMBB);
 
   Register FinalStackProbed = Uses64BitFramePtr ? X86::R11
                               : Is64Bit         ? X86::R11D
                                                 : X86::EAX;
void X86FrameLowering::emitStackProbeInlineWindowsCoreCLR64(
   //    ProbeReg = LoopReg - PageSize
   //    [ProbeReg] = 0
   //    if (ProbeReg > RoundReg) goto LoopMBB
   // ContinueMBB:
   //    RSP = RSP - RAX
   //    [rest of original MBB]
 
   // Set up the new basic blocks
-  MachineBasicBlock *RoundMBB = MF.CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *ContinueMBB = MF.CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *RoundMBB = MF.createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *LoopMBB = MF.createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *ContinueMBB = MF.createMachineBasicBlock(LLVM_BB);
 
   MachineFunction::iterator MBBIter = std::next(MBB.getIterator());
   MF.insert(MBBIter, RoundMBB);
   MF.insert(MBBIter, LoopMBB);
   MF.insert(MBBIter, ContinueMBB);
 
   // Split MBB and move the tail portion down to ContinueMBB.
   MachineBasicBlock::iterator BeforeMBBI = std::prev(MBBI);
void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
 
   // We want to make sure that (in worst case) less than StackProbeSize bytes
   // are not probed after the AND. This assumption is used in
   // emitStackProbeInlineGeneric.
   if (Reg == StackPtr && EmitInlineStackProbe && MaxAlign >= StackProbeSize) {
     {
       NumFrameLoopProbe++;
       MachineBasicBlock *entryMBB =
-          MF.CreateMachineBasicBlock(MBB.getBasicBlock());
+          MF.createMachineBasicBlock(MBB.getBasicBlock());
       MachineBasicBlock *headMBB =
-          MF.CreateMachineBasicBlock(MBB.getBasicBlock());
+          MF.createMachineBasicBlock(MBB.getBasicBlock());
       MachineBasicBlock *bodyMBB =
-          MF.CreateMachineBasicBlock(MBB.getBasicBlock());
+          MF.createMachineBasicBlock(MBB.getBasicBlock());
       MachineBasicBlock *footMBB =
-          MF.CreateMachineBasicBlock(MBB.getBasicBlock());
+          MF.createMachineBasicBlock(MBB.getBasicBlock());
 
       MachineFunction::iterator MBBIter = MBB.getIterator();
       MF.insert(MBBIter, entryMBB);
       MF.insert(MBBIter, headMBB);
       MF.insert(MBBIter, bodyMBB);
       MF.insert(MBBIter, footMBB);
       const unsigned MovMIOpc = Is64Bit ? X86::MOV64mi32 : X86::MOV32mi;
       Register FinalStackProbed = Uses64BitFramePtr ? X86::R11
void X86FrameLowering::adjustForSegmentedStacks(
   // its non-existent prologue, it would fail with an error. Mark the object
   // file so that such failures are not errors. See this Go language bug-report
   // https://go-review.googlesource.com/c/go/+/148819/
   if (StackSize == 0 && !MFI.hasTailCall()) {
     MF.getMMI().setHasNosplitStack(true);
     return;
   }
 
-  MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
-  MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
+  MachineBasicBlock *allocMBB = MF.createMachineBasicBlock();
+  MachineBasicBlock *checkMBB = MF.createMachineBasicBlock();
   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
   bool IsNested = false;
 
   // We need to know if the function has a nest argument only in 64 bit mode.
   if (Is64Bit)
     IsNested = HasNestArgument(&MF);
 
   // The MOV R10, RAX needs to be in a different block, since the RET we emit in
for (auto &MBB : MF) {
       }
     }
     MaxStack += MoreStackForCalls;
   }
 
   // If the stack frame needed is larger than the guaranteed then runtime checks
   // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
   if (MaxStack > Guaranteed) {
-    MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
-    MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
+    MachineBasicBlock *stackCheckMBB = MF.createMachineBasicBlock();
+    MachineBasicBlock *incStackMBB = MF.createMachineBasicBlock();
 
     for (const auto &LI : PrologueMBB.liveins()) {
       stackCheckMBB->addLiveIn(LI);
       incStackMBB->addLiveIn(LI);
     }
 
     MF.push_front(incStackMBB);
     MF.push_front(stackCheckMBB);

llvm/lib/Target/X86/X86ISelLowering.cpp

   //  eax = # XABORT_DEF
   //  s1 = eax
   //
   // sinkMBB:
   //  v = phi(s0/mainBB, s1/fallBB)
 
   MachineBasicBlock *thisMBB = MBB;
   MachineFunction *MF = MBB->getParent();
-  MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *fallMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
+  MachineBasicBlock *mainMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *fallMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *sinkMBB = MF->createMachineBasicBlock(BB);
   MF->insert(I, mainMBB);
   MF->insert(I, fallMBB);
   MF->insert(I, sinkMBB);
 
   if (isEFLAGSLiveAfter(MI, MBB)) {
     mainMBB->addLiveIn(X86::EFLAGS);
     fallMBB->addLiveIn(X86::EFLAGS);
     sinkMBB->addLiveIn(X86::EFLAGS);

     //         |     .
     //        endMBB
 
     // Registers for the PHI in endMBB
     OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
     OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
 
     const BasicBlock *LLVM_BB = MBB->getBasicBlock();
-    overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-    offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-    endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+    overflowMBB = MF->createMachineBasicBlock(LLVM_BB);
+    offsetMBB = MF->createMachineBasicBlock(LLVM_BB);
+    endMBB = MF->createMachineBasicBlock(LLVM_BB);
 
     MachineFunction::iterator MBBIter = ++MBB->getIterator();
 
     // Insert the new basic blocks
     MF->insert(MBBIter, offsetMBB);
     MF->insert(MBBIter, overflowMBB);
     MF->insert(MBBIter, endMBB);
 

   // .LBB5_4:
   //         retq
   //
 
   // We lower cascaded CMOV into two successive branches to the same block.
   // EFLAGS is used by both, so mark it as live in the second.
   const BasicBlock *LLVM_BB = ThisMBB->getBasicBlock();
   MachineFunction *F = ThisMBB->getParent();
-  MachineBasicBlock *FirstInsertedMBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *SecondInsertedMBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *FirstInsertedMBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *SecondInsertedMBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *SinkMBB = F->createMachineBasicBlock(LLVM_BB);
 
   MachineFunction::iterator It = ++ThisMBB->getIterator();
   F->insert(It, FirstInsertedMBB);
   F->insert(It, SecondInsertedMBB);
   F->insert(It, SinkMBB);
 
   // For a cascaded CMOV, we lower it to two successive branches to
   // the same block (SinkMBB).  EFLAGS is used by both, so mark it as live in

       NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() &&
       NextMIIt->getOperand(1).getReg() == MI.getOperand(0).getReg() &&
       NextMIIt->getOperand(1).isKill()) {
     return EmitLoweredCascadedSelect(MI, *NextMIIt, ThisMBB);
   }
 
   const BasicBlock *LLVM_BB = ThisMBB->getBasicBlock();
   MachineFunction *F = ThisMBB->getParent();
-  MachineBasicBlock *FalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *FalseMBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *SinkMBB = F->createMachineBasicBlock(LLVM_BB);
 
   MachineFunction::iterator It = ++ThisMBB->getIterator();
   F->insert(It, FalseMBB);
   F->insert(It, SinkMBB);
 
   // If the EFLAGS register isn't dead in the terminator, then claim that it's
   // live into the sink and copy blocks.
   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();

   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   const X86FrameLowering &TFI = *Subtarget.getFrameLowering();
   const DebugLoc &DL = MI.getDebugLoc();
   const BasicBlock *LLVM_BB = MBB->getBasicBlock();
 
   const unsigned ProbeSize = getStackProbeSize(*MF);
 
   MachineRegisterInfo &MRI = MF->getRegInfo();
-  MachineBasicBlock *testMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *tailMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *blockMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *testMBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *tailMBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *blockMBB = MF->createMachineBasicBlock(LLVM_BB);
 
   MachineFunction::iterator MBBIter = ++MBB->getIterator();
   MF->insert(MBBIter, testMBB);
   MF->insert(MBBIter, blockMBB);
   MF->insert(MBBIter, tailMBB);
 
   Register sizeVReg = MI.getOperand(1).getReg();
 

   // mallocMBB:
   //  Allocate by call to runtime
   //
   // continueMBB:
   //  ...
   //  [rest of original BB]
   //
 
-  MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *mallocMBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *bumpMBB = MF->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *continueMBB = MF->createMachineBasicBlock(LLVM_BB);
 
   MachineRegisterInfo &MRI = MF->getRegInfo();
   const TargetRegisterClass *AddrRegClass =
       getRegClassFor(getPointerTy(MF->getDataLayout()));
 
   Register mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
            bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
            tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),

 
   // Only 32-bit EH needs to worry about manually restoring stack pointers.
   if (!Subtarget.is32Bit())
     return BB;
 
   // C++ EH creates a new target block to hold the restore code, and wires up
   // the new block to the return destination with a normal JMP_4.
   MachineBasicBlock *RestoreMBB =
-      MF->CreateMachineBasicBlock(BB->getBasicBlock());
+      MF->createMachineBasicBlock(BB->getBasicBlock());
   assert(BB->succ_size() == 1);
   MF->insert(std::next(BB->getIterator()), RestoreMBB);
   RestoreMBB->transferSuccessorsAndUpdatePHIs(BB);
   BB->addSuccessor(RestoreMBB);
   MI.getOperand(0).setMBB(RestoreMBB);
 
   // Marking this as an EH pad but not a funclet entry block causes PEI to
   // restore stack pointers in the block.

   // sinkMBB:
   //  v = phi(main, restore)
   //
   // restoreMBB:
   //  if base pointer being used, load it from frame
   //  v_restore = 1
 
   MachineBasicBlock *thisMBB = MBB;
-  MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
+  MachineBasicBlock *mainMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *sinkMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *restoreMBB = MF->createMachineBasicBlock(BB);
   MF->insert(I, mainMBB);
   MF->insert(I, sinkMBB);
   MF->push_back(restoreMBB);
   restoreMBB->setHasAddressTaken();
 
   MachineInstrBuilder MIB;
 
   // Transfer the remainder of BB and its successor edges to sinkMBB.

   //         dec vreg2
   //         jne fixShadowLoopMBB # Iterate until you finish fixing
   //                              # the Shadow Stack
   // sinkMBB:
 
   MachineFunction::iterator I = ++MBB->getIterator();
   const BasicBlock *BB = MBB->getBasicBlock();
 
-  MachineBasicBlock *checkSspMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *fallMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *fixShadowMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *fixShadowLoopPrepareMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *fixShadowLoopMBB = MF->CreateMachineBasicBlock(BB);
-  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
+  MachineBasicBlock *checkSspMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *fallMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *fixShadowMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *fixShadowLoopPrepareMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *fixShadowLoopMBB = MF->createMachineBasicBlock(BB);
+  MachineBasicBlock *sinkMBB = MF->createMachineBasicBlock(BB);
   MF->insert(I, checkSspMBB);
   MF->insert(I, fallMBB);
   MF->insert(I, fixShadowMBB);
   MF->insert(I, fixShadowLoopPrepareMBB);
   MF->insert(I, fixShadowLoopMBB);
   MF->insert(I, sinkMBB);
 
   // Transfer the remainder of BB and its successor edges to sinkMBB.

   }
 
   assert(!LPadList.empty() &&
          "No landing pad destinations for the dispatch jump table!");
 
   // Create the MBBs for the dispatch code.
 
   // Shove the dispatch's address into the return slot in the function context.
-  MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *DispatchBB = MF->createMachineBasicBlock();
   DispatchBB->setIsEHPad(true);
 
-  MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *TrapBB = MF->createMachineBasicBlock();
   BuildMI(TrapBB, DL, TII->get(X86::TRAP));
   DispatchBB->addSuccessor(TrapBB);
 
-  MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *DispContBB = MF->createMachineBasicBlock();
   DispatchBB->addSuccessor(DispContBB);
 
   // Insert MBBs.
   MF->push_back(DispatchBB);
   MF->push_back(DispContBB);
   MF->push_back(TrapBB);
 
   // Insert code into the entry block that creates and registers the function

llvm/lib/Target/X86/X86IndirectThunks.cpp

void RetpolineThunkInserter::populateThunk(MachineFunction &MF) {
   }
 
   const TargetInstrInfo *TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
   assert (MF.size() == 1);
   MachineBasicBlock *Entry = &MF.front();
   Entry->clear();
 
   MachineBasicBlock *CaptureSpec =
-      MF.CreateMachineBasicBlock(Entry->getBasicBlock());
+      MF.createMachineBasicBlock(Entry->getBasicBlock());
   MachineBasicBlock *CallTarget =
-      MF.CreateMachineBasicBlock(Entry->getBasicBlock());
+      MF.createMachineBasicBlock(Entry->getBasicBlock());
   MCSymbol *TargetSym = MF.getContext().createTempSymbol();
   MF.push_back(CaptureSpec);
   MF.push_back(CallTarget);
 
   const unsigned CallOpc = Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32;
   const unsigned RetOpc = Is64Bit ? X86::RET64 : X86::RET32;
 
   Entry->addLiveIn(ThunkReg);

llvm/lib/Target/X86/X86InsertPrefetch.cpp

for (auto MI = MBB.instr_begin(); MI != MBB.instr_end();) {
       assert(!Prefetches.empty() &&
              "The Prefetches vector should contain at least a value if "
              "findPrefetchInfo returned true.");
       for (auto &PrefInfo : Prefetches) {
         unsigned PFetchInstrID = PrefInfo.InstructionID;
         int64_t Delta = PrefInfo.Delta;
         const MCInstrDesc &Desc = TII->get(PFetchInstrID);
         MachineInstr *PFetch =
-            MF.CreateMachineInstr(Desc, Current->getDebugLoc(), true);
+            MF.createMachineInstr(Desc, Current->getDebugLoc(), true);
         MachineInstrBuilder MIB(MF, PFetch);
 
         static_assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 &&
                           X86::AddrIndexReg == 2 && X86::AddrDisp == 3 &&
                           X86::AddrSegmentReg == 4,
                       "Unexpected change in X86 operand offset order.");
 
         // This assumes X86::AddBaseReg = 0, {...}ScaleAmt = 1, etc.

llvm/lib/Target/X86/X86InstrInfo.cpp

default:
       llvm_unreachable("Unexpected instruction!");
     }
 
     const DebugLoc &DL = Orig.getDebugLoc();
     BuildMI(MBB, I, DL, get(X86::MOV32ri))
         .add(Orig.getOperand(0))
         .addImm(Value);
   } else {
-    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
+    MachineInstr *MI = MBB.getParent()->cloneMachineInstr(&Orig);
     MBB.insert(I, MI);
   }
 
   MachineInstr &NewMI = *std::prev(I);
   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
 }
 
 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.

 #undef VPERM_CASES
 }
 
 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
                                                    unsigned OpIdx1,
                                                    unsigned OpIdx2) const {
   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
     if (NewMI)
-      return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
+      return *MI.getParent()->getParent()->cloneMachineInstr(&MI);
     return MI;
   };
 
   switch (MI.getOpcode()) {
   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)

 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
                                      ArrayRef<MachineOperand> MOs,
                                      MachineBasicBlock::iterator InsertPt,
                                      MachineInstr &MI,
                                      const TargetInstrInfo &TII) {
   // Create the base instruction with the memory operand as the first part.
   // Omit the implicit operands, something BuildMI can't do.
   MachineInstr *NewMI =
-      MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
+      MF.createMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
   MachineInstrBuilder MIB(MF, NewMI);
   addOperands(MIB, MOs);
 
   // Loop over the rest of the ri operands, converting them over.
   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
   for (unsigned i = 0; i != NumOps; ++i) {
     MachineOperand &MO = MI.getOperand(i + 2);
     MIB.add(MO);

 
 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
                               MachineBasicBlock::iterator InsertPt,
                               MachineInstr &MI, const TargetInstrInfo &TII,
                               int PtrOffset = 0) {
   // Omit the implicit operands, something BuildMI can't do.
   MachineInstr *NewMI =
-      MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
+      MF.createMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
   MachineInstrBuilder MIB(MF, NewMI);
 
   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI.getOperand(i);
     if (i == OpNo) {
       assert(MO.isReg() && "Expected to fold into reg operand!");
       addOperands(MIB, MOs, PtrOffset);
     } else {
if (UnfoldStore) {
         MachineOperand &MO = NewMIs[0]->getOperand(i);
         if (MO.isReg())
           MO.setIsKill(false);
       }
     }
   }
 
   // Emit the data processing instruction.
-  MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
+  MachineInstr *DataMI = MF.createMachineInstr(MCID, MI.getDebugLoc(), true);
   MachineInstrBuilder MIB(MF, DataMI);
 
   if (FoldedStore)
     MIB.addReg(Reg, RegState::Define);
   for (MachineOperand &BeforeOp : BeforeOps)
     MIB.add(BeforeOp);
   if (FoldedLoad)
     MIB.addReg(Reg);

llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp

 static MachineBasicBlock &splitEdge(MachineBasicBlock &MBB,
                                     MachineBasicBlock &Succ, int SuccCount,
                                     MachineInstr *Br, MachineInstr *&UncondBr,
                                     const X86InstrInfo &TII) {
   assert(!Succ.isEHPad() && "Shouldn't get edges to EH pads!");
 
   MachineFunction &MF = *MBB.getParent();
 
-  MachineBasicBlock &NewMBB = *MF.CreateMachineBasicBlock();
+  MachineBasicBlock &NewMBB = *MF.createMachineBasicBlock();
 
   // We have to insert the new block immediately after the current one as we
   // don't know what layout-successor relationships the successor has and we
   // may not be able to (and generally don't want to) try to fix those up.
   MF.insert(std::next(MachineFunction::iterator(&MBB)), &NewMBB);
 
   // Update the branch instruction if necessary.
   if (Br) {

llvm/lib/Target/XCore/XCoreISelLowering.cpp

XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   //  thisMBB:
   //  ...
   //   TrueVal = ...
   //   cmpTY ccX, r1, r2
   //   bCC copy1MBB
   //   fallthrough --> copy0MBB
   MachineBasicBlock *thisMBB = BB;
   MachineFunction *F = BB->getParent();
-  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *copy0MBB = F->createMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *sinkMBB = F->createMachineBasicBlock(LLVM_BB);
   F->insert(It, copy0MBB);
   F->insert(It, sinkMBB);
 
   // Transfer the remainder of BB and its successor edges to sinkMBB.
   sinkMBB->splice(sinkMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
 

llvm/tools/llvm-exegesis/lib/Assembler.cpp

 }
 
 FunctionFiller::FunctionFiller(MachineFunction &MF,
                                std::vector<unsigned> RegistersSetUp)
     : MF(MF), MCII(MF.getTarget().getMCInstrInfo()), Entry(addBasicBlock()),
       RegistersSetUp(std::move(RegistersSetUp)) {}
 
 BasicBlockFiller FunctionFiller::addBasicBlock() {
-  MachineBasicBlock *MBB = MF.CreateMachineBasicBlock();
+  MachineBasicBlock *MBB = MF.createMachineBasicBlock();
   MF.push_back(MBB);
   return BasicBlockFiller(MF, MBB, MCII);
 }
 
 ArrayRef<unsigned> FunctionFiller::getRegistersSetUp() const {
   return RegistersSetUp;
 }
 

llvm/tools/llvm-reduce/ReducerWorkItem.cpp

for (auto &SrcMI : SrcMBB) {
         auto DstReg = DstMRI->createVirtualRegister(SrcRC);
         Src2DstReg[SrcReg] = DstReg;
       }
     }
   }
 
   // Clone blocks.
   for (auto &SrcMBB : *SrcMF)
-    Src2DstMBB[&SrcMBB] = DstMF->CreateMachineBasicBlock();
+    Src2DstMBB[&SrcMBB] = DstMF->createMachineBasicBlock();
   // Link blocks.
   for (auto &SrcMBB : *SrcMF) {
     auto *DstMBB = Src2DstMBB[&SrcMBB];
     DstMF->push_back(DstMBB);
     for (auto It = SrcMBB.succ_begin(), IterEnd = SrcMBB.succ_end();
          It != IterEnd; ++It) {
       auto *SrcSuccMBB = *It;
       auto *DstSuccMBB = Src2DstMBB[SrcSuccMBB];
       DstMBB->addSuccessor(DstSuccMBB);
     }
     for (auto &LI : SrcMBB.liveins())
       DstMBB->addLiveIn(LI);
   }
   // Clone instructions.
   for (auto &SrcMBB : *SrcMF) {
     auto *DstMBB = Src2DstMBB[&SrcMBB];
     for (auto &SrcMI : SrcMBB) {
       const auto &MCID =
           DstMF->getSubtarget().getInstrInfo()->get(SrcMI.getOpcode());
-      auto *DstMI = DstMF->CreateMachineInstr(MCID, SrcMI.getDebugLoc(),
+      auto *DstMI = DstMF->createMachineInstr(MCID, SrcMI.getDebugLoc(),
                                               /*NoImplicit=*/true);
       DstMBB->push_back(DstMI);
       for (auto &SrcMO : SrcMI.operands()) {
         MachineOperand DstMO(SrcMO);
         DstMO.clearParent();
         // Update vreg.
         if (DstMO.isReg() && Src2DstReg.count(DstMO.getReg())) {
           DstMO.setReg(Src2DstReg[DstMO.getReg()]);

llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

LI.getActionDefinitionsBuilder(TargetOpcode::G_PHI)
     .clampMinNumElements(0, s32, 2);
   LI.getLegacyLegalizerInfo().computeTables();
 
   LLT PhiTy = v5s32;
   DummyGISelObserver Observer;
   LegalizerHelper Helper(*MF, LI, Observer, B);
   B.setMBB(*EntryMBB);
 
-  MachineBasicBlock *MidMBB = MF->CreateMachineBasicBlock();
-  MachineBasicBlock *EndMBB = MF->CreateMachineBasicBlock();
+  MachineBasicBlock *MidMBB = MF->createMachineBasicBlock();
+  MachineBasicBlock *EndMBB = MF->createMachineBasicBlock();
   MF->insert(MF->end(), MidMBB);
   MF->insert(MF->end(), EndMBB);
 
   EntryMBB->addSuccessor(MidMBB);
   EntryMBB->addSuccessor(EndMBB);
   MidMBB->addSuccessor(EndMBB);
 
   auto InitVal = B.buildUndef(PhiTy);

llvm/unittests/CodeGen/InstrRefLDVTest.cpp

public:
   }
 
   void setupSingleBlock() {
     // Add an entry block with nothing but 'ret void' in it.
     Function &F = const_cast<llvm::Function &>(MF->getFunction());
     auto *BB0 = BasicBlock::Create(Ctx, "entry", &F);
     IRBuilder<> IRB(BB0);
     IRB.CreateRetVoid();
-    MBB0 = MF->CreateMachineBasicBlock(BB0);
+    MBB0 = MF->createMachineBasicBlock(BB0);
     MF->insert(MF->end(), MBB0);
-    MF->RenumberBlocks();
+    MF->renumberBlocks();
 
     setupLDVObj(&*MF);
   }
 
   void setupDiamondBlocks() {
     //        entry
     //        /  \
     //      br1  br2
     //        \  /
     //         ret
     llvm::Function &F = const_cast<llvm::Function &>(MF->getFunction());
     auto *BB0 = BasicBlock::Create(Ctx, "a", &F);
     auto *BB1 = BasicBlock::Create(Ctx, "b", &F);
     auto *BB2 = BasicBlock::Create(Ctx, "c", &F);
     auto *BB3 = BasicBlock::Create(Ctx, "d", &F);
     IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2), IRB3(BB3);
     IRB0.CreateBr(BB1);
     IRB1.CreateBr(BB2);
     IRB2.CreateBr(BB3);
     IRB3.CreateRetVoid();
-    MBB0 = MF->CreateMachineBasicBlock(BB0);
+    MBB0 = MF->createMachineBasicBlock(BB0);
     MF->insert(MF->end(), MBB0);
-    MBB1 = MF->CreateMachineBasicBlock(BB1);
+    MBB1 = MF->createMachineBasicBlock(BB1);
     MF->insert(MF->end(), MBB1);
-    MBB2 = MF->CreateMachineBasicBlock(BB2);
+    MBB2 = MF->createMachineBasicBlock(BB2);
     MF->insert(MF->end(), MBB2);
-    MBB3 = MF->CreateMachineBasicBlock(BB3);
+    MBB3 = MF->createMachineBasicBlock(BB3);
     MF->insert(MF->end(), MBB3);
     MBB0->addSuccessor(MBB1);
     MBB0->addSuccessor(MBB2);
     MBB1->addSuccessor(MBB3);
     MBB2->addSuccessor(MBB3);
-    MF->RenumberBlocks();
+    MF->renumberBlocks();
 
     setupLDVObj(&*MF);
   }
 
   void setupSimpleLoop() {
     //    entry
     //     |
     //     |/-----\
     //    loopblk |
     //     |\-----/
     //     |
     //     ret
     llvm::Function &F = const_cast<llvm::Function &>(MF->getFunction());
     auto *BB0 = BasicBlock::Create(Ctx, "entry", &F);
     auto *BB1 = BasicBlock::Create(Ctx, "loop", &F);
     auto *BB2 = BasicBlock::Create(Ctx, "ret", &F);
     IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2);
     IRB0.CreateBr(BB1);
     IRB1.CreateBr(BB2);
     IRB2.CreateRetVoid();
-    MBB0 = MF->CreateMachineBasicBlock(BB0);
+    MBB0 = MF->createMachineBasicBlock(BB0);
     MF->insert(MF->end(), MBB0);
-    MBB1 = MF->CreateMachineBasicBlock(BB1);
+    MBB1 = MF->createMachineBasicBlock(BB1);
     MF->insert(MF->end(), MBB1);
-    MBB2 = MF->CreateMachineBasicBlock(BB2);
+    MBB2 = MF->createMachineBasicBlock(BB2);
     MF->insert(MF->end(), MBB2);
     MBB0->addSuccessor(MBB1);
     MBB1->addSuccessor(MBB2);
     MBB1->addSuccessor(MBB1);
-    MF->RenumberBlocks();
+    MF->renumberBlocks();
 
     setupLDVObj(&*MF);
   }
 
   void setupNestedLoops() {
     //    entry
     //     |
     //    loop1
void setupNestedLoops() {
     auto *BB3 = BasicBlock::Create(Ctx, "join", &F);
     auto *BB4 = BasicBlock::Create(Ctx, "ret", &F);
     IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2), IRB3(BB3), IRB4(BB4);
     IRB0.CreateBr(BB1);
     IRB1.CreateBr(BB2);
     IRB2.CreateBr(BB3);
     IRB3.CreateBr(BB4);
     IRB4.CreateRetVoid();
-    MBB0 = MF->CreateMachineBasicBlock(BB0);
+    MBB0 = MF->createMachineBasicBlock(BB0);
     MF->insert(MF->end(), MBB0);
-    MBB1 = MF->CreateMachineBasicBlock(BB1);
+    MBB1 = MF->createMachineBasicBlock(BB1);
     MF->insert(MF->end(), MBB1);
-    MBB2 = MF->CreateMachineBasicBlock(BB2);
+    MBB2 = MF->createMachineBasicBlock(BB2);
     MF->insert(MF->end(), MBB2);
-    MBB3 = MF->CreateMachineBasicBlock(BB3);
+    MBB3 = MF->createMachineBasicBlock(BB3);
     MF->insert(MF->end(), MBB3);
-    MBB4 = MF->CreateMachineBasicBlock(BB4);
+    MBB4 = MF->createMachineBasicBlock(BB4);
     MF->insert(MF->end(), MBB4);
     MBB0->addSuccessor(MBB1);
     MBB1->addSuccessor(MBB2);
     MBB2->addSuccessor(MBB2);
     MBB2->addSuccessor(MBB3);
     MBB3->addSuccessor(MBB1);
     MBB3->addSuccessor(MBB4);
-    MF->RenumberBlocks();
+    MF->renumberBlocks();
 
     setupLDVObj(&*MF);
   }
 
   void setupNoDominatingLoop() {
     //           entry
     //            / \
     //           /   \
void setupNoDominatingLoop() {
     auto *BB3 = BasicBlock::Create(Ctx, "joinblk", &F);
     auto *BB4 = BasicBlock::Create(Ctx, "ret", &F);
     IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2), IRB3(BB3), IRB4(BB4);
     IRB0.CreateBr(BB1);
     IRB1.CreateBr(BB2);
     IRB2.CreateBr(BB3);
     IRB3.CreateBr(BB4);
     IRB4.CreateRetVoid();
-    MBB0 = MF->CreateMachineBasicBlock(BB0);
+    MBB0 = MF->createMachineBasicBlock(BB0);
     MF->insert(MF->end(), MBB0);
-    MBB1 = MF->CreateMachineBasicBlock(BB1);
+    MBB1 = MF->createMachineBasicBlock(BB1);
     MF->insert(MF->end(), MBB1);
-    MBB2 = MF->CreateMachineBasicBlock(BB2);
+    MBB2 = MF->createMachineBasicBlock(BB2);
     MF->insert(MF->end(), MBB2);
-    MBB3 = MF->CreateMachineBasicBlock(BB3);
+    MBB3 = MF->createMachineBasicBlock(BB3);
     MF->insert(MF->end(), MBB3);
-    MBB4 = MF->CreateMachineBasicBlock(BB4);
+    MBB4 = MF->createMachineBasicBlock(BB4);
     MF->insert(MF->end(), MBB4);
     MBB0->addSuccessor(MBB1);
     MBB0->addSuccessor(MBB2);
     MBB1->addSuccessor(MBB3);
     MBB2->addSuccessor(MBB3);
     MBB3->addSuccessor(MBB1);
     MBB3->addSuccessor(MBB2);
     MBB3->addSuccessor(MBB4);
-    MF->RenumberBlocks();
+    MF->renumberBlocks();
 
     setupLDVObj(&*MF);
   }
 
   void setupBadlyNestedLoops() {
     //           entry
     //             |
     //           loop1 -o
void setupBadlyNestedLoops() {
     auto *BB3 = BasicBlock::Create(Ctx, "loop3", &F);
     auto *BB4 = BasicBlock::Create(Ctx, "ret", &F);
     IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2), IRB3(BB3), IRB4(BB4);
     IRB0.CreateBr(BB1);
     IRB1.CreateBr(BB2);
     IRB2.CreateBr(BB3);
     IRB3.CreateBr(BB4);
     IRB4.CreateRetVoid();
-    MBB0 = MF->CreateMachineBasicBlock(BB0);
+    MBB0 = MF->createMachineBasicBlock(BB0);
     MF->insert(MF->end(), MBB0);
-    MBB1 = MF->CreateMachineBasicBlock(BB1);
+    MBB1 = MF->createMachineBasicBlock(BB1);
     MF->insert(MF->end(), MBB1);
-    MBB2 = MF->CreateMachineBasicBlock(BB2);
+    MBB2 = MF->createMachineBasicBlock(BB2);
     MF->insert(MF->end(), MBB2);
-    MBB3 = MF->CreateMachineBasicBlock(BB3);
+    MBB3 = MF->createMachineBasicBlock(BB3);
     MF->insert(MF->end(), MBB3);
-    MBB4 = MF->CreateMachineBasicBlock(BB4);
+    MBB4 = MF->createMachineBasicBlock(BB4);
     MF->insert(MF->end(), MBB4);
     MBB0->addSuccessor(MBB1);
     MBB1->addSuccessor(MBB1);
     MBB1->addSuccessor(MBB2);
     MBB2->addSuccessor(MBB1);
     MBB2->addSuccessor(MBB2);
     MBB2->addSuccessor(MBB3);
     MBB3->addSuccessor(MBB2);
     MBB3->addSuccessor(MBB3);
     MBB3->addSuccessor(MBB4);
-    MF->RenumberBlocks();
+    MF->renumberBlocks();
 
     setupLDVObj(&*MF);
   }
 
   MachineFunction *readMIRBlock(const char *Input) {
     MIRStr.clear();
     StringRef S = Twine(Twine(R"MIR(
 --- |

llvm/unittests/CodeGen/LexicalScopesTest.cpp

LexicalScopesTest() : Ctx(), Mod("beehives", Ctx) {
     auto BB2 = BasicBlock::Create(Ctx, "b", &F);
     auto BB3 = BasicBlock::Create(Ctx, "c", &F);
     auto BB4 = BasicBlock::Create(Ctx, "d", &F);
     IRBuilder<> IRB1(BB1), IRB2(BB2), IRB3(BB3), IRB4(BB4);
     IRB1.CreateBr(BB2);
     IRB2.CreateBr(BB3);
     IRB3.CreateBr(BB4);
     IRB4.CreateRetVoid();
-    MBB1 = MF->CreateMachineBasicBlock(BB1);
+    MBB1 = MF->createMachineBasicBlock(BB1);
     MF->insert(MF->end(), MBB1);
-    MBB2 = MF->CreateMachineBasicBlock(BB2);
+    MBB2 = MF->createMachineBasicBlock(BB2);
     MF->insert(MF->end(), MBB2);
-    MBB3 = MF->CreateMachineBasicBlock(BB3);
+    MBB3 = MF->createMachineBasicBlock(BB3);
     MF->insert(MF->end(), MBB3);
-    MBB4 = MF->CreateMachineBasicBlock(BB4);
+    MBB4 = MF->createMachineBasicBlock(BB4);
     MF->insert(MF->end(), MBB4);
     MBB1->addSuccessor(MBB2);
     MBB1->addSuccessor(MBB3);
     MBB2->addSuccessor(MBB4);
     MBB3->addSuccessor(MBB4);
 
     // Create metadata: CU, subprogram, some blocks and an inline function
     // scope.

llvm/unittests/CodeGen/MachineInstrTest.cpp

MCInstrDesc MCID = {
       0, NumOps,  NumDefs, 0,     0, 1ULL << MCID::HasOptionalDef,
       0, nullptr, nullptr, OpInfo};
 
   // Create two MIs with different virtual reg defs and the same uses.
   unsigned VirtualDef1 = -42; // The value doesn't matter, but the sign does.
   unsigned VirtualDef2 = -43;
   unsigned VirtualUse = -44;
 
-  auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto MI1 = MF->createMachineInstr(MCID, DebugLoc());
   MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
   MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
 
-  auto MI2 = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto MI2 = MF->createMachineInstr(MCID, DebugLoc());
   MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
   MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
 
   // Check that they are identical when we ignore virtual register defs, but not
   // when we check defs.
   ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs));
   ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs));
 
   ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs));
   ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs));
 
   // Create two MIs with different virtual reg defs, and a def or use of a
   // sentinel register.
   unsigned SentinelReg = 0;
 
-  auto MI3 = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto MI3 = MF->createMachineInstr(MCID, DebugLoc());
   MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
   MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
 
-  auto MI4 = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto MI4 = MF->createMachineInstr(MCID, DebugLoc());
   MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
   MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
 
   // Check that they are never identical.
   ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::CheckDefs));
   ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::CheckDefs));
 
   ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::IgnoreVRegDefs));
TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) {
   // sure that the hash function is consistent with isEqual for various
   // combinations of them.
   unsigned VirtualDef1 = -42;
   unsigned VirtualDef2 = -43;
   unsigned VirtualReg = -44;
   unsigned SentinelReg = 0;
   unsigned PhysicalReg = 45;
 
-  auto VD1VU = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto VD1VU = MF->createMachineInstr(MCID, DebugLoc());
   VD1VU->addOperand(*MF,
                     MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
   VD1VU->addOperand(*MF,
                     MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
 
-  auto VD2VU = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto VD2VU = MF->createMachineInstr(MCID, DebugLoc());
   VD2VU->addOperand(*MF,
                     MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
   VD2VU->addOperand(*MF,
                     MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
 
-  auto VD1SU = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto VD1SU = MF->createMachineInstr(MCID, DebugLoc());
   VD1SU->addOperand(*MF,
                     MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
   VD1SU->addOperand(*MF,
                     MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
 
-  auto VD1SD = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto VD1SD = MF->createMachineInstr(MCID, DebugLoc());
   VD1SD->addOperand(*MF,
                     MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
   VD1SD->addOperand(*MF,
                     MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
 
-  auto VD2PU = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto VD2PU = MF->createMachineInstr(MCID, DebugLoc());
   VD2PU->addOperand(*MF,
                     MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
   VD2PU->addOperand(*MF,
                     MachineOperand::CreateReg(PhysicalReg, /*isDef*/ false));
 
-  auto VD2PD = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto VD2PD = MF->createMachineInstr(MCID, DebugLoc());
   VD2PD->addOperand(*MF,
                     MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
   VD2PD->addOperand(*MF,
                     MachineOperand::CreateReg(PhysicalReg, /*isDef*/ true));
 
   checkHashAndIsEqualMatch(VD1VU, VD2VU);
   checkHashAndIsEqualMatch(VD1VU, VD1SU);
   checkHashAndIsEqualMatch(VD1VU, VD1SD);
TEST(MachineInstrPrintingTest, DebugLocPrinting) {
   MCInstrDesc MCID = {0, 1, 1, 0, 0, 0, 0, nullptr, nullptr, &OpInfo};
 
   DIFile *DIF = DIFile::getDistinct(Ctx, "filename", "");
   DISubprogram *DIS = DISubprogram::getDistinct(
       Ctx, nullptr, "", "", DIF, 0, nullptr, 0, nullptr, 0, 0, DINode::FlagZero,
       DISubprogram::SPFlagZero, nullptr);
   DILocation *DIL = DILocation::get(Ctx, 1, 5, DIS);
   DebugLoc DL(DIL);
-  MachineInstr *MI = MF->CreateMachineInstr(MCID, DL);
+  MachineInstr *MI = MF->createMachineInstr(MCID, DL);
   MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true));
 
   std::string str;
   raw_string_ostream OS(str);
   MI->print(OS, /*IsStandalone*/true, /*SkipOpers*/false, /*SkipDebugLoc*/false,
             /*AddNewLine*/false);
   ASSERT_TRUE(
       StringRef(OS.str()).startswith("$noreg = UNKNOWN debug-location "));
   ASSERT_TRUE(
       StringRef(OS.str()).endswith("filename:1:5"));
 }
 
 TEST(MachineInstrSpan, DistanceBegin) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
-  auto MBB = MF->CreateMachineBasicBlock();
+  auto MBB = MF->createMachineBasicBlock();
 
   MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
 
   auto MII = MBB->begin();
   MachineInstrSpan MIS(MII, MBB);
   ASSERT_TRUE(MIS.empty());
 
-  auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto MI = MF->createMachineInstr(MCID, DebugLoc());
   MBB->insert(MII, MI);
   ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
 }
 
 TEST(MachineInstrSpan, DistanceEnd) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
-  auto MBB = MF->CreateMachineBasicBlock();
+  auto MBB = MF->createMachineBasicBlock();
 
   MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
 
   auto MII = MBB->end();
   MachineInstrSpan MIS(MII, MBB);
   ASSERT_TRUE(MIS.empty());
 
-  auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto MI = MF->createMachineInstr(MCID, DebugLoc());
   MBB->insert(MII, MI);
   ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
 }
 
 TEST(MachineInstrExtraInfo, AddExtraInfo) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
   MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
 
-  auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto MI = MF->createMachineInstr(MCID, DebugLoc());
   auto MAI = MCAsmInfo();
   auto MC = createMCContext(&MAI);
   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
                                       MachineMemOperand::MOLoad, 8, Align(8));
   SmallVector<MachineMemOperand *, 2> MMOs;
   MMOs.push_back(MMO);
   MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
   MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);

 }
 
 TEST(MachineInstrExtraInfo, ChangeExtraInfo) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
   MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
 
-  auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto MI = MF->createMachineInstr(MCID, DebugLoc());
   auto MAI = MCAsmInfo();
   auto MC = createMCContext(&MAI);
   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
                                       MachineMemOperand::MOLoad, 8, Align(8));
   SmallVector<MachineMemOperand *, 2> MMOs;
   MMOs.push_back(MMO);
   MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
   MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);

 }
 
 TEST(MachineInstrExtraInfo, RemoveExtraInfo) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
   MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
 
-  auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
+  auto MI = MF->createMachineInstr(MCID, DebugLoc());
   auto MAI = MCAsmInfo();
   auto MC = createMCContext(&MAI);
   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
                                       MachineMemOperand::MOLoad, 8, Align(8));
   SmallVector<MachineMemOperand *, 2> MMOs;
   MMOs.push_back(MMO);
   MMOs.push_back(MMO);
   MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
for (const unsigned short Opcode :
         TargetOpcode::DBG_INSTR_REF, TargetOpcode::DBG_PHI,
         TargetOpcode::DBG_LABEL}) {
     const MCInstrDesc MCID = {
         Opcode, 0,       0,
         0,      0,       (1ULL << MCID::Pseudo) | (1ULL << MCID::Variadic),
         0,      nullptr, nullptr,
         nullptr};
 
-    auto *MI = MF->CreateMachineInstr(MCID, DebugLoc());
+    auto *MI = MF->createMachineInstr(MCID, DebugLoc());
     MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ false));
 
     MI->addOperand(*MF, MachineOperand::CreateImm(0));
     MI->getOperand(1).ChangeToRegister(0, false);
 
     ASSERT_TRUE(MI->getOperand(0).isDebug());
     ASSERT_TRUE(MI->getOperand(1).isDebug());
   }
 }
 
 static_assert(std::is_trivially_copyable<MCOperand>::value,
               "trivially copyable");
 
 } // end namespace

llvm/unittests/Target/AMDGPU/ExecMayBeModifiedBeforeAnyUse.cpp

TEST(AMDGPUExecMayBeModifiedBeforeAnyUse, TheTest) {
   Module Mod("Module", Ctx);
   Mod.setDataLayout(TM->createDataLayout());
 
   auto *Type = FunctionType::get(Type::getVoidTy(Ctx), false);
   auto *F = Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &Mod);
 
   MachineModuleInfo MMI(TM.get());
   auto MF = std::make_unique<MachineFunction>(*F, *TM, ST, 42, MMI);
-  auto *BB = MF->CreateMachineBasicBlock();
+  auto *BB = MF->createMachineBasicBlock();
   MF->push_back(BB);
 
   auto E = BB->end();
   DebugLoc DL;
   const auto &TII = *ST.getInstrInfo();
   auto &MRI = MF->getRegInfo();
 
   // create machine IR