[RISCV] add the MC layer support of Zfinx extension

[achieveartificialintelligence]

Summary

This patch added the MC layer support of Zfinx extension.

Authored-by: StephenFan
Co-Authored-by: Shao-Ce Sun

[achieveartificialintelligence]

Fix

[achieveartificialintelligence]

Add arch info

[achieveartificialintelligence]

Fix

[MaskRay]

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

164

Use functionName.

There is inconsistency in the code base but functionName is used much more than FunctionName.

186

https://llvm.org/docs/CodingStandards.html#don-t-use-braces-on-simple-single-statement-bodies-of-if-else-loop-statements

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

175 ↗

(On Diff #379273)

The indentation is inconsistent. Also applies to code above.

llvm/test/MC/RISCV/rv64zhinx-valid.s

4

llvm-mc can use %s instead of < %s

I heard that not using < is a bit more convenient for some Windows users. (They do suffer from llc and opt's prevailing < %s)

13

[[@LINE+1]] is a deprecated form.
Use [[#@LINE+1]]. Applies to many places elsewhere.

llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

47

What is {{[[:space:]]}} used for?

[achieveartificialintelligence]

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

164

I fix this in D112520

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

539

After D95588 is accepted, we will reuse this.

[achieveartificialintelligence]

Rebase

[achieveartificialintelligence]

Address @MaskRay 's comments.

[achieveartificialintelligence]

Rebase

[achieveartificialintelligence]

Rebase

[achieveartificialintelligence]

Ping

[achieveartificialintelligence]

Rebase and Ping.

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

69 ↗

(On Diff #388780)

Do we need to enforce that these can't be mixed with F, D, and Zfh?

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1711

D and Zfh imply F. Is it enough to just check F?

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

77 ↗

(On Diff #388780)

Can we merge this with FPFMAD_rrr_frm_single and FPFMAH_rrr_frm_single by passing the 0b00/0b01/0b10 value from FPFMAS_rrr_frm/FPFMAD_rrr_frm/FPFMAH_rrr_frm?

This applies to most of the _single classes. We should share them if possible.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

489 ↗

(On Diff #388780)

Aren't these aliases only valid for RV64. You need IN32X aliases for RV32 right?

[achieveartificialintelligence]

Address @craig.topper 's comments.

[achieveartificialintelligence]

Gentle Ping and Rebase.

[achieveartificialintelligence]

Update Part of Zfinx Codes

[achieveartificialintelligence]

I'll finish the rest of code, if this patch is acceptable.

[achieveartificialintelligence]

Ping.

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

290 ↗

(On Diff #396373)

@kito-cheng or @khchen is the right way to do this? Or should it be in updateImplication? Where do we have Zfhmin imply f or d imply f today?

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

34 ↗

(On Diff #396373)

Can you add let RenderMethod = "addRegOperands"; here. That should let you remove addGPRAsFPROperands from RISCVAsmParser.cpp. Similar for the other AsmOperandClasses.

[craig.topper]

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

170

Can we make use of let DecoderMethod = on RegisterClass to avoid these aliases?

[achieveartificialintelligence]

Address @craig.topper 's comments.

[achieveartificialintelligence]

Rebase

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

124 ↗

(On Diff #397193)

Can we use DAGOperand instead of RegisterOperand? I think that should allow you to avoid adding GPROp, FPR32Op, FPR64Op, and FPR16Op. You can just use the RegisterClasses. Both RegisterClass and RegisterOperand inherit from DAGOperand.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

217 ↗

(On Diff #397193)

Why do the aliases not apply to Zfinx?

[achieveartificialintelligence]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

217 ↗

(On Diff #397193)

Because the first argument is FPFMA_rrr_frm Inst, if we use multiclass here, it'll be FFPFMA_rrr_frm Inst, FFPFMA_rrr_frm Inst_INX. I don't know is there a better way?

[achieveartificialintelligence]

Use DAGOperand instead of RegisterOperand

[achieveartificialintelligence]

Fix issue in RISCVISAInfo.cpp

[achieveartificialintelligence]

Inspired by D116019, use multiclass in Alias

[achieveartificialintelligence]

update

[achieveartificialintelligence]

Ping. Zfinx has been ratified, could we spend some time on this patch?

[achieveartificialintelligence]

update

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

687 ↗

(On Diff #399270)

Do we need the equivalent of this for Zfinx and Zdinx?

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

228 ↗

(On Diff #399270)

Don't we need IN32X aliases too?

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

552

Is possible to reference GPR here to avoid listing the allocation order again? Similar to how GPRNoX0 does (sub GPR, X0). Not sure if there is a way to be exactly another list.

[achieveartificialintelligence]

Address @craig.topper's comments

[achieveartificialintelligence]

Rebase

[achieveartificialintelligence]

rebase

[achieveartificialintelligence]

Ping. Any other suggestions?

[craig.topper]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

136

Does putting this back the way it was and using "(add GPR)" in GPRF16, GPRF32, and GPRF64 work?

[achieveartificialintelligence]

Address @craig.topper's comments. Thanks!

[asb]

Thanks for your work on this. The way you've managed to use multiclasses to handle this with the 'ExtInfo' definitions takes a bit of unpicking to follow, but it does a really good job of keeping the instruction definitions largely unmodified. Nice!

I've got a few requests/questions on the test coverage:

• I'm not sure the inclusion of the load/store instructions in the z[d,f,h]inx test cases has much value, given those instructions are unmodified?
• Given that the set of F/D/Zfh instructions that _aren't_ supported under z[d,f,h]inx is relatively short, it's probably worth being exhaustive in the *-invalid.s test cases. It's only 8 instructions for Zfinx for instance.
• The *-invalid.s test cases should have coverage for using a floating point register with an operation that is supported by Z[d,f,h]inx
• The zdinx test cases don't include any coverage for when odd registers are used, but I think it should

[asb]

Not an issue for this MC-layer patch, but I've created https://github.com/riscv/riscv-zfinx/issues/14 to point out what seems to be an incorrect statement about the status quo on the ABI for 32-bit floating point types on RV64 in the Zfinx spec.

[achieveartificialintelligence]

@asb Thank you very much! Could you please take a look at what needs to be modified now?

[achieveartificialintelligence]

Separate the Zhinxmin and Zhinx extensions. Inspired by D118581

[luismarques]

Assuming this will be merged soon, do you want to submit a backport request for the 14.0 branch?

[achieveartificialintelligence]

In D93298#3296515, @luismarques wrote:

Assuming this will be merged soon, do you want to submit a backport request for the 14.0 branch?

Yes.

[Jim]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

556

Is XLenRI correct for GPRPF64? RV32 has size 32.

[craig.topper]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

556

I'm not sure the RegInfos are correct for the other classes either. The RegInfos override the register size, the spill size, and spill alignment. I think those should all be based on the FP type.

So I don't think any of these should have a RegInfos.

[achieveartificialintelligence]

Address comments.

[achieveartificialintelligence]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

556

Without RegInfo, it would cause spill size to be changed for a large number of other tests.

[Jim]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

558

Is register pair only on RV32 for used as f64?

[achieveartificialintelligence]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

558

Yes.

[asb]

I think all my comments have been addressed. @craig.topper - are you happy your RegInfo question is addressed?

[craig.topper]

In D93298#3326230, @asb wrote:

I think all my comments have been addressed. @craig.topper - are you happy your RegInfo question is addressed?

I'm happy.

[asb]

In that case, LGTM (needs a rebase though). Thanks for your patience on this @achieveartificialintelligence.

[achieveartificialintelligence]

Thanks all!

[krasimir]

It appears that this is causing an assertion segfault in a rustc test over at our experimental rust + llvm@head bot:
https://buildkite.com/llvm-project/rust-llvm-integrate-prototype/builds/8430#167e6de5-2dd5-41c3-87d7-b6e3f3908371/262-706
The test is https://github.com/rust-lang/rust/blob/master/src/test/assembly/asm/riscv-types.rs. These two lines appear to cause it (code compiles fine when removed):

• check_reg!(a0_f32 f32 "a0" "mv"); https://github.com/rust-lang/rust/blob/f838a425e3134d036a7d9632935111a569ac7446/src/test/assembly/asm/riscv-types.rs#L178
• check_reg!(a0_f64 f64 "a0" "mv"); https://github.com/rust-lang/rust/blob/f838a425e3134d036a7d9632935111a569ac7446/src/test/assembly/asm/riscv-types.rs#L192

The assertion:

Impossible reg-to-reg copy
UNREACHABLE executed at [...]/rust/src/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:350

The IR for riscv-types.rs:

; ModuleID = 'riscv_types.4cedf4b7-cgu.0'
source_filename = "riscv_types.4cedf4b7-cgu.0"
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
target triple = "riscv64"

@extern_static = external dso_local global i8
@alloc55 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"reg_i8" }>, align 1
@alloc56 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"reg_i16" }>, align 1
@alloc57 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"reg_i32" }>, align 1
@alloc58 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"reg_f32" }>, align 1
@alloc59 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"reg_i64" }>, align 1
@alloc60 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"reg_f64" }>, align 1
@alloc61 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"reg_ptr" }>, align 1
@alloc62 = private unnamed_addr constant <{ [8 x i8] }> <{ [8 x i8] c"freg_f32" }>, align 1
@alloc63 = private unnamed_addr constant <{ [8 x i8] }> <{ [8 x i8] c"freg_f64" }>, align 1
@alloc64 = private unnamed_addr constant <{ [5 x i8] }> <{ [5 x i8] c"a0_i8" }>, align 1
@alloc65 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_i16" }>, align 1
@alloc66 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_i32" }>, align 1
@alloc67 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_f32" }>, align 1
@alloc68 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_i64" }>, align 1
@alloc69 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_f64" }>, align 1
@alloc70 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_ptr" }>, align 1
@alloc71 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"fa0_f32" }>, align 1
@alloc72 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"fa0_f64" }>, align 1

; Function Attrs: nounwind
define dso_local void @sym_fn() unnamed_addr #0 {
start:
  tail call void asm sideeffect alignstack "call ${0:c}", "s,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(void ()* nonnull @extern_func) #1, !srcloc !1
  ret void
}

; Function Attrs: nounwind
define dso_local void @sym_static() unnamed_addr #0 {
start:
  tail call void asm sideeffect alignstack "lb t0, ${0:c}", "s,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i8* nonnull @extern_static) #1, !srcloc !2
  ret void
}

; Function Attrs: nounwind
define dso_local i8 @reg_i8(i8 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [6 x i8] }>* @alloc55 to [0 x i8]*), i64 6) #1
  %0 = tail call i8 asm sideeffect alignstack "mv ${0}, ${1}", "=&r,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i8 %x) #1, !srcloc !3
  ret i8 %0
}

; Function Attrs: nounwind
define dso_local i16 @reg_i16(i16 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc56 to [0 x i8]*), i64 7) #1
  %0 = tail call i16 asm sideeffect alignstack "mv ${0}, ${1}", "=&r,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i16 %x) #1, !srcloc !3
  ret i16 %0
}

; Function Attrs: nounwind
define dso_local i32 @reg_i32(i32 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc57 to [0 x i8]*), i64 7) #1
  %0 = tail call i32 asm sideeffect alignstack "mv ${0}, ${1}", "=&r,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i32 %x) #1, !srcloc !3
  ret i32 %0
}

; Function Attrs: nounwind
define dso_local float @reg_f32(float %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc58 to [0 x i8]*), i64 7) #1
  %0 = tail call float asm sideeffect alignstack "mv ${0}, ${1}", "=&r,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(float %x) #1, !srcloc !3
  ret float %0
}

; Function Attrs: nounwind
define dso_local i64 @reg_i64(i64 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc59 to [0 x i8]*), i64 7) #1
  %0 = tail call i64 asm sideeffect alignstack "mv ${0}, ${1}", "=&r,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i64 %x) #1, !srcloc !3
  ret i64 %0
}

; Function Attrs: nounwind
define dso_local double @reg_f64(double %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc60 to [0 x i8]*), i64 7) #1
  %0 = tail call double asm sideeffect alignstack "mv ${0}, ${1}", "=&r,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(double %x) #1, !srcloc !3
  ret double %0
}

; Function Attrs: nounwind
define dso_local i8* @reg_ptr(i8* %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc61 to [0 x i8]*), i64 7) #1
  %0 = tail call i8* asm sideeffect alignstack "mv ${0}, ${1}", "=&r,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i8* %x) #1, !srcloc !3
  ret i8* %0
}

; Function Attrs: nounwind
define dso_local float @freg_f32(float %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [8 x i8] }>* @alloc62 to [0 x i8]*), i64 8) #1
  %0 = tail call float asm sideeffect alignstack "fmv.s ${0}, ${1}", "=&f,f,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(float %x) #1, !srcloc !3
  ret float %0
}

; Function Attrs: nounwind
define dso_local double @freg_f64(double %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [8 x i8] }>* @alloc63 to [0 x i8]*), i64 8) #1
  %0 = tail call double asm sideeffect alignstack "fmv.d ${0}, ${1}", "=&f,f,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(double %x) #1, !srcloc !3
  ret double %0
}

; Function Attrs: nounwind
define dso_local i8 @a0_i8(i8 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [5 x i8] }>* @alloc64 to [0 x i8]*), i64 5) #1
  %0 = tail call i8 asm sideeffect alignstack "mv a0, a0", "={x10},{x10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i8 %x) #1, !srcloc !4
  ret i8 %0
}

; Function Attrs: nounwind
define dso_local i16 @a0_i16(i16 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [6 x i8] }>* @alloc65 to [0 x i8]*), i64 6) #1
  %0 = tail call i16 asm sideeffect alignstack "mv a0, a0", "={x10},{x10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i16 %x) #1, !srcloc !4
  ret i16 %0
}

; Function Attrs: nounwind
define dso_local i32 @a0_i32(i32 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [6 x i8] }>* @alloc66 to [0 x i8]*), i64 6) #1
  %0 = tail call i32 asm sideeffect alignstack "mv a0, a0", "={x10},{x10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i32 %x) #1, !srcloc !4
  ret i32 %0
}

; Function Attrs: nounwind
define dso_local float @a0_f32(float %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [6 x i8] }>* @alloc67 to [0 x i8]*), i64 6) #1
  %0 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(float %x) #1, !srcloc !4
  ret float %0
}

; Function Attrs: nounwind
define dso_local i64 @a0_i64(i64 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [6 x i8] }>* @alloc68 to [0 x i8]*), i64 6) #1
  %0 = tail call i64 asm sideeffect alignstack "mv a0, a0", "={x10},{x10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i64 %x) #1, !srcloc !4
  ret i64 %0
}

; Function Attrs: nounwind
define dso_local double @a0_f64(double %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [6 x i8] }>* @alloc69 to [0 x i8]*), i64 6) #1
  %0 = tail call double asm sideeffect alignstack "mv a0, a0", "={x10},{x10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(double %x) #1, !srcloc !4
  ret double %0
}

; Function Attrs: nounwind
define dso_local i8* @a0_ptr(i8* %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [6 x i8] }>* @alloc70 to [0 x i8]*), i64 6) #1
  %0 = tail call i8* asm sideeffect alignstack "mv a0, a0", "={x10},{x10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i8* %x) #1, !srcloc !4
  ret i8* %0
}

; Function Attrs: nounwind
define dso_local float @fa0_f32(float %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc71 to [0 x i8]*), i64 7) #1
  %0 = tail call float asm sideeffect alignstack "fmv.s fa0, fa0", "={f10},{f10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(float %x) #1, !srcloc !4
  ret float %0
}

; Function Attrs: nounwind
define dso_local double @fa0_f64(double %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc72 to [0 x i8]*), i64 7) #1
  %0 = tail call double asm sideeffect alignstack "fmv.d fa0, fa0", "={f10},{f10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(double %x) #1, !srcloc !4
  ret double %0
}

; Function Attrs: nounwind
declare dso_local void @extern_func() unnamed_addr #0

; Function Attrs: nounwind
declare dso_local void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1, i64) unnamed_addr #0

attributes #0 = { nounwind "target-cpu"="generic-rv64" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0}

!0 = !{i32 1, !"Code Model", i32 3}
!1 = !{i32 1048}
!2 = !{i32 1281}
!3 = !{i32 1670}
!4 = !{i32 2113}

@achieveartificialintelligence could you please take a look? Any ideas what's going wrong here?

[jrtc27]

In D93298#3331641, @krasimir wrote:

It appears that this is causing an assertion segfault in a rustc test over at our experimental rust + llvm@head bot:
https://buildkite.com/llvm-project/rust-llvm-integrate-prototype/builds/8430#167e6de5-2dd5-41c3-87d7-b6e3f3908371/262-706
The test is https://github.com/rust-lang/rust/blob/master/src/test/assembly/asm/riscv-types.rs. These two lines appear to cause it (code compiles fine when removed):

• check_reg!(a0_f32 f32 "a0" "mv"); https://github.com/rust-lang/rust/blob/f838a425e3134d036a7d9632935111a569ac7446/src/test/assembly/asm/riscv-types.rs#L178
• check_reg!(a0_f64 f64 "a0" "mv"); https://github.com/rust-lang/rust/blob/f838a425e3134d036a7d9632935111a569ac7446/src/test/assembly/asm/riscv-types.rs#L192

The assertion:

Impossible reg-to-reg copy
UNREACHABLE executed at [...]/rust/src/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:350

...

This is just MC layer support. Inline assembly interacts with CodeGen; I assume the register classes/constraints still need updating to support Zfinx.

llvm/test/MC/RISCV/rv32i-invalid.s

1

This is an unrelated change

[achieveartificialintelligence]

@krasimir Since I don't have a rust environment, can you help me to test if D120130 works?

[jrtc27]

In D93298#3332020, @achieveartificialintelligence wrote:

@krasimir Since I don't have a rust environment, can you help me to test if D120130 works?

Hm, actually, looking at the log, it doesn't appear to be trying to use Zfinx? My guess is that putting a float in a GPR has broken as that's now legal but should only be legal for Zfinx?

[xbolva00]

It appears that this is causing an assertion segfault in a rustc test over at our experimental rust + llvm@head bot:

I dont think that patch author is required to debug this issue for "experimental rust + llvm@head" - downstream.

Since I don't have a rust environment

There is no requirement, indeed. LLVM devs are not responsible to keep ""experimental rust + llvm@head" working.

[jrtc27]

In D93298#3332038, @xbolva00 wrote:

It appears that this is causing an assertion segfault in a rustc test over at our experimental rust + llvm@head bot:

I dont think that patch author is required to debug this issue for "experimental rust + llvm@head" - downstream.

Since I don't have a rust environment

There is no requirement, indeed. LLVM devs are not responsible to keep ""experimental rust + llvm@head" working.

They're required to assist with fixing regressions that show when compiling legitimate IR. An IR reproducer was given, so no Rust toolchain knowledge should be needed, at that point it's the LLVM dev's responsibility, and if they can't fix it in a timely manner then it should be backed out.

[xbolva00]

In D93298#3332058, @jrtc27 wrote:

In D93298#3332038, @xbolva00 wrote:

It appears that this is causing an assertion segfault in a rustc test over at our experimental rust + llvm@head bot:

I dont think that patch author is required to debug this issue for "experimental rust + llvm@head" - downstream.

Since I don't have a rust environment

There is no requirement, indeed. LLVM devs are not responsible to keep ""experimental rust + llvm@head" working.

They're required to assist with fixing regressions that show when compiling legitimate IR. An IR reproducer was given, so no Rust toolchain knowledge should be needed, at that point it's the LLVM dev's responsibility, and if they can't fix it in a timely manner then it should be backed out.

Then yeah, if IR is provided and is standard one, this is okay. Consider to add that IR as testcase for the fix.

[nikic]

Because I happened to also run into this, reduced IR for -mtriple=riscv32 -mattr=+d is:

define float @test(float %x) {
  %1 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10}"(float 0.000000e+00)
  ret float 0.000000e+00
}

[krasimir]

@achieveartificialintelligence any progress with the problematic IR? Have you been able to reproduce using nikic's reduced example?

[achieveartificialintelligence]

In D93298#3342452, @krasimir wrote:

@achieveartificialintelligence any progress with the problematic IR? Have you been able to reproduce using nikic's reduced example?

Sorry, I don't have a solution right now.

[krasimir]

In D93298#3342480, @achieveartificialintelligence wrote:

In D93298#3342452, @krasimir wrote:

@achieveartificialintelligence any progress with the problematic IR? Have you been able to reproduce using nikic's reduced example?

Sorry, I don't have a solution right now.

Could we revert this until then?

[craig.topper]

Here's a fix that I tested on the original repreoduce. It detects that we picked one of the new register classes and tries to redirect back to the normal GPR register class if the GPR register class has the same width. I also checked for MVT::Other to use the GPR class if there was no type.

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 3daf2d03de03..4984872139c5 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -10893,7 +10893,28 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
     }
   }
 
-  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
+  std::pair<Register, const TargetRegisterClass*> Res;
+  Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
+
+  if (Res.second == &RISCV::GPRF32RegClass) {
+    if (!Subtarget.is64Bit() || VT == MVT::Other)
+      return std::make_pair(Res.first, &RISCV::GPRRegClass);
+    return std::make_pair(0, nullptr);
+  }
+
+  if (Res.second == &RISCV::GPRF64RegClass) {
+    if (Subtarget.is64Bit() || VT == MVT::Other)
+      return std::make_pair(Res.first, &RISCV::GPRRegClass);
+    return std::make_pair(0, nullptr);
+  }
+
+  if (Res.second == &RISCV::GPRF16RegClass) {
+    if (VT == MVT::Other)
+      return std::make_pair(Res.first, &RISCV::GPRRegClass);
+    return std::make_pair(0, nullptr);
+  }
+
+  return Res;
 }

[achieveartificialintelligence]

Thanks for @craig.topper's patch!

[achieveartificialintelligence]

Can you help test if this patch works fine now? @krasimir

[achieveartificialintelligence]

Rebase

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

10923–10924 ↗

(On Diff #411719)

[achieveartificialintelligence]

Address @jrtc27's comments

[achieveartificialintelligence]

Are there any other errors now? @krasimir @nikic

[craig.topper]

llvm/test/CodeGen/RISCV/zfinx-types.ll

5 ↗

(On Diff #411375)

I'm not sure the Zfh or D RUN lines are really doing anything. Especially the Zfh.

The same bug did happen with double, D extension and RV64 so should probably test that.

[achieveartificialintelligence]

Address @craig.topper's comment

[craig.topper]

llvm/test/CodeGen/RISCV/zfinx-types.ll

5 ↗

(On Diff #411375)

I see you added rv64, but didn't add a test case that uses double instead of float.

[krasimir]

@achieveartificialintelligence thank you for looking into this, sorry for the late reply!

It looks like the latest version addresses @nikic's IR reproducer with -mtriple=riscv32.

There seems to be an error trying this out with -mtriple=riscv64:

% cat test.ll
define float @test(float %x) {
  %1 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10}"(float 0.000000e+00)
  ret float 0.000000e+00
}
% llc -mtriple=riscv32 -mattr=+d test.ll
% llc -mtriple=riscv64 -mattr=+d test.ll
error: couldn't allocate output register for constraint '{x10}'

I'm not sure if this is intended to work -mtriple=riscv64, but judging by the newly added test RUN: llc -mtriple=riscv64 ... line it seems like it should?

[craig.topper]

In D93298#3354313, @krasimir wrote:

@achieveartificialintelligence thank you for looking into this, sorry for the late reply!

It looks like the latest version addresses @nikic's IR reproducer with -mtriple=riscv32.

There seems to be an error trying this out with -mtriple=riscv64:

% cat test.ll
define float @test(float %x) {
  %1 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10}"(float 0.000000e+00)
  ret float 0.000000e+00
}
% llc -mtriple=riscv32 -mattr=+d test.ll
% llc -mtriple=riscv64 -mattr=+d test.ll
error: couldn't allocate output register for constraint '{x10}'

I'm not sure if this is intended to work -mtriple=riscv64, but judging by the newly added test RUN: llc -mtriple=riscv64 ... line it seems like it should?

My patch was only partially correct. I'll fix it

[craig.topper]

In D93298#3355088, @craig.topper wrote:

In D93298#3354313, @krasimir wrote:

@achieveartificialintelligence thank you for looking into this, sorry for the late reply!

It looks like the latest version addresses @nikic's IR reproducer with -mtriple=riscv32.

There seems to be an error trying this out with -mtriple=riscv64:

% cat test.ll
define float @test(float %x) {
  %1 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10}"(float 0.000000e+00)
  ret float 0.000000e+00
}
% llc -mtriple=riscv32 -mattr=+d test.ll
% llc -mtriple=riscv64 -mattr=+d test.ll
error: couldn't allocate output register for constraint '{x10}'

I'm not sure if this is intended to work -mtriple=riscv64, but judging by the newly added test RUN: llc -mtriple=riscv64 ... line it seems like it should?

My patch was only partially correct. I'll fix it

I just pushed 6cb42cd6669785f3b611106e1b6b38bbe65733a9 to hopefully fix this.

[jrtc27]

Does a double with r for RV32 work with that fix? That's supposed to give the low half of the register. You might need to also deal with the register pair class?

[jrtc27]

Never mind, I see you added a test for that case

[krasimir]

I just pushed 6cb42cd6669785f3b611106e1b6b38bbe65733a9 to hopefully fix this.

Thank you Craig! That fixed it.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

#include "RISCVGenAsmMatcher.inc"
   OperandMatchResultTy parseAtomicMemOp(OperandVector &Operands);
   OperandMatchResultTy parseOperandWithModifier(OperandVector &Operands);
   OperandMatchResultTy parseBareSymbol(OperandVector &Operands);
   OperandMatchResultTy parseCallSymbol(OperandVector &Operands);
   OperandMatchResultTy parsePseudoJumpSymbol(OperandVector &Operands);
   OperandMatchResultTy parseJALOffset(OperandVector &Operands);
   OperandMatchResultTy parseVTypeI(OperandVector &Operands);
   OperandMatchResultTy parseMaskReg(OperandVector &Operands);
+  OperandMatchResultTy parseGPRAsFPR(OperandVector &Operands);
 
   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
 
   bool parseDirectiveOption();
   bool parseDirectiveAttribute();
   bool parseDirectiveInsn(SMLoc L);
 
   void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
enum class KindTy {
     Register,
     Immediate,
     SystemRegister,
     VType,
   } Kind;
 
   bool IsRV64;
 
+  bool IsGPRAsFPR;
+
   struct RegOp {
     MCRegister RegNum;
   };
 
   struct ImmOp {
     const MCExpr *Val;
   };
 
public:
   bool isSystemRegister() const { return Kind == KindTy::SystemRegister; }
   bool isVType() const { return Kind == KindTy::VType; }
 
   bool isGPR() const {
     return Kind == KindTy::Register &&
            RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum);
   }
 
+  bool isGPRAsFPR() const { return isGPR() && IsGPRAsFPR; }
+
+  bool isGPRPF64AsFPR() const {
+    return isGPR() && IsGPRAsFPR && !IsRV64 && !((Reg.RegNum - RISCV::X0) & 1);
+  }
+
+  bool isGPRF64AsFPR() const { return isGPR() && IsGPRAsFPR && IsRV64; }
+
   static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm,
                                   RISCVMCExpr::VariantKind &VK) {
     if (auto *RE = dyn_cast<RISCVMCExpr>(Expr)) {
       VK = RE->getKind();
       return RE->evaluateAsConstant(Imm);
     }
 
     if (auto CE = dyn_cast<MCConstantExpr>(Expr)) {
static std::unique_ptr<RISCVOperand> createToken(StringRef Str, SMLoc S,
     Op->Tok = Str;
     Op->StartLoc = S;
     Op->EndLoc = S;
     Op->IsRV64 = IsRV64;
     return Op;
   }
 
   static std::unique_ptr<RISCVOperand> createReg(unsigned RegNo, SMLoc S,
-                                                 SMLoc E, bool IsRV64) {
+                                                 SMLoc E, bool IsRV64,
+                                                 bool IsGPRAsFPR = false) {
     auto Op = std::make_unique<RISCVOperand>(KindTy::Register);
     Op->Reg.RegNum = RegNo;
     Op->StartLoc = S;
     Op->EndLoc = E;
     Op->IsRV64 = IsRV64;
+    Op->IsGPRAsFPR = IsGPRAsFPR;
     return Op;
   }
 
   static std::unique_ptr<RISCVOperand> createImm(const MCExpr *Val, SMLoc S,
                                                  SMLoc E, bool IsRV64) {
     auto Op = std::make_unique<RISCVOperand>(KindTy::Immediate);
     Op->Imm.Val = Val;
     Op->StartLoc = S;
public:
   }
 
   // Used by the TableGen Code
   void addRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getReg()));
   }
 
+  void addGPRAsFPROperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(getReg()));
+  }
+
+  void addGPRPF64AsFPROperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands");
+    Inst.addOperand(MCOperand::createReg(getReg()));
+  }
+
+  void addGPRF64AsFPROperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands");
+    Inst.addOperand(MCOperand::createReg(getReg()));
+  }
+
   void addImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     addExpr(Inst, getImm());
   }
 
   void addFenceArgOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     // isFenceArg has validated the operand, meaning this cast is safe

 }
 
 static MCRegister convertFPR64ToFPR32(MCRegister Reg) {
   assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register");
   return Reg - RISCV::F0_D + RISCV::F0_F;
 }
 
 static MCRegister convertVRToVRMx(const MCRegisterInfo &RI, MCRegister Reg,
                                   unsigned Kind) {
   unsigned RegClassID;
   if (Kind == MCK_VRM2)
     RegClassID = RISCV::VRM2RegClassID;
   else if (Kind == MCK_VRM4)
     RegClassID = RISCV::VRM4RegClassID;
   else if (Kind == MCK_VRM8)
     RegClassID = RISCV::VRM8RegClassID;
   else
unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
   }
   // As the parser couldn't differentiate an FPR16 from an FPR64, coerce the
   // register from FPR64 to FPR16 if necessary.
   if (IsRegFPR64 && Kind == MCK_FPR16) {
     Op.Reg.RegNum = convertFPR64ToFPR16(Reg);
     return Match_Success;
   }
   // As the parser couldn't differentiate an VRM2/VRM4/VRM8 from an VR, coerce
   // the register from VR to VRM2/VRM4/VRM8 if necessary.
   if (IsRegVR && (Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8)) {
     Op.Reg.RegNum = convertVRToVRMx(*getContext().getRegisterInfo(), Reg, Kind);
     if (Op.Reg.RegNum == 0)
       return Match_InvalidOperand;
     return Match_Success;
   }
   return Match_InvalidOperand;
 }
 
 bool RISCVAsmParser::generateImmOutOfRangeError(
     OperandVector &Operands, uint64_t ErrorInfo, int64_t Lower, int64_t Upper,
     Twine Msg = "immediate must be an integer in the range") {
   SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
   return Error(ErrorLoc, Msg + " [" + Twine(Lower) + ", " + Twine(Upper) + "]");
 }
 
case AsmToken::Identifier:
     SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
     getLexer().Lex();
     Operands.push_back(RISCVOperand::createReg(RegNo, S, E, isRV64()));
   }
 
   return MatchOperand_Success;
 }
 
+OperandMatchResultTy RISCVAsmParser::parseGPRAsFPR(OperandVector &Operands) {
+  switch (getLexer().getKind()) {
+  default:
+    return MatchOperand_NoMatch;
+  case AsmToken::Identifier:
+    StringRef Name = getLexer().getTok().getIdentifier();
+    MCRegister RegNo;
+    matchRegisterNameHelper(isRV32E(), RegNo, Name);
+
+    if (RegNo == RISCV::NoRegister)
+      return MatchOperand_NoMatch;
+    SMLoc S = getLoc();
+    SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
+    getLexer().Lex();
+    Operands.push_back(RISCVOperand::createReg(
+        RegNo, S, E, isRV64(),
+        !getSTI().hasFeature(RISCV::FeatureStdExtF) &&
+            !getSTI().hasFeature(RISCV::FeatureStdExtD) &&
+            !getSTI().hasFeature(RISCV::FeatureStdExtZfh)));
+  }
+  return MatchOperand_Success;
+}
+
 OperandMatchResultTy
 RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) {
   if (getLexer().isNot(AsmToken::LParen)) {
     Error(getLoc(), "expected '('");
     return MatchOperand_ParseFail;
   }
 
   getParser().Lex(); // Eat '('

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

 //===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the RISCVDisassembler class.
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
   if (RegNo >= 8)
     return MCDisassembler::Fail;
 
   MCRegister Reg = RISCV::X8 + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint64_t RegNo,
+                                              uint64_t Address,
+                                              const void *Decoder) {
+  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
+}
+
+static DecodeStatus DecodeGPRF32RegisterClass(MCInst &Inst, uint64_t RegNo,
+                                              uint64_t Address,
+                                              const void *Decoder) {
+  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
+}
+
+static DecodeStatus DecodeGPRF64RegisterClass(MCInst &Inst, uint64_t RegNo,
+                                             uint64_t Address,
+                                             const void *Decoder) {
+  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
+}
+
+static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint64_t RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo >= 32 || RegNo & 1) {
+    return MCDisassembler::Fail;
+  }
+
+  MCRegister Reg = RISCV::X0 + RegNo;
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo,
                                           uint64_t Address,
                                           const void *Decoder) {
   if (RegNo >= 32)
     return MCDisassembler::Fail;
 
   MCRegister Reg = RISCV::V0 + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
 
   // It's a 32 bit instruction if bit 0 and 1 are 1.
   if ((Bytes[0] & 0x3) == 0x3) {
     if (Bytes.size() < 4) {
       Size = 0;
       return MCDisassembler::Fail;
     }
     Insn = support::endian::read32le(Bytes.data());
+     if (STI.getFeatureBits()[RISCV::FeatureExtZdinx] &&
+        !STI.getFeatureBits()[RISCV::Feature64Bit]) {
+      LLVM_DEBUG(dbgs() << "Trying RV32DZfinx table (Double in Integer and"
+      "rv32)\n");
+      Result = decodeInstruction(DecoderTableRV32DZfinx32, MI, Insn, Address,
+                                   this, STI);
+      if (Result != MCDisassembler::Fail) {
+        Size = 4;
+        return Result;
+      }
+    }
+
+    if (STI.getFeatureBits()[RISCV::FeatureExtZfinx]) {
+      LLVM_DEBUG(dbgs() << "Trying RVZfinx table (Float in Integer):\n");
+      // Calling the auto-generated decoder function.
+      Result = decodeInstruction(DecoderTableRVZfinx32, MI, Insn, Address, this,
+                                       STI);
+      if (Result != MCDisassembler::Fail) {
+        Size = 4;
+        return Result;
+      }
+    }
     LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
     Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
     Size = 4;
   } else {
     if (Bytes.size() < 2) {
       Size = 0;
       return MCDisassembler::Fail;
     }

llvm/lib/Target/RISCV/RISCV.td

 def FeatureStdExtZfh
     : SubtargetFeature<"experimental-zfh", "HasStdExtZfh", "true",
                        "'Zfh' (Half-Precision Floating-Point)",
                        [FeatureStdExtF]>;
 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
                              AssemblerPredicate<(all_of FeatureStdExtZfh),
                              "'Zfh' (Half-Precision Floating-Point)">;
 
+def FeatureExtZfinx
+    : SubtargetFeature<"experimental-zfinx", "HasStdExtZfinx", "true",
+                       "'Zfinx' (Float in Integer)">;
+def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
+                               AssemblerPredicate<(all_of FeatureExtZfinx),
+                               "'Zfinx' (Float in Integer)">;
+
+def FeatureExtZdinx
+    : SubtargetFeature<"experimental-zdinx", "HasStdExtZdinx", "true",
+                       "'Zdinx' (Double in Integer)",
+                       [FeatureExtZfinx]>;
+def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
+                                AssemblerPredicate<(all_of FeatureExtZdinx),
+                                "'Zdinx' (Double in Integer)">;
+
+def FeatureExtZhinx
+    : SubtargetFeature<"experimental-zhinx", "HasStdExtZhinx", "true",
+                       "'Zhinx' (Half Float in Integer)",
+                       [FeatureExtZfinx]>;
+def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
+                                AssemblerPredicate<(all_of FeatureExtZhinx),
+                                "'Zhinx' (Half Float in Integer)">;
+
+def FeatureExtZhinxmin
+    : SubtargetFeature<"experimental-zhinxmin", "HasStdExtZhinxmin", "true",
+                       "'Zhinxmin' (Half Float in Integer Minimal)",
+                       [FeatureExtZfinx]>;
+def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
+                                AssemblerPredicate<(all_of FeatureExtZhinxmin),
+                                "'Zhinxmin' (Half Float in Integer Minimal)">;
+
+// Some instructions belong to both the Zhinx and Zfinxmin.
+// They should be enabled if either has been specified.
+def HasStdExtZhinxOrZhinxmin
+    : Predicate<"Subtarget->hasStdExtZhinx() || Subtarget->hasStdExtZhinxmin()">,
+                AssemblerPredicate<(any_of FeatureExtZhinx, FeatureExtZhinxmin),
+                                   "'Zhinx' (Half Float in Integer) or "
+                                   "'Zhinxmin' (Half Float in Integer Minimal)">;
+
 def FeatureStdExtC
     : SubtargetFeature<"c", "HasStdExtC", "true",
                        "'C' (Compressed Instructions)">;
 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
                            AssemblerPredicate<(all_of FeatureStdExtC),
                            "'C' (Compressed Instructions)">;
 
 def FeatureStdExtZba

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 include "RISCVInstrInfoM.td"
 include "RISCVInstrInfoA.td"
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoB.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"
+include "RISCVInstrInfoZfinx.td"
+include "RISCVInstrInfoZdinx.td"
+include "RISCVInstrInfoZhinx.td"

llvm/lib/Target/RISCV/RISCVInstrInfoZdinx.td

+//===- RISCVInstrInfoZdinx.td - RISC-V 'Zdinx' instructions -*- tblgen -*-====//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Zdinx'
+// double in integer.
+// This version is still experimental as the 'Zdinx' extension hasn't been
+// ratified yet.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def GPRPF64AsFPR : AsmOperandClass {
+  let Name = "GPRPF64AsFPR";
+  let ParserMethod = "parseGPRAsFPR";
+}
+
+def GPRF64AsFPR : AsmOperandClass {
+  let Name = "GPRF64AsFPR";
+  let ParserMethod = "parseGPRAsFPR";
+}
+
+def GPRF64Op : RegisterOperand<GPRF64> {
+  let ParserMatchClass = GPRF64AsFPR;
+}
+
+def GPRPF64Op : RegisterOperand<GPRPF64> {
+  let ParserMatchClass = GPRPF64AsFPR;
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "RVZfinx" in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPFMADINX_rrr_frm<RISCVOpcode opcode, string opcodestr, RegisterOperand freg>
+    : RVInstR4Frm<0b01, opcode, (outs freg:$rd),
+               (ins freg:$rs1, freg:$rs2, freg:$rs3, frmarg:$funct3),
+                opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPALUDINX_rr<bits<7> funct7, bits<3> funct3, string opcodestr, RegisterOperand freg>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs freg:$rd),
+              (ins freg:$rs1, freg:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPALUDINX_rr_frm<bits<7> funct7, string opcodestr, RegisterOperand freg>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs freg:$rd),
+                (ins freg:$rs1, freg:$rs2, frmarg:$funct3), opcodestr,
+                 "$rd, $rs1, $rs2, $funct3">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPCmpDINX_rr<bits<3> funct3, string opcodestr, RegisterOperand freg>
+    : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPROp:$rd),
+              (ins freg:$rs1, freg:$rs2), opcodestr, "$rd, $rs1, $rs2">,
+      Sched<[WriteFCmp64, ReadFCmp64, ReadFCmp64]>;
+} // DecoderNamespace = "RVZfinx"
+
+class FPFMADINXDynFrmAlias<FPFMADINX_rrr_frm Inst, string OpcodeStr, RegisterOperand freg>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
+                (Inst freg:$rd, freg:$rs1, freg:$rs2, freg:$rs3, 0b111)>;
+
+class FPALUDINXDynFrmAlias<FPALUDINX_rr_frm Inst, string OpcodeStr, RegisterOperand freg>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                (Inst freg:$rd, freg:$rs1, freg:$rs2, 0b111)>;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+// Instructions in Zdinx extension on RV64
+let Predicates = [HasStdExtZdinx, IsRV64] in {
+def FMADD_D_INX  : FPFMADINX_rrr_frm<OPC_MADD, "fmadd.d", GPRF64Op>,
+                   Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
+def              : FPFMADINXDynFrmAlias<FMADD_D_INX, "fmadd.d", GPRF64Op>;
+def FMSUB_D_INX  : FPFMADINX_rrr_frm<OPC_MSUB, "fmsub.d", GPRF64Op>,
+                   Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
+def              : FPFMADINXDynFrmAlias<FMSUB_D_INX, "fmsub.d", GPRF64Op>;
+def FNMSUB_D_INX : FPFMADINX_rrr_frm<OPC_NMSUB, "fnmsub.d", GPRF64Op>,
+                   Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
+def              : FPFMADINXDynFrmAlias<FNMSUB_D_INX, "fnmsub.d", GPRF64Op>;
+def FNMADD_D_INX : FPFMADINX_rrr_frm<OPC_NMADD, "fnmadd.d", GPRF64Op>,
+                   Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
+def              : FPFMADINXDynFrmAlias<FNMADD_D_INX, "fnmadd.d", GPRF64Op>;
+
+def FADD_D_INX : FPALUDINX_rr_frm<0b0000001, "fadd.d", GPRF64Op>,
+                 Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
+def            : FPALUDINXDynFrmAlias<FADD_D_INX, "fadd.d", GPRF64Op>;
+def FSUB_D_INX : FPALUDINX_rr_frm<0b0000101, "fsub.d", GPRF64Op>,
+                 Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
+def            : FPALUDINXDynFrmAlias<FSUB_D_INX, "fsub.d", GPRF64Op>;
+def FMUL_D_INX : FPALUDINX_rr_frm<0b0001001, "fmul.d", GPRF64Op>,
+                 Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>;
+def            : FPALUDINXDynFrmAlias<FMUL_D_INX, "fmul.d", GPRF64Op>;
+def FDIV_D_INX : FPALUDINX_rr_frm<0b0001101, "fdiv.d", GPRF64Op>,
+                 Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>;
+def            : FPALUDINXDynFrmAlias<FDIV_D_INX, "fdiv.d", GPRF64Op>;
+
+def FSQRT_D_INX : FPUnaryOpINX_r_frm<0b0101101, GPRF64Op, GPRF64Op, "fsqrt.d">,
+                  Sched<[WriteFSqrt64, ReadFSqrt64]> {
+  let rs2 = 0b00000;
+}
+def             : FPUnaryOpINXDynFrmAlias<FSQRT_D_INX, "fsqrt.d", GPRF64Op, GPRF64Op>;
+
+def FSGNJ_D_INX  : FPALUDINX_rr<0b0010001, 0b000, "fsgnj.d", GPRF64Op>,
+                   Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
+def FSGNJN_D_INX : FPALUDINX_rr<0b0010001, 0b001, "fsgnjn.d", GPRF64Op>,
+                   Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
+def FSGNJX_D_INX : FPALUDINX_rr<0b0010001, 0b010, "fsgnjx.d", GPRF64Op>,
+                   Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
+def FMIN_D_INX   : FPALUDINX_rr<0b0010101, 0b000, "fmin.d", GPRF64Op>,
+                   Sched<[WriteFMinMax64, ReadFMinMax64, ReadFMinMax64]>;
+def FMAX_D_INX   : FPALUDINX_rr<0b0010101, 0b001, "fmax.d", GPRF64Op>,
+                   Sched<[WriteFMinMax64, ReadFMinMax64, ReadFMinMax64]>;
+
+def FCVT_S_D_INX : FPUnaryOpINX_r_frm<0b0100000, GPRF32Op, GPRF64Op, "fcvt.s.d">,
+                   Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]> {
+  let rs2 = 0b00001;
+}
+def              : FPUnaryOpINXDynFrmAlias<FCVT_S_D_INX, "fcvt.s.d", GPRF32Op, GPRF64Op>;
+
+def FCVT_D_S_INX : FPUnaryOpINX_r<0b0100001, 0b000, GPRF64Op, GPRF32Op, "fcvt.d.s">,
+                   Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]> {
+  let rs2 = 0b00000;
+}
+
+def FEQ_D_INX : FPCmpDINX_rr<0b010, "feq.d", GPRF64Op>;
+def FLT_D_INX : FPCmpDINX_rr<0b001, "flt.d", GPRF64Op>;
+def FLE_D_INX : FPCmpDINX_rr<0b000, "fle.d", GPRF64Op>;
+
+def FCLASS_D_INX : FPUnaryOpINX_r<0b1110001, 0b001, GPROp, GPRF64Op, "fclass.d">,
+                   Sched<[WriteFClass64, ReadFClass64]> {
+  let rs2 = 0b00000;
+}
+
+def FCVT_W_D_INX : FPUnaryOpINX_r_frm<0b1100001, GPROp, GPRF64Op, "fcvt.w.d">,
+                   Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> {
+  let rs2 = 0b00000;
+}
+def              : FPUnaryOpINXDynFrmAlias<FCVT_W_D_INX, "fcvt.w.d", GPROp, GPRF64Op>;
+
+def FCVT_WU_D_INX : FPUnaryOpINX_r_frm<0b1100001, GPROp, GPRF64Op, "fcvt.wu.d">,
+                    Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> {
+  let rs2 = 0b00001;
+}
+def               : FPUnaryOpINXDynFrmAlias<FCVT_WU_D_INX, "fcvt.wu.d", GPROp, GPRF64Op>;
+
+def FCVT_D_W_INX : FPUnaryOpINX_r<0b1101001, 0b000, GPRF64Op, GPROp, "fcvt.d.w">,
+                   Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> {
+  let rs2 = 0b00000;
+}
+
+def FCVT_D_WU_INX : FPUnaryOpINX_r<0b1101001, 0b000, GPRF64Op, GPROp, "fcvt.d.wu">,
+                    Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> {
+  let rs2 = 0b00001;
+}
+
+def FCVT_L_D_INX : FPUnaryOpINX_r_frm<0b1100001, GPROp, GPRF64Op, "fcvt.l.d">,
+                   Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]> {
+  let rs2 = 0b00010;
+}
+def              : FPUnaryOpINXDynFrmAlias<FCVT_L_D_INX, "fcvt.l.d", GPROp, GPRF64Op>;
+
+def FCVT_LU_D_INX : FPUnaryOpINX_r_frm<0b1100001, GPROp, GPRF64Op, "fcvt.lu.d">,
+                    Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]> {
+  let rs2 = 0b00011;
+}
+def               : FPUnaryOpINXDynFrmAlias<FCVT_LU_D_INX, "fcvt.lu.d", GPROp, GPRF64Op>;
+
+def FCVT_D_L_INX : FPUnaryOpINX_r_frm<0b1101001, GPRF64Op, GPROp, "fcvt.d.l">,
+                   Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]> {
+  let rs2 = 0b00010;
+}
+def              : FPUnaryOpINXDynFrmAlias<FCVT_D_L_INX, "fcvt.d.l", GPRF64Op, GPROp>;
+
+def FCVT_D_LU_INX : FPUnaryOpINX_r_frm<0b1101001, GPRF64Op, GPROp, "fcvt.d.lu">,
+                    Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]> {
+  let rs2 = 0b00011;
+}
+def               : FPUnaryOpINXDynFrmAlias<FCVT_D_LU_INX, "fcvt.d.lu", GPRF64Op, GPROp>;
+} // Predicates = [HasStdExtZdinx, IsRV64]
+
+// Instruction in Zdinx extension on RV32
+let Predicates = [HasStdExtZdinx, IsRV32] in {
+let DecoderNamespace = "RV32DZfinx" in {
+def FMADD_D_IN32X  : FPFMADINX_rrr_frm<OPC_MADD, "fmadd.d", GPRPF64Op>,
+                     Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
+def FMSUB_D_IN32X  : FPFMADINX_rrr_frm<OPC_MSUB, "fmsub.d", GPRPF64Op>,
+                     Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
+def FNMSUB_D_IN32X : FPFMADINX_rrr_frm<OPC_NMSUB, "fnmsub.d", GPRPF64Op>,
+                     Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
+def FNMADD_D_IN32X : FPFMADINX_rrr_frm<OPC_NMADD, "fnmadd.d", GPRPF64Op>,
+                     Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
+
+def FADD_D_IN32X : FPALUDINX_rr_frm<0b0000001, "fadd.d", GPRPF64Op>,
+                   Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
+def FSUB_D_IN32X : FPALUDINX_rr_frm<0b0000101, "fsub.d", GPRPF64Op>,
+                   Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
+def FMUL_D_IN32X : FPALUDINX_rr_frm<0b0001001, "fmul.d", GPRPF64Op>,
+                   Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>;
+def FDIV_D_IN32X : FPALUDINX_rr_frm<0b0001101, "fdiv.d", GPRPF64Op>,
+                   Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>;
+
+def FSQRT_D_IN32X : FPUnaryOpINX_r_frm<0b0101101, GPRPF64Op, GPRPF64Op, "fsqrt.d">,
+                    Sched<[WriteFSqrt64, ReadFSqrt64]> {
+  let rs2 = 0b00000;
+}
+
+def FSGNJ_D_IN32X  : FPALUDINX_rr<0b0010001, 0b000, "fsgnj.d", GPRPF64Op>,
+                     Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
+def FSGNJN_D_IN32X : FPALUDINX_rr<0b0010001, 0b001, "fsgnjn.d", GPRPF64Op>,
+                     Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
+def FSGNJX_D_IN32X : FPALUDINX_rr<0b0010001, 0b010, "fsgnjx.d", GPRPF64Op>,
+                     Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
+def FMIN_D_IN32X   : FPALUDINX_rr<0b0010101, 0b000, "fmin.d", GPRPF64Op>,
+                     Sched<[WriteFMinMax64, ReadFMinMax64, ReadFMinMax64]>;
+def FMAX_D_IN32X   : FPALUDINX_rr<0b0010101, 0b001, "fmax.d", GPRPF64Op>,
+                     Sched<[WriteFMinMax64, ReadFMinMax64, ReadFMinMax64]>;
+
+def FCVT_S_D_IN32X : FPUnaryOpINX_r_frm<0b0100000, GPRF32Op, GPRPF64Op, "fcvt.s.d">,
+                     Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]> {
+  let rs2 = 0b00001;
+}
+
+def FCVT_D_S_IN32X : FPUnaryOpINX_r<0b0100001, 0b000, GPRPF64Op, GPRF32Op, "fcvt.d.s">,
+                     Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]> {
+  let rs2 = 0b00000;
+}
+
+def FEQ_D_IN32X : FPCmpDINX_rr<0b010, "feq.d", GPRPF64Op>;
+def FLT_D_IN32X : FPCmpDINX_rr<0b001, "flt.d", GPRPF64Op>;
+def FLE_D_IN32X : FPCmpDINX_rr<0b000, "fle.d", GPRPF64Op>;
+
+def FCLASS_D_IN32X : FPUnaryOpINX_r<0b1110001, 0b001, GPROp, GPRPF64Op, "fclass.d">,
+                     Sched<[WriteFClass64, ReadFClass64]> {
+  let rs2 = 0b00000;
+}
+
+def FCVT_W_D_IN32X : FPUnaryOpINX_r_frm<0b1100001, GPROp, GPRPF64Op, "fcvt.w.d">,
+                     Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> {
+  let rs2 = 0b00000;
+}
+
+def FCVT_WU_D_IN32X : FPUnaryOpINX_r_frm<0b1100001, GPROp, GPRPF64Op, "fcvt.wu.d">,
+                      Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> {
+  let rs2 = 0b00001;
+}
+
+def FCVT_D_W_IN32X : FPUnaryOpINX_r<0b1101001, 0b000, GPRPF64Op, GPROp, "fcvt.d.w">,
+                     Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> {
+  let rs2 = 0b00000;
+}
+
+def FCVT_D_WU_IN32X : FPUnaryOpINX_r<0b1101001, 0b000, GPRPF64Op, GPROp, "fcvt.d.wu">,
+                      Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> {
+  let rs2 = 0b00001;
+}
+} // DecoderNamespace = "RV32DZfinx"
+
+def        : FPFMADINXDynFrmAlias<FMADD_D_IN32X, "fmadd.d", GPRPF64Op>;
+def        : FPFMADINXDynFrmAlias<FMSUB_D_IN32X, "fmsub.d", GPRPF64Op>;
+def        : FPFMADINXDynFrmAlias<FNMSUB_D_IN32X, "fnmsub.d", GPRPF64Op>;
+def        : FPALUDINXDynFrmAlias<FADD_D_IN32X, "fadd.d", GPRPF64Op>;
+def        : FPFMADINXDynFrmAlias<FNMADD_D_IN32X, "fnmadd.d", GPRPF64Op>;
+def        : FPALUDINXDynFrmAlias<FSUB_D_IN32X, "fsub.d", GPRPF64Op>;
+def        : FPALUDINXDynFrmAlias<FMUL_D_IN32X, "fmul.d", GPRPF64Op>;
+def        : FPALUDINXDynFrmAlias<FDIV_D_IN32X, "fdiv.d", GPRPF64Op>;
+def        : FPUnaryOpINXDynFrmAlias<FCVT_W_D_IN32X, "fcvt.w.d", GPROp, GPRPF64Op>;
+def        : FPUnaryOpINXDynFrmAlias<FSQRT_D_IN32X, "fsqrt.d", GPRPF64Op, GPRPF64Op>;
+def        : FPUnaryOpINXDynFrmAlias<FCVT_S_D_IN32X, "fcvt.s.d", GPRF32Op, GPRPF64Op>;
+def        : FPUnaryOpINXDynFrmAlias<FCVT_WU_D_IN32X, "fcvt.wu.d", GPROp, GPRPF64Op>;
+} // Predicates = [HasStdExtZdinx, IsRV32]
+
+//===----------------------------------------------------------------------===//
+// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZdinx, IsRV64] in {
+def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX GPRF64Op:$rd, GPRF64Op:$rs, GPRF64Op:$rs)>;
+def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_INX GPRF64Op:$rd, GPRF64Op:$rs, GPRF64Op:$rs)>;
+
+// fgt.d/fge.d are recognised by the GNU assembler but the canonical
+// flt.d/fle.d forms will always be printed. Therefore, set a zero weight.
+def : InstAlias<"fgt.d $rd, $rs, $rt",
+                (FLT_D_INX GPROp:$rd, GPRF64Op:$rt, GPRF64Op:$rs), 0>;
+def : InstAlias<"fge.d $rd, $rs, $rt",
+                (FLE_D_INX GPROp:$rd, GPRF64Op:$rt, GPRF64Op:$rs), 0>;
+} // Predicates = [HasStdExtZdinx, IsRV64]
+
+let Predicates = [HasStdExtZdinx, IsRV32] in {
+def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_IN32X GPRPF64Op:$rd, GPRPF64Op:$rs, GPRPF64Op:$rs)>;
+def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_IN32X GPRPF64Op:$rd, GPRPF64Op:$rs, GPRPF64Op:$rs)>;
+
+// fgt.d/fge.d are recognised by the GNU assembler but the canonical
+// flt.d/fle.d forms will always be printed. Therefore, set a zero weight.
+def : InstAlias<"fgt.d $rd, $rs, $rt",
+                (FLT_D_IN32X GPROp:$rd, GPRPF64Op:$rt, GPRPF64Op:$rs), 0>;
+def : InstAlias<"fge.d $rd, $rs, $rt",
+                (FLE_D_IN32X GPROp:$rd, GPRPF64Op:$rt, GPRPF64Op:$rs), 0>;
+} // Predicates = [HasStdExtZdinx, IsRV32]

llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td

+//=== RISCVInstrInfoZfinx.td - RISC-V 'Zfinx' instructions -*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Zfinx'
+// float in integer.
+// This version is still experimental as the 'Zfinx' extension hasn't been
+// ratified yet.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def GPRAsFPR : AsmOperandClass {
+  let Name = "GPRAsFPR";
+  let ParserMethod = "parseGPRAsFPR";
+}
+
+def GPRF32Op : RegisterOperand<GPRF32> {
+  let ParserMatchClass = GPRAsFPR;
+}
+
+def GPROp : RegisterOperand<GPR> {
+  let ParserMatchClass = GPRAsFPR;
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "RVZfinx" in {
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPFMASINX_rrr_frm<RISCVOpcode opcode, string opcodestr>
+    : RVInstR4Frm<0b00, opcode, (outs GPRF32Op:$rd),
+                  (ins GPRF32Op:$rs1, GPRF32Op:$rs2, GPRF32Op:$rs3, frmarg:$funct3),
+                  opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
+
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPALUSINX_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs GPRF32Op:$rd),
+              (ins GPRF32Op:$rs1, GPRF32Op:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPALUSINX_rr_frm<bits<7> funct7, string opcodestr>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs GPRF32Op:$rd),
+                 (ins GPRF32Op:$rs1, GPRF32Op:$rs2, frmarg:$funct3), opcodestr,
+                  "$rd, $rs1, $rs2, $funct3">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPUnaryOpINX_r<bits<7> funct7, bits<3> funct3, RegisterOperand rdty,
+                RegisterOperand rs1ty, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1),
+              opcodestr, "$rd, $rs1">;
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPUnaryOpINXINX_r<bits<7> funct7, bits<3> funct3, RegisterOperand rdty,
+                RegisterOperand rs1ty, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1),
+              opcodestr, "$rd, $rs1">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPUnaryOpINX_r_frm<bits<7> funct7, RegisterOperand rdty, RegisterOperand rs1ty,
+                      string opcodestr>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd),
+                 (ins rs1ty:$rs1, frmarg:$funct3), opcodestr,
+                  "$rd, $rs1, $funct3">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPCmpSINX_rr<bits<3> funct3, string opcodestr>
+    : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPROp:$rd),
+              (ins GPRF32Op:$rs1, GPRF32Op:$rs2), opcodestr, "$rd, $rs1, $rs2">,
+      Sched<[WriteFCmp32, ReadFCmp32, ReadFCmp32]>;
+
+} // DecoderNamespace = "RVZfinx"
+
+class FPFMASINXDynFrmAlias<FPFMASINX_rrr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
+                (Inst GPRF32Op:$rd, GPRF32Op:$rs1, GPRF32Op:$rs2, GPRF32Op:$rs3, 0b111)>;
+
+class FPALUSINXDynFrmAlias<FPALUSINX_rr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                (Inst GPRF32Op:$rd, GPRF32Op:$rs1, GPRF32Op:$rs2, 0b111)>;
+
+class FPUnaryOpINXDynFrmAlias<FPUnaryOpINX_r_frm Inst, string OpcodeStr,
+                           RegisterOperand rdty, RegisterOperand rs1ty>
+    : InstAlias<OpcodeStr#" $rd, $rs1",
+                (Inst rdty:$rd, rs1ty:$rs1, 0b111)>;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+// Instructions in Zfinx extension on RV32/64
+let Predicates = [HasStdExtZfinx] in {
+
+def FMADD_S_INX  : FPFMASINX_rrr_frm<OPC_MADD, "fmadd.s">,
+                   Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
+def              : FPFMASINXDynFrmAlias<FMADD_S_INX, "fmadd.s">;
+def FMSUB_S_INX  : FPFMASINX_rrr_frm<OPC_MSUB, "fmsub.s">,
+                   Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
+def              : FPFMASINXDynFrmAlias<FMSUB_S_INX, "fmsub.s">;
+def FNMSUB_S_INX : FPFMASINX_rrr_frm<OPC_NMSUB, "fnmsub.s">,
+                   Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
+def              : FPFMASINXDynFrmAlias<FNMSUB_S_INX, "fnmsub.s">;
+def FNMADD_S_INX : FPFMASINX_rrr_frm<OPC_NMADD, "fnmadd.s">,
+                   Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
+def              : FPFMASINXDynFrmAlias<FNMADD_S_INX, "fnmadd.s">;
+
+def FADD_S_INX : FPALUSINX_rr_frm<0b0000000, "fadd.s">,
+                 Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
+def            : FPALUSINXDynFrmAlias<FADD_S_INX, "fadd.s">;
+def FSUB_S_INX : FPALUSINX_rr_frm<0b0000100, "fsub.s">,
+                 Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
+def            : FPALUSINXDynFrmAlias<FSUB_S_INX, "fsub.s">;
+def FMUL_S_INX : FPALUSINX_rr_frm<0b0001000, "fmul.s">,
+                 Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>;
+def            : FPALUSINXDynFrmAlias<FMUL_S_INX, "fmul.s">;
+def FDIV_S_INX : FPALUSINX_rr_frm<0b0001100, "fdiv.s">,
+                 Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>;
+def            : FPALUSINXDynFrmAlias<FDIV_S_INX, "fdiv.s">;
+
+def FSQRT_S_INX : FPUnaryOpINX_r_frm<0b0101100, GPRF32Op, GPRF32Op, "fsqrt.s">,
+                  Sched<[WriteFSqrt32, ReadFSqrt32]> {
+  let rs2 = 0b00000;
+}
+def             : FPUnaryOpINXDynFrmAlias<FSQRT_S_INX, "fsqrt.s", GPRF32Op, GPRF32Op>;
+
+def FSGNJ_S_INX  : FPALUSINX_rr<0b0010000, 0b000, "fsgnj.s">,
+                   Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>;
+def FSGNJN_S_INX : FPALUSINX_rr<0b0010000, 0b001, "fsgnjn.s">,
+                   Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>;
+def FSGNJX_S_INX : FPALUSINX_rr<0b0010000, 0b010, "fsgnjx.s">,
+                   Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>;
+def FMIN_S_INX   : FPALUSINX_rr<0b0010100, 0b000, "fmin.s">,
+                   Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>;
+def FMAX_S_INX   : FPALUSINX_rr<0b0010100, 0b001, "fmax.s">,
+                   Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>;
+
+def FCVT_W_S_INX : FPUnaryOpINX_r_frm<0b1100000, GPROp, GPRF32Op, "fcvt.w.s">,
+                   Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> {
+  let rs2 = 0b00000;
+}
+def              : FPUnaryOpINXDynFrmAlias<FCVT_W_S_INX, "fcvt.w.s", GPROp, GPRF32Op>;
+
+def FCVT_WU_S_INX : FPUnaryOpINX_r_frm<0b1100000, GPROp, GPRF32Op, "fcvt.wu.s">,
+                    Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> {
+  let rs2 = 0b00001;
+}
+def               : FPUnaryOpINXDynFrmAlias<FCVT_WU_S_INX, "fcvt.wu.s", GPROp, GPRF32Op>;
+
+def FEQ_S_INX : FPCmpSINX_rr<0b010, "feq.s">;
+def FLT_S_INX : FPCmpSINX_rr<0b001, "flt.s">;
+def FLE_S_INX : FPCmpSINX_rr<0b000, "fle.s">;
+
+def FCLASS_S_INX : FPUnaryOpINX_r<0b1110000, 0b001, GPROp, GPRF32Op, "fclass.s">,
+                   Sched<[WriteFClass32, ReadFClass32]> {
+  let rs2 = 0b00000;
+}
+
+def FCVT_S_W_INX : FPUnaryOpINX_r_frm<0b1101000, GPRF32Op, GPROp, "fcvt.s.w">,
+                   Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> {
+  let rs2 = 0b00000;
+}
+def              : FPUnaryOpINXDynFrmAlias<FCVT_S_W_INX, "fcvt.s.w", GPRF32Op, GPROp>;
+
+def FCVT_S_WU_INX : FPUnaryOpINX_r_frm<0b1101000, GPRF32Op, GPROp, "fcvt.s.wu">,
+                    Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> {
+  let rs2 = 0b00001;
+}
+def               : FPUnaryOpINXDynFrmAlias<FCVT_S_WU_INX, "fcvt.s.wu", GPRF32Op, GPROp>;
+
+} // Predicates = [HasStdExtZfinx]
+
+// Instructions in Zfinx extension on RV64
+let Predicates = [HasStdExtZfinx, IsRV64] in {
+def FCVT_L_S_INX  : FPUnaryOpINX_r_frm<0b1100000, GPROp, GPRF32Op, "fcvt.l.s">,
+                    Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> {
+  let rs2 = 0b00010;
+}
+def               : FPUnaryOpINXDynFrmAlias<FCVT_L_S_INX, "fcvt.l.s", GPROp, GPRF32Op>;
+
+def FCVT_LU_S_INX  : FPUnaryOpINX_r_frm<0b1100000, GPROp, GPRF32Op, "fcvt.lu.s">,
+                     Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> {
+  let rs2 = 0b00011;
+}
+def                : FPUnaryOpINXDynFrmAlias<FCVT_LU_S_INX, "fcvt.lu.s", GPROp, GPRF32Op>;
+
+def FCVT_S_L_INX : FPUnaryOpINX_r_frm<0b1101000, GPRF32Op, GPROp, "fcvt.s.l">,
+                   Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> {
+  let rs2 = 0b00010;
+}
+def              : FPUnaryOpINXDynFrmAlias<FCVT_S_L_INX, "fcvt.s.l", GPRF32Op, GPROp>;
+
+def FCVT_S_LU_INX : FPUnaryOpINX_r_frm<0b1101000, GPRF32Op, GPROp, "fcvt.s.lu">,
+                    Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> {
+  let rs2 = 0b00011;
+}
+def               : FPUnaryOpINXDynFrmAlias<FCVT_S_LU_INX, "fcvt.s.lu", GPRF32Op, GPROp>;
+} // Predicates = [HasStdExtZfinx, IsRV64]
+
+//===----------------------------------------------------------------------===//
+// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZfinx] in {
+
+def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S_INX GPRF32Op:$rd, GPRF32Op:$rs, GPRF32Op:$rs)>;
+def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S_INX GPRF32Op:$rd, GPRF32Op:$rs, GPRF32Op:$rs)>;
+
+// fgt.s/fge.s are recognised by the GNU assembler but the canonical
+// flt.s/fle.s forms will always be printed. Therefore, set a zero weight.
+def : InstAlias<"fgt.s $rd, $rs, $rt",
+                (FLT_S_INX GPROp:$rd, GPRF32Op:$rt, GPRF32Op:$rs), 0>;
+def : InstAlias<"fge.s $rd, $rs, $rt",
+                (FLE_S_INX GPROp:$rd, GPRF32Op:$rt, GPRF32Op:$rs), 0>;
+
+} // Predicates = [HasStdExtZfinx]

llvm/lib/Target/RISCV/RISCVInstrInfoZhinx.td

+//===- RISCVInstrInfoZhinx.td - RISC-V 'Zhinx' instructions -*- tblgen -*-====//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Zhinx'
+// half float in integer.
+// This version is still experimental as the 'Zhinx' extension hasn't been
+// ratified yet.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def GPRF16Op : RegisterOperand<GPRF16> {
+  let ParserMatchClass = GPRAsFPR;
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "RVZfinx" in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPFMAHINX_rrr_frm<RISCVOpcode opcode, string opcodestr>
+    : RVInstR4Frm<0b10, opcode, (outs GPRF16Op:$rd),
+                  (ins GPRF16Op:$rs1, GPRF16Op:$rs2, GPRF16Op:$rs3, frmarg:$funct3),
+                  opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPALUHINX_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs GPRF16Op:$rd),
+              (ins GPRF16Op:$rs1, GPRF16Op:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPALUHINX_rr_frm<bits<7> funct7, string opcodestr>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs GPRF16Op:$rd),
+                 (ins GPRF16Op:$rs1, GPRF16Op:$rs2, frmarg:$funct3), opcodestr,
+                  "$rd, $rs1, $rs2, $funct3">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPCmpHINX_rr<bits<3> funct3, string opcodestr>
+    : RVInstR<0b1010010, funct3, OPC_OP_FP, (outs GPROp:$rd),
+              (ins GPRF16Op:$rs1, GPRF16Op:$rs2), opcodestr, "$rd, $rs1, $rs2">,
+      Sched<[WriteFCmp16, ReadFCmp16, ReadFCmp16]>;
+} // DecoderNamespace = "RVZfinx"
+
+class FPFMAHINXDynFrmAlias<FPFMAHINX_rrr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
+                (Inst GPRF16Op:$rd, GPRF16Op:$rs1, GPRF16Op:$rs2, GPRF16Op:$rs3, 0b111)>;
+
+class FPALUHINXDynFrmAlias<FPALUHINX_rr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                (Inst GPRF16Op:$rd, GPRF16Op:$rs1, GPRF16Op:$rs2, 0b111)>;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+// instructions in Zhinx extension on RV32/64
+let Predicates = [HasStdExtZhinx] in {
+def FMADD_H_INX  : FPFMAHINX_rrr_frm<OPC_MADD, "fmadd.h">,
+                   Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>;
+def              : FPFMAHINXDynFrmAlias<FMADD_H_INX, "fmadd.h">;
+def FMSUB_H_INX  : FPFMAHINX_rrr_frm<OPC_MSUB, "fmsub.h">,
+                   Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>;
+def              : FPFMAHINXDynFrmAlias<FMSUB_H_INX, "fmsub.h">;
+def FNMSUB_H_INX : FPFMAHINX_rrr_frm<OPC_NMSUB, "fnmsub.h">,
+                   Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>;
+def              : FPFMAHINXDynFrmAlias<FNMSUB_H_INX, "fnmsub.h">;
+def FNMADD_H_INX : FPFMAHINX_rrr_frm<OPC_NMADD, "fnmadd.h">,
+                   Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>;
+def              : FPFMAHINXDynFrmAlias<FNMADD_H_INX, "fnmadd.h">;
+
+def FADD_H_INX : FPALUHINX_rr_frm<0b0000010, "fadd.h">,
+                 Sched<[WriteFALU16, ReadFALU16, ReadFALU16]>;
+def            : FPALUHINXDynFrmAlias<FADD_H_INX, "fadd.h">;
+def FSUB_H_INX : FPALUHINX_rr_frm<0b0000110, "fsub.h">,
+                 Sched<[WriteFALU16, ReadFALU16, ReadFALU16]>;
+def            : FPALUHINXDynFrmAlias<FSUB_H_INX, "fsub.h">;
+def FMUL_H_INX : FPALUHINX_rr_frm<0b0001010, "fmul.h">,
+                 Sched<[WriteFMul16, ReadFMul16, ReadFMul16]>;
+def            : FPALUHINXDynFrmAlias<FMUL_H_INX, "fmul.h">;
+def FDIV_H_INX : FPALUHINX_rr_frm<0b0001110, "fdiv.h">,
+                 Sched<[WriteFDiv16, ReadFDiv16, ReadFDiv16]>;
+def            : FPALUHINXDynFrmAlias<FDIV_H_INX, "fdiv.h">;
+
+def FSQRT_H_INX : FPUnaryOpINX_r_frm<0b0101110, GPRF16Op, GPRF16Op, "fsqrt.h">,
+                  Sched<[WriteFSqrt16, ReadFSqrt16]> {
+  let rs2 = 0b00000;
+}
+def             : FPUnaryOpINXDynFrmAlias<FSQRT_H_INX, "fsqrt.h", GPRF16Op, GPRF16Op>;
+
+def FSGNJ_H_INX  : FPALUHINX_rr<0b0010010, 0b000, "fsgnj.h">,
+                   Sched<[WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16]>;
+def FSGNJN_H_INX : FPALUHINX_rr<0b0010010, 0b001, "fsgnjn.h">,
+                   Sched<[WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16]>;
+def FSGNJX_H_INX : FPALUHINX_rr<0b0010010, 0b010, "fsgnjx.h">,
+                   Sched<[WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16]>;
+def FMIN_H_INX   : FPALUHINX_rr<0b0010110, 0b000, "fmin.h">,
+                   Sched<[WriteFMinMax16, ReadFMinMax16, ReadFMinMax16]>;
+def FMAX_H_INX   : FPALUHINX_rr<0b0010110, 0b001, "fmax.h">,
+                   Sched<[WriteFMinMax16, ReadFMinMax16, ReadFMinMax16]>;
+
+def FCVT_W_H_INX : FPUnaryOpINX_r_frm<0b1100010, GPROp, GPRF16Op, "fcvt.w.h">,
+                   Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]> {
+  let rs2 = 0b00000;
+}
+def              : FPUnaryOpINXDynFrmAlias<FCVT_W_H_INX, "fcvt.w.h", GPROp, GPRF16Op>;
+
+def FCVT_WU_H_INX : FPUnaryOpINX_r_frm<0b1100010, GPROp, GPRF16Op, "fcvt.wu.h">,
+                    Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]> {
+  let rs2 = 0b00001;
+}
+def               : FPUnaryOpINXDynFrmAlias<FCVT_WU_H_INX, "fcvt.wu.h", GPROp, GPRF16Op>;
+
+def FCVT_H_W_INX : FPUnaryOpINX_r_frm<0b1101010, GPRF16Op, GPROp, "fcvt.h.w">,
+                   Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]> {
+  let rs2 = 0b00000;
+}
+def              : FPUnaryOpINXDynFrmAlias<FCVT_H_W_INX, "fcvt.h.w", GPRF16Op, GPROp>;
+
+def FCVT_H_WU_INX : FPUnaryOpINX_r_frm<0b1101010, GPRF16Op, GPROp, "fcvt.h.wu">,
+                    Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]> {
+  let rs2 = 0b00001;
+}
+def               : FPUnaryOpINXDynFrmAlias<FCVT_H_WU_INX, "fcvt.h.wu", GPRF16Op, GPROp>;
+
+def FEQ_H_INX : FPCmpHINX_rr<0b010, "feq.h">;
+def FLT_H_INX : FPCmpHINX_rr<0b001, "flt.h">;
+def FLE_H_INX : FPCmpHINX_rr<0b000, "fle.h">;
+
+def FCLASS_H_INX : FPUnaryOpINX_r<0b1110010, 0b001, GPROp, GPRF16Op, "fclass.h">,
+                   Sched<[WriteFClass16, ReadFClass16]> {
+  let rs2 = 0b00000;
+}
+} // Predicates = [HasStdExtZhinx]
+
+let Predicates = [HasStdExtZhinxOrZhinxmin] in {
+def FCVT_H_S_INX : FPUnaryOpINX_r_frm<0b0100010, GPRF16Op, GPRF32Op, "fcvt.h.s">,
+                   Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]> {
+  let rs2 = 0b00000;
+}
+def              : FPUnaryOpINXDynFrmAlias<FCVT_H_S_INX, "fcvt.h.s", GPRF16Op, GPRF32Op>;
+
+def FCVT_S_H_INX : FPUnaryOpINX_r<0b0100000, 0b000, GPRF32Op, GPRF16Op, "fcvt.s.h">,
+                   Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]> {
+  let rs2 = 0b00010;
+}
+} // Predicates = [HasStdExtZhinx]
+
+
+// Instructions in Zhinx extension on RV64
+let Predicates = [HasStdExtZhinx, IsRV64] in {
+def FCVT_L_H_INX  : FPUnaryOpINX_r_frm<0b1100010, GPROp, GPRF16Op, "fcvt.l.h">,
+                    Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]> {
+  let rs2 = 0b00010;
+}
+def               : FPUnaryOpINXDynFrmAlias<FCVT_L_H_INX, "fcvt.l.h", GPROp, GPRF16Op>;
+
+def FCVT_LU_H_INX  : FPUnaryOpINX_r_frm<0b1100010, GPROp, GPRF16Op, "fcvt.lu.h">,
+                     Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]> {
+  let rs2 = 0b00011;
+}
+def                : FPUnaryOpINXDynFrmAlias<FCVT_LU_H_INX, "fcvt.lu.h", GPROp, GPRF16Op>;
+
+def FCVT_H_L_INX : FPUnaryOpINX_r_frm<0b1101010, GPRF16Op, GPROp, "fcvt.h.l">,
+                   Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]> {
+  let rs2 = 0b00010;
+}
+def              : FPUnaryOpINXDynFrmAlias<FCVT_H_L_INX, "fcvt.h.l", GPRF16Op, GPROp>;
+
+def FCVT_H_LU_INX : FPUnaryOpINX_r_frm<0b1101010, GPRF16Op, GPROp, "fcvt.h.lu">,
+                    Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]> {
+  let rs2 = 0b00011;
+}
+def               : FPUnaryOpINXDynFrmAlias<FCVT_H_LU_INX, "fcvt.h.lu", GPRF16Op, GPROp>;
+} // Predicates = [HasStdExtZhinx, IsRV64]
+
+// instructions in Zhinx or zhinxmin, and Zdinx extensions
+let Predicates = [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx] in {
+def FCVT_H_D_INX : FPUnaryOpINX_r_frm<0b0100010, GPRF16Op, GPRF64Op, "fcvt.h.d">,
+                   Sched<[WriteFCvtF64ToF16, ReadFCvtF64ToF16]> {
+  let rs2 = 0b00001;
+}
+def              : FPUnaryOpINXDynFrmAlias<FCVT_H_D_INX, "fcvt.h.d", GPRF16Op, GPRF64Op>;
+
+def FCVT_D_H_INX : FPUnaryOpINX_r<0b0100001, 0b000, GPRF64Op, GPRF16Op, "fcvt.d.h">,
+                   Sched<[WriteFCvtF16ToF64, ReadFCvtF16ToF64]> {
+  let rs2 = 0b00010;
+}
+} // Predicates = [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx]
+
+//===----------------------------------------------------------------------===//
+// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZhinx] in {
+def : InstAlias<"fabs.h $rd, $rs", (FSGNJX_H_INX GPRF16Op:$rd, GPRF16Op:$rs, GPRF16Op:$rs)>;
+def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H_INX GPRF16Op:$rd, GPRF16Op:$rs, GPRF16Op:$rs)>;
+
+// fgt.h/fge.h are recognised by the GNU assembler but the canonical
+// flt.h/fle.h forms will always be printed. Therefore, set a zero weight.
+def : InstAlias<"fgt.h $rd, $rs, $rt",
+                (FLT_H_INX GPROp:$rd, GPRF16Op:$rt, GPRF16Op:$rs), 0>;
+def : InstAlias<"fge.h $rd, $rs, $rt",
+                (FLE_H_INX GPROp:$rd, GPRF16Op:$rt, GPRF16Op:$rs), 0>;
+} // Predicates = [HasStdExtZhinx]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

 def sub_vrm1_1 : SubRegIndex<64, 64>;
 def sub_vrm1_2 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_0>;
 def sub_vrm1_3 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_1>;
 def sub_vrm1_4 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_0>;
 def sub_vrm1_5 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_1>;
 def sub_vrm1_6 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_0>;
 def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>;
 
+def sub_32_hi  : SubRegIndex<32, 32>;
 } // Namespace = "RISCV"
 
 // Integer registers
 // CostPerUse is set higher for registers that may not be compressible as they
 // are not part of GPRC, the most restrictive register class used by the
 // compressed instruction set. This will influence the greedy register
 // allocator to reduce the use of registers that can't be encoded in 16 bit
 // instructions. This affects register allocation even when compressed
let RegAltNameIndices = [ABIRegAltName] in {
   def X29 : RISCVReg<29,"x29", ["t4"]>, DwarfRegNum<[29]>;
   def X30 : RISCVReg<30,"x30", ["t5"]>, DwarfRegNum<[30]>;
   def X31 : RISCVReg<31,"x31", ["t6"]>, DwarfRegNum<[31]>;
   }
 }
 
 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
                                [i32,  i64]>;
 def XLenRI : RegInfoByHwMode<
       [RV32,              RV64],
       [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
 
 // The order of registers represents the preferred allocation sequence.
 // Registers are listed in the order caller-save, callee-save, specials.
 def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add
     (sequence "X%u", 10, 17),
     (sequence "X%u", 5, 7),
     (sequence "X%u", 28, 31),
     (sequence "X%u", 8, 9),
     (sequence "X%u", 18, 27),
     (sequence "X%u", 0, 4)
   )> {
   let RegInfos = XLenRI;
 }
 
 def GPRX0 : RegisterClass<"RISCV", [XLenVT], 32, (add X0)> {
   let RegInfos = XLenRI;
 }
 
 // The order of registers represents the preferred allocation sequence.
 // Registers are listed in the order caller-save, callee-save, specials.
 def GPRNoX0 : RegisterClass<"RISCV", [XLenVT], 32, (add

 
 defvar VMaskVTs = [vbool64_t, vbool32_t, vbool16_t, vbool8_t,
                    vbool4_t, vbool2_t, vbool1_t];
 
 def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> {
   let Size = 64;
 }
 
+let RegAltNameIndices = [ABIRegAltName] in {
+  foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,
+                   24, 26, 28, 30] in {
+    defvar Reg = !cast<Register>("X"#Index);
+    def X#Index#_PD : RISCVRegWithSubRegs<Index, Reg.AsmName,
+                       [!cast<Register>("X"#Index),
+                        !cast<Register>("X"#!add(Index, 1))],
+                       Reg.AltNames> {
+      let SubRegIndices = [sub_32, sub_32_hi];
+    }
+  }
+}
+
+def GPRF16 : RegisterClass<"RISCV", [f16], 16, (add
+    (sequence "X%u", 10, 17),
+    (sequence "X%u", 5, 7),
+    (sequence "X%u", 28, 31),
+    (sequence "X%u", 8, 9),
+    (sequence "X%u", 18, 27),
+    (sequence "X%u", 0, 4)
+)>;
+
+def GPRF32 : RegisterClass<"RISCV", [f32], 32, (add
+    (sequence "X%u", 10, 17),
+    (sequence "X%u", 5, 7),
+    (sequence "X%u", 28, 31),
+    (sequence "X%u", 8, 9),
+    (sequence "X%u", 18, 27),
+    (sequence "X%u", 0, 4)
+)>;
+
+def GPRF64 : RegisterClass<"RISCV", [f64], 64, (add
+    (sequence "X%u", 10, 17),
+    (sequence "X%u", 5, 7),
+    (sequence "X%u", 28, 31),
+    (sequence "X%u", 8, 9),
+    (sequence "X%u", 18, 27),
+    (sequence "X%u", 0, 4)
+)>;
+
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
+    X10_PD, X12_PD, X14_PD, X16_PD,
+    X6_PD,
+    X28_PD, X30_PD,
+    X8_PD,
+    X18_PD, X20_PD, X22_PD, X24_PD, X26_PD,
+    X0_PD, X2_PD, X4_PD
+)>;
+
 // The register class is added for inline assembly for vector mask types.
 def VM : VReg<[vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t,
                vbool32_t, vbool64_t],
            (add (sequence "V%u", 25, 31),
                 (sequence "V%u", 8, 24),
                 (sequence "V%u", 0, 7)), 1>;
 
 foreach m = LMULList.m in {

 // NOTE: The alignment and size are bogus values. The Size needs to be non-zero
 // or tablegen will use "untyped" to determine the size which will assert.
 let isAllocatable = 0 in
 def AnyReg : RegisterClass<"RISCV", [untyped], 32,
                            (add (sequence "X%u", 0, 31),
                                 (sequence "F%u_D", 0, 31),
                                 (sequence "V%u", 0, 31))> {
   let Size = 32;
 }

llvm/lib/Target/RISCV/RISCVSubtarget.h

class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasStdExtZbr = false;
   bool HasStdExtZbs = false;
   bool HasStdExtZbt = false;
   bool HasStdExtZbproposedc = false;
   bool HasStdExtV = false;
   bool HasStdExtZvlsseg = false;
   bool HasStdExtZvamo = false;
   bool HasStdExtZfh = false;
+  bool HasStdExtZfinx = false;
+  bool HasStdExtZdinx = false;
+  bool HasStdExtZhinx = false;
+  bool HasStdExtZhinxmin = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
   bool EnableSaveRestore = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
   uint8_t MaxInterleaveFactor = 2;
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
   BitVector UserReservedRegister;
   RISCVFrameLowering FrameLowering;
   RISCVInstrInfo InstrInfo;
   RISCVRegisterInfo RegInfo;
   RISCVTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
 
public:
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 
   const RISCVFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
   const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const RISCVRegisterInfo *getRegisterInfo() const override {
     return &RegInfo;
   }
   const RISCVTargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
   bool enableMachineScheduler() const override { return true; }
   bool hasStdExtM() const { return HasStdExtM; }
public:
   bool hasStdExtZbr() const { return HasStdExtZbr; }
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
+  bool hasStdExtZfinx() const { return HasStdExtZfinx; }
+  bool hasStdExtZdinx() const { return HasStdExtZdinx; }
+  bool hasStdExtZhinx() const { return HasStdExtZhinx; }
+  bool hasStdExtZhinxmin() const { return HasStdExtZhinxmin; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
   bool enableSaveRestore() const { return EnableSaveRestore; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
   RISCVABI::ABI getTargetABI() const { return TargetABI; }
public:
   // of 0 means nothing is known about that particular limit beyond what's
   // implied by the architecture.
   unsigned getMaxRVVVectorSizeInBits() const;
   unsigned getMinRVVVectorSizeInBits() const;
   unsigned getMaxLMULForFixedLengthVectors() const;
   unsigned getMaxELENForFixedLengthVectors() const;
   bool useRVVForFixedLengthVectors() const;
 };
 } // End llvm namespace
 
 #endif

llvm/test/MC/RISCV/rv32i-invalid.s

 # RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
 
 # Out of range immediates
 ## fencearg
 fence iorw, iore # CHECK: :[[@LINE]]:13: error: operand must be formed of letters selected in-order from 'iorw'
 fence wr, wr # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw'
 fence rw, rr # CHECK: :[[@LINE]]:11: error: operand must be formed of letters selected in-order from 'iorw'
 fence 1, rw # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw'
 fence unknown, unknown # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw'

 jal gp, %lo(a) # CHECK: :[[@LINE]]:9: error: immediate must be a multiple of 2 bytes in the range [-1048576, 1048574]
 jal gp, %hi(2) # CHECK: :[[@LINE]]:9: error: immediate must be a multiple of 2 bytes in the range [-1048576, 1048574]
 jal gp, %hi(b) # CHECK: :[[@LINE]]:9: error: immediate must be a multiple of 2 bytes in the range [-1048576, 1048574]
 jal gp, %pcrel_hi(3) # CHECK: :[[@LINE]]:9: error: immediate must be a multiple of 2 bytes in the range [-1048576, 1048574]
 jal gp, %pcrel_hi(c) # CHECK: :[[@LINE]]:9: error: immediate must be a multiple of 2 bytes in the range [-1048576, 1048574]
 jal gp, %pcrel_lo(4) # CHECK: :[[@LINE]]:9: error: immediate must be a multiple of 2 bytes in the range [-1048576, 1048574]
 jal gp, %pcrel_lo(d) # CHECK: :[[@LINE]]:9: error: immediate must be a multiple of 2 bytes in the range [-1048576, 1048574]
 
-# Bare symbol names when an operand modifier is required and unsupported 
+# Bare symbol names when an operand modifier is required and unsupported
 # operand modifiers.
 
 lui a0, foo # CHECK: :[[@LINE]]:9: error: operand must be a symbol with %hi/%tprel_hi modifier or an integer in the range [0, 1048575]
 lui a0, %lo(foo) # CHECK: :[[@LINE]]:9: error: operand must be a symbol with %hi/%tprel_hi modifier or an integer in the range [0, 1048575]
 lui a0, %pcrel_lo(foo) # CHECK: :[[@LINE]]:9: error: operand must be a symbol with %hi/%tprel_hi modifier or an integer in the range [0, 1048575]
 lui a0, %pcrel_hi(foo) # CHECK: :[[@LINE]]:9: error: operand must be a symbol with %hi/%tprel_hi modifier or an integer in the range [0, 1048575]
 
 auipc a0, foo # CHECK: :[[@LINE]]:11: error: operand must be a symbol with a %pcrel_hi/%got_pcrel_hi/%tls_ie_pcrel_hi/%tls_gd_pcrel_hi modifier or an integer in the range [0, 1048575]

 ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 
 # Instruction not in the base ISA
 mul a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'M' (Integer Multiplication and Division)
 amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions)
 fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
 fadd.h ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point)
+fadd.h a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer)
+fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer)
+fadd.d a0, a0, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer)
 
 # Using floating point registers when integer registers are expected
 addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 
 # fence.tso accepts no operands
 fence.tso rw, rw # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

llvm/test/MC/RISCV/rv32zdinx-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zdinx < %s 2>&1 | FileCheck %s
+
+# Invalid instructions
+flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+fmv.x.w s0, s1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+
+# Invalid register names
+lw f15, 100(a0) # CHECK: :[[@LINE]]:4: error: invalid operand for instruction
+lw t1, 100(a10) # CHECK: :[[@LINE]]:12: error: expected register
+fadd.d a100, a2, a3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction

llvm/test/MC/RISCV/rv32zdinx-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zdinx -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zdinx < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zdinx -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zdinx -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zdinx < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zdinx -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: lw s0, 12(a0)
+# CHECK-ASM: encoding: [0x03,0x24,0xc5,0x00]
+lw s0, 12(a0)
+# CHECK-ASM-AND-OBJ: lw s1, 4(ra)
+# CHECK-ASM: encoding: [0x83,0xa4,0x40,0x00]
+lw s1, +4(ra)
+# CHECK-ASM-AND-OBJ: lw s2, -2048(a3)
+# CHECK-ASM: encoding: [0x03,0xa9,0x06,0x80]
+lw s2, -2048(x13)
+# CHECK-ASM-AND-OBJ: lw s3, -2048(s1)
+# CHECK-ASM: encoding: [0x83,0xa9,0x04,0x80]
+lw s3, %lo(2048)(s1)
+# CHECK-ASM-AND-OBJ: lw s4, 2047(s2)
+# CHECK-ASM: encoding: [0x03,0x2a,0xf9,0x7f]
+lw s4, 2047(s2)
+# CHECK-ASM-AND-OBJ: lw s5, 0(s3)
+# CHECK-ASM: encoding: [0x83,0xaa,0x09,0x00]
+lw s5, 0(s3)
+
+# CHECK-ASM-AND-OBJ: sw s6, 2047(s4)
+# CHECK-ASM: encoding: [0xa3,0x2f,0x6a,0x7f]
+sw s6, 2047(s4)
+# CHECK-ASM-AND-OBJ: sw s7, -2048(s5)
+# CHECK-ASM: encoding: [0x23,0xa0,0x7a,0x81]
+sw s7, -2048(s5)
+# CHECK-ASM-AND-OBJ: sw s8, -2048(s6)
+# CHECK-ASM: encoding: [0x23,0x20,0x8b,0x81]
+sw s8, %lo(2048)(s6)
+# CHECK-ASM-AND-OBJ: sw s9, 999(s7)
+# CHECK-ASM: encoding: [0xa3,0xa3,0x9b,0x3f]
+sw s9, 999(s7)
+
+# CHECK-ASM-AND-OBJ: fmadd.d a0, a2, a4, a6, dyn
+# CHECK-ASM: encoding: [0x43,0x75,0xe6,0x82]
+fmadd.d x10, x12, x14, x16, dyn
+# CHECK-ASM-AND-OBJ: fmsub.d a0, a2, a4, a6, dyn
+# CHECK-ASM: encoding: [0x47,0x75,0xe6,0x82]
+fmsub.d x10, x12, x14, x16, dyn
+# CHECK-ASM-AND-OBJ: fnmsub.d a0, a2, a4, a6, dyn
+# CHECK-ASM: encoding: [0x4b,0x75,0xe6,0x82]
+fnmsub.d x10, x12, x14, x16, dyn
+# CHECK-ASM-AND-OBJ: fnmadd.d a0, a2, a4, a6, dyn
+# CHECK-ASM: encoding: [0x4f,0x75,0xe6,0x82]
+fnmadd.d x10, x12, x14, x16, dyn
+
+# CHECK-ASM-AND-OBJ: fadd.d s10, t3, t5, dyn
+# CHECK-ASM: encoding: [0x53,0x7d,0xee,0x03]
+fadd.d x26, x28, x30, dyn
+# CHECK-ASM-AND-OBJ: fsub.d s10, t3, t5, dyn
+# CHECK-ASM: encoding: [0x53,0x7d,0xee,0x0b]
+fsub.d x26, x28, x30, dyn
+# CHECK-ASM-AND-OBJ: fmul.d s10, t3, t5, dyn
+# CHECK-ASM: encoding: [0x53,0x7d,0xee,0x13]
+fmul.d x26, x28, x30, dyn
+# CHECK-ASM-AND-OBJ: fdiv.d s10, t3, t5, dyn
+# CHECK-ASM: encoding: [0x53,0x7d,0xee,0x1b]
+fdiv.d x26, x28, x30, dyn
+# CHECK-ASM-AND-OBJ: fsqrt.d s4, s6, dyn
+# CHECK-ASM: encoding: [0x53,0x7a,0x0b,0x5a]
+fsqrt.d x20, x22, dyn
+# CHECK-ASM-AND-OBJ: fsgnj.d s10, t3, t5
+# CHECK-ASM: encoding: [0x53,0x0d,0xee,0x23]
+fsgnj.d x26, x28, x30
+# CHECK-ASM-AND-OBJ: fsgnjn.d s10, t3, t5
+# CHECK-ASM: encoding: [0x53,0x1d,0xee,0x23]
+fsgnjn.d x26, x28, x30
+# CHECK-ASM-AND-OBJ: fsgnjx.d s10, t3, t5
+# CHECK-ASM: encoding: [0x53,0x2d,0xee,0x23]
+fsgnjx.d x26, x28, x30
+# CHECK-ASM-AND-OBJ: fmin.d s10, t3, t5
+# CHECK-ASM: encoding: [0x53,0x0d,0xee,0x2b]
+fmin.d x26, x28, x30
+# CHECK-ASM-AND-OBJ: fmax.d s10, t3, t5
+# CHECK-ASM: encoding: [0x53,0x1d,0xee,0x2b]
+fmax.d x26, x28, x30
+
+# CHECK-ASM-AND-OBJ: fcvt.s.d s10, t3, dyn
+# CHECK-ASM: encoding: [0x53,0x7d,0x1e,0x40]
+fcvt.s.d x26, x28, dyn
+# CHECK-ASM-AND-OBJ: fcvt.d.s s10, t3
+# CHECK-ASM: encoding: [0x53,0x0d,0x0e,0x42]
+fcvt.d.s x26, x28
+# CHECK-ASM-AND-OBJ: feq.d s10, t3, t5
+# CHECK-ASM: encoding: [0x53,0x2d,0xee,0xa3]
+feq.d x26, x28, x30
+# CHECK-ASM-AND-OBJ: flt.d s10, t3, t5
+# CHECK-ASM: encoding: [0x53,0x1d,0xee,0xa3]
+flt.d x26, x28, x30
+# CHECK-ASM-AND-OBJ: fle.d s10, t3, t5
+# CHECK-ASM: encoding: [0x53,0x0d,0xee,0xa3]
+fle.d x26, x28, x30
+# CHECK-ASM-AND-OBJ: fclass.d s10, t3
+# CHECK-ASM: encoding: [0x53,0x1d,0x0e,0xe2]
+fclass.d x26, x28
+
+# CHECK-ASM-AND-OBJ: fcvt.w.d s4, s6, dyn
+# CHECK-ASM: encoding: [0x53,0x7a,0x0b,0xc2]
+fcvt.w.d x20, x22, dyn
+# CHECK-ASM-AND-OBJ: fcvt.d.w s10, t3
+# CHECK-ASM: encoding: [0x53,0x0d,0x0e,0xd2]
+fcvt.d.w x26, x28
+# CHECK-ASM-AND-OBJ: fcvt.d.wu s10, t3
+# CHECK-ASM: encoding: [0x53,0x0d,0x1e,0xd2]
+fcvt.d.wu x26, x28
+
+# Rounding modes
+
+# CHECK-ASM-AND-OBJ: fmadd.d a0, a2, a4, a6, rne
+# CHECK-ASM: encoding: [0x43,0x05,0xe6,0x82]
+fmadd.d x10, x12, x14, x16, rne
+# CHECK-ASM-AND-OBJ: fmsub.d a0, a2, a4, a6, rtz
+# CHECK-ASM: encoding: [0x47,0x15,0xe6,0x82]
+fmsub.d x10, x12, x14, x16, rtz
+# CHECK-ASM-AND-OBJ: fnmsub.d a0, a2, a4, a6, rdn
+# CHECK-ASM: encoding: [0x4b,0x25,0xe6,0x82]
+fnmsub.d x10, x12, x14, x16, rdn
+# CHECK-ASM-AND-OBJ: fnmadd.d a0, a2, a4, a6, rup
+# CHECK-ASM: encoding: [0x4f,0x35,0xe6,0x82]
+fnmadd.d x10, x12, x14, x16, rup
+
+# CHECK-ASM-AND-OBJ: fadd.d s10, t3, t5, rmm
+# CHECK-ASM: encoding: [0x53,0x4d,0xee,0x03]
+fadd.d x26, x28, x30, rmm
+# CHECK-ASM-AND-OBJ: fsub.d s10, t3, t5, dyn
+# CHECK-ASM: encoding: [0x53,0x7d,0xee,0x0b]
+fsub.d x26, x28, x30, dyn
+# CHECK-ASM-AND-OBJ: fmul.d s10, t3, t5, rne
+# CHECK-ASM: encoding: [0x53,0x0d,0xee,0x13]
+fmul.d x26, x28, x30, rne
+# CHECK-ASM-AND-OBJ: fdiv.d s10, t3, t5, rtz
+# CHECK-ASM: encoding: [0x53,0x1d,0xee,0x1b]
+fdiv.d x26, x28, x30, rtz
+
+# CHECK-ASM-AND-OBJ: fsqrt.d s4, s6, rdn
+# CHECK-ASM: encoding: [0x53,0x2a,0x0b,0x5a]
+fsqrt.d x20, x22, rdn
+# CHECK-ASM-AND-OBJ: fcvt.s.d s4, s6, rup
+# CHECK-ASM: encoding: [0x53,0x3a,0x1b,0x40]
+fcvt.s.d x20, x22, rup
+# CHECK-ASM-AND-OBJ: fcvt.w.d s4, s6, rmm
+# CHECK-ASM: encoding: [0x53,0x4a,0x0b,0xc2]
+fcvt.w.d x20, x22, rmm
+# CHECK-ASM-AND-OBJ: fcvt.wu.d s4, s6, dyn
+# CHECK-ASM: encoding: [0x53,0x7a,0x1b,0xc2]
+fcvt.wu.d x20, x22, dyn

llvm/test/MC/RISCV/rv32zfinx-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfinx < %s 2>&1 | FileCheck %s
+
+# Invalid instructions
+flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+fmv.x.d s0, s1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+fadd.d t1, t3, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer)
+
+# Invalid register names
+lw f15, 100(a0) # CHECK: :[[@LINE]]:4: error: invalid operand for instruction
+lw t1, 100(a10) # CHECK: :[[@LINE]]:12: error: expected register
+fadd.s a100, a2, a3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction

llvm/test/MC/RISCV/rv32zfinx-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfinx -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfinx -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfinx < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zfinx -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfinx < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zfinx -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: lw s0, 12(a0)
+# CHECK-ASM: encoding: [0x03,0x24,0xc5,0x00]
+lw s0, 12(a0)
+# CHECK-ASM-AND-OBJ: lw s1, 4(ra)
+# CHECK-ASM: encoding: [0x83,0xa4,0x40,0x00]
+lw s1, +4(ra)
+# CHECK-ASM-AND-OBJ: lw s2, -2048(a3)
+# CHECK-ASM: encoding: [0x03,0xa9,0x06,0x80]
+lw s2, -2048(x13)
+# CHECK-ASM-AND-OBJ: lw s3, -2048(s1)
+# CHECK-ASM: encoding: [0x83,0xa9,0x04,0x80]
+lw s3, %lo(2048)(s1)
+# CHECK-ASM-AND-OBJ: lw s4, 2047(s2)
+# CHECK-ASM: encoding: [0x03,0x2a,0xf9,0x7f]
+lw s4, 2047(s2)
+# CHECK-ASM-AND-OBJ: lw s5, 0(s3)
+# CHECK-ASM: encoding: [0x83,0xaa,0x09,0x00]
+lw s5, 0(s3)
+
+# CHECK-ASM-AND-OBJ: sw s6, 2047(s4)
+# CHECK-ASM: encoding: [0xa3,0x2f,0x6a,0x7f]
+sw s6, 2047(s4)
+# CHECK-ASM-AND-OBJ: sw s7, -2048(s5)
+# CHECK-ASM: encoding: [0x23,0xa0,0x7a,0x81]
+sw s7, -2048(s5)
+# CHECK-ASM-AND-OBJ: sw s8, -2048(s6)
+# CHECK-ASM: encoding: [0x23,0x20,0x8b,0x81]
+sw s8, %lo(2048)(s6)
+# CHECK-ASM-AND-OBJ: sw s9, 999(s7)
+# CHECK-ASM: encoding: [0xa3,0xa3,0x9b,0x3f]
+sw s9, 999(s7)
+
+# CHECK-ASM-AND-OBJ: fmadd.s a0, a1, a2, a3, dyn
+# CHECK-ASM: encoding: [0x43,0xf5,0xc5,0x68]
+fmadd.s x10, x11, x12, x13, dyn
+# CHECK-ASM-AND-OBJ: fmsub.s a4, a5, a6, a7, dyn
+# CHECK-ASM: encoding: [0x47,0xf7,0x07,0x89]
+fmsub.s x14, x15, x16, x17, dyn
+# CHECK-ASM-AND-OBJ: fnmsub.s s2, s3, s4, s5, dyn
+# CHECK-ASM: encoding: [0x4b,0xf9,0x49,0xa9]
+fnmsub.s x18, x19, x20, x21, dyn
+# CHECK-ASM-AND-OBJ: fnmadd.s s6, s7, s8, s9, dyn
+# CHECK-ASM: encoding: [0x4f,0xfb,0x8b,0xc9]
+fnmadd.s x22, x23, x24, x25, dyn
+
+# CHECK-ASM-AND-OBJ: fadd.s s10, s11, t3, dyn
+# CHECK-ASM: encoding: [0x53,0xfd,0xcd,0x01]
+fadd.s x26, x27, x28, dyn
+# CHECK-ASM-AND-OBJ: fsub.s t4, t5, t6, dyn
+# CHECK-ASM: encoding: [0xd3,0x7e,0xff,0x09]
+fsub.s x29, x30, x31, dyn
+# CHECK-ASM-AND-OBJ: fmul.s s0, s1, s2, dyn
+# CHECK-ASM: encoding: [0x53,0xf4,0x24,0x11]
+fmul.s s0, s1, s2, dyn
+# CHECK-ASM-AND-OBJ: fdiv.s s3, s4, s5, dyn
+# CHECK-ASM: encoding: [0xd3,0x79,0x5a,0x19]
+fdiv.s s3, s4, s5, dyn
+# CHECK-ASM-AND-OBJ: fsqrt.s t1, t2, dyn
+# CHECK-ASM: encoding: [0x53,0xf3,0x03,0x58]
+fsqrt.s t1, t2, dyn
+# CHECK-ASM-AND-OBJ: fsgnj.s s1, a0, a1
+# CHECK-ASM: encoding: [0xd3,0x04,0xb5,0x20]
+fsgnj.s s1, a0, a1
+# CHECK-ASM-AND-OBJ: fsgnjn.s a1, a3, a4
+# CHECK-ASM: encoding: [0xd3,0x95,0xe6,0x20]
+fsgnjn.s a1, a3, a4
+# CHECK-ASM-AND-OBJ: fsgnjx.s a4, a3, a2
+# CHECK-ASM: encoding: [0x53,0xa7,0xc6,0x20]
+fsgnjx.s a4, a3, a2
+# CHECK-ASM-AND-OBJ: fmin.s a5, a6, a7
+# CHECK-ASM: encoding: [0xd3,0x07,0x18,0x29]
+fmin.s a5, a6, a7
+# CHECK-ASM-AND-OBJ: fmax.s s2, s3, s4
+# CHECK-ASM: encoding: [0x53,0x99,0x49,0x29]
+fmax.s s2, s3, s4
+# CHECK-ASM-AND-OBJ: fcvt.w.s a0, s5, dyn
+# CHECK-ASM: encoding: [0x53,0xf5,0x0a,0xc0]
+fcvt.w.s a0, s5, dyn
+# CHECK-ASM-AND-OBJ: fcvt.wu.s a1, s6, dyn
+# CHECK-ASM: encoding: [0xd3,0x75,0x1b,0xc0]
+fcvt.wu.s a1, s6, dyn
+# CHECK-ASM-AND-OBJ: feq.s a1, s8, s9
+# CHECK-ASM: encoding: [0xd3,0x25,0x9c,0xa1]
+feq.s a1, s8, s9
+# CHECK-ASM-AND-OBJ: flt.s a2, s10, s11
+# CHECK-ASM: encoding: [0x53,0x16,0xbd,0xa1]
+flt.s a2, s10, s11
+# CHECK-ASM-AND-OBJ: fle.s a3, t3, t4
+# CHECK-ASM: encoding: [0xd3,0x06,0xde,0xa1]
+fle.s a3, t3, t4
+# CHECK-ASM-AND-OBJ: fclass.s a3, t5
+# CHECK-ASM: encoding: [0xd3,0x16,0x0f,0xe0]
+fclass.s a3, t5
+# CHECK-ASM-AND-OBJ: fcvt.s.w t6, a4, dyn
+# CHECK-ASM: encoding: [0xd3,0x7f,0x07,0xd0]
+fcvt.s.w t6, a4, dyn
+# CHECK-ASM-AND-OBJ: fcvt.s.wu s0, a5, dyn
+# CHECK-ASM: encoding: [0x53,0xf4,0x17,0xd0]
+fcvt.s.wu s0, a5, dyn
+
+# Rounding modes
+
+# CHECK-ASM-AND-OBJ: fmadd.s a0, a1, a2, a3, rne
+# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x68]
+fmadd.s x10, x11, x12, x13, rne
+# CHECK-ASM-AND-OBJ: fmsub.s a4, a5, a6, a7, rtz
+# CHECK-ASM: encoding: [0x47,0x97,0x07,0x89]
+fmsub.s x14, x15, x16, x17, rtz
+# CHECK-ASM-AND-OBJ: fnmsub.s s2, s3, s4, s5, rdn
+# CHECK-ASM: encoding: [0x4b,0xa9,0x49,0xa9]
+fnmsub.s x18, x19, x20, x21, rdn
+# CHECK-ASM-AND-OBJ: fnmadd.s s6, s7, s8, s9, rup
+# CHECK-ASM: encoding: [0x4f,0xbb,0x8b,0xc9]
+fnmadd.s x22, x23, x24, x25, rup
+# CHECK-ASM-AND-OBJ: fmadd.s a0, a1, a2, a3, rmm
+# CHECK-ASM: encoding: [0x43,0xc5,0xc5,0x68]
+fmadd.s x10, x11, x12, x13, rmm
+# CHECK-ASM-AND-OBJ: fmsub.s a4, a5, a6, a7
+# CHECK-ASM: encoding: [0x47,0xf7,0x07,0x89]
+fmsub.s x14, x15, x16, x17, dyn
+
+# CHECK-ASM-AND-OBJ: fadd.s s10, s11, t3, rne
+# CHECK-ASM: encoding: [0x53,0x8d,0xcd,0x01]
+fadd.s x26, x27, x28, rne
+# CHECK-ASM-AND-OBJ: fsub.s t4, t5, t6, rtz
+# CHECK-ASM: encoding: [0xd3,0x1e,0xff,0x09]
+fsub.s x29, x30, x31, rtz
+# CHECK-ASM-AND-OBJ: fmul.s s0, s1, s2, rdn
+# CHECK-ASM: encoding: [0x53,0xa4,0x24,0x11]
+fmul.s s0, s1, s2, rdn
+# CHECK-ASM-AND-OBJ: fdiv.s s3, s4, s5, rup
+# CHECK-ASM: encoding: [0xd3,0x39,0x5a,0x19]
+fdiv.s s3, s4, s5, rup
+
+# CHECK-ASM-AND-OBJ: fsqrt.s t1, t2, rmm
+# CHECK-ASM: encoding: [0x53,0xc3,0x03,0x58]
+fsqrt.s t1, t2, rmm
+# CHECK-ASM-AND-OBJ: fcvt.w.s a0, s5, rup
+# CHECK-ASM: encoding: [0x53,0xb5,0x0a,0xc0]
+fcvt.w.s a0, s5, rup
+# CHECK-ASM-AND-OBJ: fcvt.wu.s a1, s6, rdn
+# CHECK-ASM: encoding: [0xd3,0x25,0x1b,0xc0]
+fcvt.wu.s a1, s6, rdn
+# CHECK-ASM-AND-OBJ: fcvt.s.w t6, a4, rtz
+# CHECK-ASM: encoding: [0xd3,0x1f,0x07,0xd0]
+fcvt.s.w t6, a4, rtz
+# CHECK-ASM-AND-OBJ: fcvt.s.wu s0, a5, rne
+# CHECK-ASM: encoding: [0x53,0x84,0x17,0xd0]
+fcvt.s.wu s0, a5, rne

llvm/test/MC/RISCV/rv32zhinx-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zhinx < %s 2>&1 | FileCheck %s
+
+# Invalid instructions
+flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+fmv.x.h s0, s1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+
+# Invalid register names
+lw f15, 100(a0) # CHECK: :[[@LINE]]:4: error: invalid operand for instruction
+lw t1, 100(a10) # CHECK: :[[@LINE]]:12: error: expected register
+fadd.h a100, a2, a3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction

llvm/test/MC/RISCV/rv32zhinx-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zhinx < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zhinx -M no-aliases -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zhinx < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zhinx -M no-aliases -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: lh s0, 12(a0)
+# CHECK-ASM: encoding: [0x03,0x14,0xc5,0x00]
+lh s0, 12(a0)
+# CHECK-ASM-AND-OBJ: lh s1, 4(ra)
+# CHECK-ASM: encoding: [0x83,0x94,0x40,0x00]
+lh s1, +4(ra)
+# CHECK-ASM-AND-OBJ: lh s2, -2048(a3)
+# CHECK-ASM: encoding: [0x03,0x99,0x06,0x80]
+lh s2, -2048(x13)
+# CHECK-ASM-AND-OBJ: lh s3, -2048(s1)
+# CHECK-ASM: encoding: [0x83,0x99,0x04,0x80]
+lh s3, %lo(2048)(s1)
+# CHECK-ASM-AND-OBJ: lh s4, 2047(s2)
+# CHECK-ASM: encoding: [0x03,0x1a,0xf9,0x7f]
+lh s4, 2047(s2)
+# CHECK-ASM-AND-OBJ: lh s5, 0(s3)
+# CHECK-ASM: encoding: [0x83,0x9a,0x09,0x00]
+lh s5, 0(s3)
+
+# CHECK-ASM-AND-OBJ: sh s6, 2047(s4)
+# CHECK-ASM: encoding: [0xa3,0x1f,0x6a,0x7f]
+sh s6, 2047(s4)
+# CHECK-ASM-AND-OBJ: sh s7, -2048(s5)
+# CHECK-ASM: encoding: [0x23,0x90,0x7a,0x81]
+sh s7, -2048(s5)
+# CHECK-ASM-AND-OBJ: sh s0, -2048(s6)
+# CHECK-ASM: encoding: [0x23,0x10,0x8b,0x80]
+sh x8, %lo(2048)(s6)
+# CHECK-ASM-AND-OBJ: sh s1, 999(s7)
+# CHECK-ASM: encoding: [0xa3,0x93,0x9b,0x3e]
+sh x9, 999(s7)
+
+# CHECK-ASM-AND-OBJ: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ASM: encoding: [0x43,0xf5,0xc5,0x6c]
+fmadd.h x10, x11, x12, x13, dyn
+# CHECK-ASM-AND-OBJ: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ASM: encoding: [0x47,0xf7,0x07,0x8d]
+fmsub.h x14, x15, x16, x17, dyn
+# CHECK-ASM-AND-OBJ: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ASM: encoding: [0x4b,0xf9,0x49,0xad]
+fnmsub.h x18, x19, x20, x21, dyn
+# CHECK-ASM-AND-OBJ: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ASM: encoding: [0x4f,0xfb,0x8b,0xcd]
+fnmadd.h x22, x23, x24, x25, dyn
+
+# CHECK-ASM-AND-OBJ: fadd.h s10, s11, t3, dyn
+# CHECK-ASM: encoding: [0x53,0xfd,0xcd,0x05]
+fadd.h x26, x27, x28, dyn
+# CHECK-ASM-AND-OBJ: fsub.h t4, t5, t6, dyn
+# CHECK-ASM: encoding: [0xd3,0x7e,0xff,0x0d]
+fsub.h x29, x30, x31, dyn
+# CHECK-ASM-AND-OBJ: fmul.h s0, s1, s2, dyn
+# CHECK-ASM: encoding: [0x53,0xf4,0x24,0x15]
+fmul.h s0, s1, s2, dyn
+# CHECK-ASM-AND-OBJ: fdiv.h s3, s4, s5, dyn
+# CHECK-ASM: encoding: [0xd3,0x79,0x5a,0x1d]
+fdiv.h s3, s4, s5, dyn
+# CHECK-ASM-AND-OBJ: fsqrt.h s6, s7, dyn
+# CHECK-ASM: encoding: [0x53,0xfb,0x0b,0x5c]
+fsqrt.h s6, s7, dyn
+# CHECK-ASM-AND-OBJ: fsgnj.h s1, a0, a1
+# CHECK-ASM: encoding: [0xd3,0x04,0xb5,0x24]
+fsgnj.h x9, x10, x11
+# CHECK-ASM-AND-OBJ: fsgnjn.h a1, a3, a4
+# CHECK-ASM: encoding: [0xd3,0x95,0xe6,0x24]
+fsgnjn.h x11, x13, x14
+# CHECK-ASM-AND-OBJ: fsgnjx.h a4, a3, a2
+# CHECK-ASM: encoding: [0x53,0xa7,0xc6,0x24]
+fsgnjx.h x14, x13, x12
+# CHECK-ASM-AND-OBJ: fmin.h a5, a6, a7
+# CHECK-ASM: encoding: [0xd3,0x07,0x18,0x2d]
+fmin.h x15, x16, x17
+# CHECK-ASM-AND-OBJ: fmax.h s2, s3, s4
+# CHECK-ASM: encoding: [0x53,0x99,0x49,0x2d]
+fmax.h x18, x19, x20
+# CHECK-ASM-AND-OBJ: fcvt.w.h a0, s5, dyn
+# CHECK-ASM: encoding: [0x53,0xf5,0x0a,0xc4]
+fcvt.w.h x10, x21, dyn
+# CHECK-ASM-AND-OBJ: fcvt.wu.h a1, s6, dyn
+# CHECK-ASM: encoding: [0xd3,0x75,0x1b,0xc4]
+fcvt.wu.h x11, x22, dyn
+# CHECK-ASM-AND-OBJ: feq.h a1, s8, s9
+# CHECK-ASM: encoding: [0xd3,0x25,0x9c,0xa5]
+feq.h x11, x24, x25
+# CHECK-ASM-AND-OBJ: flt.h a2, s10, s11
+# CHECK-ASM: encoding: [0x53,0x16,0xbd,0xa5]
+flt.h x12, x26, x27
+# CHECK-ASM-AND-OBJ: fle.h a3, t3, t4
+# CHECK-ASM: encoding: [0xd3,0x06,0xde,0xa5]
+fle.h x13, x28, x29
+# CHECK-ASM-AND-OBJ: fclass.h a3, t5
+# CHECK-ASM: encoding: [0xd3,0x16,0x0f,0xe4]
+fclass.h x13, x30
+# CHECK-ASM-AND-OBJ: fcvt.h.w t6, a4, dyn
+# CHECK-ASM: encoding: [0xd3,0x7f,0x07,0xd4]
+fcvt.h.w x31, x14, dyn
+# CHECK-ASM-AND-OBJ: fcvt.h.wu s0, a5, dyn
+# CHECK-ASM: encoding: [0x53,0xf4,0x17,0xd4]
+fcvt.h.wu s0, x15, dyn
+
+# Rounding modes
+
+# CHECK-ASM-AND-OBJ: fmadd.h a0, a1, a2, a3, rne
+# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x6c]
+fmadd.h x10, x11, x12, x13, rne
+# CHECK-ASM-AND-OBJ: fmsub.h a4, a5, a6, a7, rtz
+# CHECK-ASM: encoding: [0x47,0x97,0x07,0x8d]
+fmsub.h x14, x15, x16, x17, rtz
+# CHECK-ASM-AND-OBJ: fnmsub.h s2, s3, s4, s5, rdn
+# CHECK-ASM: encoding: [0x4b,0xa9,0x49,0xad]
+fnmsub.h x18, x19, x20, x21, rdn
+# CHECK-ASM-AND-OBJ: fnmadd.h s6, s7, s8, s9, rup
+# CHECK-ASM: encoding: [0x4f,0xbb,0x8b,0xcd]
+fnmadd.h x22, x23, x24, x25, rup
+# CHECK-ASM-AND-OBJ: fmadd.h a0, a1, a2, a3, rmm
+# CHECK-ASM: encoding: [0x43,0xc5,0xc5,0x6c]
+fmadd.h x10, x11, x12, x13, rmm
+# CHECK-ASM-AND-OBJ: fmsub.h a4, a5, a6, a7
+# CHECK-ASM: encoding: [0x47,0xf7,0x07,0x8d]
+fmsub.h x14, x15, x16, x17, dyn
+
+# CHECK-ASM-AND-OBJ: fadd.h s10, s11, t3, rne
+# CHECK-ASM: encoding: [0x53,0x8d,0xcd,0x05]
+fadd.h x26, x27, x28, rne
+# CHECK-ASM-AND-OBJ: fsub.h t4, t5, t6, rtz
+# CHECK-ASM: encoding: [0xd3,0x1e,0xff,0x0d]
+fsub.h x29, x30, x31, rtz
+# CHECK-ASM-AND-OBJ: fmul.h s0, s1, s2, rdn
+# CHECK-ASM: encoding: [0x53,0xa4,0x24,0x15]
+fmul.h s0, s1, s2, rdn
+# CHECK-ASM-AND-OBJ: fdiv.h s3, s4, s5, rup
+# CHECK-ASM: encoding: [0xd3,0x39,0x5a,0x1d]
+fdiv.h s3, s4, s5, rup
+
+# CHECK-ASM-AND-OBJ: fsqrt.h s6, s7, rmm
+# CHECK-ASM: encoding: [0x53,0xcb,0x0b,0x5c]
+fsqrt.h s6, s7, rmm
+# CHECK-ASM-AND-OBJ: fcvt.w.h a0, s5, rup
+# CHECK-ASM: encoding: [0x53,0xb5,0x0a,0xc4]
+fcvt.w.h x10, x21, rup
+# CHECK-ASM-AND-OBJ: fcvt.wu.h a1, s6, rdn
+# CHECK-ASM: encoding: [0xd3,0x25,0x1b,0xc4]
+fcvt.wu.h x11, x22, rdn
+# CHECK-ASM-AND-OBJ: fcvt.h.w t6, a4, rtz
+# CHECK-ASM: encoding: [0xd3,0x1f,0x07,0xd4]
+fcvt.h.w x31, x14, rtz
+# CHECK-ASM-AND-OBJ: fcvt.h.wu s0, a5, rne
+# CHECK-ASM: encoding: [0x53,0x84,0x17,0xd4]
+fcvt.h.wu s0, a5, rne

llvm/test/MC/RISCV/rv32zhinxmin-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zhinxmin < %s 2>&1 | FileCheck %s
+
+# Invalid instructions
+flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+fmv.x.h s0, s1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+
+# Invalid register names
+lw f15, 100(a0) # CHECK: :[[@LINE]]:4: error: invalid operand for instruction
+lw t1, 100(a10) # CHECK: :[[@LINE]]:12: error: expected register
+fadd.h a100, a2, a3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+
+# Valid in Zhinx
+fmadd.h x10, x11, x12, x13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer)

llvm/test/MC/RISCV/rv32zhinxmin-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinxmin -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinxmin -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zhinxmin < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zhinxmin -M no-aliases -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zhinxmin < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zhinxmin -M no-aliases -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: lh s0, 12(a0)
+# CHECK-ASM: encoding: [0x03,0x14,0xc5,0x00]
+lh s0, 12(a0)
+# CHECK-ASM-AND-OBJ: lh s1, 4(ra)
+# CHECK-ASM: encoding: [0x83,0x94,0x40,0x00]
+lh s1, +4(ra)
+# CHECK-ASM-AND-OBJ: lh s2, -2048(a3)
+# CHECK-ASM: encoding: [0x03,0x99,0x06,0x80]
+lh s2, -2048(x13)
+# CHECK-ASM-AND-OBJ: lh s3, -2048(s1)
+# CHECK-ASM: encoding: [0x83,0x99,0x04,0x80]
+lh s3, %lo(2048)(s1)
+# CHECK-ASM-AND-OBJ: lh s4, 2047(s2)
+# CHECK-ASM: encoding: [0x03,0x1a,0xf9,0x7f]
+lh s4, 2047(s2)
+# CHECK-ASM-AND-OBJ: lh s5, 0(s3)
+# CHECK-ASM: encoding: [0x83,0x9a,0x09,0x00]
+lh s5, 0(s3)
+
+# CHECK-ASM-AND-OBJ: sh s6, 2047(s4)
+# CHECK-ASM: encoding: [0xa3,0x1f,0x6a,0x7f]
+sh s6, 2047(s4)
+# CHECK-ASM-AND-OBJ: sh s7, -2048(s5)
+# CHECK-ASM: encoding: [0x23,0x90,0x7a,0x81]
+sh s7, -2048(s5)
+# CHECK-ASM-AND-OBJ: sh s0, -2048(s6)
+# CHECK-ASM: encoding: [0x23,0x10,0x8b,0x80]
+sh x8, %lo(2048)(s6)
+# CHECK-ASM-AND-OBJ: sh s1, 999(s7)
+# CHECK-ASM: encoding: [0xa3,0x93,0x9b,0x3e]
+sh x9, 999(s7)
+
+# CHECK-ASM-AND-OBJ: fcvt.s.h a0, a1
+# CHECK-ASM: encoding: [0x53,0x85,0x25,0x40]
+fcvt.s.h a0, a1
+
+# CHECK-ASM-AND-OBJ: fcvt.h.s a0, a1, dyn
+# CHECK-ASM: encoding: [0x53,0xf5,0x05,0x44]
+fcvt.h.s a0, a1

llvm/test/MC/RISCV/rv64zdinx-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zdinx < %s 2>&1 | FileCheck %s
+
+# Invalid Instructions
+fmv.x.d t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+fmv.d.x a5, t5 # CHECK: :[[@LINE]]:9:  error: invalid operand for instruction

llvm/test/MC/RISCV/rv64zdinx-valid.s

+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zdinx -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zdinx < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zdinx -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zdinx < %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-RV32 %s
+
+# CHECK-ASM-AND-OBJ: fcvt.l.d a0, t0, dyn
+# CHECK-ASM: encoding: [0x53,0xf5,0x22,0xc2]
+# CHECK-RV32: :[[@LINE+1]]:14: error: invalid operand for instruction
+fcvt.l.d a0, t0, dyn
+# CHECK-ASM-AND-OBJ: fcvt.lu.d a1, t1, dyn
+# CHECK-ASM: encoding: [0xd3,0x75,0x33,0xc2]
+# CHECK-RV32: :[[@LINE+1]]:15: error: invalid operand for instruction
+fcvt.lu.d a1, t1, dyn
+# CHECK-ASM-AND-OBJ: fcvt.d.l t3, a3, dyn
+# CHECK-ASM: encoding: [0x53,0xfe,0x26,0xd2]
+# CHECK-RV32: :[[@LINE+1]]:10: error: invalid operand for instruction
+fcvt.d.l t3, a3, dyn
+# CHECK-ASM-AND-OBJ: fcvt.d.lu t4, a4, dyn
+# CHECK-ASM: encoding: [0xd3,0x7e,0x37,0xd2]
+# CHECK-RV32: :[[@LINE+1]]:11: error: invalid operand for instruction
+fcvt.d.lu t4, a4, dyn
+
+# Rounding modes
+# CHECK-ASM-AND-OBJ: fcvt.d.l t3, a3, rne
+# CHECK-ASM: encoding: [0x53,0x8e,0x26,0xd2]
+# CHECK-RV32: :[[@LINE+1]]:10: error: invalid operand for instruction
+fcvt.d.l t3, a3, rne
+# CHECK-ASM-AND-OBJ: fcvt.d.lu t4, a4, rtz
+# CHECK-ASM: encoding: [0xd3,0x1e,0x37,0xd2]
+# CHECK-RV32: :[[@LINE+1]]:11: error: invalid operand for instruction
+fcvt.d.lu t4, a4, rtz
+# CHECK-ASM-AND-OBJ: fcvt.l.d a0, t0, rdn
+# CHECK-ASM: encoding: [0x53,0xa5,0x22,0xc2]
+# CHECK-RV32: :[[@LINE+1]]:14: error: invalid operand for instruction
+fcvt.l.d a0, t0, rdn
+# CHECK-ASM-AND-OBJ: fcvt.lu.d a1, t1, rup
+# CHECK-ASM: encoding: [0xd3,0x35,0x33,0xc2]
+# CHECK-RV32: :[[@LINE+1]]:15: error: invalid operand for instruction
+fcvt.lu.d a1, t1, rup

llvm/test/MC/RISCV/rv64zfinx-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zdinx < %s 2>&1 | FileCheck %s
+
+# Invalid instructions
+fmv.x.w t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+fmv.w.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction

llvm/test/MC/RISCV/rv64zfinx-valid.s

+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfinx -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfinx < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zfinx -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfinx < %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-RV32 %s
+
+# CHECK-ASM-AND-OBJ: fcvt.l.s a0, t0, dyn
+# CHECK-ASM: encoding: [0x53,0xf5,0x22,0xc0]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.l.s a0, t0, dyn
+# CHECK-ASM-AND-OBJ: fcvt.lu.s a1, t1, dyn
+# CHECK-ASM: encoding: [0xd3,0x75,0x33,0xc0]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.lu.s a1, t1, dyn
+# CHECK-ASM-AND-OBJ: fcvt.s.l t2, a2, dyn
+# CHECK-ASM: encoding: [0xd3,0x73,0x26,0xd0]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.s.l t2, a2, dyn
+# CHECK-ASM-AND-OBJ: fcvt.s.lu t3, a3, dyn
+# CHECK-ASM: encoding: [0x53,0xfe,0x36,0xd0]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.s.lu t3, a3, dyn
+
+# Rounding modes
+# CHECK-ASM-AND-OBJ: fcvt.l.s a4, t4, rne
+# CHECK-ASM: encoding: [0x53,0x87,0x2e,0xc0]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.l.s a4, t4, rne
+# CHECK-ASM-AND-OBJ: fcvt.lu.s a5, t5, rtz
+# CHECK-ASM: encoding: [0xd3,0x17,0x3f,0xc0]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.lu.s a5, t5, rtz
+# CHECK-ASM-AND-OBJ: fcvt.s.l t6, a6, rdn
+# CHECK-ASM: encoding: [0xd3,0x2f,0x28,0xd0]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.s.l t6, a6, rdn
+# CHECK-ASM-AND-OBJ: fcvt.s.lu s7, a7, rup
+# CHECK-ASM: encoding: [0xd3,0xbb,0x38,0xd0]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.s.lu s7, a7, rup

llvm/test/MC/RISCV/rv64zhinx-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zdinx < %s 2>&1 | FileCheck %s
+
+# Invalid instructions
+fmv.x.h t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+fmv.h.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction

llvm/test/MC/RISCV/rv64zhinx-valid.s

+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zhinx < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zhinx -M no-aliases -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zhinx < %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-RV32 %s
+
+# CHECK-ASM-AND-OBJ: fcvt.l.h a0, t0, dyn
+# CHECK-ASM: encoding: [0x53,0xf5,0x22,0xc4]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.l.h a0, t0, dyn
+# CHECK-ASM-AND-OBJ: fcvt.lu.h a1, t1, dyn
+# CHECK-ASM: encoding: [0xd3,0x75,0x33,0xc4]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.lu.h a1, t1, dyn
+# CHECK-ASM-AND-OBJ: fcvt.h.l t2, a2, dyn
+# CHECK-ASM: encoding: [0xd3,0x73,0x26,0xd4]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.h.l t2, a2, dyn
+# CHECK-ASM-AND-OBJ: fcvt.h.lu t3, a3, dyn
+# CHECK-ASM: encoding: [0x53,0xfe,0x36,0xd4]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.h.lu t3, a3, dyn
+
+# Rounding modes
+# CHECK-ASM-AND-OBJ: fcvt.l.h a4, t4, rne
+# CHECK-ASM: encoding: [0x53,0x87,0x2e,0xc4]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.l.h a4, t4, rne
+# CHECK-ASM-AND-OBJ: fcvt.lu.h a5, t5, rtz
+# CHECK-ASM: encoding: [0xd3,0x17,0x3f,0xc4]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.lu.h a5, t5, rtz
+# CHECK-ASM-AND-OBJ: fcvt.h.l t6, a6, rdn
+# CHECK-ASM: encoding: [0xd3,0x2f,0x28,0xd4]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.h.l t6, a6, rdn
+# CHECK-ASM-AND-OBJ: fcvt.h.lu s7, a7, rup
+# CHECK-ASM: encoding: [0xd3,0xbb,0x38,0xd4]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fcvt.h.lu s7, a7, rup

llvm/test/MC/RISCV/rv64zhinxmin-valid.s

+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx,+experimental-zdinx -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zhinx,+experimental-zdinx < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zhinx,+experimental-zdinx -M no-aliases -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: fcvt.d.h a0, a2
+# CHECK-ASM: encoding: [0x53,0x05,0x26,0x42]
+fcvt.d.h a0, a2
+
+# CHECK-ASM-AND-OBJ: fcvt.h.d a0, a2, dyn
+# CHECK-ASM: encoding: [0x53,0x75,0x16,0x44]
+fcvt.h.d a0, a2, dyn

llvm/test/MC/RISCV/rvzdinx-aliases-valid.s

+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zdinx -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zdinx \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zdinx < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-zdinx -M no-aliases - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zdinx < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-zdinx - \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===----------------------------------------------------------------------===##
+## Aliases which omit the rounding mode.
+##===----------------------------------------------------------------------===##
+
+# CHECK-INST: fcvt.l.d a0, t0, dyn
+# CHECK-ALIAS: fcvt.l.d a0, t0{{[[:space:]]}}
+fcvt.l.d a0, t0
+# CHECK-INST: fcvt.lu.d a1, t1, dyn
+# CHECK-ALIAS: fcvt.lu.d a1, t1{{[[:space:]]}}
+fcvt.lu.d a1, t1
+# CHECK-INST: fcvt.d.l t3, a3, dyn
+# CHECK-ALIAS: fcvt.d.l t3, a3{{[[:space:]]}}
+fcvt.d.l t3, a3
+# CHECK-INST: fcvt.d.lu t4, a4, dyn
+# CHECK-ALIAS: fcvt.d.lu t4, a4{{[[:space:]]}}
+fcvt.d.lu t4, a4

llvm/test/MC/RISCV/rvzfinx-aliases-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfinx -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfinx \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfinx -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfinx \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zfinx < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-zfinx -M no-aliases - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zfinx < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zfinx < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-zfinx -M no-aliases - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zfinx < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===----------------------------------------------------------------------===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===----------------------------------------------------------------------===##
+
+# CHECK-INST: fsgnjx.s s1, s2, s2
+# CHECK-ALIAS: fabs.s s1, s2
+fabs.s s1, s2
+# CHECK-INST: fsgnjn.s s2, s3, s3
+# CHECK-ALIAS: fneg.s s2, s3
+fneg.s s2, s3
+
+# CHECK-INST: flt.s tp, s6, s5
+# CHECK-ALIAS: flt.s tp, s6, s5
+fgt.s x4, s5, s6
+# CHECK-INST: fle.s t2, s1, s0
+# CHECK-ALIAS: fle.s t2, s1, s0
+fge.s x7, x8, x9
+
+##===----------------------------------------------------------------------===##
+## Aliases which omit the rounding mode.
+##===----------------------------------------------------------------------===##
+
+# CHECK-INST: fmadd.s a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.s a0, a1, a2, a3{{[[:space:]]}}
+fmadd.s x10, x11, x12, x13
+# CHECK-INST: fmsub.s a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.s a4, a5, a6, a7{{[[:space:]]}}
+fmsub.s x14, x15, x16, x17
+# CHECK-INST: fnmsub.s s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.s s2, s3, s4, s5{{[[:space:]]}}
+fnmsub.s x18, x19, x20, x21
+# CHECK-INST: fnmadd.s s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.s s6, s7, s8, s9{{[[:space:]]}}
+fnmadd.s x22, x23, x24, x25
+# CHECK-INST: fadd.s s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.s s10, s11, t3{{[[:space:]]}}
+fadd.s x26, x27, x28
+# CHECK-INST: fsub.s t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.s t4, t5, t6{{[[:space:]]}}
+fsub.s x29, x30, x31
+# CHECK-INST: fmul.s s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.s s0, s1, s2{{[[:space:]]}}
+fmul.s s0, s1, s2
+# CHECK-INST: fdiv.s s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.s s3, s4, s5{{[[:space:]]}}
+fdiv.s s3, s4, s5
+# CHECK-INST: sqrt.s s6, s7, dyn
+# CHECK-ALIAS: sqrt.s s6, s7{{[[:space:]]}}
+fsqrt.s s6, s7
+# CHECK-INST: fcvt.w.s a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.s a0, s5{{[[:space:]]}}
+fcvt.w.s a0, s5
+# CHECK-INST: fcvt.wu.s a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.s a1, s6{{[[:space:]]}}
+fcvt.wu.s a1, s6
+# CHECK-INST: fcvt.s.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.s.w t6, a4{{[[:space:]]}}
+fcvt.s.w t6, a4
+# CHECK-INST: fcvt.s.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.s.wu s0, a5{{[[:space:]]}}
+fcvt.s.wu s0, a5

llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===----------------------------------------------------------------------===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===----------------------------------------------------------------------===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+
+##===----------------------------------------------------------------------===##
+## Aliases which omit the rounding mode.
+##===----------------------------------------------------------------------===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3{{[[:space:]]}}
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7{{[[:space:]]}}
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5{{[[:space:]]}}
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9{{[[:space:]]}}
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3{{[[:space:]]}}
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6{{[[:space:]]}}
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2{{[[:space:]]}}
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5{{[[:space:]]}}
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7{{[[:space:]]}}
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5{{[[:space:]]}}
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6{{[[:space:]]}}
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4{{[[:space:]]}}
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5{{[[:space:]]}}
+fcvt.h.wu s0, a5