[RISCV][NFC] Use foreach to refactor vector load/store whole register instructions' definition.

[jacquesguan]

Summary

Refactor vector load/store whole register instructions' definition with foreach format.

[jacquesguan]

ping

[asb]

Thanks for the patch Jianjian. This is a matter of personal taste, so I'll happily defer to those who are more actively contributing to the RVV tablegen files, but IMHO the reduced readability due to the casts and string concatenation in the new version mean it's not clear this is an improvement over the current code.

[jacquesguan]

In D116019#3224688, @asb wrote:

Thanks for the patch Jianjian. This is a matter of personal taste, so I'll happily defer to those who are more actively contributing to the RVV tablegen files, but IMHO the reduced readability due to the casts and string concatenation in the new version mean it's not clear this is an improvement over the current code.

Thanks for your advice, I will close this one.

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 def VSM_V : VUnitStrideStoreMask<"vsm.v">,
              Sched<[WriteVSTM, ReadVSTM, ReadVSTX]>;
 def : InstAlias<"vle1.v $vd, (${rs1})",
                 (VLM_V VR:$vd, GPR:$rs1), 0>;
 def : InstAlias<"vse1.v $vs3, (${rs1})",
                 (VSM_V VR:$vs3, GPR:$rs1), 0>;
 
 defm VL1R : VWholeLoadN<0, "vl1r", VR>;
-defm VL2R : VWholeLoadN<1, "vl2r", VRM2>;
-defm VL4R : VWholeLoadN<3, "vl4r", VRM4>;
-defm VL8R : VWholeLoadN<7, "vl8r", VRM8>;
-
 def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>;
-def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>;
-def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VRM4:$vd, GPR:$rs1)>;
-def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>;
-
 def VS1R_V : VWholeStore<0, "vs1r.v", VR>,
              Sched<[WriteVST1R, ReadVST1R, ReadVSTX]>;
-def VS2R_V : VWholeStore<1, "vs2r.v", VRM2>,
-             Sched<[WriteVST2R, ReadVST2R, ReadVSTX]>;
-def VS4R_V : VWholeStore<3, "vs4r.v", VRM4>,
-             Sched<[WriteVST4R, ReadVST4R, ReadVSTX]>;
-def VS8R_V : VWholeStore<7, "vs8r.v", VRM8>,
-             Sched<[WriteVST8R, ReadVST8R, ReadVSTX]>;
+
+foreach n = [2, 4, 8] in {
+  defvar vrc = !cast<VReg>("VRM"#n);
+
+  defm VL#n#R : VWholeLoadN<!add(n, -1), "vl"#n#"r", vrc>;
+  def : InstAlias<"vl"#n#"r.v $vd, (${rs1})",
+                  (!cast<Instruction>(VL#n#RE8_V) vrc:$vd, GPR:$rs1)>;
+  def VS#n#R_V : VWholeStore<!add(n, -1), "vs"#n#"r.v", vrc>,
+                 Sched<[!cast<SchedWrite>("WriteVST"#n#"R"),
+                        !cast<SchedRead>("ReadVST"#n#"R"), ReadVSTX]>;
+}
 
 // Vector Single-Width Integer Add and Subtract
 defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>;
 defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
 defm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>;
 
 def : InstAlias<"vneg.v $vd, $vs$vm", (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;