[RISCV] Fix zfinx test error in rust

[achieveartificialintelligence]

Summary

In D93298: It appears that this is causing an assertion segfault in a rustc test over at our experimental rust + llvm@head bot:
https://buildkite.com/llvm-project/rust-llvm-integrate-prototype/builds/8430#167e6de5-2dd5-41c3-87d7-b6e3f3908371/262-706
The test is https://github.com/rust-lang/rust/blob/master/src/test/assembly/asm/riscv-types.rs

[xbolva00]

Missing test

[achieveartificialintelligence]

In D120130#3332052, @xbolva00 wrote:

Missing test

Tests are in the rust environment.

[xbolva00]

I see IR here https://reviews.llvm.org/D93298#3331641

[jrtc27]

In D120130#3332072, @achieveartificialintelligence wrote:

In D120130#3332052, @xbolva00 wrote:

Missing test

Tests are in the rust environment.

That's no good for us, Rust isn't part of LLVM

[jrtc27]

I'm unconvinced this is quite the right fix for the bug. I agree we need this code, but I disagree that this code should be needed when Zfinx isn't in use. Without Zfinx, we should never have GFPR* be legal in the first place, surely?

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

260

Surely for floats in GPRs we should just use a GPR move? It'll compress better and avoids unnecessary FPU usage.

[durin42]

I ran the Rust testsuite with this change applied to LLVM and it fails the same way as before. Probably easy to catch if you use the IR reported in the other change?

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

static bool isConvertibleToVMV_V_V(const RISCVSubtarget &STI,
 
   return false;
 }
 
 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MBBI,
                                  const DebugLoc &DL, MCRegister DstReg,
                                  MCRegister SrcReg, bool KillSrc) const {
   if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
     BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
         .addReg(SrcReg, getKillRegState(KillSrc))
         .addImm(0);
     return;
   }
 
   // FPR->FPR copies and VR->VR copies.
   unsigned Opc;
   bool IsScalableVector = true;
   unsigned NF = 1;
   RISCVII::VLMUL LMul = RISCVII::LMUL_1;
   unsigned SubRegIdx = RISCV::sub_vrm1_0;
-  if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) {
+  if (RISCV::FPR16RegClass.contains(DstReg, SrcReg) ||
+      RISCV::GPRF16RegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::FSGNJ_H;
     IsScalableVector = false;
-  } else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {
+  } else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg) ||
+             RISCV::GPRF32RegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::FSGNJ_S;
     IsScalableVector = false;
-  } else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) {
+  } else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg) ||
+             RISCV::GPRF64RegClass.contains(DstReg, SrcReg) ||
+             RISCV::GPRPF64RegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::FSGNJ_D;
     IsScalableVector = false;
   } else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::PseudoVMV1R_V;
     LMul = RISCVII::LMUL_1;
   } else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::PseudoVMV2R_V;
     LMul = RISCVII::LMUL_2;