[RISCV] add the MC layer support of Zfinx extension

[achieveartificialintelligence]

Summary

This patch added the MC layer support of Zfinx extension.

Authored-by: StephenFan
Co-Authored-by: Shao-Ce Sun

[achieveartificialintelligence]

Fix

[achieveartificialintelligence]

Add arch info

[achieveartificialintelligence]

Fix

[MaskRay]

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

164

Use functionName.

There is inconsistency in the code base but functionName is used much more than FunctionName.

186

https://llvm.org/docs/CodingStandards.html#don-t-use-braces-on-simple-single-statement-bodies-of-if-else-loop-statements

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

175 ↗

(On Diff #379273)

The indentation is inconsistent. Also applies to code above.

llvm/test/MC/RISCV/rv64zhinx-valid.s

3 ↗

(On Diff #379273)

llvm-mc can use %s instead of < %s

I heard that not using < is a bit more convenient for some Windows users. (They do suffer from llc and opt's prevailing < %s)

12 ↗

(On Diff #379273)

[[@LINE+1]] is a deprecated form.
Use [[#@LINE+1]]. Applies to many places elsewhere.

llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

46 ↗

(On Diff #379273)

What is {{[[:space:]]}} used for?

[achieveartificialintelligence]

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

164

I fix this in D112520

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

539 ↗

(On Diff #373170)

After D95588 is accepted, we will reuse this.

[achieveartificialintelligence]

Rebase

[achieveartificialintelligence]

Address @MaskRay 's comments.

[achieveartificialintelligence]

Rebase

[achieveartificialintelligence]

Rebase

[achieveartificialintelligence]

Ping

[achieveartificialintelligence]

Rebase and Ping.

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

69 ↗

(On Diff #388780)

Do we need to enforce that these can't be mixed with F, D, and Zfh?

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1718 ↗

(On Diff #388780)

D and Zfh imply F. Is it enough to just check F?

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

77 ↗

(On Diff #388780)

Can we merge this with FPFMAD_rrr_frm_single and FPFMAH_rrr_frm_single by passing the 0b00/0b01/0b10 value from FPFMAS_rrr_frm/FPFMAD_rrr_frm/FPFMAH_rrr_frm?

This applies to most of the _single classes. We should share them if possible.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

489 ↗

(On Diff #388780)

Aren't these aliases only valid for RV64. You need IN32X aliases for RV32 right?

[achieveartificialintelligence]

Address @craig.topper 's comments.

[achieveartificialintelligence]

Gentle Ping and Rebase.

[achieveartificialintelligence]

Update Part of Zfinx Codes

[achieveartificialintelligence]

I'll finish the rest of code, if this patch is acceptable.

[achieveartificialintelligence]

Ping.

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

290 ↗

(On Diff #396373)

@kito-cheng or @khchen is the right way to do this? Or should it be in updateImplication? Where do we have Zfhmin imply f or d imply f today?

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

34 ↗

(On Diff #396373)

Can you add let RenderMethod = "addRegOperands"; here. That should let you remove addGPRAsFPROperands from RISCVAsmParser.cpp. Similar for the other AsmOperandClasses.

[craig.topper]

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

170

Can we make use of let DecoderMethod = on RegisterClass to avoid these aliases?

[achieveartificialintelligence]

Address @craig.topper 's comments.

[achieveartificialintelligence]

Rebase

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

124 ↗

(On Diff #397193)

Can we use DAGOperand instead of RegisterOperand? I think that should allow you to avoid adding GPROp, FPR32Op, FPR64Op, and FPR16Op. You can just use the RegisterClasses. Both RegisterClass and RegisterOperand inherit from DAGOperand.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

217 ↗

(On Diff #397193)

Why do the aliases not apply to Zfinx?

[achieveartificialintelligence]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

217 ↗

(On Diff #397193)

Because the first argument is FPFMA_rrr_frm Inst, if we use multiclass here, it'll be FFPFMA_rrr_frm Inst, FFPFMA_rrr_frm Inst_INX. I don't know is there a better way?

[achieveartificialintelligence]

Use DAGOperand instead of RegisterOperand

[achieveartificialintelligence]

Fix issue in RISCVISAInfo.cpp

[achieveartificialintelligence]

Inspired by D116019, use multiclass in Alias

[achieveartificialintelligence]

update

[achieveartificialintelligence]

Ping. Zfinx has been ratified, could we spend some time on this patch?

[achieveartificialintelligence]

update

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

687 ↗

(On Diff #399270)

Do we need the equivalent of this for Zfinx and Zdinx?

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

228 ↗

(On Diff #399270)

Don't we need IN32X aliases too?

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

552 ↗

(On Diff #399270)

Is possible to reference GPR here to avoid listing the allocation order again? Similar to how GPRNoX0 does (sub GPR, X0). Not sure if there is a way to be exactly another list.

[achieveartificialintelligence]

Address @craig.topper's comments

[achieveartificialintelligence]

Rebase

[achieveartificialintelligence]

rebase

[achieveartificialintelligence]

Ping. Any other suggestions?

[craig.topper]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

137 ↗

(On Diff #400733)

Does putting this back the way it was and using "(add GPR)" in GPRF16, GPRF32, and GPRF64 work?

[achieveartificialintelligence]

Address @craig.topper's comments. Thanks!

[asb]

Thanks for your work on this. The way you've managed to use multiclasses to handle this with the 'ExtInfo' definitions takes a bit of unpicking to follow, but it does a really good job of keeping the instruction definitions largely unmodified. Nice!

I've got a few requests/questions on the test coverage:

• I'm not sure the inclusion of the load/store instructions in the z[d,f,h]inx test cases has much value, given those instructions are unmodified?
• Given that the set of F/D/Zfh instructions that _aren't_ supported under z[d,f,h]inx is relatively short, it's probably worth being exhaustive in the *-invalid.s test cases. It's only 8 instructions for Zfinx for instance.
• The *-invalid.s test cases should have coverage for using a floating point register with an operation that is supported by Z[d,f,h]inx
• The zdinx test cases don't include any coverage for when odd registers are used, but I think it should

[asb]

Not an issue for this MC-layer patch, but I've created https://github.com/riscv/riscv-zfinx/issues/14 to point out what seems to be an incorrect statement about the status quo on the ABI for 32-bit floating point types on RV64 in the Zfinx spec.

[achieveartificialintelligence]

@asb Thank you very much! Could you please take a look at what needs to be modified now?

[achieveartificialintelligence]

Separate the Zhinxmin and Zhinx extensions. Inspired by D118581

[luismarques]

Assuming this will be merged soon, do you want to submit a backport request for the 14.0 branch?

[achieveartificialintelligence]

In D93298#3296515, @luismarques wrote:

Assuming this will be merged soon, do you want to submit a backport request for the 14.0 branch?

Yes.

[Jim]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

555 ↗

(On Diff #404910)

Is XLenRI correct for GPRPF64? RV32 has size 32.

[craig.topper]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

555 ↗

(On Diff #404910)

I'm not sure the RegInfos are correct for the other classes either. The RegInfos override the register size, the spill size, and spill alignment. I think those should all be based on the FP type.

So I don't think any of these should have a RegInfos.

[achieveartificialintelligence]

Address comments.

[achieveartificialintelligence]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

555 ↗

(On Diff #404910)

Without RegInfo, it would cause spill size to be changed for a large number of other tests.

[Jim]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

557 ↗

(On Diff #407482)

Is register pair only on RV32 for used as f64?

[achieveartificialintelligence]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

557 ↗

(On Diff #407482)

Yes.

[asb]

I think all my comments have been addressed. @craig.topper - are you happy your RegInfo question is addressed?

[craig.topper]

In D93298#3326230, @asb wrote:

I think all my comments have been addressed. @craig.topper - are you happy your RegInfo question is addressed?

I'm happy.

[asb]

In that case, LGTM (needs a rebase though). Thanks for your patience on this @achieveartificialintelligence.

[achieveartificialintelligence]

Thanks all!

[krasimir]

It appears that this is causing an assertion segfault in a rustc test over at our experimental rust + llvm@head bot:
https://buildkite.com/llvm-project/rust-llvm-integrate-prototype/builds/8430#167e6de5-2dd5-41c3-87d7-b6e3f3908371/262-706
The test is https://github.com/rust-lang/rust/blob/master/src/test/assembly/asm/riscv-types.rs. These two lines appear to cause it (code compiles fine when removed):

• check_reg!(a0_f32 f32 "a0" "mv"); https://github.com/rust-lang/rust/blob/f838a425e3134d036a7d9632935111a569ac7446/src/test/assembly/asm/riscv-types.rs#L178
• check_reg!(a0_f64 f64 "a0" "mv"); https://github.com/rust-lang/rust/blob/f838a425e3134d036a7d9632935111a569ac7446/src/test/assembly/asm/riscv-types.rs#L192

The assertion:

Impossible reg-to-reg copy
UNREACHABLE executed at [...]/rust/src/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:350

The IR for riscv-types.rs:

; ModuleID = 'riscv_types.4cedf4b7-cgu.0'
source_filename = "riscv_types.4cedf4b7-cgu.0"
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
target triple = "riscv64"

@extern_static = external dso_local global i8
@alloc55 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"reg_i8" }>, align 1
@alloc56 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"reg_i16" }>, align 1
@alloc57 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"reg_i32" }>, align 1
@alloc58 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"reg_f32" }>, align 1
@alloc59 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"reg_i64" }>, align 1
@alloc60 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"reg_f64" }>, align 1
@alloc61 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"reg_ptr" }>, align 1
@alloc62 = private unnamed_addr constant <{ [8 x i8] }> <{ [8 x i8] c"freg_f32" }>, align 1
@alloc63 = private unnamed_addr constant <{ [8 x i8] }> <{ [8 x i8] c"freg_f64" }>, align 1
@alloc64 = private unnamed_addr constant <{ [5 x i8] }> <{ [5 x i8] c"a0_i8" }>, align 1
@alloc65 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_i16" }>, align 1
@alloc66 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_i32" }>, align 1
@alloc67 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_f32" }>, align 1
@alloc68 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_i64" }>, align 1
@alloc69 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_f64" }>, align 1
@alloc70 = private unnamed_addr constant <{ [6 x i8] }> <{ [6 x i8] c"a0_ptr" }>, align 1
@alloc71 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"fa0_f32" }>, align 1
@alloc72 = private unnamed_addr constant <{ [7 x i8] }> <{ [7 x i8] c"fa0_f64" }>, align 1

; Function Attrs: nounwind
define dso_local void @sym_fn() unnamed_addr #0 {
start:
  tail call void asm sideeffect alignstack "call ${0:c}", "s,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(void ()* nonnull @extern_func) #1, !srcloc !1
  ret void
}

; Function Attrs: nounwind
define dso_local void @sym_static() unnamed_addr #0 {
start:
  tail call void asm sideeffect alignstack "lb t0, ${0:c}", "s,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i8* nonnull @extern_static) #1, !srcloc !2
  ret void
}

; Function Attrs: nounwind
define dso_local i8 @reg_i8(i8 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [6 x i8] }>* @alloc55 to [0 x i8]*), i64 6) #1
  %0 = tail call i8 asm sideeffect alignstack "mv ${0}, ${1}", "=&r,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i8 %x) #1, !srcloc !3
  ret i8 %0
}

; Function Attrs: nounwind
define dso_local i16 @reg_i16(i16 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc56 to [0 x i8]*), i64 7) #1
  %0 = tail call i16 asm sideeffect alignstack "mv ${0}, ${1}", "=&r,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i16 %x) #1, !srcloc !3
  ret i16 %0
}

; Function Attrs: nounwind
define dso_local i32 @reg_i32(i32 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc57 to [0 x i8]*), i64 7) #1
  %0 = tail call i32 asm sideeffect alignstack "mv ${0}, ${1}", "=&r,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i32 %x) #1, !srcloc !3
  ret i32 %0
}

; Function Attrs: nounwind
define dso_local float @reg_f32(float %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc58 to [0 x i8]*), i64 7) #1
  %0 = tail call float asm sideeffect alignstack "mv ${0}, ${1}", "=&r,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(float %x) #1, !srcloc !3
  ret float %0
}

; Function Attrs: nounwind
define dso_local i64 @reg_i64(i64 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc59 to [0 x i8]*), i64 7) #1
  %0 = tail call i64 asm sideeffect alignstack "mv ${0}, ${1}", "=&r,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i64 %x) #1, !srcloc !3
  ret i64 %0
}

; Function Attrs: nounwind
define dso_local double @reg_f64(double %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc60 to [0 x i8]*), i64 7) #1
  %0 = tail call double asm sideeffect alignstack "mv ${0}, ${1}", "=&r,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(double %x) #1, !srcloc !3
  ret double %0
}

; Function Attrs: nounwind
define dso_local i8* @reg_ptr(i8* %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc61 to [0 x i8]*), i64 7) #1
  %0 = tail call i8* asm sideeffect alignstack "mv ${0}, ${1}", "=&r,r,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i8* %x) #1, !srcloc !3
  ret i8* %0
}

; Function Attrs: nounwind
define dso_local float @freg_f32(float %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [8 x i8] }>* @alloc62 to [0 x i8]*), i64 8) #1
  %0 = tail call float asm sideeffect alignstack "fmv.s ${0}, ${1}", "=&f,f,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(float %x) #1, !srcloc !3
  ret float %0
}

; Function Attrs: nounwind
define dso_local double @freg_f64(double %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [8 x i8] }>* @alloc63 to [0 x i8]*), i64 8) #1
  %0 = tail call double asm sideeffect alignstack "fmv.d ${0}, ${1}", "=&f,f,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(double %x) #1, !srcloc !3
  ret double %0
}

; Function Attrs: nounwind
define dso_local i8 @a0_i8(i8 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [5 x i8] }>* @alloc64 to [0 x i8]*), i64 5) #1
  %0 = tail call i8 asm sideeffect alignstack "mv a0, a0", "={x10},{x10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i8 %x) #1, !srcloc !4
  ret i8 %0
}

; Function Attrs: nounwind
define dso_local i16 @a0_i16(i16 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [6 x i8] }>* @alloc65 to [0 x i8]*), i64 6) #1
  %0 = tail call i16 asm sideeffect alignstack "mv a0, a0", "={x10},{x10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i16 %x) #1, !srcloc !4
  ret i16 %0
}

; Function Attrs: nounwind
define dso_local i32 @a0_i32(i32 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [6 x i8] }>* @alloc66 to [0 x i8]*), i64 6) #1
  %0 = tail call i32 asm sideeffect alignstack "mv a0, a0", "={x10},{x10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i32 %x) #1, !srcloc !4
  ret i32 %0
}

; Function Attrs: nounwind
define dso_local float @a0_f32(float %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [6 x i8] }>* @alloc67 to [0 x i8]*), i64 6) #1
  %0 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(float %x) #1, !srcloc !4
  ret float %0
}

; Function Attrs: nounwind
define dso_local i64 @a0_i64(i64 %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [6 x i8] }>* @alloc68 to [0 x i8]*), i64 6) #1
  %0 = tail call i64 asm sideeffect alignstack "mv a0, a0", "={x10},{x10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i64 %x) #1, !srcloc !4
  ret i64 %0
}

; Function Attrs: nounwind
define dso_local double @a0_f64(double %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [6 x i8] }>* @alloc69 to [0 x i8]*), i64 6) #1
  %0 = tail call double asm sideeffect alignstack "mv a0, a0", "={x10},{x10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(double %x) #1, !srcloc !4
  ret double %0
}

; Function Attrs: nounwind
define dso_local i8* @a0_ptr(i8* %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [6 x i8] }>* @alloc70 to [0 x i8]*), i64 6) #1
  %0 = tail call i8* asm sideeffect alignstack "mv a0, a0", "={x10},{x10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(i8* %x) #1, !srcloc !4
  ret i8* %0
}

; Function Attrs: nounwind
define dso_local float @fa0_f32(float %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc71 to [0 x i8]*), i64 7) #1
  %0 = tail call float asm sideeffect alignstack "fmv.s fa0, fa0", "={f10},{f10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(float %x) #1, !srcloc !4
  ret float %0
}

; Function Attrs: nounwind
define dso_local double @fa0_f64(double %x) unnamed_addr #0 {
start:
  tail call void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1 bitcast (<{ [7 x i8] }>* @alloc72 to [0 x i8]*), i64 7) #1
  %0 = tail call double asm sideeffect alignstack "fmv.d fa0, fa0", "={f10},{f10},~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(double %x) #1, !srcloc !4
  ret double %0
}

; Function Attrs: nounwind
declare dso_local void @extern_func() unnamed_addr #0

; Function Attrs: nounwind
declare dso_local void @dont_merge([0 x i8]* noalias noundef nonnull readonly align 1, i64) unnamed_addr #0

attributes #0 = { nounwind "target-cpu"="generic-rv64" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0}

!0 = !{i32 1, !"Code Model", i32 3}
!1 = !{i32 1048}
!2 = !{i32 1281}
!3 = !{i32 1670}
!4 = !{i32 2113}

@achieveartificialintelligence could you please take a look? Any ideas what's going wrong here?

[jrtc27]

In D93298#3331641, @krasimir wrote:

It appears that this is causing an assertion segfault in a rustc test over at our experimental rust + llvm@head bot:
https://buildkite.com/llvm-project/rust-llvm-integrate-prototype/builds/8430#167e6de5-2dd5-41c3-87d7-b6e3f3908371/262-706
The test is https://github.com/rust-lang/rust/blob/master/src/test/assembly/asm/riscv-types.rs. These two lines appear to cause it (code compiles fine when removed):

• check_reg!(a0_f32 f32 "a0" "mv"); https://github.com/rust-lang/rust/blob/f838a425e3134d036a7d9632935111a569ac7446/src/test/assembly/asm/riscv-types.rs#L178
• check_reg!(a0_f64 f64 "a0" "mv"); https://github.com/rust-lang/rust/blob/f838a425e3134d036a7d9632935111a569ac7446/src/test/assembly/asm/riscv-types.rs#L192

The assertion:

Impossible reg-to-reg copy
UNREACHABLE executed at [...]/rust/src/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:350

...

This is just MC layer support. Inline assembly interacts with CodeGen; I assume the register classes/constraints still need updating to support Zfinx.

llvm/test/MC/RISCV/rv32i-invalid.s

1 ↗

(On Diff #407482)

This is an unrelated change

[achieveartificialintelligence]

@krasimir Since I don't have a rust environment, can you help me to test if D120130 works?

[jrtc27]

In D93298#3332020, @achieveartificialintelligence wrote:

@krasimir Since I don't have a rust environment, can you help me to test if D120130 works?

Hm, actually, looking at the log, it doesn't appear to be trying to use Zfinx? My guess is that putting a float in a GPR has broken as that's now legal but should only be legal for Zfinx?

[xbolva00]

It appears that this is causing an assertion segfault in a rustc test over at our experimental rust + llvm@head bot:

I dont think that patch author is required to debug this issue for "experimental rust + llvm@head" - downstream.

Since I don't have a rust environment

There is no requirement, indeed. LLVM devs are not responsible to keep ""experimental rust + llvm@head" working.

[jrtc27]

In D93298#3332038, @xbolva00 wrote:

It appears that this is causing an assertion segfault in a rustc test over at our experimental rust + llvm@head bot:

I dont think that patch author is required to debug this issue for "experimental rust + llvm@head" - downstream.

Since I don't have a rust environment

There is no requirement, indeed. LLVM devs are not responsible to keep ""experimental rust + llvm@head" working.

They're required to assist with fixing regressions that show when compiling legitimate IR. An IR reproducer was given, so no Rust toolchain knowledge should be needed, at that point it's the LLVM dev's responsibility, and if they can't fix it in a timely manner then it should be backed out.

[xbolva00]

In D93298#3332058, @jrtc27 wrote:

In D93298#3332038, @xbolva00 wrote:

It appears that this is causing an assertion segfault in a rustc test over at our experimental rust + llvm@head bot:

I dont think that patch author is required to debug this issue for "experimental rust + llvm@head" - downstream.

Since I don't have a rust environment

There is no requirement, indeed. LLVM devs are not responsible to keep ""experimental rust + llvm@head" working.

They're required to assist with fixing regressions that show when compiling legitimate IR. An IR reproducer was given, so no Rust toolchain knowledge should be needed, at that point it's the LLVM dev's responsibility, and if they can't fix it in a timely manner then it should be backed out.

Then yeah, if IR is provided and is standard one, this is okay. Consider to add that IR as testcase for the fix.

[nikic]

Because I happened to also run into this, reduced IR for -mtriple=riscv32 -mattr=+d is:

define float @test(float %x) {
  %1 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10}"(float 0.000000e+00)
  ret float 0.000000e+00
}

[krasimir]

@achieveartificialintelligence any progress with the problematic IR? Have you been able to reproduce using nikic's reduced example?

[achieveartificialintelligence]

In D93298#3342452, @krasimir wrote:

@achieveartificialintelligence any progress with the problematic IR? Have you been able to reproduce using nikic's reduced example?

Sorry, I don't have a solution right now.

[krasimir]

In D93298#3342480, @achieveartificialintelligence wrote:

In D93298#3342452, @krasimir wrote:

@achieveartificialintelligence any progress with the problematic IR? Have you been able to reproduce using nikic's reduced example?

Sorry, I don't have a solution right now.

Could we revert this until then?

[craig.topper]

Here's a fix that I tested on the original repreoduce. It detects that we picked one of the new register classes and tries to redirect back to the normal GPR register class if the GPR register class has the same width. I also checked for MVT::Other to use the GPR class if there was no type.

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 3daf2d03de03..4984872139c5 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -10893,7 +10893,28 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
     }
   }
 
-  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
+  std::pair<Register, const TargetRegisterClass*> Res;
+  Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
+
+  if (Res.second == &RISCV::GPRF32RegClass) {
+    if (!Subtarget.is64Bit() || VT == MVT::Other)
+      return std::make_pair(Res.first, &RISCV::GPRRegClass);
+    return std::make_pair(0, nullptr);
+  }
+
+  if (Res.second == &RISCV::GPRF64RegClass) {
+    if (Subtarget.is64Bit() || VT == MVT::Other)
+      return std::make_pair(Res.first, &RISCV::GPRRegClass);
+    return std::make_pair(0, nullptr);
+  }
+
+  if (Res.second == &RISCV::GPRF16RegClass) {
+    if (VT == MVT::Other)
+      return std::make_pair(Res.first, &RISCV::GPRRegClass);
+    return std::make_pair(0, nullptr);
+  }
+
+  return Res;
 }

[achieveartificialintelligence]

Thanks for @craig.topper's patch!

[achieveartificialintelligence]

Can you help test if this patch works fine now? @krasimir

[achieveartificialintelligence]

Rebase

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

10923–10924 ↗

(On Diff #411719)

[achieveartificialintelligence]

Address @jrtc27's comments

[achieveartificialintelligence]

Are there any other errors now? @krasimir @nikic

[craig.topper]

llvm/test/CodeGen/RISCV/zfinx-types.ll

5 ↗

(On Diff #411375)

I'm not sure the Zfh or D RUN lines are really doing anything. Especially the Zfh.

The same bug did happen with double, D extension and RV64 so should probably test that.

[achieveartificialintelligence]

Address @craig.topper's comment

[craig.topper]

llvm/test/CodeGen/RISCV/zfinx-types.ll

5 ↗

(On Diff #411375)

I see you added rv64, but didn't add a test case that uses double instead of float.

[krasimir]

@achieveartificialintelligence thank you for looking into this, sorry for the late reply!

It looks like the latest version addresses @nikic's IR reproducer with -mtriple=riscv32.

There seems to be an error trying this out with -mtriple=riscv64:

% cat test.ll
define float @test(float %x) {
  %1 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10}"(float 0.000000e+00)
  ret float 0.000000e+00
}
% llc -mtriple=riscv32 -mattr=+d test.ll
% llc -mtriple=riscv64 -mattr=+d test.ll
error: couldn't allocate output register for constraint '{x10}'

I'm not sure if this is intended to work -mtriple=riscv64, but judging by the newly added test RUN: llc -mtriple=riscv64 ... line it seems like it should?

[craig.topper]

In D93298#3354313, @krasimir wrote:

@achieveartificialintelligence thank you for looking into this, sorry for the late reply!

It looks like the latest version addresses @nikic's IR reproducer with -mtriple=riscv32.

There seems to be an error trying this out with -mtriple=riscv64:

% cat test.ll
define float @test(float %x) {
  %1 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10}"(float 0.000000e+00)
  ret float 0.000000e+00
}
% llc -mtriple=riscv32 -mattr=+d test.ll
% llc -mtriple=riscv64 -mattr=+d test.ll
error: couldn't allocate output register for constraint '{x10}'

I'm not sure if this is intended to work -mtriple=riscv64, but judging by the newly added test RUN: llc -mtriple=riscv64 ... line it seems like it should?

My patch was only partially correct. I'll fix it

[craig.topper]

In D93298#3355088, @craig.topper wrote:

In D93298#3354313, @krasimir wrote:

@achieveartificialintelligence thank you for looking into this, sorry for the late reply!

It looks like the latest version addresses @nikic's IR reproducer with -mtriple=riscv32.

There seems to be an error trying this out with -mtriple=riscv64:

% cat test.ll
define float @test(float %x) {
  %1 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10}"(float 0.000000e+00)
  ret float 0.000000e+00
}
% llc -mtriple=riscv32 -mattr=+d test.ll
% llc -mtriple=riscv64 -mattr=+d test.ll
error: couldn't allocate output register for constraint '{x10}'

I'm not sure if this is intended to work -mtriple=riscv64, but judging by the newly added test RUN: llc -mtriple=riscv64 ... line it seems like it should?

My patch was only partially correct. I'll fix it

I just pushed 6cb42cd6669785f3b611106e1b6b38bbe65733a9 to hopefully fix this.

[jrtc27]

Does a double with r for RV32 work with that fix? That's supposed to give the low half of the register. You might need to also deal with the register pair class?

[jrtc27]

Never mind, I see you added a test for that case

[krasimir]

I just pushed 6cb42cd6669785f3b611106e1b6b38bbe65733a9 to hopefully fix this.

Thank you Craig! That fixed it.

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

 
   // It's a 32 bit instruction if bit 0 and 1 are 1.
   if ((Bytes[0] & 0x3) == 0x3) {
     if (Bytes.size() < 4) {
       Size = 0;
       return MCDisassembler::Fail;
     }
     Insn = support::endian::read32le(Bytes.data());
+
+    if (STI.getFeatureBits()[RISCV::FeatureExtZfinx]) {
+      LLVM_DEBUG(dbgs() << "Trying RVZfinx table (Float in Integer):\n");
+      // Calling the auto-generated decoder function.
+      Result = decodeInstruction(DecoderTableRVZfinx32, MI, Insn, Address, this,
+                                 STI);
+      if (Result != MCDisassembler::Fail) {
+        Size = 4;
+        return Result;
+      }
+    }
+
     LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
     Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
     Size = 4;
   } else {
     if (Bytes.size() < 2) {
       Size = 0;
       return MCDisassembler::Fail;
     }
     Insn = support::endian::read16le(Bytes.data());
 
     if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {
       LLVM_DEBUG(
           dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n");
       // Calling the auto-generated decoder function.
       Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
                                  this, STI);
       if (Result != MCDisassembler::Fail) {
         Size = 2;
         return Result;
       }

llvm/lib/Target/RISCV/RISCV.td

 def FeatureExtZfh
     : SubtargetFeature<"experimental-zfh", "HasStdExtZfh", "true",
                        "'Zfh' (Half-Precision Floating-Point)",
                        [FeatureStdExtF]>;
 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
                              AssemblerPredicate<(all_of FeatureExtZfh),
                              "'Zfh' (Half-Precision Floating-Point)">;
 
+def FeatureExtZfinx
+    : SubtargetFeature<"experimental-zfinx", "HasStdExtZfinx", "true",
+                       "'Zfinx' (Float in Integer)">;
+def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
+                             AssemblerPredicate<(all_of FeatureExtZfinx),
+                             "'Zfinx' (Float in Integer)">;
+
 def FeatureStdExtC
     : SubtargetFeature<"c", "HasStdExtC", "true",
                        "'C' (Compressed Instructions)">;
 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
                            AssemblerPredicate<(all_of FeatureStdExtC),
                            "'C' (Compressed Instructions)">;
 
 def FeatureExtZbb

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 include "RISCVInstrInfoM.td"
 include "RISCVInstrInfoA.td"
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoB.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"
+include "RISCVInstrInfoZfinx.td"

llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td

+//=== RISCVInstrInfoZfinx.td - RISC-V 'Zfinx' instructions -*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Zfinx'
+// float in integer.
+// This version is still experimental as the 'Zfinx' extension hasn't been
+// ratified yet.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZfinx] in {
+let DecoderNamespace = "RVZfinx",
+    hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+
+// Common
+class Zfinx_FPUnaryOp_r<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd), (ins GPR:$rs1),
+              opcodestr, "$rd, $rs1">;
+
+class Zfinx_FPUnaryOp_r_frm<bits<7> funct7, string opcodestr>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs GPR:$rd),
+                 (ins GPR:$rs1, frmarg:$funct3), opcodestr,
+                  "$rd, $rs1, $funct3">;
+
+// Zfh Part
+class Zfinx_FPFMAH_rrr_frm<RISCVOpcode opcode, string opcodestr>
+    : RVInstR4<0b10, opcode, (outs GPR:$rd),
+               (ins GPR:$rs1, GPR:$rs2, GPR:$rs3, frmarg:$funct3),
+                opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
+
+class Zfinx_FPALUH_rr_frm<bits<7> funct7, string opcodestr>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs GPR:$rd),
+                 (ins GPR:$rs1, GPR:$rs2, frmarg:$funct3), opcodestr,
+                  "$rd, $rs1, $rs2, $funct3">;
+
+class Zfinx_FPALUH_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+class Zfinx_FPCmpH_rr<bits<3> funct3, string opcodestr>
+    : RVInstR<0b1010010, funct3, OPC_OP_FP, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">,
+      Sched<[]>;
+
+// F Part
+class Zfinx_FPFMAS_rrr_frm<RISCVOpcode opcode, string opcodestr>
+    : RVInstR4<0b00, opcode, (outs GPR:$rd),
+               (ins GPR:$rs1, GPR:$rs2, GPR:$rs3, frmarg:$funct3),
+                opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
+
+class Zfinx_FPALUS_rr_frm<bits<7> funct7, string opcodestr>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs GPR:$rd),
+                 (ins GPR:$rs1, GPR:$rs2, frmarg:$funct3), opcodestr,
+                  "$rd, $rs1, $rs2, $funct3">;
+
+class Zfinx_FPALUS_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+class Zfinx_FPCmpS_rr<bits<3> funct3, string opcodestr>
+    : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">,
+      Sched<[WriteFCmp32, ReadFCmp32, ReadFCmp32]>;
+
+// D Part
+class Zfinx_FPFMAD_rrr_frm<RISCVOpcode opcode, string opcodestr>
+    : RVInstR4<0b01, opcode, (outs GPR:$rd),
+               (ins GPR:$rs1, GPR:$rs2, GPR:$rs3, frmarg:$funct3),
+                opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
+
+class Zfinx_FPALUD_rr_frm<bits<7> funct7, string opcodestr>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs GPR:$rd),
+                (ins GPR:$rs1, GPR:$rs2, frmarg:$funct3), opcodestr,
+                 "$rd, $rs1, $rs2, $funct3">;
+
+class Zfinx_FPALUD_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+class Zfinx_FPCmpD_rr<bits<3> funct3, string opcodestr>
+    : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">,
+      Sched<[WriteFCmp64, ReadFCmp64, ReadFCmp64]>;
+} // DecoderNamespace = "RVZfinx", hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates alias
+//===----------------------------------------------------------------------===//
+
+// Zfh Part
+class Zfinx_FPFMAHDynFrmAlias<Zfinx_FPFMAH_rrr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
+                (Inst GPR:$rd, GPR:$rs1, GPR:$rs2, GPR:$rs3, 0b111)>;
+
+class Zfinx_FPALUHDynFrmAlias<Zfinx_FPALUH_rr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                (Inst GPR:$rd, GPR:$rs1, GPR:$rs2, 0b111)>;
+
+// F Part
+class Zfinx_FPFMASDynFrmAlias<Zfinx_FPFMAS_rrr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
+                (Inst GPR:$rd, GPR:$rs1, GPR:$rs2, GPR:$rs3, 0b111)>;
+
+class Zfinx_FPALUSDynFrmAlias<Zfinx_FPALUS_rr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                (Inst GPR:$rd, GPR:$rs1, GPR:$rs2, 0b111)>;
+class Zfinx_FPUnaryOpDynFrmAlias<Zfinx_FPUnaryOp_r_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1",
+                (Inst GPR:$rd, GPR:$rs1, 0b111)>;
+
+// D Part
+class Zfinx_FPFMADDynFrmAlias<Zfinx_FPFMAD_rrr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
+                (Inst GPR:$rd, GPR:$rs1, GPR:$rs2, GPR:$rs3, 0b111)>;
+
+class Zfinx_FPALUDDynFrmAlias<Zfinx_FPALUD_rr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                (Inst GPR:$rd, GPR:$rs1, GPR:$rs2, 0b111)>;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+multiclass Zfinx_FPFMAH<RISCVOpcode opcode, string opcodestr>{
+  def _H : Zfinx_FPFMAH_rrr_frm<opcode, opcodestr#".h">, Sched<[]>;
+  def _S : Zfinx_FPFMAS_rrr_frm<opcode, opcodestr#".s">, Sched<[]>;
+  def _D : Zfinx_FPFMAD_rrr_frm<opcode, opcodestr#".d">, Sched<[]>;
+}
+
+defm Zfinx_FMADD  : Zfinx_FPFMAH<OPC_MADD, "fmadd">;
+def               : Zfinx_FPFMAHDynFrmAlias<Zfinx_FMADD_H, "fmadd.h">;
+def               : Zfinx_FPFMASDynFrmAlias<Zfinx_FMADD_S, "fmadd.s">;
+def               : Zfinx_FPFMADDynFrmAlias<Zfinx_FMADD_D, "fmadd.d">;
+defm Zfinx_FMSUB  : Zfinx_FPFMAH<OPC_MSUB, "fmsub">;
+def               : Zfinx_FPFMAHDynFrmAlias<Zfinx_FMSUB_H, "fmsub.h">;
+def               : Zfinx_FPFMASDynFrmAlias<Zfinx_FMSUB_S, "fmsub.s">;
+def               : Zfinx_FPFMADDynFrmAlias<Zfinx_FMSUB_D, "fmsub.d">;
+defm Zfinx_FNMSUB : Zfinx_FPFMAH<OPC_NMSUB, "fnmsub">;
+def               : Zfinx_FPFMAHDynFrmAlias<Zfinx_FNMSUB_H, "fnmsub.h">;
+def               : Zfinx_FPFMASDynFrmAlias<Zfinx_FNMSUB_S, "fnmsub.s">;
+def               : Zfinx_FPFMADDynFrmAlias<Zfinx_FNMSUB_D, "fnmsub.d">;
+defm Zfinx_FNMADD : Zfinx_FPFMAH<OPC_NMADD, "fnmadd">;
+def               : Zfinx_FPFMAHDynFrmAlias<Zfinx_FNMADD_H, "fnmadd.h">;
+def               : Zfinx_FPFMASDynFrmAlias<Zfinx_FNMADD_S, "fnmadd.s">;
+def               : Zfinx_FPFMADDynFrmAlias<Zfinx_FNMADD_D, "fnmadd.d">;
+
+multiclass Zfinx_FPALU_frm<bits<7> funct7, string opcodestr> {
+  def _H : Zfinx_FPALUH_rr_frm<!add(funct7,0b10), "fadd.h">, Sched<[]>;
+  def _S : Zfinx_FPALUS_rr_frm<!add(funct7,0b00), "fadd.s">, Sched<[]>;
+  def _D : Zfinx_FPALUD_rr_frm<!add(funct7,0b01), "fadd.d">, Sched<[]>;
+}
+defm Zfinx_FADD : Zfinx_FPALU_frm<0b0000000, "fadd">;
+def             : Zfinx_FPALUHDynFrmAlias<Zfinx_FADD_H, "fadd.h">;
+def             : Zfinx_FPALUSDynFrmAlias<Zfinx_FADD_S, "fadd.s">;
+def             : Zfinx_FPALUDDynFrmAlias<Zfinx_FADD_D, "fadd.d">;
+defm Zfinx_FSUB : Zfinx_FPALU_frm<0b0000100, "fsub">;
+def             : Zfinx_FPALUHDynFrmAlias<Zfinx_FSUB_H, "fsub.h">;
+def             : Zfinx_FPALUSDynFrmAlias<Zfinx_FSUB_S, "fsub.s">;
+def             : Zfinx_FPALUDDynFrmAlias<Zfinx_FSUB_D, "fsub.d">;
+defm Zfinx_FMUL : Zfinx_FPALU_frm<0b0001000, "fmul">;
+def             : Zfinx_FPALUHDynFrmAlias<Zfinx_FMUL_H, "fmul.h">;
+def             : Zfinx_FPALUSDynFrmAlias<Zfinx_FMUL_S, "fmul.s">;
+def             : Zfinx_FPALUDDynFrmAlias<Zfinx_FMUL_D, "fmul.d">;
+defm Zfinx_FDIV : Zfinx_FPALU_frm<0b0001100, "fdiv">;
+def             : Zfinx_FPALUHDynFrmAlias<Zfinx_FDIV_H, "fdiv.h">;
+def             : Zfinx_FPALUSDynFrmAlias<Zfinx_FDIV_S, "fdiv.s">;
+def             : Zfinx_FPALUDDynFrmAlias<Zfinx_FDIV_D, "fdiv.d">;
+
+multiclass Zfinx_FPUnaryOp_frm<string opcodestr> {
+  let rs2 = 0b00000 in {
+  def _H : Zfinx_FPUnaryOp_r_frm<0b0101110, opcodestr#".h">, Sched<[]>;
+  def _S : Zfinx_FPUnaryOp_r_frm<0b0101100, opcodestr#".s">, Sched<[]>;
+  def _D : Zfinx_FPUnaryOp_r_frm<0b0101101, opcodestr#".d">, Sched<[]>;
+  }
+}
+defm Zfinx_FSQRT  : Zfinx_FPUnaryOp_frm<"fsqrt">;
+def               : Zfinx_FPUnaryOpDynFrmAlias<Zfinx_FSQRT_H, "fsqrt.h">;
+def               : Zfinx_FPUnaryOpDynFrmAlias<Zfinx_FSQRT_S, "fsqrt.s">;
+def               : Zfinx_FPUnaryOpDynFrmAlias<Zfinx_FSQRT_D, "fsqrt.d">;
+
+multiclass Zfinx_FPALU<bits<7> funct7, bits<3> funct3, string opcodestr> {
+  def _H : Zfinx_FPALUH_rr<!add(funct7,0b10), funct3, opcodestr#".h">,
+                           Sched<[]>;
+  def _S : Zfinx_FPALUS_rr<!add(funct7,0b00), funct3, opcodestr#".s">,
+                           Sched<[]>;
+  def _D : Zfinx_FPALUD_rr<!add(funct7,0b01), funct3, opcodestr#".d">,
+                           Sched<[]>;
+}
+defm Zfinx_FSGNJ  : Zfinx_FPALU<0b0010000, 0b000, "fsgnj">;
+defm Zfinx_FSGNJN : Zfinx_FPALU<0b0010000, 0b001, "fsgnjn">;
+defm Zfinx_FSGNJX : Zfinx_FPALU<0b0010000, 0b010, "fsgnjx">;
+defm Zfinx_FMIN   : Zfinx_FPALU<0b0010100, 0b000, "fmin">;
+defm Zfinx_FMAX   : Zfinx_FPALU<0b0010100, 0b001, "fmax">;
+
+multiclass Zfinx_FPCmp<bits<3> funct3, string opcodestr>{
+  def _H : Zfinx_FPCmpH_rr<funct3, opcodestr#".h">;
+  def _S : Zfinx_FPCmpS_rr<funct3, opcodestr#".s">;
+  def _D : Zfinx_FPCmpD_rr<funct3, opcodestr#".d">;
+}
+defm Zfinx_FEQ : Zfinx_FPCmp<0b010, "feq">;
+defm Zfinx_FLT : Zfinx_FPCmp<0b001, "flt">;
+defm Zfinx_FLE : Zfinx_FPCmp<0b000, "fle">;
+
+multiclass Zfinx_FPUnOp<bits<7> funct7, string opcodestr>{
+  let rs2 = 0b00000 in {
+    def _H : Zfinx_FPUnaryOp_r<!add(funct7,0b10), 0b001, opcodestr#".h">,
+                               Sched<[]>;
+    def _S : Zfinx_FPUnaryOp_r<!add(funct7,0b00), 0b001, opcodestr#".s">,
+                               Sched<[]>;
+    def _D : Zfinx_FPUnaryOp_r<!add(funct7,0b01), 0b001, opcodestr#".d">,
+                               Sched<[]>;
+  }
+}
+defm Zfinx_FCLASS : Zfinx_FPUnOp<0b1110000, "fclass">;
+
+} // Predicates = [HasStdExtZfinx]

llvm/lib/Target/RISCV/RISCVSubtarget.h

   bool HasStdExtZbr = false;
   bool HasStdExtZbs = false;
   bool HasStdExtZbt = false;
   bool HasStdExtZbproposedc = false;
   bool HasStdExtV = false;
   bool HasStdExtZvlsseg = false;
   bool HasStdExtZvamo = false;
   bool HasStdExtZfh = false;
+  bool HasStdExtZfinx = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
   bool EnableSaveRestore = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
   BitVector UserReservedRegister;
   RISCVFrameLowering FrameLowering;
   RISCVInstrInfo InstrInfo;
   RISCVRegisterInfo RegInfo;
   RISCVTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
 
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
   RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
                                                   StringRef CPU,
                                                   StringRef TuneCPU,

   bool hasStdExtZbr() const { return HasStdExtZbr; }
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
+  bool hasStdExtZfinx() const { return HasStdExtZfinx; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
   bool enableSaveRestore() const { return EnableSaveRestore; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
   RISCVABI::ABI getTargetABI() const { return TargetABI; }
   bool isRegisterReservedByUser(Register i) const {
     assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
     return UserReservedRegister[i];
   }
 
 protected:
   // GlobalISel related APIs.
   std::unique_ptr<CallLowering> CallLoweringInfo;
   std::unique_ptr<InstructionSelector> InstSelector;
   std::unique_ptr<LegalizerInfo> Legalizer;
   std::unique_ptr<RegisterBankInfo> RegBankInfo;
 

llvm/test/MC/RISCV/rv32d-invalid.s

 fsd ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 
 # Invalid register names
 fld ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
 fld ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
 fsgnjn.d fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 
 # Integer registers where FP regs are expected
-fadd.d a2, a1, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+fadd.d a2, a1, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer)
 
 # FP registers where integer regs are expected
 fcvt.wu.d ft2, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

llvm/test/MC/RISCV/rv32zfh-invalid.s

 fmadd.h f10, f11, f12, ree # CHECK: :[[@LINE]]:24: error: invalid operand for instruction
 
 # Invalid rounding modes
 fmadd.h f10, f11, f12, f13, ree # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic
 fmsub.h f14, f15, f16, f17, 0 # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic
 fnmsub.h f18, f19, f20, f21, 0b111 # CHECK: :[[@LINE]]:30: error: operand must be a valid floating point rounding mode mnemonic
 
 # Integer registers where FP regs are expected
-fadd.h a2, a1, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+fadd.h a2, a1, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer)
 
 # FP registers where integer regs are expected
 fcvt.wu.h ft2, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

llvm/test/MC/RISCV/rvzfinx-valid.s

+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zfinx %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zfinx %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zfinx %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmadd.h a0, a1, a2, a3
+# CHECK-INST: fmadd.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x43,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 43 f5 c5 6c <unknown>
+
+fmsub.h a0, a1, a2, a3
+# CHECK-INST: fmsub.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x47,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 47 f5 c5 6c <unknown>
+
+fnmsub.h a0, a1, a2, a3
+# CHECK-INST: fnmsub.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x4b,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4b f5 c5 6c <unknown>
+
+fnmadd.h a0, a1, a2, a3
+# CHECK-INST: fnmadd.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x4f,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4f f5 c5 6c <unknown>
+
+fadd.h a0, a1, a2
+# CHECK-INST: fadd.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x04]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 04 <unknown>
+
+fsub.h a0, a1, a2
+# CHECK-INST: fsub.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x0c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 0c <unknown>
+
+fmul.h a0, a1, a2
+# CHECK-INST: fmul.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x14]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 14 <unknown>
+
+fdiv.h a0, a1, a2
+# CHECK-INST: fdiv.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x1c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 1c <unknown>
+
+fsqrt.h a0, a1
+# CHECK-INST: fsqrt.h a0, a1
+# CHECK-ENCODING: [0x53,0xf5,0x05,0x5c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 05 5c <unknown>
+
+fsgnj.h a0, a1, a2
+# CHECK-INST: fsgnj.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 24 <unknown>
+
+fsgnjn.h a0, a1, a2
+# CHECK-INST: fsgnjn.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 24 <unknown>
+
+fsgnjx.h a0, a1, a2
+# CHECK-INST: fsgnjx.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 24 <unknown>
+
+fmin.h a0, a1, a2
+# CHECK-INST: fmin.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x2c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 2c <unknown>
+
+fmax.h a0, a1, a2
+# CHECK-INST: fmax.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x2c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 2c <unknown>
+
+feq.h a0, a1, a2
+# CHECK-INST: feq.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 a4 <unknown>
+
+flt.h a0, a1, a2
+# CHECK-INST: flt.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 a4 <unknown>
+
+fle.h a0, a1, a2
+# CHECK-INST: fle.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 a4 <unknown>
+
+fclass.h a0, a1
+# CHECK-INST: fclass.h a0, a1
+# CHECK-ENCODING: [0x53,0x95,0x05,0xe4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 05 e4 <unknown>
+
+fmadd.s a0, a1, a2, a3
+# CHECK-INST: fmadd.s a0, a1, a2, a3
+# CHECK-ENCODING: [0x43,0xf5,0xc5,0x68]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 43 f5 c5 68 <unknown>
+
+fmsub.s a0, a1, a2, a3
+# CHECK-INST: fmsub.s a0, a1, a2, a3
+# CHECK-ENCODING: [0x47,0xf5,0xc5,0x68]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 47 f5 c5 68 <unknown>
+
+fnmsub.s a0, a1, a2, a3
+# CHECK-INST: fnmsub.s a0, a1, a2, a3
+# CHECK-ENCODING: [0x4b,0xf5,0xc5,0x68]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4b f5 c5 68 <unknown>
+
+fnmadd.s a0, a1, a2, a3
+# CHECK-INST: fnmadd.s a0, a1, a2, a3
+# CHECK-ENCODING: [0x4f,0xf5,0xc5,0x68]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4f f5 c5 68 <unknown>
+
+fadd.s a0, a1, a2
+# CHECK-INST: fadd.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x00]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 00 <unknown>
+
+fsub.s a0, a1, a2
+# CHECK-INST: fsub.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x08]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 08 <unknown>
+
+fmul.s a0, a1, a2
+# CHECK-INST: fmul.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x10]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 10 <unknown>
+
+fdiv.s a0, a1, a2
+# CHECK-INST: fdiv.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x18]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 18 <unknown>
+
+fsqrt.s a0, a1
+# CHECK-INST: fsqrt.s a0, a1
+# CHECK-ENCODING: [0x53,0xf5,0x05,0x58]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 05 58 <unknown>
+
+fsgnj.s a0, a1, a2
+# CHECK-INST: fsgnj.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x20]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 20 <unknown>
+
+fsgnjn.s a0, a1, a2
+# CHECK-INST: fsgnjn.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x20]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 20 <unknown>
+
+fsgnjx.s a0, a1, a2
+# CHECK-INST: fsgnjx.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0x20]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 20 <unknown>
+
+fmin.s a0, a1, a2
+# CHECK-INST: fmin.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x28]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 28 <unknown>
+
+fmax.s a0, a1, a2
+# CHECK-INST: fmax.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x28]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 28 <unknown>
+
+feq.s a0, a1, a2
+# CHECK-INST: feq.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0xa0]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 a0 <unknown>
+
+flt.s a0, a1, a2
+# CHECK-INST: flt.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0xa0]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 a0 <unknown>
+
+fle.s a0, a1, a2
+# CHECK-INST: fle.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0xa0]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 a0 <unknown>
+
+fclass.s a0, a1
+# CHECK-INST: fclass.s a0, a1
+# CHECK-ENCODING: [0x53,0x95,0x05,0xe0]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 05 e0 <unknown>
+
+fmadd.d a0, a1, a2, a3
+# CHECK-INST: fmadd.d a0, a1, a2, a3
+# CHECK-ENCODING: [0x43,0xf5,0xc5,0x6a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 43 f5 c5 6a <unknown>
+
+fmsub.d a0, a1, a2, a3
+# CHECK-INST: fmsub.d a0, a1, a2, a3
+# CHECK-ENCODING: [0x47,0xf5,0xc5,0x6a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 47 f5 c5 6a <unknown>
+
+fnmsub.d a0, a1, a2, a3
+# CHECK-INST: fnmsub.d a0, a1, a2, a3
+# CHECK-ENCODING: [0x4b,0xf5,0xc5,0x6a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4b f5 c5 6a <unknown>
+
+fnmadd.d a0, a1, a2, a3
+# CHECK-INST: fnmadd.d a0, a1, a2, a3
+# CHECK-ENCODING: [0x4f,0xf5,0xc5,0x6a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4f f5 c5 6a <unknown>
+
+fadd.d a0, a1, a2
+# CHECK-INST: fadd.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x02]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 02 <unknown>
+
+fsub.d a0, a1, a2
+# CHECK-INST: fsub.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x0a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 0a <unknown>
+
+fmul.d a0, a1, a2
+# CHECK-INST: fmul.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x12]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 12 <unknown>
+
+fdiv.d a0, a1, a2
+# CHECK-INST: fdiv.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x1a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 1a <unknown>
+
+fsqrt.d a0, a1
+# CHECK-INST: fsqrt.d a0, a1
+# CHECK-ENCODING: [0x53,0xf5,0x05,0x5a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 05 5a <unknown>
+
+fsgnj.d a0, a1, a2
+# CHECK-INST: fsgnj.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x22]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 22 <unknown>
+
+fsgnjn.d a0, a1, a2
+# CHECK-INST: fsgnjn.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x22]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 22 <unknown>
+
+fsgnjx.d a0, a1, a2
+# CHECK-INST: fsgnjx.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0x22]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 22 <unknown>
+
+fmin.d a0, a1, a2
+# CHECK-INST: fmin.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x2a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 2a <unknown>
+
+fmax.d a0, a1, a2
+# CHECK-INST: fmax.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x2a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 2a <unknown>
+
+feq.d a0, a1, a2
+# CHECK-INST: feq.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0xa2]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 a2 <unknown>
+
+flt.d a0, a1, a2
+# CHECK-INST: flt.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0xa2]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 a2 <unknown>
+
+fle.d a0, a1, a2
+# CHECK-INST: fle.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0xa2]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 a2 <unknown>
+
+fclass.d a0, a1
+# CHECK-INST: fclass.d a0, a1
+# CHECK-ENCODING: [0x53,0x95,0x05,0xe2]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 05 e2 <unknown>