[SVE] Replace / operator in TypeSize/ElementCount with divideCoefficientBy

[david-arm]

Summary

After some recent upstream discussion we decided that it was best
to avoid having the / operator for both ElementCount and TypeSize,
since this could give the impression that these classes can be used
in the same way as basic integer integer types. However, division
for scalable types is a bit odd because we are only dividing the
minimum quantity by a value, as opposed to something like:

(MinSize * Vscale) / SomeValue

This is why when performing division it's important the caller
first establishes whether the operation makes sense, perhaps by
calling isKnownMultipleOf() prior to division. The caller must now
explictly call divideCoefficientBy() on the class to perform the operation.

[sdesmalen]

llvm/include/llvm/Support/TypeSize.h

60

As we discussed in the SVE sync-up call, mul isn't strictly needed but rather added for consistency.
That raises the question whether operator- and operator+ also need to have a sub and add functions, as those are not "mathematically correct" either given they only support adding either 2 scalable, or 2 fixed-sized sizes, and they assert otherwise.

188

Given the particular reasons for adding these in favour of the overloaded operators, these functions need a clear description that explains why we've done so, and why the results may not be entirely arithmatically correct when uses of this function assume vscale to be some specific value at compile-time.

241

Please add a description for this method.

[ctetreau]

llvm/include/llvm/Support/TypeSize.h

60

I think given the outcome of the call today, operator* can probably stay.

If we're going to document the header that "if it behaves the same as in real math, then it's an operator. If not, it's a named function", then this multiply is fine.

64

I would suggest renaming this to something more self-documenting. Perhaps coefficientDiv? This has the added benefit of making it seem less strange that it's a named divide rather than operator/

186–188

Same comment as ElementCount

[david-arm]

• Reverted the operator* change.
• Added comments to the new functions.

[sdesmalen]

llvm/include/llvm/Support/TypeSize.h

64

Agree that the use of coefficient is a good addition. Perhaps this is getting into bike-shedding territory, but then I'd probably prefer the more verbose divideCoefficientBy as this reads a bit more intuitive to me (and follows a natural way of phrasing similar to isKnownMultipleOf). Any thoughts?

[paulwalker-arm]

I'm not a great fan of the coefficientDiv name but once in I doubt I'll give it a second thought. That said, because by far the most common usage is coefficientDiv(2), whose intent is clearly to knowingly split something into two equal parts I'm wondering if adding a halve() utility function will keep the main usage short and meaningful and then there's even less reason to care about the name of coefficientDiv.

llvm/include/llvm/Support/TypeSize.h

73–76

I don't think it's a good idea to promote incompatible usages of this function. Let's keep the messaging simple with only a true result being something that is meaningful, which is inline with the other isKnown methods.

242–245

As above.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

19500

Should this use isKnownMultipleOf to match the coefficientDiv you've introduced?

llvm/lib/CodeGen/TargetLoweringBase.cpp

837–838

SVT.getHalfNumVectorElementsVT(Context) ?

llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp

64

Comment needs updating, I'd just drop the overloaded '*' and '/' part.

[david-arm]

I think that introducing a halve() function makes sense and I'll replace div(2) with halve(), unless someone strongly objects? I don't have strong feelings about the name to be honest, I'm personally happy enough to stick with coefficientDiv. @ctetreau any thoughts on Sander's suggestion of divideCoefficientBy?

[david-arm]

• Introduced a new halve() function to replace the common case of coefficientDiv(2).
• Updated the comments about isKnownMultipleOf.

[ctetreau]

In D87700#2290260, @david-arm wrote:

... thoughts on Sander's suggestion of divideCoefficientBy?

I think the important thing is that the function has "coefficient" in the name. I prefer my name because it's shorter, but if more people prefer Sander's suggestion that's fine.

My general philosophy is "the name should imply what the function does" and not "the name should read like an english sentence". We're not COBOL programmers after all :)

[ctetreau]

I'm not in love with the halve function. I count 8 places where it's used in real code in this patch, which really isn't that much. I think having it in there will establish a precedent and encourage people to add a million "common case" helpers (why not double? quarter/quadruple? next/prev power of 2?) for constructing different sized ElementCounts.

Really, EC.halve() isn't that much less verbose than EC.coefficientDiv(2), and I suspect it will usually appear on its own line as an assignment since VectorType already has getHalfElementsVectorType.

[paulwalker-arm]

I think the precedent has already been set as VectorType and ValueType already deem doubling and halving to be special enough to have explicit operations, albeit they save more effort that what's being saved here. Personally I just think

ElementCount.halve()

is more meaningful/readable than

assert(ElementCount.isKnownMultiple(2));
ElementCount.coefficientDiv(2);

Whereas ElementCount * 2 is already meaningful enough.

[ctetreau]

I just wanted to voice my concerns for halve(). If nobody else has an opinion on the subject, then I'll not hold the review up over it.

[ctetreau]

I'm fine with the substance of this patch. Once we come to an agreement about what color the bikeshed should be, I think it's good to go.

[paulwalker-arm]

@david-arm The main priority is to remove the operator overloads so if universally using divideCoefficientBy pleases the most people then let's just do that.

llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp

65–66

If halve is kept then it makes sense to add an explicit test for it here.

65–66

Oops, please ignore what looks like a stale review comment :(

[sdesmalen]

I'm happy colour of the bikeshed. Please re-run clang-format on it though.

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

2639

clang-format?

[paulwalker-arm]

Formatting issues aside this LGTM.

clang/lib/CodeGen/CGBuiltin.cpp

Value *CodeGenFunction::EmitCommonNeonBuiltinExpr(
   switch (BuiltinID) {
   default: break;
   case NEON::BI__builtin_neon_splat_lane_v:
   case NEON::BI__builtin_neon_splat_laneq_v:
   case NEON::BI__builtin_neon_splatq_lane_v:
   case NEON::BI__builtin_neon_splatq_laneq_v: {
     auto NumElements = VTy->getElementCount();
     if (BuiltinID == NEON::BI__builtin_neon_splatq_lane_v)
-      NumElements = NumElements * 2;
+      NumElements = NumElements.mul(2);
     if (BuiltinID == NEON::BI__builtin_neon_splat_laneq_v)
-      NumElements = NumElements / 2;
+      NumElements = NumElements.div(2);
 
     Ops[0] = Builder.CreateBitCast(Ops[0], VTy);
     return EmitNeonSplat(Ops[0], cast<ConstantInt>(Ops[1]), NumElements);
   }
   case NEON::BI__builtin_neon_vpadd_v:
   case NEON::BI__builtin_neon_vpaddq_v:
     // We don't allow fp/int overloading of intrinsics.
     if (VTy->getElementType()->isFloatingPointTy() &&
case Intrinsic::aarch64_sve_ld3:
     break;
   case Intrinsic::aarch64_sve_ld4:
     N = 4;
     break;
   default:
     llvm_unreachable("unknown intrinsic!");
   }
   auto RetTy = llvm::VectorType::get(VTy->getElementType(),
-                                     VTy->getElementCount() * N);
+                                     VTy->getElementCount().mul(N));
 
-  Value *Predicate = EmitSVEPredicateCast(Ops[0], VTy);
+  Value *Predicate = EmitSVEPredicateCast(Ops[0], VTy);
   Value *BasePtr= Builder.CreateBitCast(Ops[1], VecPtrTy);
   Value *Offset = Ops.size() > 2 ? Ops[2] : Builder.getInt32(0);
   BasePtr = Builder.CreateGEP(VTy, BasePtr, Offset);
   BasePtr = Builder.CreateBitCast(BasePtr, EltPtrTy);
 
   Function *F = CGM.getIntrinsic(IntID, {RetTy, Predicate->getType()});
   return Builder.CreateCall(F, { Predicate, BasePtr });
 }
case Intrinsic::aarch64_sve_st3:
     N = 3;
     break;
   case Intrinsic::aarch64_sve_st4:
     N = 4;
     break;
   default:
     llvm_unreachable("unknown intrinsic!");
   }
-  auto TupleTy =
-      llvm::VectorType::get(VTy->getElementType(), VTy->getElementCount() * N);
+  auto TupleTy = llvm::VectorType::get(VTy->getElementType(),
+                                       VTy->getElementCount().mul(N));
 
   Value *Predicate = EmitSVEPredicateCast(Ops[0], VTy);
   Value *BasePtr = Builder.CreateBitCast(Ops[1], VecPtrTy);
   Value *Offset = Ops.size() > 3 ? Ops[2] : Builder.getInt32(0);
   Value *Val = Ops.back();
   BasePtr = Builder.CreateGEP(VTy, BasePtr, Offset);
   BasePtr = Builder.CreateBitCast(BasePtr, EltPtrTy);
 
Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
   case SVE::BI__builtin_sve_svtbl2_u64:
   case SVE::BI__builtin_sve_svtbl2_s64:
   case SVE::BI__builtin_sve_svtbl2_f16:
   case SVE::BI__builtin_sve_svtbl2_bf16:
   case SVE::BI__builtin_sve_svtbl2_f32:
   case SVE::BI__builtin_sve_svtbl2_f64: {
     SVETypeFlags TF(Builtin->TypeModifier);
     auto VTy = cast<llvm::VectorType>(getSVEType(TF));
-    auto TupleTy = llvm::VectorType::get(VTy->getElementType(),
-                                         VTy->getElementCount() * 2);
+    auto TupleTy = llvm::VectorType::getDoubleElementsVectorType(VTy);
     Function *FExtr =
         CGM.getIntrinsic(Intrinsic::aarch64_sve_tuple_get, {VTy, TupleTy});
     Value *V0 = Builder.CreateCall(FExtr, {Ops[0], Builder.getInt32(0)});
     Value *V1 = Builder.CreateCall(FExtr, {Ops[0], Builder.getInt32(1)});
     Function *F = CGM.getIntrinsic(Intrinsic::aarch64_sve_tbl2, VTy);
     return Builder.CreateCall(F, {V0, V1, Ops[1]});
   }
   }

llvm/include/llvm/CodeGen/ValueTypes.h

#endif
     }
 
     /// Return the number of bits overwritten by a store of the specified value
     /// type.
     ///
     /// If the value type is a scalable vector type, the scalable property will
     /// be set and the runtime size will be a positive integer multiple of the
     /// base size.
-    TypeSize getStoreSizeInBits() const {
-      return getStoreSize() * 8;
-    }
+    TypeSize getStoreSizeInBits() const { return getStoreSize().mul(8); }
 
     /// Rounds the bit-width of the given integer EVT up to the nearest power of
     /// two (and at least to eight), and returns the integer EVT with that
     /// number of bits.
     EVT getRoundIntegerType(LLVMContext &Context) const {
       assert(isInteger() && !isVector() && "Invalid integer type!");
       unsigned BitWidth = getSizeInBits();
       if (BitWidth <= 8)
#endif
 
     // Return a VT for a vector type with the same element type but
     // half the number of elements. The type returned may be an
     // extended type.
     EVT getHalfNumVectorElementsVT(LLVMContext &Context) const {
       EVT EltVT = getVectorElementType();
       auto EltCnt = getVectorElementCount();
       assert(EltCnt.isKnownEven() && "Splitting vector, but not in half!");
-      return EVT::getVectorVT(Context, EltVT, EltCnt / 2);
+      return EVT::getVectorVT(Context, EltVT, EltCnt.div(2));
+    }
+
+    // Return a VT for a vector type with the same element type but
+    // double the number of elements. The type returned may be an
+    // extended type.
+    EVT getDoubleNumVectorElementsVT(LLVMContext &Context) const {
+      EVT EltVT = getVectorElementType();
+      auto EltCnt = getVectorElementCount();
+      return EVT::getVectorVT(Context, EltVT, EltCnt.mul(2));
     }
 
     /// Returns true if the given vector is a power of 2.
     bool isPow2VectorType() const {
       unsigned NElts = getVectorMinNumElements();
       return !(NElts & (NElts - 1));
     }
 

llvm/include/llvm/IR/DataLayout.h

public:
   /// Returns the maximum number of bits that may be overwritten by
   /// storing the specified type; always a multiple of 8.
   ///
   /// If Ty is a scalable vector type, the scalable property will be set and
   /// the runtime size will be a positive integer multiple of the base size.
   ///
   /// For example, returns 40 for i36 and 80 for x86_fp80.
   TypeSize getTypeStoreSizeInBits(Type *Ty) const {
-    return 8 * getTypeStoreSize(Ty);
+    return getTypeStoreSize(Ty).mul(8);
   }
 
   /// Returns true if no extra padding bits are needed when storing the
   /// specified type.
   ///
   /// For example, returns false for i19 that has a 24-bit store size.
   bool typeSizeEqualsStoreSize(Type *Ty) const {
     return getTypeSizeInBits(Ty) == getTypeStoreSizeInBits(Ty);
public:
   /// specified type, including alignment padding; always a multiple of 8.
   ///
   /// If Ty is a scalable vector type, the scalable property will be set and
   /// the runtime size will be a positive integer multiple of the base size.
   ///
   /// This is the amount that alloca reserves for this type. For example,
   /// returns 96 or 128 for x86_fp80, depending on alignment.
   TypeSize getTypeAllocSizeInBits(Type *Ty) const {
-    return 8 * getTypeAllocSize(Ty);
+    return getTypeAllocSize(Ty).mul(8);
   }
 
   /// Returns the minimum ABI-required alignment for the specified type.
   /// FIXME: Deprecate this function once migration to Align is over.
   unsigned getABITypeAlignment(Type *Ty) const;
 
   /// Returns the minimum ABI-required alignment for the specified type.
   Align getABITypeAlign(Type *Ty) const;
inline TypeSize DataLayout::getTypeSizeInBits(Type *Ty) const {
   assert(Ty->isSized() && "Cannot getTypeInfo() on a type that is unsized!");
   switch (Ty->getTypeID()) {
   case Type::LabelTyID:
     return TypeSize::Fixed(getPointerSizeInBits(0));
   case Type::PointerTyID:
     return TypeSize::Fixed(getPointerSizeInBits(Ty->getPointerAddressSpace()));
   case Type::ArrayTyID: {
     ArrayType *ATy = cast<ArrayType>(Ty);
-    return ATy->getNumElements() *
-           getTypeAllocSizeInBits(ATy->getElementType());
+    return getTypeAllocSizeInBits(ATy->getElementType())
+        .mul(ATy->getNumElements());
   }
   case Type::StructTyID:
     // Get the layout annotation... which is lazily created on demand.
     return TypeSize::Fixed(
                         getStructLayout(cast<StructType>(Ty))->getSizeInBits());
   case Type::IntegerTyID:
     return TypeSize::Fixed(Ty->getIntegerBitWidth());
   case Type::HalfTyID:

llvm/include/llvm/IR/DerivedTypes.h

public:
   }
 
   /// This static method returns a VectorType with half as many elements as the
   /// input type and the same element type.
   static VectorType *getHalfElementsVectorType(VectorType *VTy) {
     auto EltCnt = VTy->getElementCount();
     assert(EltCnt.isKnownEven() &&
            "Cannot halve vector with odd number of elements.");
-    return VectorType::get(VTy->getElementType(), EltCnt/2);
+    return VectorType::get(VTy->getElementType(), EltCnt.div(2));
   }
 
   /// This static method returns a VectorType with twice as many elements as the
   /// input type and the same element type.
   static VectorType *getDoubleElementsVectorType(VectorType *VTy) {
     auto EltCnt = VTy->getElementCount();
     assert((EltCnt.getKnownMinValue() * 2ull) <= UINT_MAX &&
            "Too many elements in vector");
-    return VectorType::get(VTy->getElementType(), EltCnt * 2);
+    return VectorType::get(VTy->getElementType(), EltCnt.mul(2));
   }
 
   /// Return true if the specified type is valid as a element type.
   static bool isValidElementType(Type *ElemTy);
 
   /// Return an ElementCount instance to represent the (possibly scalable)
   /// number of elements in the vector.
   inline ElementCount getElementCount() const;

llvm/include/llvm/Support/MachineValueType.h

public:
     }
 
     /// Return a VT for a vector type with the same element type but
     /// half the number of elements.
     MVT getHalfNumVectorElementsVT() const {
       MVT EltVT = getVectorElementType();
       auto EltCnt = getVectorElementCount();
       assert(EltCnt.isKnownEven() && "Splitting vector, but not in half!");
-      return getVectorVT(EltVT, EltCnt / 2);
+      return getVectorVT(EltVT, EltCnt.div(2));
     }
 
     /// Returns true if the given vector is a power of 2.
     bool isPow2VectorType() const {
       unsigned NElts = getVectorNumElements();
       return !(NElts & (NElts - 1));
     }
 
public:
     }
 
     /// Return the number of bits overwritten by a store of the specified value
     /// type.
     ///
     /// If the value type is a scalable vector type, the scalable property will
     /// be set and the runtime size will be a positive integer multiple of the
     /// base size.
-    TypeSize getStoreSizeInBits() const {
-      return getStoreSize() * 8;
-    }
+    TypeSize getStoreSizeInBits() const { return getStoreSize().mul(8); }
 
     /// Returns true if the number of bits for the type is a multiple of an
     /// 8-bit byte.
     bool isByteSized() const {
       return getSizeInBits().isByteSized();
     }
 
     /// Return true if this has more bits than VT.

llvm/include/llvm/Support/TypeSize.h

private:
   /// methods below are preferred, as users should always make a
   /// conscious choice on the type of `ElementCount` they are
   /// requesting.
   ElementCount(unsigned Min, bool Scalable) : Min(Min), Scalable(Scalable) {}
 
 public:
   ElementCount() = default;
 
-  ElementCount operator*(unsigned RHS) {
-    return { Min * RHS, Scalable };
-  }
-  ElementCount operator/(unsigned RHS) {
-    assert(Min % RHS == 0 && "Min is not a multiple of RHS.");
-    return { Min / RHS, Scalable };
-  }
-
   friend ElementCount operator-(const ElementCount &LHS,
                                 const ElementCount &RHS) {
     assert(LHS.Scalable == RHS.Scalable &&
            "Arithmetic using mixed scalable and fixed types");
     return {LHS.Min - RHS.Min, LHS.Scalable};
   }
 
   bool operator==(const ElementCount& RHS) const {
     return Min == RHS.Min && Scalable == RHS.Scalable;
   }
   bool operator!=(const ElementCount& RHS) const {
     return !(*this == RHS);
   }
   bool operator==(unsigned RHS) const { return Min == RHS && !Scalable; }
   bool operator!=(unsigned RHS) const { return !(*this == RHS); }
 
-  ElementCount &operator*=(unsigned RHS) {
-    Min *= RHS;
-    return *this;
+  ElementCount mul(unsigned RHS) const {
+    return ElementCount(Min * RHS, Scalable);
   }
 
-  ElementCount &operator/=(unsigned RHS) {
-    Min /= RHS;
-    return *this;
+  ElementCount div(unsigned RHS) const {
+    return ElementCount(Min / RHS, Scalable);
   }
 
   ElementCount NextPowerOf2() const {
     return {(unsigned)llvm::NextPowerOf2(Min), Scalable};
   }
 
   bool isKnownMultipleOf(unsigned RHS) const {
     return Min % RHS == 0;
   }
 
   static ElementCount getFixed(unsigned Min) { return {Min, false}; }
   static ElementCount getScalable(unsigned Min) { return {Min, true}; }
   static ElementCount get(unsigned Min, bool Scalable) {
     return {Min, Scalable};
   }
 
   /// Printing function.
   void print(raw_ostream &OS) const {
     if (Scalable)
public:
   friend bool operator<=(const TypeSize &LHS, const TypeSize &RHS) {
     return !(RHS < LHS);
   }
 
   friend bool operator>=(const TypeSize &LHS, const TypeSize& RHS) {
     return !(LHS < RHS);
   }
 
-  // Convenience operators to obtain relative sizes independently of
-  // the scalable flag.
-  TypeSize operator*(unsigned RHS) const {
-    return { MinSize * RHS, IsScalable };
-  }
-
-  friend TypeSize operator*(const unsigned LHS, const TypeSize &RHS) {
-    return { LHS * RHS.MinSize, RHS.IsScalable };
-  }
+  TypeSize mul(uint64_t RHS) const { return {MinSize * RHS, IsScalable}; }
 
-  TypeSize operator/(unsigned RHS) const {
-    return { MinSize / RHS, IsScalable };
-  }
+  TypeSize div(uint64_t RHS) const { return {MinSize / RHS, IsScalable}; }
 
   TypeSize &operator-=(TypeSize RHS) {
     assert(IsScalable == RHS.IsScalable &&
            "Subtraction using mixed scalable and fixed types");
     MinSize -= RHS.MinSize;
     return *this;
   }
 
   TypeSize &operator+=(TypeSize RHS) {
     assert(IsScalable == RHS.IsScalable &&
            "Addition using mixed scalable and fixed types");
     MinSize += RHS.MinSize;
     return *this;
   }
 
   friend TypeSize operator-(const TypeSize &LHS, const TypeSize &RHS) {
     assert(LHS.IsScalable == RHS.IsScalable &&
            "Arithmetic using mixed scalable and fixed types");
     return {LHS.MinSize - RHS.MinSize, LHS.IsScalable};
   }
 
-  friend TypeSize operator/(const TypeSize &LHS, const TypeSize &RHS) {
-    assert(LHS.IsScalable == RHS.IsScalable &&
-           "Arithmetic using mixed scalable and fixed types");
-    return {LHS.MinSize / RHS.MinSize, LHS.IsScalable};
-  }
-
-  friend TypeSize operator%(const TypeSize &LHS, const TypeSize &RHS) {
-    assert(LHS.IsScalable == RHS.IsScalable &&
-           "Arithmetic using mixed scalable and fixed types");
-    return {LHS.MinSize % RHS.MinSize, LHS.IsScalable};
-  }
-
   // Return the minimum size with the assumption that the size is exact.
   // Use in places where a scalable size doesn't make sense (e.g. non-vector
   // types, or vectors in backends which don't support scalable vectors).
   uint64_t getFixedSize() const {
     assert(!IsScalable && "Request for a fixed size on a scalable object");
     return MinSize;
   }
 
public:
   }
 
   // Returns true if the type size is non-zero.
   bool isNonZero() const { return MinSize != 0; }
 
   // Returns true if the type size is zero.
   bool isZero() const { return MinSize == 0; }
 
+  bool isKnownMultipleOf(uint64_t RHS) const { return MinSize % RHS == 0; }
+
   // Casts to a uint64_t if this is a fixed-width size.
   //
   // This interface is deprecated and will be removed in a future version
   // of LLVM in favour of upgrading uses that rely on this implicit conversion
   // to uint64_t. Calls to functions that return a TypeSize should use the
   // proper interfaces to TypeSize.
   // In practice this is mostly calls to MVT/EVT::getSizeInBits().
   //
   // To determine how to upgrade the code:
   //
   //   if (<algorithm works for both scalable and fixed-width vectors>)
#else
     if (isScalable())
       WithColor::warning() << "Compiler has made implicit assumption that "
                               "TypeSize is not scalable. This may or may not "
                               "lead to broken code.\n";
     return getKnownMinSize();
 #endif
   }
 
-  // Additional convenience operators needed to avoid ambiguous parses.
-  // TODO: Make uint64_t the default operator?
-  TypeSize operator*(uint64_t RHS) const {
-    return { MinSize * RHS, IsScalable };
-  }
-
-  TypeSize operator*(int RHS) const {
-    return { MinSize * RHS, IsScalable };
-  }
-
-  TypeSize operator*(int64_t RHS) const {
-    return { MinSize * RHS, IsScalable };
-  }
-
-  friend TypeSize operator*(const uint64_t LHS, const TypeSize &RHS) {
-    return { LHS * RHS.MinSize, RHS.IsScalable };
-  }
-
-  friend TypeSize operator*(const int LHS, const TypeSize &RHS) {
-    return { LHS * RHS.MinSize, RHS.IsScalable };
-  }
-
-  friend TypeSize operator*(const int64_t LHS, const TypeSize &RHS) {
-    return { LHS * RHS.MinSize, RHS.IsScalable };
-  }
-
-  TypeSize operator/(uint64_t RHS) const {
-    return { MinSize / RHS, IsScalable };
-  }
-
-  TypeSize operator/(int RHS) const {
-    return { MinSize / RHS, IsScalable };
-  }
-
-  TypeSize operator/(int64_t RHS) const {
-    return { MinSize / RHS, IsScalable };
-  }
-
   TypeSize NextPowerOf2() const {
     return TypeSize(llvm::NextPowerOf2(MinSize), IsScalable);
   }
 };
 
 /// Returns a TypeSize with a known minimum size that is the next integer
 /// (mod 2**64) that is greater than or equal to \p Value and is a multiple
 /// of \p Align. \p Align must be non-zero.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
   if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
       LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) {
     EVT VecTy = N0.getOperand(0).getValueType();
     EVT ExTy = N0.getValueType();
     EVT TrTy = N->getValueType(0);
 
     auto EltCnt = VecTy.getVectorElementCount();
     unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
-    auto NewEltCnt = EltCnt * SizeRatio;
+    auto NewEltCnt = EltCnt.mul(SizeRatio);
 
     EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, NewEltCnt);
     assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
 
     SDValue EltNo = N0->getOperand(1);
     if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
       int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
       int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
for (SDValue Op : N->ops()) {
     SrcOps.push_back(Op.getOperand(0));
   }
 
   // The wider cast must be supported by the target. This is unusual because
   // the operation support type parameter depends on the opcode. In addition,
   // check the other type in the cast to make sure this is really legal.
   EVT VT = N->getValueType(0);
   EVT SrcEltVT = SrcVT.getVectorElementType();
-  ElementCount NumElts = SrcVT.getVectorElementCount() * N->getNumOperands();
+  ElementCount NumElts = SrcVT.getVectorElementCount().mul(N->getNumOperands());
   EVT ConcatSrcVT = EVT::getVectorVT(*DAG.getContext(), SrcEltVT, NumElts);
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   switch (CastOpcode) {
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP:
     if (!TLI.isOperationLegalOrCustom(CastOpcode, ConcatSrcVT) ||
         !TLI.isTypeLegal(VT))
       return SDValue();
static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) {
   unsigned NumElts = VT.getVectorMinNumElements();
 
   // The definition of EXTRACT_SUBVECTOR states that the index must be a
   // multiple of the minimum number of elements in the result type.
   assert(Index % NumElts == 0 && "The extract subvector index is not a "
                                  "multiple of the result's element count");
 
   // It's fine to use TypeSize here as we know the offset will not be negative.
-  TypeSize Offset = VT.getStoreSize() * (Index / NumElts);
+  TypeSize Offset = VT.getStoreSize().mul(Index / NumElts);
 
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   if (!TLI.shouldReduceLoadWidth(Ld, Ld->getExtensionType(), VT))
     return SDValue();
 
   // The narrow load will be offset from the base address of the old load if
   // we are extracting from something besides index 0 (little-endian).
   SDLoc DL(Extract);
SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
   if (V.getOpcode() == ISD::BITCAST &&
       V.getOperand(0).getValueType().isVector()) {
     SDValue SrcOp = V.getOperand(0);
     EVT SrcVT = SrcOp.getValueType();
     unsigned SrcNumElts = SrcVT.getVectorMinNumElements();
     unsigned DestNumElts = V.getValueType().getVectorMinNumElements();
     if ((SrcNumElts % DestNumElts) == 0) {
       unsigned SrcDestRatio = SrcNumElts / DestNumElts;
-      ElementCount NewExtEC = NVT.getVectorElementCount() * SrcDestRatio;
+      ElementCount NewExtEC = NVT.getVectorElementCount().mul(SrcDestRatio);
       EVT NewExtVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(),
                                       NewExtEC);
       if (TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NewExtVT)) {
         SDLoc DL(N);
         SDValue NewIndex = DAG.getVectorIdxConstant(ExtIdx * SrcDestRatio, DL);
         SDValue NewExtract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NewExtVT,
                                          V.getOperand(0), NewIndex);
         return DAG.getBitcast(NVT, NewExtract);
       }
     }
     if ((DestNumElts % SrcNumElts) == 0) {
       unsigned DestSrcRatio = DestNumElts / SrcNumElts;
       if ((NVT.getVectorMinNumElements() % DestSrcRatio) == 0) {
-        ElementCount NewExtEC = NVT.getVectorElementCount() / DestSrcRatio;
+        ElementCount NewExtEC = NVT.getVectorElementCount().div(DestSrcRatio);
         EVT ScalarVT = SrcVT.getScalarType();
         if ((ExtIdx % DestSrcRatio) == 0) {
           SDLoc DL(N);
           unsigned IndexValScaled = ExtIdx / DestSrcRatio;
           EVT NewExtVT =
               EVT::getVectorVT(*DAG.getContext(), ScalarVT, NewExtEC);
           if (TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NewExtVT)) {
             SDValue NewIndex = DAG.getVectorIdxConstant(IndexValScaled, DL);
if ((N0.isUndef() || N0SrcSVT == N1SrcSVT) &&
       EVT NewVT;
       SDLoc DL(N);
       SDValue NewIdx;
       LLVMContext &Ctx = *DAG.getContext();
       ElementCount NumElts = VT.getVectorElementCount();
       unsigned EltSizeInBits = VT.getScalarSizeInBits();
       if ((EltSizeInBits % N1SrcSVT.getSizeInBits()) == 0) {
         unsigned Scale = EltSizeInBits / N1SrcSVT.getSizeInBits();
-        NewVT = EVT::getVectorVT(Ctx, N1SrcSVT, NumElts * Scale);
+        NewVT = EVT::getVectorVT(Ctx, N1SrcSVT, NumElts.mul(Scale));
         NewIdx = DAG.getVectorIdxConstant(InsIdx * Scale, DL);
       } else if ((N1SrcSVT.getSizeInBits() % EltSizeInBits) == 0) {
         unsigned Scale = N1SrcSVT.getSizeInBits() / EltSizeInBits;
         if (NumElts.isKnownMultipleOf(Scale) && (InsIdx % Scale) == 0) {
-          NewVT = EVT::getVectorVT(Ctx, N1SrcSVT, NumElts / Scale);
+          NewVT = EVT::getVectorVT(Ctx, N1SrcSVT, NumElts.div(Scale));
           NewIdx = DAG.getVectorIdxConstant(InsIdx / Scale, DL);
         }
       }
       if (NewIdx && hasOperation(ISD::INSERT_SUBVECTOR, NewVT)) {
         SDValue Res = DAG.getBitcast(NewVT, N0Src);
         Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, NewVT, Res, N1Src, NewIdx);
         return DAG.getBitcast(VT, Res);
       }

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

void DAGTypeLegalizer::GetSplitVector(SDValue Op, SDValue &Lo,
   assert(Lo.getNode() && "Operand isn't split");
   ;
 }
 
 void DAGTypeLegalizer::SetSplitVector(SDValue Op, SDValue Lo,
                                       SDValue Hi) {
   assert(Lo.getValueType().getVectorElementType() ==
              Op.getValueType().getVectorElementType() &&
-         Lo.getValueType().getVectorElementCount() * 2 ==
+         Lo.getValueType().getVectorElementCount().mul(2) ==
              Op.getValueType().getVectorElementCount() &&
          Hi.getValueType() == Lo.getValueType() &&
          "Invalid type for split vector");
   // Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
   AnalyzeNewValue(Lo);
   AnalyzeNewValue(Hi);
 
   // Remember that this is the result of the node.

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
   //   - the type of an extended (by doubling element size) source is legal, and
   //   - the type of that extended source when split is legal.
   //
   // This won't necessarily completely legalize the operation, but it will
   // more effectively move in the right direction and prevent falling down
   // to scalarization in many cases due to the input vector being split too
   // far.
   if ((SrcVT.getVectorMinNumElements() & 1) == 0 &&
-      SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
+      SrcVT.getSizeInBits().mul(2) < DestVT.getSizeInBits()) {
     LLVMContext &Ctx = *DAG.getContext();
     EVT NewSrcVT = SrcVT.widenIntegerVectorElementType(Ctx);
     EVT SplitSrcVT = SrcVT.getHalfNumVectorElementsVT(Ctx);
 
     EVT SplitLoVT, SplitHiVT;
     std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
     if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
         TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
 
   // Truncate them to 1/2 the element size.
   //
   // This assumes the number of elements is a power of two; any vector that
   // isn't should be widened, not split.
   EVT HalfElementVT = IsFloat ?
     EVT::getFloatingPointVT(InElementSize/2) :
     EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
-  EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
-                                NumElements/2);
+  EVT HalfVT =
+      EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements.div(2));
 
   SDValue HalfLo;
   SDValue HalfHi;
   SDValue Chain;
   if (N->isStrictFPOpcode()) {
     HalfLo = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other},
                          {N->getOperand(0), InLoVec});
     HalfHi = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other},
SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
   SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
   SDLoc DL(N);
   GetSplitVector(N->getOperand(0), Lo0, Hi0);
   GetSplitVector(N->getOperand(1), Lo1, Hi1);
   auto PartEltCnt = Lo0.getValueType().getVectorElementCount();
 
   LLVMContext &Context = *DAG.getContext();
   EVT PartResVT = EVT::getVectorVT(Context, MVT::i1, PartEltCnt);
-  EVT WideResVT = EVT::getVectorVT(Context, MVT::i1, PartEltCnt*2);
+  EVT WideResVT = EVT::getVectorVT(Context, MVT::i1, PartEltCnt.mul(2));
 
   LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
   HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
   SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
 
   EVT OpVT = N->getOperand(0).getValueType();
   ISD::NodeType ExtendCode =
       TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
if (!LdTy.isVector())  {
     ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i + 1, End);
   }
 
   ConcatOps[--Idx] = LdOps[i];
   for (--i; i >= 0; --i) {
     EVT NewLdTy = LdOps[i].getValueType();
     if (NewLdTy != LdTy) {
       // Create a larger vector.
+      TypeSize LdTySize = LdTy.getSizeInBits();
+      TypeSize NewLdTySize = NewLdTy.getSizeInBits();
+      assert(NewLdTySize.isScalable() == LdTySize.isScalable() &&
+             NewLdTySize.isKnownMultipleOf(LdTySize.getKnownMinSize()));
       unsigned NumOps =
-          (NewLdTy.getSizeInBits() / LdTy.getSizeInBits()).getKnownMinSize();
-      assert(
-          (NewLdTy.getSizeInBits() % LdTy.getSizeInBits()).getKnownMinSize() ==
-          0);
+          NewLdTySize.getKnownMinSize() / LdTySize.getKnownMinSize();
       SmallVector<SDValue, 16> WidenOps(NumOps);
       unsigned j = 0;
       for (; j != End-Idx; ++j)
         WidenOps[j] = ConcatOps[Idx+j];
       for (; j != NumOps; ++j)
         WidenOps[j] = DAG.getUNDEF(LdTy);
 
       ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
                                      WidenOps);
       Idx = End - 1;
       LdTy = NewLdTy;
     }
     ConcatOps[--Idx] = LdOps[i];
   }
 
-  if (WidenWidth == LdTy.getSizeInBits() * (End - Idx))
+  TypeSize LdTySize = LdTy.getSizeInBits();
+  if (WidenWidth == LdTySize.mul(End - Idx))
     return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
                        makeArrayRef(&ConcatOps[Idx], End - Idx));
 
   // We need to fill the rest with undefs to build the vector.
-  unsigned NumOps = (WidenWidth / LdTy.getSizeInBits()).getKnownMinSize();
+  unsigned NumOps = WidenWidth.getKnownMinSize() / LdTySize.getKnownMinSize();
   SmallVector<SDValue, 16> WidenOps(NumOps);
   SDValue UndefVal = DAG.getUNDEF(LdTy);
   {
     unsigned i = 0;
     for (; i != End-Idx; ++i)
       WidenOps[i] = ConcatOps[Idx+i];
     for (; i != NumOps; ++i)
       WidenOps[i] = UndefVal;

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

static SDValue foldCONCAT_VECTORS(const SDLoc &DL, EVT VT,
                                   ArrayRef<SDValue> Ops,
                                   SelectionDAG &DAG) {
   assert(!Ops.empty() && "Can't concatenate an empty list of vectors!");
   assert(llvm::all_of(Ops,
                       [Ops](SDValue Op) {
                         return Ops[0].getValueType() == Op.getValueType();
                       }) &&
          "Concatenation of vectors with inconsistent value types!");
-  assert((Ops[0].getValueType().getVectorElementCount() * Ops.size()) ==
+  assert((Ops[0].getValueType().getVectorElementCount().mul(Ops.size())) ==
              VT.getVectorElementCount() &&
          "Incorrect element count in vector concatenation!");
 
   if (Ops.size() == 1)
     return Ops[0];
 
   // Concat of UNDEFs is UNDEF.
   if (llvm::all_of(Ops, [](SDValue Op) { return Op.isUndef(); }))

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

if (NumParts > 1) {
     }
 
     // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
     // intermediate operands.
     EVT BuiltVectorTy =
         IntermediateVT.isVector()
             ? EVT::getVectorVT(
                   *DAG.getContext(), IntermediateVT.getScalarType(),
-                  IntermediateVT.getVectorElementCount() * NumParts)
+                  IntermediateVT.getVectorElementCount().mul(NumParts))
             : EVT::getVectorVT(*DAG.getContext(),
                                IntermediateVT.getScalarType(),
                                NumIntermediates);
     Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
                                                 : ISD::BUILD_VECTOR,
                       DL, BuiltVectorTy, Ops);
   }
 
static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
   assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
 
   assert(IntermediateVT.isScalableVector() == ValueVT.isScalableVector() &&
          "Mixing scalable and fixed vectors when copying in parts");
 
   Optional<ElementCount> DestEltCnt;
 
   if (IntermediateVT.isVector())
-    DestEltCnt = IntermediateVT.getVectorElementCount() * NumIntermediates;
+    DestEltCnt = IntermediateVT.getVectorElementCount().mul(NumIntermediates);
   else
     DestEltCnt = ElementCount::getFixed(NumIntermediates);
 
   EVT BuiltVectorTy = EVT::getVectorVT(
       *DAG.getContext(), IntermediateVT.getScalarType(), DestEltCnt.getValue());
   if (ValueVT != BuiltVectorTy) {
     if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, BuiltVectorTy))
       Val = Widened;

llvm/lib/CodeGen/TargetLoweringBase.cpp

assert((LA == TypeLegal || LA == TypeSoftenFloat ||
             LA == TypeSoftPromoteHalf ||
             (NVT.isVector() ||
              ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
            "Promote may not follow Expand or Promote");
 
     if (LA == TypeSplitVector)
       return LegalizeKind(LA,
                           EVT::getVectorVT(Context, SVT.getVectorElementType(),
-                                           SVT.getVectorElementCount() / 2));
+                                           SVT.getVectorElementCount().div(2)));
     if (LA == TypeScalarizeVector)
       return LegalizeKind(LA, SVT.getVectorElementType());
     return LegalizeKind(LA, NVT);
   }
 
   // Handle Extended Scalar Types.
   if (!VT.isVector()) {
     assert(VT.isInteger() && "Float types must be simple");
     unsigned BitSize = VT.getSizeInBits();
     // First promote to a power-of-two size, then expand if necessary.
if (EltVT.isInteger()) {
 
     // Examine the element type.
     LegalizeKind LK = getTypeConversion(Context, EltVT);
 
     // If type is to be expanded, split the vector.
     //  <4 x i140> -> <2 x i140>
     if (LK.first == TypeExpandInteger)
       return LegalizeKind(TypeSplitVector,
-                          EVT::getVectorVT(Context, EltVT, NumElts / 2));
+                          VT.getHalfNumVectorElementsVT(Context));
 
     // Promote the integer element types until a legal vector type is found
     // or until the element integer type is too big. If a legal type was not
     // found, fallback to the usual mechanism of widening/splitting the
     // vector.
     EVT OldEltVT = EltVT;
     while (true) {
       // Increase the bitwidth of the element to the next pow-of-two
TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
 
   // Widen odd vectors to next power of two.
   if (!VT.isPow2VectorType()) {
     EVT NVT = VT.getPow2VectorType(Context);
     return LegalizeKind(TypeWidenVector, NVT);
   }
 
   // Vectors with illegal element types are expanded.
-  EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorElementCount() / 2);
+  EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorElementCount().div(2));
   return LegalizeKind(TypeSplitVector, NVT);
 }
 
 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
                                           unsigned &NumIntermediates,
                                           MVT &RegisterVT,
                                           TargetLoweringBase *TLI) {
   // Figure out the right, legal destination reg to copy into.
if (!isPowerOf2_32(EC.getKnownMinValue())) {
     EC = ElementCount::getFixed(1);
   }
 
   // Divide the input until we get to a supported size. This will
   // always end up with an EC that represent a scalar or a scalable
   // scalar.
   while (EC.getKnownMinValue() > 1 &&
          !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) {
-    EC /= 2;
+    EC = EC.div(2);
     NumVectorRegs <<= 1;
   }
 
   NumIntermediates = NumVectorRegs;
 
   MVT NewVT = MVT::getVectorVT(EltTy, EC);
   if (!TLI->isTypeLegal(NewVT))
     NewVT = EltTy;
if (VT.isScalableVector() && !isPowerOf2_32(EltCnt.getKnownMinValue())) {
 
     NumIntermediates = VT.getVectorElementCount().getKnownMinValue() /
                        PartVT.getVectorElementCount().getKnownMinValue();
 
     // FIXME: This code needs to be extended to handle more complex vector
     // breakdowns, like nxv7i64 -> nxv8i64 -> 4 x nxv2i64. Currently the only
     // supported cases are vectors that are broken down into equal parts
     // such as nxv6i64 -> 3 x nxv2i64.
-    assert((PartVT.getVectorElementCount() * NumIntermediates) ==
+    assert((PartVT.getVectorElementCount().mul(NumIntermediates)) ==
                VT.getVectorElementCount() &&
            "Expected an integer multiple of PartVT");
     IntermediateVT = PartVT;
     RegisterVT = getRegisterType(Context, IntermediateVT);
     return NumIntermediates;
   }
 
   // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally
   // we could break down into LHS/RHS like LegalizeDAG does.
   if (!isPowerOf2_32(EltCnt.getKnownMinValue())) {
     NumVectorRegs = EltCnt.getKnownMinValue();
     EltCnt = ElementCount::getFixed(1);
   }
 
   // Divide the input until we get to a supported size.  This will always
   // end with a scalar if the target doesn't support vectors.
   while (EltCnt.getKnownMinValue() > 1 &&
          !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) {
-    EltCnt /= 2;
+    EltCnt = EltCnt.div(2);
     NumVectorRegs <<= 1;
   }
 
   NumIntermediates = NumVectorRegs;
 
   EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt);
   if (!isTypeLegal(NewVT))
     NewVT = EltTy;

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

static EVT getPackedVectorTypeFromPredicateType(LLVMContext &Ctx, EVT PredVT,
 
   if (PredVT != MVT::nxv16i1 && PredVT != MVT::nxv8i1 &&
       PredVT != MVT::nxv4i1 && PredVT != MVT::nxv2i1)
     return EVT();
 
   ElementCount EC = PredVT.getVectorElementCount();
   EVT ScalarVT =
       EVT::getIntegerVT(Ctx, AArch64::SVEBitsPerBlock / EC.getKnownMinValue());
-  EVT MemVT = EVT::getVectorVT(Ctx, ScalarVT, EC * NumVec);
+  EVT MemVT = EVT::getVectorVT(Ctx, ScalarVT, EC.mul(NumVec));
 
   return MemVT;
 }
 
 /// Return the EVT of the data associated to a memory operation in \p
 /// Root. If such EVT cannot be retrived, it returns an invalid EVT.
 static EVT getMemVTFromNode(LLVMContext &Ctx, SDNode *Root) {
   if (isa<MemSDNode>(Root))

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (InVT.isScalableVector()) {
 
     if (!isTypeLegal(VT) || !VT.isInteger())
       return SDValue();
 
     SDValue Vec0 = Op.getOperand(0);
     SDValue Vec1 = Op.getOperand(1);
 
     // Ensure the subvector is half the size of the main vector.
-    if (VT.getVectorElementCount() != (InVT.getVectorElementCount() * 2))
+    if (VT.getVectorElementCount() != (InVT.getVectorElementCount().mul(2)))
       return SDValue();
 
     // Extend elements of smaller vector...
     EVT WideVT = InVT.widenIntegerVectorElementType(*(DAG.getContext()));
     SDValue ExtVec = DAG.getNode(ISD::ANY_EXTEND, DL, WideVT, Vec1);
 
     if (Idx == 0) {
       SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0);

 #ifndef NDEBUG
   // Check the assumption that all input vectors are the same type.
   for (unsigned I = 0; I < NumVecs; ++I)
     assert(VT == TLI.getMemValueType(DL, CI.getArgOperand(I)->getType()) &&
            "Invalid type.");
 #endif
   // memVT is `NumVecs * VT`.
   Info.memVT = EVT::getVectorVT(CI.getType()->getContext(), VT.getScalarType(),
-                                EC * NumVecs);
+                                EC.mul(NumVecs));
   Info.ptrVal = CI.getArgOperand(CI.getNumArgOperands() - 1);
   Info.offset = 0;
   Info.align.reset();
   Info.flags = MachineMemOperand::MOStore;
   return true;
 }
 
 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
static std::map<unsigned, std::pair<unsigned, unsigned>> IntrinsicMap = {
       {Intrinsic::aarch64_sve_ld3, {3, AArch64ISD::SVE_LD3_MERGE_ZERO}},
       {Intrinsic::aarch64_sve_ld4, {4, AArch64ISD::SVE_LD4_MERGE_ZERO}}};
 
   std::tie(N, Opcode) = IntrinsicMap[Intrinsic];
   assert(VT.getVectorElementCount().getKnownMinValue() % N == 0 &&
          "invalid tuple vector type!");
 
   EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
-                                 VT.getVectorElementCount() / N);
+                                 VT.getVectorElementCount().div(N));
   assert(isTypeLegal(SplitVT));
 
   SmallVector<EVT, 5> VTs(N, SplitVT);
   VTs.push_back(MVT::Other); // Chain
   SDVTList NodeTys = DAG.getVTList(VTs);
 
   SDValue PseudoLoad = DAG.getNode(Opcode, DL, NodeTys, LoadOps);
   SmallVector<SDValue, 4> PseudoLoadOps;
if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) {
     SDValue ExtOp = Src->getOperand(0);
     auto VT = cast<VTSDNode>(N->getOperand(1))->getVT();
     EVT EltTy = VT.getVectorElementType();
     (void)EltTy;
 
     assert((EltTy == MVT::i8 || EltTy == MVT::i16 || EltTy == MVT::i32) &&
            "Sign extending from an invalid type");
 
-    EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
-                                 VT.getVectorElementType(),
-                                 VT.getVectorElementCount() * 2);
+    EVT ExtVT = VT.getDoubleNumVectorElementsVT(*DAG.getContext());
 
     SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ExtOp.getValueType(),
                               ExtOp, DAG.getValueType(ExtVT));
 
     return DAG.getNode(SOpc, DL, N->getValueType(0), Ext);
   }
 
   // SVE load nodes (e.g. AArch64ISD::GLD1) are straightforward candidates
case Intrinsic::aarch64_sve_tuple_create4: {
       SDValue Chain = N->getOperand(0);
 
       SmallVector<SDValue, 4> Opnds;
       for (unsigned I = 2; I < N->getNumOperands(); ++I)
         Opnds.push_back(N->getOperand(I));
 
       EVT VT = Opnds[0].getValueType();
       EVT EltVT = VT.getVectorElementType();
-      EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
-                                    VT.getVectorElementCount() *
-                                        (N->getNumOperands() - 2));
+      EVT DestVT = EVT::getVectorVT(
+          *DAG.getContext(), EltVT,
+          VT.getVectorElementCount().mul((N->getNumOperands() - 2)));
       SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, DestVT, Opnds);
       return DAG.getMergeValues({Concat, Chain}, DL);
     }
     case Intrinsic::aarch64_sve_ld2:
     case Intrinsic::aarch64_sve_ld3:
     case Intrinsic::aarch64_sve_ld4: {
       SDLoc DL(N);
       SDValue Chain = N->getOperand(0);
void AArch64TargetLowering::ReplaceExtractSubVectorResults(
 
   SDLoc DL(N);
   EVT VT = N->getValueType(0);
 
   // The following checks bail if this is not a halving operation.
 
   ElementCount ResEC = VT.getVectorElementCount();
 
-  if (InVT.getVectorElementCount() != (ResEC * 2))
+  if (InVT.getVectorElementCount() != (ResEC.mul(2)))
     return;
 
   auto *CIndex = dyn_cast<ConstantSDNode>(N->getOperand(1));
   if (!CIndex)
     return;
 
   unsigned Index = CIndex->getZExtValue();
   if ((Index != 0) && (Index != ResEC.getKnownMinValue()))

llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp

unsigned getNumOps(Type *VT) {
     return getNumOps(VT->getScalarType(),
                      cast<FixedVectorType>(VT)->getNumElements());
   }
 
   //
   /// Return the estimated number of vector ops required for an operation on
   /// \p VT * N.
   unsigned getNumOps(Type *ST, unsigned N) {
-    return std::ceil((ST->getPrimitiveSizeInBits() * N).getFixedSize() /
+    return std::ceil((ST->getPrimitiveSizeInBits().mul(N)).getFixedSize() /
                      double(TTI.getRegisterBitWidth(true)));
   }
 
   /// Return the set of vectors that a matrix value is lowered to.
   ///
   /// If we lowered \p MatrixVal, just return the cache result matrix. Otherwise
   /// split the flat vector \p MatrixVal containing a matrix with shape \p SI
   /// into vectors.

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

 /// type is irregular if its allocated size doesn't equal the store size of an
 /// element of the corresponding vector type at the given vectorization factor.
 static bool hasIrregularType(Type *Ty, const DataLayout &DL, ElementCount VF) {
   assert(!VF.isScalable() && "scalable vectors not yet supported.");
   // Determine if an array of VF elements of type Ty is "bitcast compatible"
   // with a <VF x Ty> vector.
   if (VF.isVector()) {
     auto *VectorTy = VectorType::get(Ty, VF);
-    return VF * DL.getTypeAllocSize(Ty) != DL.getTypeStoreSize(VectorTy);
+    uint64_t TySize = DL.getTypeAllocSize(Ty).getFixedSize();
+    TypeSize VFTy = TypeSize(TySize * VF.getKnownMinValue(), VF.isScalable());
+    return VFTy != DL.getTypeStoreSize(VectorTy);
   }
 
   // If the vectorization factor is one, we just check if an array of type Ty
   // requires padding between elements.
   return DL.getTypeAllocSizeInBits(Ty) != DL.getTypeSizeInBits(Ty);
 }
 
 /// A helper function that returns the reciprocal of the block probability of
void InnerLoopVectorizer::vectorizeInterleaveGroup(
     VPValue *Addr, VPValue *BlockInMask) {
   Instruction *Instr = Group->getInsertPos();
   const DataLayout &DL = Instr->getModule()->getDataLayout();
 
   // Prepare for the vector type of the interleaved load/store.
   Type *ScalarTy = getMemInstValueType(Instr);
   unsigned InterleaveFactor = Group->getFactor();
   assert(!VF.isScalable() && "scalable vectors not yet supported.");
-  auto *VecTy = VectorType::get(ScalarTy, VF * InterleaveFactor);
+  auto *VecTy = VectorType::get(ScalarTy, VF.mul(InterleaveFactor));
 
   // Prepare for the new pointers.
   SmallVector<Value *, 2> AddrParts;
   unsigned Index = Group->getIndex(Instr);
 
   // TODO: extend the masked interleaved-group support to reversed access.
   assert((!BlockInMask || !Group->isReverse()) &&
          "Reversed masked interleave-group not supported.");
unsigned LoopVectorizationCostModel::getInterleaveGroupCost(Instruction *I,
   auto *VectorTy = cast<VectorType>(ToVectorTy(ValTy, VF));
   unsigned AS = getLoadStoreAddressSpace(I);
 
   auto Group = getInterleavedAccessGroup(I);
   assert(Group && "Fail to get an interleaved access group.");
 
   unsigned InterleaveFactor = Group->getFactor();
   assert(!VF.isScalable() && "scalable vectors not yet supported.");
-  auto *WideVecTy = VectorType::get(ValTy, VF * InterleaveFactor);
+  auto *WideVecTy = VectorType::get(ValTy, VF.mul(InterleaveFactor));
 
   // Holds the indices of existing members in an interleaved load group.
   // An interleaved store group doesn't need this as it doesn't allow gaps.
   SmallVector<unsigned, 4> Indices;
   if (isa<LoadInst>(I)) {
     for (unsigned i = 0; i < InterleaveFactor; i++)
       if (Group->getMember(i))
         Indices.push_back(i);
if (CM.foldTailByMasking() && !Legal->getReductionVars().empty()) {
     }
   }
 
   std::string PlanName;
   raw_string_ostream RSO(PlanName);
   ElementCount VF = ElementCount::getFixed(Range.Start);
   Plan->addVF(VF);
   RSO << "Initial VPlan for VF={" << VF;
-  for (VF *= 2; VF.getKnownMinValue() < Range.End; VF *= 2) {
+  for (VF = VF.mul(2); VF.getKnownMinValue() < Range.End; VF = VF.mul(2)) {
     Plan->addVF(VF);
     RSO << "," << VF;
   }
   RSO << "},UF>=1";
   RSO.flush();
   Plan->setName(PlanName);
 
   return Plan;

llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp

TEST(ScalableVectorMVTsTest, HelperFuncs) {
   // Create with inline llvm::ElementCount
   EVT Vnx2i64 = EVT::getVectorVT(Ctx, MVT::i64, ElementCount::getScalable(2));
   ASSERT_TRUE(Vnx2i64.isScalableVector());
 
   // Check that changing scalar types/element count works
   EXPECT_EQ(Vnx2i32.widenIntegerVectorElementType(Ctx), Vnx2i64);
   EXPECT_EQ(Vnx4i32.getHalfNumVectorElementsVT(Ctx), Vnx2i32);
 
   // Check that overloaded '*' and '/' operators work
-  EXPECT_EQ(EVT::getVectorVT(Ctx, MVT::i64, EltCnt * 2), MVT::nxv4i64);
-  EXPECT_EQ(EVT::getVectorVT(Ctx, MVT::i64, EltCnt / 2), MVT::nxv1i64);
+  EXPECT_EQ(EVT::getVectorVT(Ctx, MVT::i64, EltCnt.mul(2)), MVT::nxv4i64);
+  EXPECT_EQ(EVT::getVectorVT(Ctx, MVT::i64, EltCnt.div(2)), MVT::nxv1i64);
 
   // Check that float->int conversion works
   EVT Vnx2f64 = EVT::getVectorVT(Ctx, MVT::f64, ElementCount::getScalable(2));
   EXPECT_EQ(Vnx2f64.changeTypeToInteger(), Vnx2i64);
 
   // Check fields inside llvm::ElementCount
   EltCnt = Vnx4i32.getVectorElementCount();
   EXPECT_EQ(EltCnt.getKnownMinValue(), 4U);

llvm/unittests/IR/VectorTypesTest.cpp

TEST(VectorTypesTest, FixedLength) {
 
   auto EltCnt = ElementCount::getFixed(4);
   auto *V4Int64Ty = dyn_cast<FixedVectorType>(VectorType::get(Int64Ty, EltCnt));
   ASSERT_NE(nullptr, V4Int64Ty);
   EXPECT_EQ(V4Int64Ty->getNumElements(), 4U);
   EXPECT_EQ(V4Int64Ty->getElementType()->getScalarSizeInBits(), 64U);
 
   auto *V2Int64Ty =
-      dyn_cast<FixedVectorType>(VectorType::get(Int64Ty, EltCnt / 2));
+      dyn_cast<FixedVectorType>(VectorType::get(Int64Ty, EltCnt.div(2)));
   ASSERT_NE(nullptr, V2Int64Ty);
   EXPECT_EQ(V2Int64Ty->getNumElements(), 2U);
   EXPECT_EQ(V2Int64Ty->getElementType()->getScalarSizeInBits(), 64U);
 
   auto *V8Int64Ty =
-      dyn_cast<FixedVectorType>(VectorType::get(Int64Ty, EltCnt * 2));
+      dyn_cast<FixedVectorType>(VectorType::get(Int64Ty, EltCnt.mul(2)));
   ASSERT_NE(nullptr, V8Int64Ty);
   EXPECT_EQ(V8Int64Ty->getNumElements(), 8U);
   EXPECT_EQ(V8Int64Ty->getElementType()->getScalarSizeInBits(), 64U);
 
   auto *V4Float64Ty =
       dyn_cast<FixedVectorType>(VectorType::get(Float64Ty, EltCnt));
   ASSERT_NE(nullptr, V4Float64Ty);
   EXPECT_EQ(V4Float64Ty->getNumElements(), 4U);
TEST(VectorTypesTest, Scalable) {
   auto EltCnt = ElementCount::getScalable(4);
   auto *ScV4Int64Ty =
       dyn_cast<ScalableVectorType>(VectorType::get(Int64Ty, EltCnt));
   ASSERT_NE(nullptr, ScV4Int64Ty);
   EXPECT_EQ(ScV4Int64Ty->getMinNumElements(), 4U);
   EXPECT_EQ(ScV4Int64Ty->getElementType()->getScalarSizeInBits(), 64U);
 
   auto *ScV2Int64Ty =
-      dyn_cast<ScalableVectorType>(VectorType::get(Int64Ty, EltCnt / 2));
+      dyn_cast<ScalableVectorType>(VectorType::get(Int64Ty, EltCnt.div(2)));
   ASSERT_NE(nullptr, ScV2Int64Ty);
   EXPECT_EQ(ScV2Int64Ty->getMinNumElements(), 2U);
   EXPECT_EQ(ScV2Int64Ty->getElementType()->getScalarSizeInBits(), 64U);
 
   auto *ScV8Int64Ty =
-      dyn_cast<ScalableVectorType>(VectorType::get(Int64Ty, EltCnt * 2));
+      dyn_cast<ScalableVectorType>(VectorType::get(Int64Ty, EltCnt.mul(2)));
   ASSERT_NE(nullptr, ScV8Int64Ty);
   EXPECT_EQ(ScV8Int64Ty->getMinNumElements(), 8U);
   EXPECT_EQ(ScV8Int64Ty->getElementType()->getScalarSizeInBits(), 64U);
 
   auto *ScV4Float64Ty =
       dyn_cast<ScalableVectorType>(VectorType::get(Float64Ty, EltCnt));
   ASSERT_NE(nullptr, ScV4Float64Ty);
   EXPECT_EQ(ScV4Float64Ty->getMinNumElements(), 4U);