[AIX][XCOFF] change the operand of branch instruction from symbol name to qualified symbol name for function declarations

[DiggerLin]

Summary

1. in the patch , remove setting storageclass in function .getXCOFFSection and construct function of class MCSectionXCOFF

there are

XCOFF::StorageMappingClass MappingClass;
XCOFF::SymbolType Type;
XCOFF::StorageClass StorageClass;
in the MCSectionXCOFF class,
these attribute only used in the XCOFFObjectWriter, (asm path do not need the StorageClass)

we need get the value of StorageClass, Type,MappingClass before we invoke the getXCOFFSection every time.

actually , we can get the StorageClass of the MCSectionXCOFF from it's delegated symbol.

2. we also change the oprand of branch instruction from symbol name to qualify symbol name.

for example change
bl .foo
extern .foo
to
bl .foo[PR]
extern .foo[PR]

3. and if there is reference indirect call a function bar.

we also add

extern .bar[PR]

[jasonliu]

llvm/include/llvm/MC/MCSectionXCOFF.h

66

How necessary is this convenient function? It might be better to just let people do the call to QualName themselves to avoid confusion, as storage class is not a property of MCSection any more.

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

1535

After this change, do we still have any call to hasRepresentedCsectSet? If not, could we remove that function all together?

llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp

2166–2167

comment needs to be update here.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1905

There seems to be a switch of execution order here, any reason for that?

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5172

I don't think it's necessary to change the name, as the sister function in TLOF have the same name but still return qualname when needed.

5176

Dont use twine in local. You could do

Context.getXCOFFSection(("." + Twine(SymName)).str(), ....

llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll

138

nit: align the spaces.

[Xiangling_L]

As you mentioned in the summary, this patch seems be addressing two orthogonal things:

1. remove SC from MCSectionXCOFF and let it only be a property of MCSymbolXCOFF
2. when branching to an undefined function, branch to qualname instead.

If I am right, I would suggest we split them into two patches.

And for the second patch when branching to an undefined function, branch to qualname instead, I think we need to adjust the patch title to a more accurate one[maybe [AIX][XCOFF] change the operand of branch instruction from symbol name to qualified symbol name for function declarations]since the scope is actually limited to function declarations only.

llvm/include/llvm/MC/MCSectionXCOFF.h

50

I am wondering why do we want to set a default SC here? It seems redundant.

llvm/include/llvm/MC/MCSymbolXCOFF.h

38

It looks like this assertion is still useful to prevent someone from setting SC twice or setting other SC for a same symbol accidentally, if we don't need to set a default SC as I mentioned above.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1705

Please update the comment accordingly.

[jasonliu]

llvm/include/llvm/MC/MCSectionXCOFF.h

50

We transfer SC property from MCSectionXCOFF to MCSymbolXCOFF. MCSectionXCOFF represents a csect. A csect by default have XCOFF::C_HIDEXT Storage class. Without this, we would not be able to get storage class from a MCSectionXCOFF when that csect do not need to emitLinkage.

llvm/include/llvm/MC/MCSymbolXCOFF.h

38

If I understand correctly, we would actually set MCSectionXCOFF/csect's SC twice in some scenarios. First time being the default HIDE_EXT. Second time, when someone called emitLinkage on a csect's qualname symbol (and we could set it to C_EXT at that time.

[Xiangling_L]

llvm/include/llvm/MC/MCSectionXCOFF.h

50

Did you mean emitSymbolAttribute? I guess this matters more on object file generation path? Since on assembly path, `The .lglobl pseudo-op does not have to apply to any csect name. The assembler automatically generates the symbol table entry for any csect name with a class of C_HIDEXT unless there is an
explicit .globl pseudo-op applied to the csect name.`

[jasonliu]

llvm/include/llvm/MC/MCSectionXCOFF.h

50

emitLinkage would call emitSymbolAttribute on the object generation path. And yes, this matters more on object generation path.

[DiggerLin]

llvm/include/llvm/MC/MCSectionXCOFF.h

66

what about change the function name to getQualNameSymbolStorageClass() ? I think we need a wrapper for it.

llvm/include/llvm/MC/MCSymbolXCOFF.h

38

yes, we need to set twice as jason explain

[DiggerLin]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1905

for the object path, the function executePostLayoutBinding() and writeObject() was called in doFinalization() indirectly, we need to run

for (MCSymbol *Sym : ExtSymSDNodeSymbols)
   OutStreamer->emitSymbolAttribute(Sym, MCSA_Extern);

to set the symbol atttribute before PPCAsmPrinter::doFinalization.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5172

MCSymbol *TargetLoweringObjectFileXCOFF::getFunctionEntryPointSymbol() return .foo not .foo[PR] .
in order to not to confuse ,I use the name getFunctionEntryPointQualNameSymbol() to get .foo[PR]

5176

agree. changed

[DiggerLin]

In D84765#2199956, @Xiangling_L wrote:

As you mentioned in the summary, this patch seems be addressing two orthogonal things:

1. remove SC from MCSectionXCOFF and let it only be a property of MCSymbolXCOFF
2. when branching to an undefined function, branch to qualname instead.

If I am right, I would suggest we split them into two patches.

And for the second patch when branching to an undefined function, branch to qualname instead, I think we need to adjust the patch title to a more accurate one[maybe [AIX][XCOFF] change the operand of branch instruction from symbol name to qualified symbol name for function declarations]since the scope is actually limited to function declarations only.

In D84765#2199956, @Xiangling_L wrote:

As you mentioned in the summary, this patch seems be addressing two orthogonal things:

1. remove SC from MCSectionXCOFF and let it only be a property of MCSymbolXCOFF
2. when branching to an undefined function, branch to qualname instead.

If I am right, I would suggest we split them into two patches.

And for the second patch when branching to an undefined function, branch to qualname instead, I think we need to adjust the patch title to a more accurate one[maybe [AIX][XCOFF] change the operand of branch instruction from symbol name to qualified symbol name for function declarations]since the scope is actually limited to function declarations only.

In D84765#2199956, @Xiangling_L wrote:

As you mentioned in the summary, this patch seems be addressing two orthogonal things:

1. remove SC from MCSectionXCOFF and let it only be a property of MCSymbolXCOFF
2. when branching to an undefined function, branch to qualname instead.

If I am right, I would suggest we split them into two patches.

And for the second patch when branching to an undefined function, branch to qualname instead, I think we need to adjust the patch title to a more accurate one[maybe [AIX][XCOFF] change the operand of branch instruction from symbol name to qualified symbol name for function declarations]since the scope is actually limited to function declarations only.

you can take a look on the first diff of the patch. I tried to do "remove SC from MCSectionXCOFF and let it only be a property of MCSymbolXCOFF" only in the first diff.
if only remove SC from MCSectionXCOFF, the emitLinkage set the storageClass of the symbol which is not qualname represent symbol of the MCSectionXCOFF. I need to add
some middle source code (in llvm/lib/MC/MCXCOFFStreamer.cpp of first diff) to set the storageClasss of the qualname represent symbol of the MCSectionXCOFF. and the code will be removed later when we implement the second patch. It will waste our time to review.

[DiggerLin]

address comment

[jasonliu]

llvm/include/llvm/MC/MCSectionXCOFF.h

66

Please try to address all the clang-format/clang-tidy message.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5171

Suggestion for the comment:
...... C-linkage name. A Qualname is returned here because an external function entry point is a csect with XTY_ER property.

5172

By looking at what this function does. It seems the name should be getExternalFunctionEntryPointSymbol, as it's always returning a function entry point to an external function. That's an important information that we should include in the name.

[jasonliu]

llvm/include/llvm/MC/MCSymbolXCOFF.h

49

nit: For the implementation of getRepresentedCsect and setRepresentedCsect, please remove

|| RepresentedCsect->getCSectType() == XCOFF::XTY_ER

and

|| C->getCSectType() == XCOFF::XTY_ER

from their asserts, as right now every RepresentedCsect symbol must be a qualname.

[DiggerLin]

address comment

[jasonliu]

Thanks. LGTM.

llvm/include/llvm/MC/MCContext.h

public:
 
     MCSectionWasm *getWasmSection(const Twine &Section, SectionKind K,
                                   const MCSymbolWasm *Group, unsigned UniqueID,
                                   const char *BeginSymName);
 
     MCSectionXCOFF *getXCOFFSection(StringRef Section,
                                     XCOFF::StorageMappingClass MappingClass,
                                     XCOFF::SymbolType CSectType,
-                                    XCOFF::StorageClass StorageClass,
                                     SectionKind K,
                                     const char *BeginSymName = nullptr);
 
     // Create and save a copy of STI and return a reference to the copy.
     MCSubtargetInfo &getSubtargetCopy(const MCSubtargetInfo &STI);
 
     /// @}
 

llvm/include/llvm/MC/MCSectionXCOFF.h

 // 3) An external reference providing a symbol table entry for a symbol
 //    contained in another XCOFF object file. External reference csects are not
 //    implemented yet.
 class MCSectionXCOFF final : public MCSection {
   friend class MCContext;
 
   XCOFF::StorageMappingClass MappingClass;
   XCOFF::SymbolType Type;
-  XCOFF::StorageClass StorageClass;
   MCSymbolXCOFF *const QualName;
   StringRef SymbolTableName;
   static constexpr unsigned DefaultAlignVal = 4;
 
   MCSectionXCOFF(StringRef Name, XCOFF::StorageMappingClass SMC,
-                 XCOFF::SymbolType ST, XCOFF::StorageClass SC, SectionKind K,
-                 MCSymbolXCOFF *QualName, MCSymbol *Begin,
-                 StringRef SymbolTableName)
+                 XCOFF::SymbolType ST, SectionKind K, MCSymbolXCOFF *QualName,
+                 MCSymbol *Begin, StringRef SymbolTableName)
       : MCSection(SV_XCOFF, Name, K, Begin), MappingClass(SMC), Type(ST),
-        StorageClass(SC), QualName(QualName), SymbolTableName(SymbolTableName) {
+        QualName(QualName), SymbolTableName(SymbolTableName) {
     assert((ST == XCOFF::XTY_SD || ST == XCOFF::XTY_CM || ST == XCOFF::XTY_ER) &&
            "Invalid or unhandled type for csect.");
     assert(QualName != nullptr && "QualName is needed.");
-    QualName->setStorageClass(SC);
     QualName->setRepresentedCsect(this);
+    QualName->setStorageClass(XCOFF::C_HIDEXT);
     // A csect is 4 byte aligned by default, except for undefined symbol csects.
     if (Type != XCOFF::XTY_ER)
       setAlignment(Align(DefaultAlignVal));
   }
 
   void printCsectDirective(raw_ostream &OS) const;
 
 public:
   ~MCSectionXCOFF();
 
   static bool classof(const MCSection *S) {
     return S->getVariant() == SV_XCOFF;
   }
 
   XCOFF::StorageMappingClass getMappingClass() const { return MappingClass; }
-  XCOFF::StorageClass getStorageClass() const { return StorageClass; }
+  XCOFF::StorageClass getStorageClass() const { return QualName->getStorageClass(); }
   XCOFF::SymbolType getCSectType() const { return Type; }
   MCSymbolXCOFF *getQualNameSymbol() const { return QualName; }
 
   void PrintSwitchToSection(const MCAsmInfo &MAI, const Triple &T,
                             raw_ostream &OS,
                             const MCExpr *Subsection) const override;
   bool UseCodeAlign() const override;
   bool isVirtualSection() const override;
   StringRef getSymbolTableName() const { return SymbolTableName; }
 };
 
 } // end namespace llvm
 
 #endif

llvm/include/llvm/MC/MCSymbolXCOFF.h

if (Name.back() == ']') {
       std::tie(Lhs, Rhs) = Name.rsplit('[');
       assert(!Rhs.empty() && "Invalid SMC format in XCOFF symbol.");
       return Lhs;
     }
     return Name;
   }
 
   void setStorageClass(XCOFF::StorageClass SC) {
-    assert((!StorageClass.hasValue() || StorageClass.getValue() == SC) &&
-           "Redefining StorageClass of XCOFF MCSymbol.");
     StorageClass = SC;
   };
 
   XCOFF::StorageClass getStorageClass() const {
     assert(StorageClass.hasValue() &&
            "StorageClass not set on XCOFF MCSymbol.");
     return StorageClass.getValue();
   }
 
   StringRef getUnqualifiedName() const { return getUnqualifiedName(getName()); }
 
-  bool hasRepresentedCsectSet() const { return RepresentedCsect != nullptr; }
-
   MCSectionXCOFF *getRepresentedCsect() const;
 
   void setRepresentedCsect(MCSectionXCOFF *C);
 
   void setVisibilityType(XCOFF::VisibilityType SVT) { VisibilityType = SVT; };
 
   XCOFF::VisibilityType getVisibilityType() const { return VisibilityType; }
 
   bool hasRename() const { return !SymbolTableName.empty(); }

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

for (const Function &F : M) {
 
     if (F.isIntrinsic())
       continue;
 
     // Handle the XCOFF case.
     // Variable `Name` is the function descriptor symbol (see above). Get the
     // function entry point symbol.
     MCSymbol *FnEntryPointSym = TLOF.getFunctionEntryPointSymbol(&F, TM);
-    if (cast<MCSymbolXCOFF>(FnEntryPointSym)->hasRepresentedCsectSet())
-      // Emit linkage for the function entry point.
-      emitLinkage(&F, FnEntryPointSym);
 
     // Emit linkage for the function descriptor.
     emitLinkage(&F, Name);
   }
 
   // Emit the remarks section contents.
   // FIXME: Figure out when is the safest time to emit this section. It should
   // not come after debug info.

llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp

 
 MCSection *TargetLoweringObjectFileXCOFF::getSectionForExternalReference(
     const GlobalObject *GO, const TargetMachine &TM) const {
   assert(GO->isDeclarationForLinker() &&
          "Tried to get ER section for a defined global.");
 
   SmallString<128> Name;
   getNameWithPrefix(Name, GO, TM);
-  XCOFF::StorageClass SC =
-      TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(GO);
 
   // Externals go into a csect of type ER.
   return getContext().getXCOFFSection(
       Name, isa<Function>(GO) ? XCOFF::XMC_DS : XCOFF::XMC_UA, XCOFF::XTY_ER,
-      SC, SectionKind::getMetadata());
+      SectionKind::getMetadata());
 }
 
 MCSection *TargetLoweringObjectFileXCOFF::SelectSectionForGlobal(
     const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {
   assert(!TM.getDataSections() &&
          "XCOFF unique data sections not yet implemented.");
 
   // Common symbols go into a csect with matching name which will get mapped
   // into the .bss section.
   if (Kind.isBSSLocal() || Kind.isCommon()) {
     SmallString<128> Name;
     getNameWithPrefix(Name, GO, TM);
-    XCOFF::StorageClass SC =
-        TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(GO);
     return getContext().getXCOFFSection(
         Name, Kind.isBSSLocal() ? XCOFF::XMC_BS : XCOFF::XMC_RW, XCOFF::XTY_CM,
-        SC, Kind, /* BeginSymbolName */ nullptr);
+        Kind, /* BeginSymbolName */ nullptr);
   }
 
   if (Kind.isMergeableCString()) {
     Align Alignment = GO->getParent()->getDataLayout().getPreferredAlign(
         cast<GlobalVariable>(GO));
 
     unsigned EntrySize = getEntrySizeForKind(Kind);
     std::string SizeSpec = ".rodata.str" + utostr(EntrySize) + ".";
     SmallString<128> Name;
     Name = SizeSpec + utostr(Alignment.value());
 
     return getContext().getXCOFFSection(
         Name, XCOFF::XMC_RO, XCOFF::XTY_SD,
-        TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(GO),
         Kind, /* BeginSymbolName */ nullptr);
   }
 
   if (Kind.isText()) {
     if (TM.getFunctionSections()) {
       return cast<MCSymbolXCOFF>(getFunctionEntryPointSymbol(GO, TM))
           ->getRepresentedCsect();
     }
MCSection *TargetLoweringObjectFileXCOFF::getSectionForJumpTable(
   assert (!F.getComdat() && "Comdat not supported on XCOFF.");
   //TODO: Enable emiting jump table to unique sections when we support it.
   return ReadOnlySection;
 }
 
 bool TargetLoweringObjectFileXCOFF::shouldPutJumpTableInFunctionSection(
     bool UsesLabelDifference, const Function &F) const {
   return false;
 }
 
 /// Given a mergeable constant with the specified size and relocation
 /// information, return a section that it should be placed in.
 MCSection *TargetLoweringObjectFileXCOFF::getSectionForConstant(
     const DataLayout &DL, SectionKind Kind, const Constant *C,
     Align &Alignment) const {
   //TODO: Enable emiting constant pool to unique sections when we support it.
   return ReadOnlySection;
assert(
         isa_and_nonnull<Function>(cast<GlobalAlias>(Func)->getBaseObject()))) &&
       "Func must be a function or an alias which has a function as base "
       "object.");
   SmallString<128> NameStr;
   NameStr.push_back('.');
   getNameWithPrefix(NameStr, Func, TM);
 
   // When -function-sections is enabled, it's not necessary to emit
   // function entry point label any more. We will use function entry
-  // point csect instead. For function delcarations, it's okay to continue
-  // using label semantic because undefined symbols gets treated as csect with
-  // XTY_ER property anyway.
-  if (TM.getFunctionSections() && !Func->isDeclaration() &&
+  // point csect instead. And for function delcarations, the undefined symbols
+  // gets treated as csect with XTY_ER property.
+  if ((TM.getFunctionSections() || Func->isDeclaration()) &&
       isa<Function>(Func)) {
-    XCOFF::StorageClass SC =
-        TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(Func);
-    return cast<MCSectionXCOFF>(getContext().getXCOFFSection(
-                                    NameStr, XCOFF::XMC_PR, XCOFF::XTY_SD, SC,
-                                    SectionKind::getText()))
+    return cast<MCSectionXCOFF>(
+               getContext().getXCOFFSection(
+                   NameStr, XCOFF::XMC_PR,
+                   Func->isDeclaration() ? XCOFF::XTY_ER : XCOFF::XTY_SD,
         ->getQualNameSymbol();
   }
 
   return getContext().getOrCreateSymbol(NameStr);
 }
 
 MCSection *TargetLoweringObjectFileXCOFF::getSectionForFunctionDescriptor(
     const Function *F, const TargetMachine &TM) const {
   SmallString<128> NameStr;
   getNameWithPrefix(NameStr, F, TM);
   return getContext().getXCOFFSection(NameStr, XCOFF::XMC_DS, XCOFF::XTY_SD,
-                                      getStorageClassForGlobal(F),
                                       SectionKind::getData());
 }
 
 MCSection *TargetLoweringObjectFileXCOFF::getSectionForTOCEntry(
     const MCSymbol *Sym) const {
   return getContext().getXCOFFSection(
       cast<MCSymbolXCOFF>(Sym)->getSymbolTableName(), XCOFF::XMC_TC,
-      XCOFF::XTY_SD, XCOFF::C_HIDEXT, SectionKind::getData());
+      XCOFF::XTY_SD, SectionKind::getData());
 }

llvm/lib/MC/MCContext.cpp

MCSectionWasm *MCContext::getWasmSection(const Twine &Section, SectionKind Kind,
   Begin->setFragment(F);
 
   return Result;
 }
 
 MCSectionXCOFF *MCContext::getXCOFFSection(StringRef Section,
                                            XCOFF::StorageMappingClass SMC,
                                            XCOFF::SymbolType Type,
-                                           XCOFF::StorageClass SC,
                                            SectionKind Kind,
                                            const char *BeginSymName) {
   // Do the lookup. If we have a hit, return it.
   auto IterBool = XCOFFUniquingMap.insert(
       std::make_pair(XCOFFSectionKey{Section.str(), SMC}, nullptr));
   auto &Entry = *IterBool.first;
   if (!IterBool.second)
     return Entry.second;
 
   // Otherwise, return a new section.
   StringRef CachedName = Entry.first.SectionName;
   MCSymbolXCOFF *QualName = cast<MCSymbolXCOFF>(getOrCreateSymbol(
       CachedName + "[" + XCOFF::getMappingClassString(SMC) + "]"));
 
   MCSymbol *Begin = nullptr;
   if (BeginSymName)
     Begin = createTempSymbol(BeginSymName, false);
 
   // QualName->getUnqualifiedName() and CachedName are the same except when
   // CachedName contains invalid character(s) such as '$' for an XCOFF symbol.
   MCSectionXCOFF *Result = new (XCOFFAllocator.Allocate())
-      MCSectionXCOFF(QualName->getUnqualifiedName(), SMC, Type, SC, Kind,
-                     QualName, Begin, CachedName);
+      MCSectionXCOFF(QualName->getUnqualifiedName(), SMC, Type, Kind, QualName,
+                     Begin, CachedName);
   Entry.second = Result;
 
   auto *F = new MCDataFragment();
   Result->getFragmentList().insert(Result->begin(), F);
   F->setParent(Result);
 
   if (Begin)
     Begin->setFragment(F);

llvm/lib/MC/MCObjectFileInfo.cpp

void MCObjectFileInfo::initWasmMCObjectFileInfo(const Triple &T) {
   // TODO: Define more sections.
 }
 
 void MCObjectFileInfo::initXCOFFMCObjectFileInfo(const Triple &T) {
   // The default csect for program code. Functions without a specified section
   // get placed into this csect. The choice of csect name is not a property of
   // the ABI or object file format. For example, the XL compiler uses an unnamed
   // csect for program code.
-  TextSection = Ctx->getXCOFFSection(
-      ".text", XCOFF::StorageMappingClass::XMC_PR, XCOFF::XTY_SD,
-      XCOFF::C_HIDEXT, SectionKind::getText());
-
-  DataSection = Ctx->getXCOFFSection(
-      ".data", XCOFF::StorageMappingClass::XMC_RW, XCOFF::XTY_SD,
-      XCOFF::C_HIDEXT, SectionKind::getData());
-
-  ReadOnlySection = Ctx->getXCOFFSection(
-      ".rodata", XCOFF::StorageMappingClass::XMC_RO, XCOFF::XTY_SD,
-      XCOFF::C_HIDEXT, SectionKind::getReadOnly());
-
-  TOCBaseSection = Ctx->getXCOFFSection(
-      "TOC", XCOFF::StorageMappingClass::XMC_TC0, XCOFF::XTY_SD,
-      XCOFF::C_HIDEXT, SectionKind::getData());
+  TextSection =
+      Ctx->getXCOFFSection(".text", XCOFF::StorageMappingClass::XMC_PR,
+                           XCOFF::XTY_SD, SectionKind::getText());
+
+  DataSection =
+      Ctx->getXCOFFSection(".data", XCOFF::StorageMappingClass::XMC_RW,
+                           XCOFF::XTY_SD, SectionKind::getData());
+
+  ReadOnlySection =
+      Ctx->getXCOFFSection(".rodata", XCOFF::StorageMappingClass::XMC_RO,
+                           XCOFF::XTY_SD, SectionKind::getReadOnly());
+
+  TOCBaseSection =
+      Ctx->getXCOFFSection("TOC", XCOFF::StorageMappingClass::XMC_TC0,
+                           XCOFF::XTY_SD, SectionKind::getData());
 
   // The TOC-base always has 0 size, but 4 byte alignment.
   TOCBaseSection->setAlignment(Align(4));
 
   // DWARF sections for XCOFF are not csects. They are special STYP_DWARF
   // sections, and the individual DWARF sections are distinguished by their
   // section subtype.
   // TODO: Populate the DWARF sections appropriately.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

 void PPCAIXAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
   if (isSpecialLLVMGlobalArrayToSkip(GV))
     return;
 
   assert(!GV->getName().startswith("llvm.") &&
          "Unhandled intrinsic global variable.");
   ValidateGV(GV);
 
-  // Create the symbol, set its storage class.
   MCSymbolXCOFF *GVSym = cast<MCSymbolXCOFF>(getSymbol(GV));
-  GVSym->setStorageClass(
-      TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(GV));
 
   if (GV->isDeclarationForLinker()) {
     emitLinkage(GV, GVSym);
     return;
   }
 
   SectionKind GVKind = getObjFileLowering().getKindForGlobal(GV, TM);
   if (!GVKind.isGlobalWriteableData() && !GVKind.isReadOnly())
     report_fatal_error("Encountered a global variable kind that is "
                        "not supported yet.");
 
   MCSectionXCOFF *Csect = cast<MCSectionXCOFF>(
       getObjFileLowering().SectionForGlobal(GV, GVKind, TM));
 
   // Switch to the containing csect.
   OutStreamer->SwitchSection(Csect);
 
   const DataLayout &DL = GV->getParent()->getDataLayout();
 
   // Handle common symbols.
   if (GVKind.isCommon() || GVKind.isBSSLocal()) {
     Align Alignment = GV->getAlign().getValueOr(DL.getPreferredAlign(GV));
     uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());
+    GVSym->setStorageClass(
+        TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(GV));
 
     if (GVKind.isBSSLocal())
       OutStreamer->emitXCOFFLocalCommonSymbol(
           OutContext.getOrCreateSymbol(GVSym->getUnqualifiedName()), Size,
           GVSym, Alignment.value());
     else
       OutStreamer->emitCommonSymbol(GVSym, Size, Alignment.value());
     return;
void PPCAIXAsmPrinter::emitInstruction(const MachineInstr *MI) {
   case PPC::BL8:
   case PPC::BL:
   case PPC::BL8_NOP:
   case PPC::BL_NOP: {
     const MachineOperand &MO = MI->getOperand(0);
     if (MO.isSymbol()) {
       MCSymbolXCOFF *S =
           cast<MCSymbolXCOFF>(OutContext.getOrCreateSymbol(MO.getSymbolName()));
-      if (!S->hasRepresentedCsectSet()) {
-        // On AIX, an undefined symbol needs to be associated with a
-        // MCSectionXCOFF to get the correct storage mapping class.
-        // In this case, XCOFF::XMC_PR.
-        MCSectionXCOFF *Sec = OutContext.getXCOFFSection(
-            S->getName(), XCOFF::XMC_PR, XCOFF::XTY_ER, XCOFF::C_EXT,
-            SectionKind::getMetadata());
-        S->setRepresentedCsect(Sec);
-      }
       ExtSymSDNodeSymbols.insert(S);
     }
   } break;
   case PPC::BL_TLS:
   case PPC::BL8_TLS:
   case PPC::BL8_TLS_:
   case PPC::BL8_NOP_TLS:
     report_fatal_error("TLS call not yet implemented");
   case PPC::TAILB:
   case PPC::TAILB8:
   case PPC::TAILBA:
   case PPC::TAILBA8:
   case PPC::TAILBCTR:
   case PPC::TAILBCTR8:
     if (MI->getOperand(0).isSymbol())
       report_fatal_error("Tail call for extern symbol not yet supported.");
     break;
   }
   return PPCAsmPrinter::emitInstruction(MI);
 }
 
 bool PPCAIXAsmPrinter::doFinalization(Module &M) {
-  bool Ret = PPCAsmPrinter::doFinalization(M);
   for (MCSymbol *Sym : ExtSymSDNodeSymbols)
     OutStreamer->emitSymbolAttribute(Sym, MCSA_Extern);
-  return Ret;
+  return PPCAsmPrinter::doFinalization(M);
 }
 
 /// createPPCAsmPrinterPass - Returns a pass that prints the PPC assembly code
 /// for a MachineFunction to the given output stream, in a format that the
 /// Darwin assembler can deal with.
 ///
 static AsmPrinter *
 createPPCAsmPrinterPass(TargetMachine &tm,

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

bool UsePlt =
       Subtarget.getTargetMachine().getRelocationModel() == Reloc::PIC_;
 
   const auto getAIXFuncEntryPointSymbolSDNode = [&](const GlobalValue *GV) {
     const TargetMachine &TM = Subtarget.getTargetMachine();
     const TargetLoweringObjectFile *TLOF = TM.getObjFileLowering();
     MCSymbolXCOFF *S =
         cast<MCSymbolXCOFF>(TLOF->getFunctionEntryPointSymbol(GV, TM));
 
-    if (GV->isDeclaration() && !S->hasRepresentedCsectSet()) {
-      // On AIX, an undefined symbol needs to be associated with a
-      // MCSectionXCOFF to get the correct storage mapping class.
-      // In this case, XCOFF::XMC_PR.
-      const XCOFF::StorageClass SC =
-          TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(GV);
-      auto &Context = DAG.getMachineFunction().getMMI().getContext();
-      MCSectionXCOFF *Sec = Context.getXCOFFSection(
-          S->getSymbolTableName(), XCOFF::XMC_PR, XCOFF::XTY_ER, SC,
-          SectionKind::getMetadata());
-      S->setRepresentedCsect(Sec);
-    }
-
     MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
     return DAG.getMCSymbol(S, PtrVT);
   };
 
   if (isFunctionGlobalAddress(Callee)) {
     const GlobalValue *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
 
     if (Subtarget.isAIXABI()) {
if (Subtarget.isAIXABI()) {
       // ExternalSymbol's, then we pick up the user-declared version.
       const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
       if (const Function *F =
               dyn_cast_or_null<Function>(Mod->getNamedValue(SymName)))
         return getAIXFuncEntryPointSymbolSDNode(F);
 
       // On AIX, direct function calls reference the symbol for the function's
       // entry point, which is named by prepending a "." before the function's
-      // C-linkage name.
-      const auto getFunctionEntryPointSymbol = [&](StringRef SymName) {
+      // C-linkage name and storage mapping classs[PR].
+      const auto getFunctionEntryPointQualNameSymbol = [&](StringRef SymName) {
         auto &Context = DAG.getMachineFunction().getMMI().getContext();
-        return cast<MCSymbolXCOFF>(
-            Context.getOrCreateSymbol(Twine(".") + Twine(SymName)));
+        MCSectionXCOFF *Sec = Context.getXCOFFSection(
+            (Twine(".") + Twine(SymName)).str(), XCOFF::XMC_PR, XCOFF::XTY_ER,
+            SectionKind::getMetadata());
+        return Sec->getQualNameSymbol();
       };
 
-      SymName = getFunctionEntryPointSymbol(SymName)->getName().data();
+      SymName = getFunctionEntryPointQualNameSymbol(SymName)->getName().data();
     }
     return DAG.getTargetExternalSymbol(SymName, Callee.getValueType(),
                                        UsePlt ? PPCII::MO_PLT : 0);
   }
 
   // No transformation needed.
   assert(Callee.getNode() && "What no callee?");
   return Callee;
 }
 
 static SDValue getOutputChainFromCallSeq(SDValue CallSeqStart) {
   assert(CallSeqStart.getOpcode() == ISD::CALLSEQ_START &&
          "Expected a CALLSEQ_STARTSDNode.");
 
   // The last operand is the chain, except when the node has glue. If the node
   // has glue, then the last operand is the glue, and the chain is the second
   // last operand.
   SDValue LastValue = CallSeqStart.getValue(CallSeqStart->getNumValues() - 1);

llvm/test/CodeGen/PowerPC/aix-cc-abi.ll

 ; CHECK-LABEL: name:            caller
 
 ; 32BIT:        liveins:
 ; 32BIT-NEXT:   - { reg: '$r3', virtual-reg: '' }
 ; 32BIT:        body:             |
 ; 32BIT-NEXT:   bb.0.entry:
 ; 32BIT:         liveins: $r3
 ; 32BIT:          ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT:          BL_NOP <mcsymbol .call_test_bool>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1, implicit-def $r3
+; 32BIT:          BL_NOP <mcsymbol .call_test_bool[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1, implicit-def $r3
 ; 32BIT:          ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; 64BIT:        liveins:
 ; 64BIT-NEXT:   - { reg: '$x3', virtual-reg: '' }
 ; 64BIT:        body:             |
 ; 64BIT-NEXT:    bb.0.entry:
 ; 64BIT-NEXT:     liveins: $x3
 ; 64BIT:          ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT:          BL8_NOP <mcsymbol .call_test_bool>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def $x3
+; 64BIT:          BL8_NOP <mcsymbol .call_test_bool[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def $x3
 ; 64BIT:          ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 @f1 = global float 0.000000e+00, align 4
 @d1 = global double 0.000000e+00, align 8
 
 define void @call_test_floats() {
 entry:
   %0 = load float, float* @f1, align 4

 ; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]], align 8)
 ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load 8 from @d1)
 ; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]] + 4)
 ; 32BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
 ; 32BIT-NEXT: renamable $r6 = LWZ 0, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]], align 8)
 ; 32BIT-NEXT: renamable $r7 = LWZ 4, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]] + 4)
 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT: $r3 = LI 42
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit $f2, implicit $r6, implicit $r7, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit $f2, implicit $r6, implicit $r7, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_vararg:
 
 ; ASM32PWR4:      stwu 1, -80(1)
 ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
 ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
 ; ASM32PWR4-NEXT: stfd 1, 64(1)
 ; ASM32PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM32PWR4-NEXT: li 3, 42
 ; ASM32PWR4-NEXT: stfd 2, 72(1)
 ; ASM32PWR4-DAG:  lwz 4, 64(1)
 ; ASM32PWR4-DAG:  lwz 5, 68(1)
 ; ASM32PWR4-DAG:  lwz 6, 72(1)
 ; ASM32PWR4-DAG:  lwz 7, 76(1)
-; ASM32PWR4-NEXT: bl .test_vararg
+; ASM32PWR4-NEXT: bl .test_vararg[PR]
 ; ASM32PWR4-NEXT: nop
 
 ; 64BIT:      renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load 4 from @f1)
 ; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @d1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store 8 into %stack.[[SLOT1]])
 ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d1)
 ; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load 8 from %stack.[[SLOT1]])
 ; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
 ; 64BIT-NEXT: renamable $x5 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]])
 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT: $x3 = LI8 42
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
 ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
 ; ASM64PWR4-NEXT: stfd 1, 112(1)
 ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM64PWR4-NEXT: li 3, 42
 ; ASM64PWR4-NEXT: stfd 2, 120(1)
 ; ASM64PWR4-NEXT: ld 4, 112(1)
 ; ASM64PWR4-NEXT: ld 5, 120(1)
-; ASM64PWR4-NEXT: bl .test_vararg
+; ASM64PWR4-NEXT: bl .test_vararg[PR]
 ; ASM64PWR4-NEXT: nop
 
 define void @call_test_vararg2() {
 entry:
   %0 = load float, float* @f1, align 4
   %conv = fpext float %0 to double
   %1 = load double, double* @d1, align 8
   call void (i32, ...) @test_vararg(i32 42, double %conv, i32 42, double %1)

 ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load 8 from @d1)
 ; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]] + 4)
 ; 32BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
 ; 32BIT-NEXT: renamable $r7 = LWZ 0, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]], align 8)
 ; 32BIT-NEXT: renamable $r8 = LWZ 4, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]] + 4)
 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT: $r3 = LI 42
 ; 32BIT-NEXT: $r6 = LI 42
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit $f2, implicit $r7, implicit $r8, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit $f2, implicit $r7, implicit $r8, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM32PWR4:      stwu 1, -80(1)
 ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
 ; ASM32PWR4-NEXT: li 6, 42
 ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
 ; ASM32PWR4-NEXT: stfd 1, 64(1)
 ; ASM32PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM32PWR4-NEXT: li 3, 42
 ; ASM32PWR4-NEXT: stfd 2, 72(1)
 ; ASM32PWR4-DAG: lwz 4, 64(1)
 ; ASM32PWR4-DAG: lwz 5, 68(1)
 ; ASM32PWR4-DAG: lwz 7, 72(1)
 ; ASM32PWR4-DAG: lwz 8, 76(1)
-; ASM32PWR4-NEXT: bl .test_vararg
+; ASM32PWR4-NEXT: bl .test_vararg[PR]
 ; ASM32PWR4-NEXT: nop
 
 ; 64BIT:      renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load 4 from @f1)
 ; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @d1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store 8 into %stack.[[SLOT1]])
 ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d1)
 ; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load 8 from %stack.[[SLOT1]])
 ; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
 ; 64BIT-NEXT: renamable $x6 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]])
 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT: $x3 = LI8 42
 ; 64BIT-NEXT: $x5 = LI8 42
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
 ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
 ; ASM64PWR4-NEXT: li 5, 42
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
 ; ASM64PWR4-NEXT: stfd 1, 112(1)
 ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM64PWR4-NEXT: li 3, 42
 ; ASM64PWR4-NEXT: stfd 2, 120(1)
 ; ASM64PWR4-NEXT: ld 4, 112(1)
 ; ASM64PWR4-NEXT: ld 6, 120(1)
-; ASM64PWR4-NEXT: bl .test_vararg
+; ASM64PWR4-NEXT: bl .test_vararg[PR]
 ; ASM64PWR4-NEXT: nop
 
 define void @call_test_vararg3() {
 entry:
   %0 = load float, float* @f1, align 4
   %conv = fpext float %0 to double
   %1 = load double, double* @d1, align 8
   call void (i32, ...) @test_vararg(i32 42, double %conv, i64 42, double %1)

 ; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]] + 4)
 ; 32BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
 ; 32BIT-NEXT: renamable $r8 = LWZ 0, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]], align 8)
 ; 32BIT-NEXT: renamable $r9 = LWZ 4, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]] + 4)
 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT: $r3 = LI 42
 ; 32BIT-NEXT: $r6 = LI 0
 ; 32BIT-NEXT: $r7 = LI 42
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit killed $r7, implicit $f2, implicit $r8, implicit $r9, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit killed $r7, implicit $f2, implicit $r8, implicit $r9, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM32PWR4:      stwu 1, -80(1)
 ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
 ; ASM32PWR4-DAG:  li 6, 0
 ; ASM32PWR4-DAG:  li 7, 42
 ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
 ; ASM32PWR4-NEXT: stfd 1, 64(1)
 ; ASM32PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM32PWR4-NEXT: li 3, 42
 ; ASM32PWR4-NEXT: stfd 2, 72(1)
 ; ASM32PWR4-DAG:  lwz 4, 64(1)
 ; ASM32PWR4-DAG:  lwz 5, 68(1)
 ; ASM32PWR4-DAG:  lwz 8, 72(1)
 ; ASM32PWR4-DAG:  lwz 9, 76(1)
-; ASM32PWR4-NEXT: bl .test_vararg
+; ASM32PWR4-NEXT: bl .test_vararg[PR]
 ; ASM32PWR4-NEXT: nop
 
 ; 64BIT:      renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load 4 from @f1)
 ; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @d1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store 8 into %stack.[[SLOT1]])
 ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d1)
 ; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load 8 from %stack.[[SLOT1]])
 ; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
 ; 64BIT-NEXT: renamable $x6 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]])
 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT: $x3 = LI8 42
 ; 64BIT-NEXT: $x5 = LI8 42
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
 ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
 ; ASM64PWR4-NEXT: li 5, 42
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
 ; ASM64PWR4-NEXT: stfd 1, 112(1)
 ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM64PWR4-NEXT: li 3, 42
 ; ASM64PWR4-NEXT: stfd 2, 120(1)
 ; ASM64PWR4-DAG:  ld 4, 112(1)
 ; ASM64PWR4-DAG:  ld 6, 120(1)
-; ASM64PWR4-NEXT: bl .test_vararg
+; ASM64PWR4-NEXT: bl .test_vararg[PR]
 ; ASM64PWR4-NEXT: nop
 
 define void @call_test_vararg4() {
 entry:
   %0 = load float, float* @f1, align 4
   call void (i32, ...) @test_vararg(i32 42, float %0)
   ret void
 }
 
 ; CHECK-LABEL:     name: call_test_vararg4
 
 ; 32BIT:      renamable $r[[REG:[0-9]+]] = LWZtoc @f1, $r2 :: (load 4 from got)
 ; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r[[REG]] :: (dereferenceable load 4 from @f1)
 ; 32BIT-NEXT: STFS renamable $f1, 0, %stack.[[SLOT:[0-9]+]] :: (store 4 into %stack.[[SLOT]])
 ; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT]] :: (load 4 from %stack.[[SLOT]])
 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT: $r3 = LI 42
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM32PWR4:      stwu 1, -64(1)
 ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
 ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM32PWR4-NEXT: li 3, 42
 ; ASM32PWR4-NEXT: stfs 1, 60(1)
 ; ASM32PWR4-NEXT: lwz 4, 60(1)
-; ASM32PWR4-NEXT: bl .test_vararg
+; ASM32PWR4-NEXT: bl .test_vararg[PR]
 ; ASM32PWR4-NEXT: nop
 
 ; 64BIT:      renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load 4 from @f1)
 ; 64BIT-NEXT: STFS renamable $f1, 0, %stack.[[SLOT:[0-9]+]] :: (store 4 into %stack.[[SLOT]])
 ; 64BIT-NEXT: renamable $x4 = LWZ8 0, %stack.[[SLOT]] :: (load 4 from %stack.[[SLOT]])
 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT: $x3 = LI8 42
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
 ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM64PWR4-NEXT: li 3, 42
 ; ASM64PWR4-NEXT: stfs 1, 124(1)
 ; ASM64PWR4-NEXT: lwz 4, 124(1)
-; ASM64PWR4-NEXT: bl .test_vararg
+; ASM64PWR4-NEXT: bl .test_vararg[PR]
 ; ASM64PWR4-NEXT: nop
 
 @c = common global i8 0, align 1
 @si = common global i16 0, align 2
 @i = common global i32 0, align 4
 @lli = common global i64 0, align 8
 @f = common global float 0.000000e+00, align 4
 @d = common global double 0.000000e+00, align 8

 ; 32BIT-DAG:  renamable $r[[REGI:[0-9]+]] = LWZ 0, killed renamable $r[[REGIADDR]] :: (dereferenceable load 4 from @i)
 ; 32BIT-DAG:  STW killed renamable $r[[REGI]], 64, $r1 :: (store 4)
 ; 32BIT-DAG:  renamable $r[[REGLLIADDR:[0-9]+]] = LWZtoc @lli, $r2 :: (load 4 from got)
 ; 32BIT-DAG:  renamable $r[[REGLLI1:[0-9]+]] = LWZ 0, renamable $r[[REGLLIADDR]] :: (dereferenceable load 4 from @lli, align 8)
 ; 32BIT-DAG:  STW killed renamable $r[[REGLLI1]], 68, $r1 :: (store 4)
 ; 32BIT-DAG:  renamable $r[[REGLLI2:[0-9]+]] = LWZ 4, killed renamable $r[[REGLLIADDR]] :: (dereferenceable load 4 from @lli + 4, align 8)
 ; 32BIT-DAG:  STW killed renamable $r[[REGLLI2]], 72, $r1 :: (store 4)
 ; 32BIT-DAG:  STW renamable $r[[REGI]], 76, $r1 :: (store 4)
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_int>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_int[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT: ADJCALLSTACKUP 80, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_stackarg_int:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32PWR4:       stwu 1, -80(1)
 ; ASM32PWR4-DAG:   li 3, 1
 ; ASM32PWR4-DAG:   li 4, 2

 ; ASM32PWR4-DAG:   lwz [[REGI:[0-9]+]], 0([[REGIADDR]])
 ; ASM32PWR4-DAG:   stw [[REGI]], 64(1)
 ; ASM32PWR4-DAG:   lwz [[REGLLIADDR:[0-9]+]], L..C7(2)
 ; ASM32PWR4-DAG:   lwz [[REGLLI1:[0-9]+]], 0([[REGLLIADDR]])
 ; ASM32PWR4-DAG:   stw [[REGLLI1]], 68(1)
 ; ASM32PWR4-DAG:   lwz [[REGLLI2:[0-9]+]], 4([[REGLLIADDR]])
 ; ASM32PWR4-DAG:   stw [[REGLLI2]], 72(1)
 ; ASM32PWR4-DAG:   stw [[REGI]], 76(1)
-; ASM32PWR4-NEXT:  bl .test_stackarg_int
+; ASM32PWR4-NEXT:  bl .test_stackarg_int[PR]
 ; ASM32PWR4-NEXT:  nop
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 64BIT-DAG:   ADJCALLSTACKDOWN 152, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-DAG:   $x3 = LI8 1
 ; 64BIT-DAG:   $x4 = LI8 2
 ; 64BIT-DAG:   $x5 = LI8 3
 ; 64BIT-DAG:   $x6 = LI8 4

 ; 64BIT-DAG:   STD killed renamable $x[[REGSI]], 120, $x1 :: (store 8)
 ; 64BIT-DAG:   renamable $x[[REGIADDR:[0-9]+]] = LDtoc @i, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[REGI:[0-9]+]] = LWZ8 0, killed renamable $x[[REGIADDR]] :: (dereferenceable load 4 from @i)
 ; 64BIT-DAG:   STD killed renamable $x[[REGI]], 128, $x1 :: (store 8)
 ; 64BIT-DAG:   renamable $x[[REGLLIADDR:[0-9]+]] = LDtoc @lli, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[REGLLI:[0-9]+]] = LD 0, killed renamable $x[[REGLLIADDR]] :: (dereferenceable load 8 from @lli)
 ; 64BIT-DAG:   STD killed renamable $x[[REGLLI]], 136, $x1 :: (store 8)
 ; 64BIT-DAG:   STD renamable $x[[REGI]], 144, $x1 :: (store 8)
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_int>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_int[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64PWR4-DAG:   stdu 1, -160(1)
 ; ASM64PWR4-DAG:   li 3, 1
 ; ASM64PWR4-DAG:   li 4, 2
 ; ASM64PWR4-DAG:   li 5, 3
 ; ASM64PWR4-DAG:   li 6, 4

 ; ASM64PWR4-DAG:   std [[REGSI]], 120(1)
 ; ASM64PWR4-DAG:   ld [[REGIADDR:[0-9]+]], L..C4(2)
 ; ASM64PWR4-DAG:   lwz [[REGI:[0-9]+]], 0([[REGIADDR]])
 ; ASM64PWR4-DAG:   std [[REGI]], 128(1)
 ; ASM64PWR4-DAG:   ld [[REGLLIADDR:[0-9]+]], L..C6(2)
 ; ASM64PWR4-DAG:   ld [[REGLLI:[0-9]+]], 0([[REGLLIADDR]])
 ; ASM64PWR4-DAG:   std [[REGLLI]], 136(1)
 ; ASM64PWR4-DAG:   std [[REGI]], 144(1)
-; ASM64PWR4-NEXT:  bl .test_stackarg_int
+; ASM64PWR4-NEXT:  bl .test_stackarg_int[PR]
 ; ASM64PWR4-NEXT:  nop
 
 ; Basic saving of floating point type arguments to the parameter save area.
 ; The float and double arguments will pass in both fpr as well as parameter save area.
 define void @call_test_stackarg_float() {
 entry:
   %0 = load float, float* @f, align 4
   %1 = load double, double* @d, align 8

 ; 32BIT-DAG:   $r9 = LI 7
 ; 32BIT-DAG:   $r10 = LI 8
 ; 32BIT-DAG:   renamable $r[[REGF:[0-9]+]] = LWZtoc @f, $r2 :: (load 4 from got)
 ; 32BIT-DAG:   renamable $f1 = LFS 0, killed renamable $r[[REGF]] :: (dereferenceable load 4 from @f)
 ; 32BIT-DAG:   renamable $r[[REGD:[0-9]+]] = LWZtoc @d, $r2 :: (load 4 from got)
 ; 32BIT-DAG:   renamable $f2 = LFD 0, killed renamable $r[[REGD]] :: (dereferenceable load 8 from @d)
 ; 32BIT-DAG:   STFS renamable $f1, 56, $r1 :: (store 4)
 ; 32BIT-DAG:   STFD renamable $f2, 60, $r1 :: (store 8)
-; 32BIT-NEXT:  BL_NOP <mcsymbol .test_stackarg_float>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $f1, implicit $f2, implicit $r2, implicit-def $r1
+; 32BIT-NEXT:  BL_NOP <mcsymbol .test_stackarg_float[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $f1, implicit $f2, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 68, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_stackarg_float:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32PWR4:      stwu 1, -80(1)
 ; ASM32PWR4-DAG:  li 3, 1
 ; ASM32PWR4-DAG:  li 4, 2
 ; ASM32PWR4-DAG:  li 5, 3
 ; ASM32PWR4-DAG:  li 6, 4
 ; ASM32PWR4-DAG:  li 7, 5
 ; ASM32PWR4-DAG:  li 8, 6
 ; ASM32PWR4-DAG:  li 9, 7
 ; ASM32PWR4-DAG:  li 10, 8
 ; ASM32PWR4-DAG:  lwz [[REGF:[0-9]+]], L..C8(2)
 ; ASM32PWR4-DAG:  lfs 1, 0([[REGF]])
 ; ASM32PWR4-DAG:  lwz [[REGD:[0-9]+]], L..C9(2)
 ; ASM32PWR4-DAG:  lfd 2, 0([[REGD:[0-9]+]])
 ; ASM32PWR4-DAG:  stfs 1, 56(1)
 ; ASM32PWR4-DAG:  stfd 2, 60(1)
-; ASM32PWR4-NEXT: bl .test_stackarg_float
+; ASM32PWR4-NEXT: bl .test_stackarg_float[PR]
 ; ASM32PWR4-NEXT: nop
 ; ASM32PWR4-NEXT: addi 1, 1, 80
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 64BIT-DAG:   ADJCALLSTACKDOWN 128, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-DAG:   $x3 = LI8 1
 ; 64BIT-DAG:   $x4 = LI8 2
 ; 64BIT-DAG:   $x5 = LI8 3
 ; 64BIT-DAG:   $x6 = LI8 4
 ; 64BIT-DAG:   $x7 = LI8 5
 ; 64BIT-DAG:   $x8 = LI8 6
 ; 64BIT-DAG:   $x9 = LI8 7
 ; 64BIT-DAG:   $x10 = LI8 8
 ; 64BIT-DAG:   renamable $x[[REGF:[0-9]+]] = LDtoc @f, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $f1 = LFS 0, killed renamable $x[[REGF]] :: (dereferenceable load 4 from @f)
 ; 64BIT-DAG:   renamable $x[[REGD:[0-9]+]] = LDtoc @d, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $f2 = LFD 0, killed renamable $x[[REGD]] :: (dereferenceable load 8 from @d)
 ; 64BIT-DAG:   STFS renamable $f1, 112, $x1 :: (store 4)
 ; 64BIT-DAG:   STFD renamable $f2, 120, $x1 :: (store 8)
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_float>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_float[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64PWR4:      stdu 1, -128(1)
 ; ASM64PWR4-DAG:  li 3, 1
 ; ASM64PWR4-DAG:  li 4, 2
 ; ASM64PWR4-DAG:  li 5, 3
 ; ASM64PWR4-DAG:  li 6, 4
 ; ASM64PWR4-DAG:  li 7, 5
 ; ASM64PWR4-DAG:  li 8, 6
 ; ASM64PWR4-DAG:  li 9, 7
 ; ASM64PWR4-DAG:  li 10, 8
 ; ASM64PWR4-DAG:  ld [[REGF:[0-9]+]], L..C7(2)
 ; ASM64PWR4-DAG:  lfs 1, 0([[REGF]])
 ; ASM64PWR4-DAG:  ld [[REGD:[0-9]+]], L..C8(2)
 ; ASM64PWR4-DAG:  lfd 2, 0([[REGD]])
 ; ASM64PWR4-DAG:  stfs 1, 112(1)
 ; ASM64PWR4-DAG:  stfd 2, 120(1)
-; ASM64PWR4-NEXT: bl .test_stackarg_float
+; ASM64PWR4-NEXT: bl .test_stackarg_float[PR]
 ; ASM64PWR4-NEXT: nop
 ; ASM64PWR4-NEXT: addi 1, 1, 128
 
 define void @call_test_stackarg_float2() {
 entry:
   %0 = load double, double* @d, align 8
   call void (i32, i32, i32, i32, i32, i32, ...) @test_stackarg_float2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, double %0)
   ret void

 ; 32BIT-DAG:   $r6 = LI 4
 ; 32BIT-DAG:   $r7 = LI 5
 ; 32BIT-DAG:   $r8 = LI 6
 ; 32BIT-DAG:   renamable $r[[REG:[0-9]+]] = LWZtoc @d, $r2 :: (load 4 from got)
 ; 32BIT-DAG:   renamable $f1 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load 8 from @d)
 ; 32BIT-DAG:   STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0)
 ; 32BIT-DAG:   renamable $r9 = LWZ 0, %stack.0 :: (load 4 from %stack.0, align 8)
 ; 32BIT-DAG:   renamable $r10 = LWZ 4, %stack.0 :: (load 4 from %stack.0 + 4)
-; 32BIT-NEXT:   BL_NOP <mcsymbol .test_stackarg_float2>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit $f1, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
+; 32BIT-NEXT:   BL_NOP <mcsymbol .test_stackarg_float2[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit $f1, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:   ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_stackarg_float2:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32PWR4:     stwu 1, -64(1)
 ; ASM32PWR4-DAG: li 3, 1
 ; ASM32PWR4-DAG: li 4, 2
 ; ASM32PWR4-DAG: li 5, 3
 ; ASM32PWR4-DAG: li 6, 4
 ; ASM32PWR4-DAG: li 7, 5
 ; ASM32PWR4-DAG: li 8, 6
 ; ASM32PWR4-DAG: lwz [[REG:[0-9]+]], L..C9(2)
 ; ASM32PWR4-DAG: lfd 1, 0([[REG]])
 ; ASM32PWR4-DAG: stfd 1, 56(1)
 ; ASM32PWR4-DAG: lwz 9, 56(1)
 ; ASM32PWR4-DAG: lwz 10, 60(1)
-; ASM32PWR4-NEXT: bl .test_stackarg_float2
+; ASM32PWR4-NEXT: bl .test_stackarg_float2[PR]
 ; ASM32PWR4-NEXT: nop
 ; ASM32PWR4-NEXT: addi 1, 1, 64
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 64BIT-DAG:   ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-DAG:   $x3 = LI8 1
 ; 64BIT-DAG:   $x4 = LI8 2
 ; 64BIT-DAG:   $x5 = LI8 3
 ; 64BIT-DAG:   $x6 = LI8 4
 ; 64BIT-DAG:   $x7 = LI8 5
 ; 64BIT-DAG:   $x8 = LI8 6
 ; 64BIT-DAG:   renamable $x[[REG:[0-9]+]] = LDtoc @d, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $f1 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d)
 ; 64BIT-DAG:   STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0)
 ; 64BIT-DAG:   renamable $x9 = LD 0, %stack.0 :: (load 8 from %stack.0)
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_float2>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_float2[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64PWR4:     stdu 1, -128(1)
 ; ASM64PWR4-DAG: li 3, 1
 ; ASM64PWR4-DAG: li 4, 2
 ; ASM64PWR4-DAG: li 5, 3
 ; ASM64PWR4-DAG: li 6, 4
 ; ASM64PWR4-DAG: li 7, 5
 ; ASM64PWR4-DAG: li 8, 6
 ; ASM64PWR4-DAG: ld [[REG:[0-9]+]], L..C8(2)
 ; ASM64PWR4-DAG: lfd 1, 0([[REG]])
 ; ASM64PWR4-DAG: stfd 1, 120(1)
 ; ASM64PWR4-DAG: ld 9, 120(1)
-; ASM64PWR4-NEXT: bl .test_stackarg_float2
+; ASM64PWR4-NEXT: bl .test_stackarg_float2[PR]
 ; ASM64PWR4-NEXT: nop
 ; ASM64PWR4-NEXT: addi 1, 1, 128
 
 ; A double arg will pass on the stack in PPC32 if there is only one available GPR.
 define void @call_test_stackarg_float3() {
 entry:
   %0 = load double, double* @d, align 8
   %1 = load float, float* @f, align 4

 ; 32BIT-DAG:   renamable $r[[REGD:[0-9]+]] = LWZtoc @d, $r2 :: (load 4 from got)
 ; 32BIT-DAG:   renamable $f1 = LFD 0, killed renamable $r[[REGD]] :: (dereferenceable load 8 from @d)
 ; 32BIT-DAG:   renamable $r[[REGF:[0-9]+]] = LWZtoc @f, $r2 :: (load 4 from got)
 ; 32BIT-DAG:   renamable $f2 = LFS 0, killed renamable $r[[REGF]] :: (dereferenceable load 4 from @f)
 ; 32BIT-DAG:   STFD renamable $f1, 52, $r1 :: (store 8)
 ; 32BIT-DAG:   STFS renamable $f2, 60, $r1 :: (store 4)
 ; 32BIT-DAG:   STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0)
 ; 32BIT-DAG:   renamable $r10 = LWZ 0, %stack.0 :: (load 4 from %stack.0, align 8)
-; 32BIT-NEXT:  BL_NOP <mcsymbol .test_stackarg_float3>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $f1, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1
+; 32BIT-NEXT:  BL_NOP <mcsymbol .test_stackarg_float3[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $f1, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 64, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_stackarg_float3:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32PWR4:       stwu 1, -80(1)
 ; ASM32PWR4-DAG:   li 3, 1
 ; ASM32PWR4-DAG:   li 4, 2
 ; ASM32PWR4-DAG:   li 5, 3
 ; ASM32PWR4-DAG:   li 6, 4
 ; ASM32PWR4-DAG:   li 7, 5
 ; ASM32PWR4-DAG:   li 8, 6
 ; ASM32PWR4-DAG:   li 9, 7
 ; ASM32PWR4-DAG:   lwz [[REGD:[0-9]+]], L..C9(2)
 ; ASM32PWR4-DAG:   lfd 1, 0([[REGD]])
 ; ASM32PWR4-DAG:   lwz [[REGF:[0-9]+]], L..C8(2)
 ; ASM32PWR4-DAG:   lfs 2, 0([[REGF]])
 ; ASM32PWR4-DAG:   stfd 1, 52(1)
 ; ASM32PWR4-DAG:   stfs 2, 60(1)
 ; ASM32PWR4-DAG:   stfd 1, 72(1)
 ; ASM32PWR4-DAG:   lwz 10, 72(1)
-; ASM32PWR4-NEXT:  bl .test_stackarg_float3
+; ASM32PWR4-NEXT:  bl .test_stackarg_float3[PR]
 ; ASM32PWR4-NEXT:  nop
 ; ASM32PWR4-NEXT:  addi 1, 1, 80
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; In 64-bit the double arg is not written to memory because it is fully stored in the last 64-bit GPR.
 ; 64BIT-DAG:   ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-DAG:   $x3 = LI8 1
 ; 64BIT-DAG:   $x4 = LI8 2
 ; 64BIT-DAG:   $x5 = LI8 3
 ; 64BIT-DAG:   $x6 = LI8 4
 ; 64BIT-DAG:   $x7 = LI8 5
 ; 64BIT-DAG:   $x8 = LI8 6
 ; 64BIT-DAG:   $x9 = LI8 7
 ; 64BIT-DAG:   renamable $x[[REGD:[0-9]+]] = LDtoc @d, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $f1 = LFD 0, killed renamable $x[[REGD]] :: (dereferenceable load 8 from @d)
 ; 64BIT-DAG:   renamable $x[[REGF:[0-9]+]] = LDtoc @f, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $f2 = LFS 0, killed renamable $x[[REGF]] :: (dereferenceable load 4 from @f)
 ; 64BIT-DAG:   STFS renamable $f2, 112, $x1 :: (store 4)
 ; 64BIT-DAG:   STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0)
 ; 64BIT-DAG:   renamable $x10 = LD 0, %stack.0 :: (load 8 from %stack.0)
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_float3>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_float3[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1
 
 ; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64PWR4:       stdu 1, -128(1)
 ; ASM64PWR4-DAG:   li 3, 1
 ; ASM64PWR4-DAG:   li 4, 2
 ; ASM64PWR4-DAG:   li 5, 3
 ; ASM64PWR4-DAG:   li 6, 4
 ; ASM64PWR4-DAG:   li 7, 5
 ; ASM64PWR4-DAG:   li 8, 6
 ; ASM64PWR4-DAG:   li 9, 7
 ; ASM64PWR4-DAG:   ld [[REGD:[0-9]+]], L..C8(2)
 ; ASM64PWR4-DAG:   lfd 1, 0([[REGD]])
 ; ASM64PWR4-DAG:   ld [[REGF:[0-9]+]], L..C7(2)
 ; ASM64PWR4-DAG:   lfs 2, 0([[REGF]])
 ; ASM64PWR4-DAG:   stfs 2, 112(1)
 ; ASM64PWR4-DAG:   stfd 1, 120(1)
 ; ASM64PWR4-DAG:   ld 10, 120(1)
-; ASM64PWR4-NEXT:  bl .test_stackarg_float3
+; ASM64PWR4-NEXT:  bl .test_stackarg_float3[PR]
 ; ASM64PWR4-NEXT:  nop
 ; ASM64PWR4-NEXT:  addi 1, 1, 128
 
 define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i64 %ll9, i16 signext %s10, i8 zeroext %c11, i32 %ui12, i32 %si13, i64 %ll14, i8 zeroext %uc15, i32 %i16) {
 entry:
   %add = add nsw i32 %i1, %i2
   %add1 = add nsw i32 %add, %i3
   %add2 = add nsw i32 %add1, %i4

llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll

 ; Confirm the expected memcpy call is independent of the call to test_byval_mem2.
 ; 32BIT:          ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:     %0:gprc = nuw ADDI $r1, 56
 ; 32BIT-NEXT:     %1:gprc = LWZtoc @gS256, $r2 :: (load 4 from got)
 ; 32BIT-NEXT:     %2:gprc = LI 256
 ; 32BIT-DAG:      $r3 = COPY %0
 ; 32BIT-DAG:      $r4 = COPY %1
 ; 32BIT-DAG:      $r5 = COPY %2
-; 32BIT-NEXT:     BL_NOP &.memcpy, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
+; 32BIT-NEXT:     BL_NOP &".memcpy[PR]", csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
 ; 32BIT-NEXT:     ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT:          ADJCALLSTACKDOWN 312, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-DAG:      $r3 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r4 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r5 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r6 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r7 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r8 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r9 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r10 = COPY %{{[0-9]+}}
 ; 32BIT-NEXT:     BL_NOP <mcsymbol .test_byval_mem2>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:     ADJCALLSTACKUP 312, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_mem2:
 
 ; ASM32BIT:       stwu 1, -320(1)
 ; ASM32BIT-DAG:   addi 3, 1, 56
 ; ASM32BIT-DAG:   lwz 4, L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   li 5, 256
-; ASM32BIT-NEXT:  bl .memcpy
+; ASM32BIT-NEXT:  bl .memcpy[PR]
 ; ASM32BIT:       bl .test_byval_mem2
 ; ASM32BIT:       addi 1, 1, 320
 
 ; Confirm the expected memcpy call is independent of the call to test_byval_mem2.
 ; 64BIT:          ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:     %0:g8rc = nuw ADDI8 $x1, 112
 ; 64BIT-NEXT:     %1:g8rc = LDtoc @gS256, $x2 :: (load 8 from got)
 ; 64BIT-NEXT:     %2:g8rc = LI8 256
 ; 64BIT-DAG:      $x3 = COPY %0
 ; 64BIT-DAG:      $x4 = COPY %1
 ; 64BIT-DAG:      $x5 = COPY %2
-; 64BIT-NEXT:     BL8_NOP &.memcpy, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1, implicit-def $x3
+; 64BIT-NEXT:     BL8_NOP &".memcpy[PR]", csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1, implicit-def $x3
 ; 64BIT-NEXT:     ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT:          ADJCALLSTACKDOWN 368, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-DAG:      $x3 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x4 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x5 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x6 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x7 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x8 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x9 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x10 = COPY %{{[0-9]+}}
 ; 64BIT-NEXT:     BL8_NOP <mcsymbol .test_byval_mem2>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:     ADJCALLSTACKUP 368, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64BIT:       stdu 1, -368(1)
 ; ASM64BIT-DAG:   addi 3, 1, 112
 ; ASM64BIT-DAG:   ld 4, L..C{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   li 5, 256
-; ASM64BIT-NEXT:  bl .memcpy
+; ASM64BIT-NEXT:  bl .memcpy[PR]
 ; ASM64BIT:       bl .test_byval_mem2
 ; ASM64BIT:       addi 1, 1, 368
 
 
 define zeroext i8 @test_byval_mem2(i32, i32, i32, i32, i32, i32, i32, i32, %struct_S256* byval(%struct_S256) align 1 %s) {
 entry:
   %gep = getelementptr inbounds %struct_S256, %struct_S256* %s, i32 0, i32 0, i32 255
   %load = load i8, i8* %gep, align 1

 ; 32BIT:          ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:     %0:gprc_and_gprc_nor0 = LWZtoc @gS57, $r2 :: (load 4 from got)
 ; 32BIT-NEXT:     %1:gprc = nuw ADDI %0, 24
 ; 32BIT-NEXT:     %2:gprc = nuw ADDI $r1, 56
 ; 32BIT-NEXT:     %3:gprc = LI 33
 ; 32BIT-DAG:      $r3 = COPY %2
 ; 32BIT-DAG:      $r4 = COPY %1
 ; 32BIT-DAG:      $r5 = COPY %3
-; 32BIT-NEXT:     BL_NOP &.memcpy, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
+; 32BIT-NEXT:     BL_NOP &".memcpy[PR]", csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
 ; 32BIT-NEXT:     ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT:          ADJCALLSTACKDOWN 92, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-DAG:      $r3 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $f1 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r5 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r6 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r7 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r8 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r9 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r10 = COPY %{{[0-9]+}}
 ; 32BIT-NEXT:     BL_NOP <mcsymbol .test_byval_mem3>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:     ADJCALLSTACKUP 92, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_mem3:
 
 ; ASM32BIT:       stwu 1, -112(1)
 ; ASM32BIT-DAG:   lwz [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   addi 3, 1, 56
 ; ASM32BIT-DAG:   addi 4, [[REG]], 24
 ; ASM32BIT-DAG:   li 5, 33
-; ASM32BIT-NEXT:  bl .memcpy
+; ASM32BIT-NEXT:  bl .memcpy[PR]
 ; ASM32BIT-DAG:   lwz 5, 0([[REG]])
 ; ASM32BIT-DAG:   lwz 6, 4([[REG]])
 ; ASM32BIT-DAG:   lwz 7, 8([[REG]])
 ; ASM32BIT-DAG:   lwz 8, 12([[REG]])
 ; ASM32BIT-DAG:   lwz 9, 16([[REG]])
 ; ASM32BIT-DAG:   lwz 10, 20([[REG]])
 ; ASM32BIT:       bl .test_byval_mem3
 ; ASM32BIT:       addi 1, 1, 112

 ; Confirm the expected memcpy call is independent of the call to test_byval_mem4.
 ; 32BIT:          ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:     %3:gprc = nuw ADDI $r1, 60
 ; 32BIT-NEXT:     %4:gprc = LWZtoc @gS256, $r2 :: (load 4 from got)
 ; 32BIT-NEXT:     %5:gprc = LI 256
 ; 32BIT-DAG:      $r3 = COPY %3
 ; 32BIT-DAG:      $r4 = COPY %4
 ; 32BIT-DAG:      $r5 = COPY %5
-; 32BIT-NEXT:     BL_NOP &.memcpy, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
+; 32BIT-NEXT:     BL_NOP &".memcpy[PR]", csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
 ; 32BIT-NEXT:     ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT:          ADJCALLSTACKDOWN 316, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-DAG:      $r3 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r4 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r5 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r6 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r7 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r8 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r9 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r10 = COPY %{{[0-9]+}}
 ; 32BIT-NEXT:     BL_NOP <mcsymbol .test_byval_mem4>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:     ADJCALLSTACKUP 316, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM32BIT:       stwu 1, -336(1)
 ; ASM32BIT-NEXT:  stw [[REG1:[0-9]+]], {{[0-9]+}}(1)
 ; ASM32BIT:       lwz [[REG1]], L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   lhz [[REG2:[0-9]+]], 28([[REG1]])
 ; ASM32BIT-DAG:   sth [[REG2]], 56(1)
 ; ASM32BIT-DAG:   lbz [[REG3:[0-9]+]], 30([[REG1]])
 ; ASM32BIT-DAG:   stb [[REG3]], 58(1)
 ; ASM32BIT-DAG:   addi 3, 1, 60
 ; ASM32BIT-DAG:   lwz 4, L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   li 5, 256
-; ASM32BIT-NEXT:  bl .memcpy
+; ASM32BIT-NEXT:  bl .memcpy[PR]
 ; ASM32BIT-DAG:   lwz 4, 0([[REG1]])
 ; ASM32BIT-DAG:   lwz 5, 4([[REG1]])
 ; ASM32BIT-DAG:   lwz 6, 8([[REG1]])
 ; ASM32BIT-DAG:   lwz 7, 12([[REG1]])
 ; ASM32BIT-DAG:   lwz 8, 16([[REG1]])
 ; ASM32BIT-DAG:   lwz 9, 20([[REG1]])
 ; ASM32BIT-DAG:   lwz 10, 24([[REG1]])
 ; ASM32BIT:       bl .test_byval_mem4
 ; ASM32BIT:       addi 1, 1, 336
 
 ; Confirm the expected memcpy call is independent of the call to test_byval_mem4.
 ; 64BIT:          ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:     %0:g8rc_and_g8rc_nox0 = LDtoc @gS256, $x2 :: (load 8 from got)
 ; 64BIT-NEXT:     %1:g8rc = nuw ADDI8 %0, 24
 ; 64BIT-NEXT:     %2:g8rc = nuw ADDI8 $x1, 112
 ; 64BIT-NEXT:     %3:g8rc = LI8 232
 ; 64BIT-DAG:      $x3 = COPY %2
 ; 64BIT-DAG:      $x4 = COPY %1
 ; 64BIT-DAG:      $x5 = COPY %3
-; 64BIT-NEXT:     BL8_NOP &.memcpy, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1, implicit-def $x3
+; 64BIT-NEXT:     BL8_NOP &".memcpy[PR]", csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1, implicit-def $x3
 ; 64BIT-NEXT:     ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT:          ADJCALLSTACKDOWN 344, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-DAG:      $x3 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x4 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x5 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x6 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x7 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x8 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x9 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x10 = COPY %{{[0-9]+}}
 ; 64BIT-NEXT:     BL8_NOP <mcsymbol .test_byval_mem4>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:     ADJCALLSTACKUP 344, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64BIT:       stdu 1, -368(1)
 ; ASM64BIT-DAG:   ld [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   addi 3, 1, 112
 ; ASM64BIT-DAG:   addi 4, [[REG1]], 24
 ; ASM64BIT-DAG:   li 5, 232
-; ASM64BIT-NEXT:  bl .memcpy
+; ASM64BIT-NEXT:  bl .memcpy[PR]
 ; ASM64BIT-DAG:   ld [[REG2:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   ld 4, 0([[REG2]])
 ; ASM64BIT-DAG:   ld 5, 8([[REG2]])
 ; ASM64BIT-DAG:   ld 6, 16([[REG2]])
 ; ASM64BIT-DAG:   lwz [[REG3:[0-9]+]], 24([[REG2]])
 ; ASM64BIT-DAG:   lhz [[REG4:[0-9]+]], 28([[REG2]])
 ; ASM64BIT-DAG:   lbz 7, 30([[REG2]])
 ; ASM64BIT-DAG:   rlwinm 7, 7, 8, 16, 23

llvm/test/CodeGen/PowerPC/aix-cc-byval.ll

 ; ASM-LABEL: .call_test_byval_5Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:  renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS5, $r2 :: (load 4 from got)
 ; 32BIT-DAG:   renamable $r[[REG1:[0-9]+]] = LBZ 4, renamable $r[[REGADDR]] :: (load 1)
 ; 32BIT-DAG:   renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
 ; 32BIT-DAG:   renamable $r4 = RLWINM killed renamable $r[[REG1]], 24, 0, 7
-; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_5Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
+; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_5Byte[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:   ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_5Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
 ; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lbz [[REG1:[0-9]+]], 4([[REGADDR]])
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   slwi 4, [[REG1]], 24
-; ASM32-NEXT:  bl .test_byval_5Byte
+; ASM32-NEXT:  bl .test_byval_5Byte[PR]
 ; ASM32-NEXT:  nop
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS5, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
 ; 64BIT-DAG:   renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1)
 ; 64BIT-DAG:   renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7
 ; 64BIT-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_5Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_5Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64:       stdu 1, -112(1)
 ; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM64-DAG:   rlwinm 3, [[REG2]], 24, 0, 7
 ; ASM64-DAG:   rldimi 3, [[REG1]], 32, 0
-; ASM64-NEXT:  bl .test_byval_5Byte
+; ASM64-NEXT:  bl .test_byval_5Byte[PR]
 ; ASM64-NEXT:  nop
 
 
 %struct.S6 = type { [6 x i8] }
 
 @gS6 = external global %struct.S6, align 1
 
 define void @call_test_byval_6Byte() {
 entry:
   %call = call zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1 @gS6)
   ret void
 }
 
 declare zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1)
 
 ; CHECK-LABEL: name: call_test_byval_6Byte{{.*}}
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:  renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS6, $r2 :: (load 4 from got)
 ; 32BIT-DAG:   renamable $r[[REG1:[0-9]+]] = LHZ 4, renamable $r[[REGADDR]] :: (load 2)
 ; 32BIT-DAG:   renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
 ; 32BIT-DAG:   renamable $r4 = RLWINM killed renamable $r[[REG1]], 16, 0, 15
-; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_6Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
+; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_6Byte[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_6Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
 ; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lhz [[REG1:[0-9]+]], 4([[REGADDR]])
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   slwi 4, [[REG1]], 16
-; ASM32-NEXT:  bl .test_byval_6Byte
+; ASM32-NEXT:  bl .test_byval_6Byte[PR]
 ; ASM32-NEXT:  nop
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS6, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
 ; 64BIT-DAG:   renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
 ; 64BIT-DAG:   renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15
 ; 64BIT-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_6Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_6Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64:       stdu 1, -112(1)
 ; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lhz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM64-DAG:   rlwinm 3, [[REG2]], 16, 0, 15
 ; ASM64-DAG:   rldimi 3, [[REG1]], 32, 0
-; ASM64-NEXT:  bl .test_byval_6Byte
+; ASM64-NEXT:  bl .test_byval_6Byte[PR]
 ; ASM64-NEXT:  nop
 
 
 %struct.S7 = type { [7 x i8] }
 
 @gS7 = external global %struct.S7, align 1
 
 define void @call_test_byval_7Byte() {

 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:  renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS7, $r2 :: (load 4 from got)
 ; 32BIT-DAG:   renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
 ; 32BIT-DAG:   renamable $r[[REG1:[0-9]+]] = LHZ 4, renamable $r[[REGADDR]] :: (load 2)
 ; 32BIT-DAG:   renamable $r[[REG2:[0-9]+]] = LBZ 6, renamable $r[[REGADDR]] :: (load 1)
 ; 32BIT-DAG:   renamable $r4 = RLWINM killed renamable $r[[REG2]], 8, 16, 23
 ; 32BIT-DAG:   renamable $r4 = RLWIMI killed renamable $r4, killed renamable $r[[REG1]], 16, 0, 15
-; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_7Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
+; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_7Byte[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_7Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
 ; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   lhz [[REG1:[0-9]+]], 4([[REGADDR]])
 ; ASM32-DAG:   lbz [[REG2:[0-9]+]], 6([[REGADDR]])
 ; ASM32-DAG:   rlwinm 4, [[REG2]], 8, 16, 23
 ; ASM32-DAG:   rlwimi 4, [[REG1]], 16, 0, 15
-; ASM32-NEXT:  bl .test_byval_7Byte
+; ASM32-NEXT:  bl .test_byval_7Byte[PR]
 ; ASM32-NEXT:  nop
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
 ; 64BIT-DAG:   renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
 ; 64BIT-DAG:   renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load 1)
 ; 64BIT-DAG:   renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
 ; 64BIT-DAG:   renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15
 ; 64BIT-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_7Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_7Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64:       stdu 1, -112(1)
 ; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lhz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG3:[0-9]+]], 6([[REGADDR]])
 ; ASM64-DAG:   rlwinm 3, [[REG3]], 8, 16, 23
 ; ASM64-DAG:   rlwimi 3, [[REG2]], 16, 0, 15
 ; ASM64-DAG:   rldimi 3, [[REG1]], 32, 0
-; ASM64-NEXT:  bl .test_byval_7Byte
+; ASM64-NEXT:  bl .test_byval_7Byte[PR]
 ; ASM64-NEXT:  nop
 
 
 %struct.S8 = type { [8 x i8] }
 
 @gS8 = external global %struct.S8, align 1
 
 define void @call_test_byval_8Byte() {
 entry:
   %call = call zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1 @gS8)
   ret void
 }
 
 declare zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1)
 
 ; CHECK-LABEL: name: call_test_byval_8Byte{{.*}}
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:  renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS8, $r2 :: (load 4 from got)
 ; 32BIT-DAG:   renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
 ; 32BIT-DAG:   renamable $r4 = LWZ 4, renamable $r[[REGADDR]] :: (load 4)
-; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_8Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
+; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_8Byte[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_8Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
 ; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   lwz 4, 4([[REGADDR]])
-; ASM32-NEXT:  bl .test_byval_8Byte
+; ASM32-NEXT:  bl .test_byval_8Byte[PR]
 ; ASM32-NEXT:  nop
 
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got)
 ; 64BIT-NEXT:  renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_8Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_8Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64:       stdu 1, -112(1)
 ; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-NEXT:  ld 3, 0([[REGADDR]])
-; ASM64-NEXT:  bl .test_byval_8Byte
+; ASM64-NEXT:  bl .test_byval_8Byte[PR]
 ; ASM64-NEXT:  nop
 
 
 %struct.S32 = type { [32 x i8] }
 
 @gS32 = external global %struct.S32, align 1
 
 define void @call_test_byval_32Byte() {

 declare i32 @test_byval_homogeneous_float_struct(%struct.F* byval(%struct.F) align 4)
 
 ; CHECK-LABEL: name: call_test_byval_homogeneous_float_struct{{.*}}
 
 ; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-DAG:   renamable $r3 = LWZ 0, %stack.0.s :: (load 4 from %stack.0.s, align 8)
 ; 32BIT-DAG:   renamable $r4 = LWZ 4, %stack.0.s :: (load 4 from %stack.0.s + 4)
 ; 32BIT-DAG:   renamable $r5 = LWZ 8, %stack.0.s :: (load 4 from %stack.0.s + 8, align 8)
-; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_homogeneous_float_struct>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
+; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_homogeneous_float_struct[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_homogeneous_float_struct:
 
 ; ASM32:       stwu 1, -80(1)
 ; ASM32-DAG:   lwz 3, 64(1)
 ; ASM32-DAG:   lwz 4, 68(1)
 ; ASM32-DAG:   lwz 5, 72(1)
-; ASM32-NEXT:  bl .test_byval_homogeneous_float_struct
+; ASM32-NEXT:  bl .test_byval_homogeneous_float_struct[PR]
 ; ASM32-NEXT:  nop
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-DAG:   renamable $x3 = LD 0, %stack.0.s :: (load 8 from %stack.0.s)
 ; 64BIT-DAG:   renamable $x4 = LWZ8 8, %stack.0.s :: (load 4 from %stack.0.s + 8, align 8)
 ; 64BIT-DAG:   renamable $x4 = RLDICR killed renamable $x4, 32, 31
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_homogeneous_float_struct>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1, implicit-def $x3
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_homogeneous_float_struct[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1, implicit-def $x3
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64:       stdu 1, -128(1)
 ; ASM64-DAG:   ld 3, 112(1)
 ; ASM64-DAG:   lwz 4, 120(1)
 ; ASM64-DAG:   sldi 4, 4, 32
-; ASM64-NEXT:  bl .test_byval_homogeneous_float_struct
+; ASM64-NEXT:  bl .test_byval_homogeneous_float_struct[PR]
 ; ASM64-NEXT:  nop

llvm/test/CodeGen/PowerPC/aix-extern-weak.ll

 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
 ; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT32 %s
 
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
 ; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT64 %s
 
 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
-; RUN: -mattr=-altivec < %s | FileCheck  %s
-
-; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
 ; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 ; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -mattr=-altivec -filetype=obj -o %t.o 2>&1 < %s | FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 

 ; COMMON:         .csect  .data[RW]
 ; COMMON:         .globl  foo_ext_weak_p
 ; BIT32-NEXT:     .align  2
 ; BIT64-NEXT:     .align  3
 ; COMMON-NEXT: foo_ext_weak_p:
 ; BIT32-NEXT:     .vbyte  4, foo_ext_weak_ref[DS]
 ; BIT64-NEXT:     .vbyte  8, foo_ext_weak_ref[DS]
 ; COMMON-NEXT:    .weak   b_w[UA]
+; COMMON-NEXT:    .weak   .foo_ext_weak_ref[PR]
 ; COMMON-NEXT:    .weak   foo_ext_weak_ref[DS]
-; COMMON-NEXT:    .weak   .foo_ext_weak
+; COMMON-NEXT:    .weak   .foo_ext_weak[PR]
 ; COMMON-NEXT:    .weak   foo_ext_weak[DS]
 ; COMMON-NEXT:    .toc
 ; COMMON-NEXT: L..C0:
 ; COMMON-NEXT:    .tc foo_ext_weak_p[TC],foo_ext_weak_p
 ; COMMON-NEXT: L..C1:
 ; COMMON-NEXT:    .tc b_w[TC],b_w[UA]
 
-; CHECK-NOT:      .weak   .foo_ext_weak_ref
-
 ; CHECKSYM:      Symbols [
 ; CHECKSYM-NEXT:   Symbol {
 ; CHECKSYM-NEXT:     Index: [[#Index:]]
 ; CHECKSYM-NEXT:     Name: .foo_ext_weak
 ; CHECKSYM-NEXT:     Value (RelocatableAddress): 0x0
 ; CHECKSYM-NEXT:     Section: N_UNDEF
 ; CHECKSYM-NEXT:     Type: 0x0
 ; CHECKSYM-NEXT:     StorageClass: C_WEAKEXT (0x6F)

 ; CHECKSYM-NEXT:       SymbolType: XTY_ER (0x0)
 ; CHECKSYM-NEXT:       StorageMappingClass: XMC_UA (0x4)
 ; CHECKSYM-NEXT:       StabInfoIndex: 0x0
 ; CHECKSYM-NEXT:       StabSectNum: 0x0
 ; CHECKSYM-NEXT:     }
 ; CHECKSYM-NEXT:   }
 ; CHECKSYM-NEXT:   Symbol {
 ; CHECKSYM-NEXT:     Index: [[#Index+6]]
-; CHECKSYM-NEXT:     Name: foo_ext_weak
+; CHECKSYM-NEXT:     Name: .foo_ext_weak_ref
 ; CHECKSYM-NEXT:     Value (RelocatableAddress): 0x0
 ; CHECKSYM-NEXT:     Section: N_UNDEF
 ; CHECKSYM-NEXT:     Type: 0x0
 ; CHECKSYM-NEXT:     StorageClass: C_WEAKEXT (0x6F)
 ; CHECKSYM-NEXT:     NumberOfAuxEntries: 1
 ; CHECKSYM-NEXT:     CSECT Auxiliary Entry {
 ; CHECKSYM-NEXT:       Index: [[#Index+7]]
 ; CHECKSYM-NEXT:       SectionLen: 0
 ; CHECKSYM-NEXT:       ParameterHashIndex: 0x0
 ; CHECKSYM-NEXT:       TypeChkSectNum: 0x0
 ; CHECKSYM-NEXT:       SymbolAlignmentLog2: 0
 ; CHECKSYM-NEXT:       SymbolType: XTY_ER (0x0)
-; CHECKSYM-NEXT:       StorageMappingClass: XMC_DS (0xA)
+; CHECKSYM-NEXT:       StorageMappingClass: XMC_PR (0x0)
 ; CHECKSYM-NEXT:       StabInfoIndex: 0x0
 ; CHECKSYM-NEXT:       StabSectNum: 0x0
 ; CHECKSYM-NEXT:     }
 ; CHECKSYM-NEXT:   }
 ; CHECKSYM-NEXT:   Symbol {
 ; CHECKSYM-NEXT:     Index: [[#Index+8]]
+; CHECKSYM-NEXT:     Name: foo_ext_weak
+; CHECKSYM-NEXT:     Value (RelocatableAddress): 0x0
+; CHECKSYM-NEXT:     Section: N_UNDEF
+; CHECKSYM-NEXT:     Type: 0x0
+; CHECKSYM-NEXT:     StorageClass: C_WEAKEXT (0x6F)
+; CHECKSYM-NEXT:     NumberOfAuxEntries: 1
+; CHECKSYM-NEXT:     CSECT Auxiliary Entry {
+; CHECKSYM-NEXT:       Index: [[#Index+9]]
+; CHECKSYM-NEXT:       SectionLen: 0
+; CHECKSYM-NEXT:       ParameterHashIndex: 0x0
+; CHECKSYM-NEXT:       TypeChkSectNum: 0x0
+; CHECKSYM-NEXT:       SymbolAlignmentLog2: 0
+; CHECKSYM-NEXT:       SymbolType: XTY_ER (0x0)
+; CHECKSYM-NEXT:       StorageMappingClass: XMC_DS (0xA)
+; CHECKSYM-NEXT:       StabInfoIndex: 0x0
+; CHECKSYM-NEXT:       StabSectNum: 0x0
+; CHECKSYM-NEXT:     }
+; CHECKSYM-NEXT:   }
+; CHECKSYM-NEXT:   Symbol {
+; CHECKSYM-NEXT:     Index: [[#Index+10]]
 ; CHECKSYM-NEXT:     Name: .text
 ; CHECKSYM-NEXT:     Value (RelocatableAddress): 0x0
 ; CHECKSYM-NEXT:     Section: .text
 ; CHECKSYM-NEXT:     Type: 0x0
 ; CHECKSYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; CHECKSYM-NEXT:     NumberOfAuxEntries: 1
 ; CHECKSYM-NEXT:     CSECT Auxiliary Entry {
-; CHECKSYM-NEXT:       Index: [[#Index+9]]
+; CHECKSYM-NEXT:       Index: [[#Index+11]]
 ; CHECKSYM-NEXT:       SectionLen: 80
 ; CHECKSYM-NEXT:       ParameterHashIndex: 0x0
 ; CHECKSYM-NEXT:       TypeChkSectNum: 0x0
 ; CHECKSYM-NEXT:       SymbolAlignmentLog2: 4
 ; CHECKSYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; CHECKSYM-NEXT:       StorageMappingClass: XMC_PR (0x0)
 ; CHECKSYM-NEXT:       StabInfoIndex: 0x0
 ; CHECKSYM-NEXT:       StabSectNum: 0x0
 ; CHECKSYM-NEXT:     }
 ; CHECKSYM-NEXT:   }
 ; CHECKSYM-NEXT:   Symbol {
-; CHECKSYM-NEXT:     Index: [[#Index+10]]
+; CHECKSYM-NEXT:     Index: [[#Index+12]]
 ; CHECKSYM-NEXT:     Name: .main
 ; CHECKSYM-NEXT:     Value (RelocatableAddress): 0x0
 ; CHECKSYM-NEXT:     Section: .text
 ; CHECKSYM-NEXT:     Type: 0x0
 ; CHECKSYM-NEXT:     StorageClass: C_EXT (0x2)
 ; CHECKSYM-NEXT:     NumberOfAuxEntries: 1
 ; CHECKSYM-NEXT:     CSECT Auxiliary Entry {
-; CHECKSYM-NEXT:       Index: [[#Index+11]]
-; CHECKSYM-NEXT:       ContainingCsectSymbolIndex: [[#Index+8]]
+; CHECKSYM-NEXT:       Index: [[#Index+13]]
+; CHECKSYM-NEXT:       ContainingCsectSymbolIndex: [[#Index+10]]
 ; CHECKSYM-NEXT:       ParameterHashIndex: 0x0
 ; CHECKSYM-NEXT:       TypeChkSectNum: 0x0
 ; CHECKSYM-NEXT:       SymbolAlignmentLog2: 0
 ; CHECKSYM-NEXT:       SymbolType: XTY_LD (0x2)
 ; CHECKSYM-NEXT:       StorageMappingClass: XMC_PR (0x0)
 ; CHECKSYM-NEXT:       StabInfoIndex: 0x0
 ; CHECKSYM-NEXT:       StabSectNum: 0x0
 ; CHECKSYM-NEXT:     }
 ; CHECKSYM-NEXT:   }
 ; CHECKSYM-NEXT:   Symbol {
-; CHECKSYM-NEXT:     Index: [[#Index+12]]
+; CHECKSYM-NEXT:     Index: [[#Index+14]]
 ; CHECKSYM-NEXT:     Name: .data
 ; CHECKSYM-NEXT:     Value (RelocatableAddress): 0x50
 ; CHECKSYM-NEXT:     Section: .data
 ; CHECKSYM-NEXT:     Type: 0x0
 ; CHECKSYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; CHECKSYM-NEXT:     NumberOfAuxEntries: 1
 ; CHECKSYM-NEXT:     CSECT Auxiliary Entry {
-; CHECKSYM-NEXT:       Index: [[#Index+13]]
+; CHECKSYM-NEXT:       Index: [[#Index+15]]
 ; CHECKSYM-NEXT:       SectionLen: 4
 ; CHECKSYM-NEXT:       ParameterHashIndex: 0x0
 ; CHECKSYM-NEXT:       TypeChkSectNum: 0x0
 ; CHECKSYM-NEXT:       SymbolAlignmentLog2: 2
 ; CHECKSYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; CHECKSYM-NEXT:       StorageMappingClass: XMC_RW (0x5)
 ; CHECKSYM-NEXT:       StabInfoIndex: 0x0
 ; CHECKSYM-NEXT:       StabSectNum: 0x0
 ; CHECKSYM-NEXT:     }
 ; CHECKSYM-NEXT:   }
 ; CHECKSYM-NEXT:   Symbol {
-; CHECKSYM-NEXT:     Index: [[#Index+14]]
+; CHECKSYM-NEXT:     Index: [[#Index+16]]
 ; CHECKSYM-NEXT:     Name: foo_ext_weak_p
 ; CHECKSYM-NEXT:     Value (RelocatableAddress): 0x50
 ; CHECKSYM-NEXT:     Section: .data
 ; CHECKSYM-NEXT:     Type: 0x0
 ; CHECKSYM-NEXT:     StorageClass: C_EXT (0x2)
 ; CHECKSYM-NEXT:     NumberOfAuxEntries: 1
 ; CHECKSYM-NEXT:     CSECT Auxiliary Entry {
-; CHECKSYM-NEXT:       Index: [[#Index+15]]
-; CHECKSYM-NEXT:       ContainingCsectSymbolIndex: [[#Index+12]]
+; CHECKSYM-NEXT:       Index: [[#Index+17]]
+; CHECKSYM-NEXT:       ContainingCsectSymbolIndex: [[#Index+14]]
 ; CHECKSYM-NEXT:       ParameterHashIndex: 0x0
 ; CHECKSYM-NEXT:       TypeChkSectNum: 0x0
 ; CHECKSYM-NEXT:       SymbolAlignmentLog2: 0
 ; CHECKSYM-NEXT:       SymbolType: XTY_LD (0x2)
 ; CHECKSYM-NEXT:       StorageMappingClass: XMC_RW (0x5)
 ; CHECKSYM-NEXT:       StabInfoIndex: 0x0
 ; CHECKSYM-NEXT:       StabSectNum: 0x0
 ; CHECKSYM-NEXT:     }
 ; CHECKSYM-NEXT:   }
 ; CHECKSYM-NEXT:   Symbol {
-; CHECKSYM-NEXT:     Index: [[#Index+16]]
+; CHECKSYM-NEXT:     Index: [[#Index+18]]
 ; CHECKSYM-NEXT:     Name: main
 ; CHECKSYM-NEXT:     Value (RelocatableAddress): 0x54
 ; CHECKSYM-NEXT:     Section: .data
 ; CHECKSYM-NEXT:     Type: 0x0
 ; CHECKSYM-NEXT:     StorageClass: C_EXT (0x2)
 ; CHECKSYM-NEXT:     NumberOfAuxEntries: 1
 ; CHECKSYM-NEXT:     CSECT Auxiliary Entry {
-; CHECKSYM-NEXT:       Index: [[#Index+17]]
+; CHECKSYM-NEXT:       Index: [[#Index+19]]
 ; CHECKSYM-NEXT:       SectionLen: 12
 ; CHECKSYM-NEXT:       ParameterHashIndex: 0x0
 ; CHECKSYM-NEXT:       TypeChkSectNum: 0x0
 ; CHECKSYM-NEXT:       SymbolAlignmentLog2: 2
 ; CHECKSYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; CHECKSYM-NEXT:       StorageMappingClass: XMC_DS (0xA)
 ; CHECKSYM-NEXT:       StabInfoIndex: 0x0
 ; CHECKSYM-NEXT:       StabSectNum: 0x0
 ; CHECKSYM-NEXT:     }
 ; CHECKSYM-NEXT:   }
 ; CHECKSYM-NEXT:   Symbol {
-; CHECKSYM-NEXT:     Index: [[#Index+18]]
+; CHECKSYM-NEXT:     Index: [[#Index+20]]
 ; CHECKSYM-NEXT:     Name: TOC
 ; CHECKSYM-NEXT:     Value (RelocatableAddress): 0x60
 ; CHECKSYM-NEXT:     Section: .data
 ; CHECKSYM-NEXT:     Type: 0x0
 ; CHECKSYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; CHECKSYM-NEXT:     NumberOfAuxEntries: 1
 ; CHECKSYM-NEXT:     CSECT Auxiliary Entry {
-; CHECKSYM-NEXT:       Index: [[#Index+19]]
+; CHECKSYM-NEXT:       Index: [[#Index+21]]
 ; CHECKSYM-NEXT:       SectionLen: 0
 ; CHECKSYM-NEXT:       ParameterHashIndex: 0x0
 ; CHECKSYM-NEXT:       TypeChkSectNum: 0x0
 ; CHECKSYM-NEXT:       SymbolAlignmentLog2: 2
 ; CHECKSYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; CHECKSYM-NEXT:       StorageMappingClass: XMC_TC0 (0xF)
 ; CHECKSYM-NEXT:       StabInfoIndex: 0x0
 ; CHECKSYM-NEXT:       StabSectNum: 0x0
 ; CHECKSYM-NEXT:     }
 ; CHECKSYM-NEXT:   }
 ; CHECKSYM-NEXT:   Symbol {
-; CHECKSYM-NEXT:     Index: [[#Index+20]]
+; CHECKSYM-NEXT:     Index: [[#Index+22]]
 ; CHECKSYM-NEXT:     Name: foo_ext_weak_p
 ; CHECKSYM-NEXT:     Value (RelocatableAddress): 0x60
 ; CHECKSYM-NEXT:     Section: .data
 ; CHECKSYM-NEXT:     Type: 0x0
 ; CHECKSYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; CHECKSYM-NEXT:     NumberOfAuxEntries: 1
 ; CHECKSYM-NEXT:     CSECT Auxiliary Entry {
-; CHECKSYM-NEXT:       Index: [[#Index+21]]
+; CHECKSYM-NEXT:       Index: [[#Index+23]]
 ; CHECKSYM-NEXT:       SectionLen: 4
 ; CHECKSYM-NEXT:       ParameterHashIndex: 0x0
 ; CHECKSYM-NEXT:       TypeChkSectNum: 0x0
 ; CHECKSYM-NEXT:       SymbolAlignmentLog2: 2
 ; CHECKSYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; CHECKSYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
 ; CHECKSYM-NEXT:       StabInfoIndex: 0x0
 ; CHECKSYM-NEXT:       StabSectNum: 0x0
 ; CHECKSYM-NEXT:     }
 ; CHECKSYM-NEXT:   }
 ; CHECKSYM-NEXT:   Symbol {
-; CHECKSYM-NEXT:     Index: [[#Index+22]]
+; CHECKSYM-NEXT:     Index: [[#Index+24]]
 ; CHECKSYM-NEXT:     Name: b_w
 ; CHECKSYM-NEXT:     Value (RelocatableAddress): 0x64
 ; CHECKSYM-NEXT:     Section: .data
 ; CHECKSYM-NEXT:     Type: 0x0
 ; CHECKSYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; CHECKSYM-NEXT:     NumberOfAuxEntries: 1
 ; CHECKSYM-NEXT:     CSECT Auxiliary Entry {
-; CHECKSYM-NEXT:       Index: [[#Index+23]]
+; CHECKSYM-NEXT:       Index: [[#Index+25]]
 ; CHECKSYM-NEXT:       SectionLen: 4
 ; CHECKSYM-NEXT:       ParameterHashIndex: 0x0
 ; CHECKSYM-NEXT:       TypeChkSectNum: 0x0
 ; CHECKSYM-NEXT:       SymbolAlignmentLog2: 2
 ; CHECKSYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; CHECKSYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
 ; CHECKSYM-NEXT:       StabInfoIndex: 0x0
 ; CHECKSYM-NEXT:       StabSectNum: 0x0
 ; CHECKSYM-NEXT:     }
 ; CHECKSYM-NEXT:   }
 ; CHECKSYM-NEXT: ]

llvm/test/CodeGen/PowerPC/aix-external-sym-sdnode-lowering.ll

 ; RUN: llc -mcpu=pwr4 -mattr=-altivec -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32BIT %s
 
 ; RUN: llc -mcpu=pwr4 -mattr=-altivec -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64BIT %s
 
 define double @call_ceil(double %n) {
 entry:
   %0 = call double @llvm.ceil.f64(double %n)
   ret double %0
 }
 
 declare double @llvm.ceil.f64(double)
 
-; 32BIT: BL_NOP &.ceil
-; 64BIT: BL8_NOP &.ceil
+; 32BIT: BL_NOP &".ceil[PR]"
+; 64BIT: BL8_NOP &".ceil[PR]"

llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll

 ;CHECK-NEXT:     .globl  foo_ptr
 ;CHECK-NEXT:     .align  2
 ;CHECK-NEXT:     foo_ptr:
 ;CHECK-NEXT:     .vbyte 4, foo[DS]
 ;CHECK-NEXT:     .globl  bar_ptr1
 ;CHECK-NEXT:     .align  2
 ;CHECK-NEXT:     bar_ptr1:
 ;CHECK-NEXT:     .vbyte 4, bar[DS]
+;CHECK-NEXT:     .extern .foo[PR]
 ;CHECK-NEXT:     .extern foo[DS]
 
 ;CHECK64:         .csect .data[RW],3
 ;CHECK64-NEXT:         .globl  foo_ptr
 ;CHECK64-NEXT:         .align  3
 ;CHECK64-NEXT:    foo_ptr:
 ;CHECK64-NEXT:         .vbyte 8, foo[DS]
 ;CHECK64-NEXT:         .globl  bar_ptr1
 ;CHECK64-NEXT:         .align  3
 ;CHECK64-NEXT:    bar_ptr1:
 ;CHECK64-NEXT:         .vbyte 8, bar[DS]
+;CHECK64-NEXT:         .extern .foo[PR]
 ;CHECK64-NEXT:         .extern foo[DS]

llvm/test/CodeGen/PowerPC/aix-sret-param.ll

 
 ; MIR:      name:            test1
 ; MIR:      stack:
 ; MIR-NEXT:  - { id: 0, name: s, type: default, offset: 0, size: 1, alignment: 8,
 
 ; MIR32:      bb.0.entry:
 ; MIR32-NEXT:   ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; MIR32-NEXT:   renamable $r3 = ADDI %stack.0.s, 0
-; MIR32-NEXT:   BL_NOP <mcsymbol .foo>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
+; MIR32-NEXT:   BL_NOP <mcsymbol .foo[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
 ; MIR32-NEXT:   ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; MIR64:      bb.0.entry:
 ; MIR64-NEXT:   ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; MIR64-NEXT:   renamable $x3 = ADDI8 %stack.0.s, 0
-; MIR64-NEXT:   BL8_NOP <mcsymbol .foo>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; MIR64-NEXT:   BL8_NOP <mcsymbol .foo[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; MIR64-NEXT:   ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 
 ; ASM-LABEL: .test1:
 
 ; ASM32:       stwu 1, -64(1)
 ; ASM32-NEXT:  addi 3, 1, 56
-; ASM32-NEXT:  bl .foo
+; ASM32-NEXT:  bl .foo[PR]
 ; ASM32-NEXT:  nop
 ; ASM32-NEXT:  addi 1, 1, 64
 
 ; ASM64:       stdu 1, -128(1)
 ; ASM64-NEXT:  addi 3, 1, 120
-; ASM64-NEXT:  bl .foo
+; ASM64-NEXT:  bl .foo[PR]
 ; ASM64-NEXT:  nop
 ; ASM64-NEXT:  addi 1, 1, 128
 
 
 
 ; MIR:      name:            test2
 ; MIR:      stack:
 ; MIR-NEXT:   - { id: 0, name: t, type: default, offset: 0, size: 24, alignment: 8,
 
 ; MIR32:       bb.0.entry:
 ; MIR32-NEXT:    ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; MIR32-NEXT:    renamable $r3 = ADDI %stack.0.t, 0
-; MIR32-NEXT:    BL_NOP <mcsymbol .bar>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
+; MIR32-NEXT:    BL_NOP <mcsymbol .bar[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
 ; MIR32-NEXT:    ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; MIR64:      bb.0.entry:
 ; MIR64-NEXT:   ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; MIR64-NEXT:   renamable $x3 = ADDI8 %stack.0.t, 0
-; MIR64-NEXT:   BL8_NOP <mcsymbol .bar>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; MIR64-NEXT:   BL8_NOP <mcsymbol .bar[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; MIR64-NEXT:   ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 
 ; ASM-LABEL: .test2:
 
 ; ASM32:        stwu 1, -80(1)
 ; ASM32-NEXT:   addi 3, 1, 56
-; ASM32-NEXT:   bl .bar
+; ASM32-NEXT:   bl .bar[PR]
 ; ASM32-NEXT:   nop
 ; ASM32-NEXT:   addi 1, 1, 80
 
 
 ; ASM64:        stdu 1, -144(1)
 ; ASM64-NEXT:   addi 3, 1, 120
-; ASM64-NEXT:   bl .bar
+; ASM64-NEXT:   bl .bar[PR]
 ; ASM64-NEXT:   nop
 ; ASM64-NEXT:   addi 1, 1, 144

llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll

 ; ASM-NEXT:    .lglobl ._Renamed..24f_o
 ; ASM-NEXT:    .align  4
 ; ASM-NEXT:    .csect _Renamed..24f_o[DS],2
 ; ASM-NEXT:    .vbyte  4, ._Renamed..24f_o     # @"f$o"
 ; ASM-NEXT:    .vbyte  4, TOC[TC0]
 ; ASM-NEXT:    .vbyte  4, 0
 ; ASM-NEXT:    .csect .text[PR],2
 ; ASM-NEXT:  ._Renamed..24f_o:
-; ASM:         bl ._Renamed..40f_o
+; ASM:         bl ._Renamed..40f_o[PR]
 ; ASM-NEXT:    nop
 ; ASM:         .rename _Renamed..26f_o[DS],"f&o" # -- Begin function f&o
 ; ASM-NEXT:    .globl  _Renamed..26f_o[DS]
 ; ASM-NEXT:    .rename ._Renamed..26f_o,".f&o"
 ; ASM-NEXT:    .globl  ._Renamed..26f_o
 ; ASM-NEXT:    .align  4
 ; ASM-NEXT:    .csect _Renamed..26f_o[DS],2
 ; ASM-NEXT:    .vbyte  4, ._Renamed..26f_o     # @"f&o"

 ; ASM:         .csect .data[RW],2
 ; ASM-NEXT:    .rename _Renamed..60f_o,"f`o"
 ; ASM-NEXT:    .globl  _Renamed..60f_o
 ; ASM-NEXT:    .align  2
 ; ASM-NEXT:  _Renamed..60f_o:
 ; ASM-NEXT:    .vbyte  4, 10                   # 0xa
 ; ASM-NEXT:    .rename _Renamed..2222f_o_[RW],"f""o"""
 ; ASM-NEXT:    .comm _Renamed..2222f_o_[RW],4,2
-; ASM-NEXT:    .rename ._Renamed..40f_o,".f@o"
-; ASM-NEXT:    .extern ._Renamed..40f_o
+; ASM-NEXT:    .rename ._Renamed..40f_o[PR],".f@o"
+; ASM-NEXT:    .extern ._Renamed..40f_o[PR]
 ; ASM-NEXT:    .rename _Renamed..40f_o[DS],"f@o"
 ; ASM-NEXT:    .extern _Renamed..40f_o[DS]
 ; ASM-NEXT:    .toc
 ; ASM-NEXT:  L..C0:
 ; ASM-NEXT:    .rename _Renamed..40f_o[TC],"f@o"
 ; ASM-NEXT:    .tc _Renamed..40f_o[TC],_Renamed..40f_o[DS]
 
 ; OBJ:       Disassembly of section .text:

llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll

 ; SYM-NEXT:     TypeChkSectNum: 0x0
 ; SYM-NEXT:     SymbolAlignmentLog2: 0
 ; SYM-NEXT:     SymbolType: XTY_ER (0x0)
 ; SYM-NEXT:     StorageMappingClass: XMC_UA (0x4)
 ; SYM-NEXT:     StabInfoIndex: 0x0
 ; SYM-NEXT:     StabSectNum: 0x0
 ; SYM-NEXT:   }
 ; SYM-NEXT: }
 ; SYM-NEXT: Symbol {
 ; SYM-NEXT:   Index: [[#UNDEF_INDX+6]]
-; SYM-NEXT:   Name: foo
+; SYM-NEXT:   Name: .foo
 ; SYM-NEXT:   Value (RelocatableAddress): 0x0
 ; SYM-NEXT:   Section: N_UNDEF
 ; SYM-NEXT:   Type: 0x0
 ; SYM-NEXT:   StorageClass: C_EXT (0x2)
 ; SYM-NEXT:   NumberOfAuxEntries: 1
 ; SYM-NEXT:   CSECT Auxiliary Entry {
 ; SYM-NEXT:     Index: [[#UNDEF_INDX+7]]
 ; SYM-NEXT:     SectionLen: 0
 ; SYM-NEXT:     ParameterHashIndex: 0x0
 ; SYM-NEXT:     TypeChkSectNum: 0x0
 ; SYM-NEXT:     SymbolAlignmentLog2: 0
 ; SYM-NEXT:     SymbolType: XTY_ER (0x0)
+; SYM-NEXT:     StorageMappingClass: XMC_PR (0x0)
+; SYM-NEXT:     StabInfoIndex: 0x0
+; SYM-NEXT:     StabSectNum: 0x0
+; SYM-NEXT:   }
+; SYM-NEXT: }
+; SYM-NEXT: Symbol {
+; SYM-NEXT:   Index: [[#UNDEF_INDX+8]]
+; SYM-NEXT:   Name: foo
+; SYM-NEXT:   Value (RelocatableAddress): 0x0
+; SYM-NEXT:   Section: N_UNDEF
+; SYM-NEXT:   Type: 0x0
+; SYM-NEXT:   StorageClass: C_EXT (0x2)
+; SYM-NEXT:   NumberOfAuxEntries: 1
+; SYM-NEXT:   CSECT Auxiliary Entry {
+; SYM-NEXT:     Index: [[#UNDEF_INDX+9]]
+; SYM-NEXT:     SectionLen: 0
+; SYM-NEXT:     ParameterHashIndex: 0x0
+; SYM-NEXT:     TypeChkSectNum: 0x0
+; SYM-NEXT:     SymbolAlignmentLog2: 0
+; SYM-NEXT:     SymbolType: XTY_ER (0x0)
 ; SYM-NEXT:     StorageMappingClass: XMC_DS (0xA)
 ; SYM-NEXT:     StabInfoIndex: 0x0
 ; SYM-NEXT:     StabSectNum: 0x0
 ; SYM-NEXT:   }
 ; SYM-NEXT: }
 
 ; Test TOC entry symbol generation.
 

llvm/test/CodeGen/PowerPC/aix-xcoff-visibility.ll

 ; CHECK:        .globl  foo_protected[DS],protected
 ; CHECK:        .globl  .foo_protected,protected
 ; CHECK:        .weak   foo_weak_h[DS],hidden
 ; CHECK:        .weak   .foo_weak_h,hidden
 
 ; CHECK:        .globl  b{{[[:space:]]*([#].*)?$}}
 ; CHECK:        .globl  b_h,hidden
 
+; CHECK:        .weak   .zoo_weak_extern_h[PR],hidden
 ; CHECK:        .weak   zoo_weak_extern_h[DS],hidden
-; CHECK:        .extern .bar_h,hidden
+; CHECK:        .extern .bar_h[PR],hidden
 ; CHECK:        .extern bar_h[DS],hidden

llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll

 ; CHECK-DAG:   renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
 ; CHECK-DAG:   renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load 8)
 ; CHECK-DAG:   renamable $x5 = LD 16, renamable $x[[REGADDR]] :: (load 8)
 ; CHECK-DAG:   renamable $x6 = LD 24, renamable $x[[REGADDR]] :: (load 8)
 ; CHECK-DAG:   renamable $x7 = LD 32, renamable $x[[REGADDR]] :: (load 8)
 ; CHECK-DAG:   renamable $x8 = LD 40, renamable $x[[REGADDR]] :: (load 8)
 ; CHECK-DAG:   renamable $x9 = LD 48, renamable $x[[REGADDR]] :: (load 8)
 ; CHECK-DAG:   renamable $x10 = LD 56, renamable $x[[REGADDR]] :: (load 8)
-; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_64Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
+; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_64Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
 ; CHECK-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .test_byval_64Byte:
 
 ; ASM:         stdu 1, -112(1)
 ; ASM-NEXT:    ld [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM-DAG:     ld 3, 0([[REG]])
 ; ASM-DAG:     ld 4, 8([[REG]])
 ; ASM-DAG:     ld 5, 16([[REG]])
 ; ASM-DAG:     ld 6, 24([[REG]])
 ; ASM-DAG:     ld 7, 32([[REG]])
 ; ASM-DAG:     ld 8, 40([[REG]])
 ; ASM-DAG:     ld 9, 48([[REG]])
 ; ASM-DAG:     ld 10, 56([[REG]])
 ; ASM-NEXT:    bl .test_byval_64Byte
 ; ASM-NEXT:    nop

llvm/test/CodeGen/PowerPC/test_call_aix.ll

 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp < %s | \
 ; RUN: FileCheck --check-prefix=32BIT %s
 
 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp < %s | \
 ; RUN: FileCheck --check-prefix=64BIT %s
 
 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
 
 declare void @foo(...)
 
 define void @test_call() {
 entry:
 ; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: BL_NOP <mcsymbol .foo>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r2, implicit-def $r1
+; 32BIT: BL_NOP <mcsymbol .foo[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r2, implicit-def $r1
 ; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: BL8_NOP <mcsymbol .foo>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x2, implicit-def $r1
+; 64BIT: BL8_NOP <mcsymbol .foo[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x2, implicit-def $r1
 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECK-LABEL: test_call
 ; CHECK: bl .foo
 ; CHECK-NEXT: nop
 
   call void bitcast (void (...)* @foo to void ()*)()
   ret void