[SveEmitter] Add range checks for immediates and predicate patterns.

[sdesmalen]

Summary

This patch adds a mechanism to easily add range checks for a builtin's
immediate operands. This patch is tested with the qdech intrinsic, which takes
both an enum for the predicate pattern, as well as an immediate for the
multiplier.

[SjoerdMeijer]

Did a first scan, looks very reasonable, just some first nits/questions inlined.

clang/include/clang/Basic/arm_sve.td

153

would it make sense to call this ImmCheck0_31?

clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_qdech.c

10

nit: why use a regexp for the argument value and not just its value?

[efriedma]

clang/lib/CodeGen/CGBuiltin.cpp

7571

I'm not sure why you need a second way to convert SVE types separate from ConvertType

[sdesmalen]

clang/include/clang/Basic/arm_sve.td

153

Sure, I can change that.

clang/lib/CodeGen/CGBuiltin.cpp

7571

For the intrinsics added here, that's indeed correct, but for others, the OverloadedTy is not necessarily the return type. This is determined by the type string in the arm_sve.td file. For example:

def SVQDECH_S : SInst<"svqdech_pat[_{d}]",   "ddIi", "s", MergeNone, "aarch64_sve_sqdech", 
                                              ^

The default type d (in this case both return value, and first parameter) is the overloaded type.

For other intrinsics, such as

def SVSHRNB      : SInst<"svshrnb[_n_{d}]",    "hdi",  "silUsUiUl", MergeNone, "aarch64_sve_shrnb",
                                                 ^

The overloaded type is the first parameter, not the result type.

clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_qdech.c

10

Mostly because for most tests, there is no ambiguity and it would be a hassle to update all the generated tests. The regular expression is also used for many similar tests in Clang for e.g. Neon or other builtins. I guess for these tests it makes sense to be more explicit which operand is out of range (given that there are two immediates). Are you happy for me to change it for these tests, but not others where there is only a single immediate (i.e. where the message cannot be ambiguous)?

[sdesmalen]

• Renamed ImmCheckPredicatePattern -> ImmCheck0_31
• Updated tests.

[SjoerdMeijer]

LGTM, please wait a day in case Eli has more comments.

[sdesmalen]

In D76678#1963576, @SjoerdMeijer wrote:

LGTM, please wait a day in case Eli has more comments.

Will do, thanks Sjoerd!

[efriedma]

LGTM

[thakis]

For CDE and MVE, the sema inc file is called arm_foo_builtin_sema. Does it make sense to call the sve one arm_sve_builtin_sema instead of arm_sve_sema_rangechecks too, for consistency?

clang/include/clang/Basic/CMakeLists.txt

clang_tablegen(arm_sve_builtins.inc -gen-arm-sve-builtins
   SOURCE arm_sve.td
   TARGET ClangARMSveBuiltins)
 clang_tablegen(arm_sve_builtin_cg.inc -gen-arm-sve-builtin-codegen
   SOURCE arm_sve.td
   TARGET ClangARMSveBuiltinCG)
 clang_tablegen(arm_sve_typeflags.inc -gen-arm-sve-typeflags
   SOURCE arm_sve.td
   TARGET ClangARMSveTypeFlags)
+clang_tablegen(arm_sve_sema_rangechecks.inc -gen-arm-sve-sema-rangechecks
+  SOURCE arm_sve.td
+  TARGET ClangARMSveSemaRangeChecks)
 clang_tablegen(arm_cde_builtins.inc -gen-arm-cde-builtin-def
   SOURCE arm_cde.td
   TARGET ClangARMCdeBuiltinsDef)
 clang_tablegen(arm_cde_builtin_cg.inc -gen-arm-cde-builtin-codegen
   SOURCE arm_cde.td
   TARGET ClangARMCdeBuiltinCG)
 clang_tablegen(arm_cde_builtin_sema.inc -gen-arm-cde-builtin-sema
   SOURCE arm_cde.td
   TARGET ClangARMCdeBuiltinSema)
 clang_tablegen(arm_cde_builtin_aliases.inc -gen-arm-cde-builtin-aliases
   SOURCE arm_cde.td
   TARGET ClangARMCdeBuiltinAliases)

clang/include/clang/Basic/TargetBuiltins.h

#undef LLVM_GET_SVE_ELTTYPES
     };
 
     enum MemEltType {
 #define LLVM_GET_SVE_MEMELTTYPES
 #include "clang/Basic/arm_sve_typeflags.inc"
 #undef LLVM_GET_SVE_MEMELTTYPES
     };
 
+    enum ImmCheckType {
+#define LLVM_GET_SVE_IMMCHECKTYPES
+#include "clang/Basic/arm_sve_typeflags.inc"
+#undef LLVM_GET_SVE_IMMCHECKTYPES
+    };
+
     SVETypeFlags(uint64_t F) : Flags(F), EltTypeShift(0), MemEltTypeShift(0) {
       EltTypeShift = llvm::countTrailingZeros(EltTypeMask);
       MemEltTypeShift = llvm::countTrailingZeros(MemEltTypeMask);
     }
 
     EltType getEltType() const {
       return (EltType)((Flags & EltTypeMask) >> EltTypeShift);
     }

clang/include/clang/Basic/arm_sve.td

 
 // Prototype modifiers
 // -------------------
 // prototype: return (arg, arg, ...)
 //
 // d: default
 // c: const pointer type
 // P: predicate type
+//
+// i: constant uint64_t
+//
+// I: Predicate Pattern (sv_pattern)
 
 // l: int64_t
 
 // A: pointer to int8_t
 // B: pointer to int16_t
 // C: pointer to int32_t
 // D: pointer to int64_t
 

 def IsLoad                    : FlagType<0x00000080>;
 def IsStore                   : FlagType<0x00000100>;
 def IsGatherLoad              : FlagType<0x00000200>;
 def IsScatterStore            : FlagType<0x00000400>;
 def IsStructLoad              : FlagType<0x00000800>;
 def IsStructStore             : FlagType<0x00001000>;
 def IsZExtReturn              : FlagType<0x00002000>; // Return value is sign-extend by default
 
+// These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h
+class ImmCheckType<int val> {
+  int Value = val;
+}
+def ImmCheckPredicatePattern    : ImmCheckType<0>;  // 0..31
+def ImmCheck1_16                : ImmCheckType<1>;  // 1..16
+
+class ImmCheck<int arg, ImmCheckType kind, int eltSizeArg = -1> {
+  int Arg = arg;
+  int EltSizeArg = eltSizeArg;
+  ImmCheckType Kind = kind;
+}
+
 // Every intrinsic subclasses Inst.
 class Inst<string n, string p, string t, MergeType mt, string i,
-           list<FlagType> ft, MemEltType met> {
+           list<FlagType> ft, list<ImmCheck> ch, MemEltType met> {
   string Name = n;
   string Prototype = p;
   string Types = t;
   string ArchGuard = "";
   int Merge = mt.Value;
   string LLVMIntrinsic = i;
   list<FlagType> Flags = ft;
+  list<ImmCheck> ImmChecks = ch;
   int MemEltType = met.Value;
 }
 
+// SInst: Instruction with signed/unsigned suffix (e.g., "s8", "u8")
+class SInst<string n, string p, string t, MergeType mt, string i = "",
+            list<FlagType> ft = [], list<ImmCheck> ch = []>
+    : Inst<n, p, t, mt, i, ft, ch, MemEltTyDefault> {
+}
+
 // MInst: Instructions which access memory
 class MInst<string n, string p, string t, list<FlagType> f,
-            MemEltType met=MemEltTyDefault, string i="">
-  : Inst<n, p, t, MergeNone, i, f, met> {}
+            MemEltType met = MemEltTyDefault, string i = "">
+    : Inst<n, p, t, MergeNone, i, f, [], met> {
+}
 
 ////////////////////////////////////////////////////////////////////////////////
 // Loads
 
 // Load one vector (scalar base)
 def SVLD1   : MInst<"svld1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad]>;
 def SVLD1SB : MInst<"svld1sb_{d}", "dPS", "silUsUiUl",       [IsLoad],               MemEltTyInt8>;
 def SVLD1UB : MInst<"svld1ub_{d}", "dPW", "silUsUiUl",       [IsLoad, IsZExtReturn], MemEltTyInt8>;

 def SVST1W_VNUM_S : MInst<"svst1w_vnum[_{d}]", "vPCld", "l",               [IsStore], MemEltTyInt32>;
 def SVST1W_VNUM_U : MInst<"svst1w_vnum[_{d}]", "vPGld", "Ul",              [IsStore], MemEltTyInt32>;
 
 // Store one vector, with no truncation, non-temporal (scalar base)
 def SVSTNT1 : MInst<"svstnt1[_{d}]", "vPpd", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefault, "aarch64_sve_stnt1">;
 
 // Store one vector, with no truncation, non-temporal (scalar base, VL displacement)
 def SVSTNT1_VNUM : MInst<"svstnt1_vnum[_{d}]", "vPpld", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefault, "aarch64_sve_stnt1">;
+
+////////////////////////////////////////////////////////////////////////////////
+// Saturating scalar arithmetic
+def SVQDECH_S : SInst<"svqdech_pat[_{d}]",   "ddIi", "s", MergeNone, "aarch64_sve_sqdech", [], [ImmCheck<2, ImmCheck1_16>]>;
+def SVQDECH_U : SInst<"svqdech_pat[_{d}]",   "ddIi", "Us", MergeNone, "aarch64_sve_uqdech", [], [ImmCheck<2, ImmCheck1_16>]>;

clang/include/clang/Sema/Sema.h

private:
   ExprResult CheckBuiltinFunctionCall(FunctionDecl *FDecl,
                                       unsigned BuiltinID, CallExpr *TheCall);
   void checkFortifiedBuiltinMemoryFunction(FunctionDecl *FD, CallExpr *TheCall);
 
   bool CheckARMBuiltinExclusiveCall(unsigned BuiltinID, CallExpr *TheCall,
                                     unsigned MaxWidth);
   bool CheckNeonBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
   bool CheckMVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
+  bool CheckSVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
   bool CheckCDEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
   bool CheckARMCoprocessorImmediate(const Expr *CoprocArg, bool WantCDE);
   bool CheckARMBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
 
   bool CheckAArch64BuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
   bool CheckBPFBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
   bool CheckHexagonBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
   bool CheckHexagonBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall);

clang/lib/CodeGen/CGBuiltin.cpp

Value *CodeGenFunction::vectorWrapScalar16(Value *Op) {
   llvm::Type *VTy = llvm::VectorType::get(Int16Ty, 4);
   Op = Builder.CreateBitCast(Op, Int16Ty);
   Value *V = UndefValue::get(VTy);
   llvm::Constant *CI = ConstantInt::get(SizeTy, 0);
   Op = Builder.CreateInsertElement(V, Op, CI);
   return Op;
 }
 
+// Return the llvm vector type corresponding to the specified element TypeFlags.
+llvm::Type *CodeGenFunction::getSVEType(const SVETypeFlags &TypeFlags) {
+  switch (TypeFlags.getEltType()) {
+  default:
+    llvm_unreachable("Invalid SVETypeFlag!");
+
+  case SVETypeFlags::EltTyInt8:
+    return llvm::VectorType::get(Builder.getInt8Ty(), {16, true});
+  case SVETypeFlags::EltTyInt16:
+    return llvm::VectorType::get(Builder.getInt16Ty(), {8, true});
+  case SVETypeFlags::EltTyInt32:
+    return llvm::VectorType::get(Builder.getInt32Ty(), {4, true});
+  case SVETypeFlags::EltTyInt64:
+    return llvm::VectorType::get(Builder.getInt64Ty(), {2, true});
+
+  case SVETypeFlags::EltTyFloat16:
+    return llvm::VectorType::get(Builder.getHalfTy(), {8, true});
+  case SVETypeFlags::EltTyFloat32:
+    return llvm::VectorType::get(Builder.getFloatTy(), {4, true});
+  case SVETypeFlags::EltTyFloat64:
+    return llvm::VectorType::get(Builder.getDoubleTy(), {2, true});
+
+  case SVETypeFlags::EltTyBool8:
+    return llvm::VectorType::get(Builder.getInt1Ty(), {16, true});
+  case SVETypeFlags::EltTyBool16:
+    return llvm::VectorType::get(Builder.getInt1Ty(), {8, true});
+  case SVETypeFlags::EltTyBool32:
+    return llvm::VectorType::get(Builder.getInt1Ty(), {4, true});
+  case SVETypeFlags::EltTyBool64:
+    return llvm::VectorType::get(Builder.getInt1Ty(), {2, true});
+  }
+}
+
 // Reinterpret the input predicate so that it can be used to correctly isolate
 // the elements of the specified datatype.
 Value *CodeGenFunction::EmitSVEPredicateCast(Value *Pred,
                                              llvm::VectorType *VTy) {
   llvm::VectorType *RTy = llvm::VectorType::get(
       IntegerType::get(getLLVMContext(), 1), VTy->getElementCount());
   if (Pred->getType() == RTy)
     return Pred;
Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
   ASTContext::GetBuiltinTypeError Error;
   getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
   assert(Error == ASTContext::GE_None && "Should not codegen an error");
 
   llvm::SmallVector<Value *, 4> Ops;
   for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
     if ((ICEArguments & (1 << i)) == 0)
       Ops.push_back(EmitScalarExpr(E->getArg(i)));
-    else
-      llvm_unreachable("Not yet implemented");
+    else {
+      // If this is required to be a constant, constant fold it so that we know
+      // that the generated intrinsic gets a ConstantInt.
+      llvm::APSInt Result;
+      if (!E->getArg(i)->isIntegerConstantExpr(Result, getContext()))
+        llvm_unreachable("Expected argument to be a constant");
+
+      // Immediates for SVE llvm intrinsics are always 32bit.  We can safely
+      // truncate because the immediate has been range checked and no valid
+      // immediate requires more than a handful of bits.
+      Result = Result.extOrTrunc(32);
+      Ops.push_back(llvm::ConstantInt::get(getLLVMContext(), Result));
+    }
   }
 
   auto *Builtin = findARMVectorIntrinsicInMap(AArch64SVEIntrinsicMap, BuiltinID,
                                               AArch64SVEIntrinsicsProvenSorted);
   SVETypeFlags TypeFlags(Builtin->TypeModifier);
   llvm::Type *Ty = ConvertType(E->getType());
   if (TypeFlags.isLoad())
     return EmitSVEMaskedLoad(E, Ty, Ops, Builtin->LLVMIntrinsic,
                              TypeFlags.isZExtReturn());
   else if (TypeFlags.isStore())
     return EmitSVEMaskedStore(E, Ops, Builtin->LLVMIntrinsic);
+  else if (Builtin->LLVMIntrinsic != 0) {
+    llvm::Type* OverloadedTy = getSVEType(TypeFlags);
+
+    Function *F = CGM.getIntrinsic(Builtin->LLVMIntrinsic, OverloadedTy);
+    Value *Call = Builder.CreateCall(F, Ops);
+    return Call;
+  }
 
   /// Should not happen
   return nullptr;
 }
 
 Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
                                                const CallExpr *E,
                                                llvm::Triple::ArchType Arch) {

clang/lib/CodeGen/CodeGenFunction.h

 class TargetInfo;
 class VarDecl;
 class ObjCForCollectionStmt;
 class ObjCAtTryStmt;
 class ObjCAtThrowStmt;
 class ObjCAtSynchronizedStmt;
 class ObjCAutoreleasePoolStmt;
 class ReturnsNonNullAttr;
+class SVETypeFlags;
 
 namespace analyze_os_log {
 class OSLogBufferLayout;
 }
 
 namespace CodeGen {
 class CodeGenTypes;
 class CGCallee;
llvm::Value *EmitNeonCall(llvm::Function *F,
                             unsigned shift = 0, bool rightshift = false);
   llvm::Value *EmitNeonSplat(llvm::Value *V, llvm::Constant *Idx);
   llvm::Value *EmitNeonShiftVector(llvm::Value *V, llvm::Type *Ty,
                                    bool negateForRightShift);
   llvm::Value *EmitNeonRShiftImm(llvm::Value *Vec, llvm::Value *Amt,
                                  llvm::Type *Ty, bool usgn, const char *name);
   llvm::Value *vectorWrapScalar16(llvm::Value *Op);
 
+  llvm::Type *getSVEType(const SVETypeFlags &TypeFlags);
   llvm::Value *EmitSVEPredicateCast(llvm::Value *Pred, llvm::VectorType *VTy);
   llvm::Value *EmitSVEMaskedLoad(const CallExpr *, llvm::Type *ReturnTy,
                                  SmallVectorImpl<llvm::Value *> &Ops,
                                  unsigned BuiltinID, bool IsZExtReturn);
   llvm::Value *EmitSVEMaskedStore(const CallExpr *,
                                   SmallVectorImpl<llvm::Value *> &Ops,
                                   unsigned BuiltinID);
   llvm::Value *EmitAArch64SVEBuiltinExpr(unsigned BuiltinID, const CallExpr *E);

clang/lib/Sema/SemaChecking.cpp

static QualType getNeonEltType(NeonTypeFlags Flags, ASTContext &Context,
   case NeonTypeFlags::Float32:
     return Context.FloatTy;
   case NeonTypeFlags::Float64:
     return Context.DoubleTy;
   }
   llvm_unreachable("Invalid NeonTypeFlag!");
 }
 
+bool Sema::CheckSVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
+  // Range check SVE intrinsics that take immediate values.
+  SmallVector<std::tuple<int,int,int>, 3> ImmChecks;
+
+  switch (BuiltinID) {
+  default:
+    return false;
+#define GET_SVE_IMMEDIATE_CHECK
+#include "clang/Basic/arm_sve_sema_rangechecks.inc"
+#undef GET_SVE_IMMEDIATE_CHECK
+  }
+
+  // Perform all the immediate checks for this builtin call.
+  bool HasError = false;
+  for (auto &I : ImmChecks) {
+    int ArgNum, CheckTy, ElementSizeInBits;
+    std::tie(ArgNum, CheckTy, ElementSizeInBits) = I;
+
+    switch ((SVETypeFlags::ImmCheckType)CheckTy) {
+    case SVETypeFlags::ImmCheckPredicatePattern:
+      if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 31))
+        HasError = true;
+      break;
+    case SVETypeFlags::ImmCheck1_16:
+      if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 1, 16))
+        HasError = true;
+      break;
+    }
+  }
+
+  return HasError;
+}
+
 bool Sema::CheckNeonBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
   llvm::APSInt Result;
   uint64_t mask = 0;
   unsigned TV = 0;
   int PtrArgNum = -1;
   bool HasConstPtr = false;
   switch (BuiltinID) {
 #define GET_NEON_OVERLOAD_CHECK
if (BuiltinID == AArch64::BI_ReadStatusReg ||
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 0x7fff);
 
   if (BuiltinID == AArch64::BI__getReg)
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31);
 
   if (CheckNeonBuiltinFunctionCall(BuiltinID, TheCall))
     return true;
 
+  if (CheckSVEBuiltinFunctionCall(BuiltinID, TheCall))
+    return true;
+
   // For intrinsics which take an immediate value as part of the instruction,
   // range check them here.
   unsigned i = 0, l = 0, u = 0;
   switch (BuiltinID) {
   default: return false;
   case AArch64::BI__builtin_arm_dmb:
   case AArch64::BI__builtin_arm_dsb:
   case AArch64::BI__builtin_arm_isb: l = 0; u = 15; break;

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdech.c

+// RUN:  %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -D__ARM_FEATURE_SVE %s | FileCheck %s
+
+#include <arm_sve.h>
+
+svint16_t test_svqdech_pat_s16(svint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_s16
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> %op, i32 0, i32 1)
+  // CHECK: ret
+  return svqdech_pat_s16(op, SV_POW2, 1);
+}
+
+svint16_t test_svqdech_pat_s16_all(svint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_s16_all
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> %op, i32 31, i32 16)
+  // CHECK: ret
+  return svqdech_pat_s16(op, SV_ALL, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_pow2(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_pow2
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 0, i32 1)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_POW2, 1);
+}
+
+svuint16_t test_svqdech_pat_u16_vl1(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_vl1
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 1, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_VL1, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_vl2(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_vl2
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 2, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_VL2, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_vl3(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_vl3
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 3, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_VL3, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_vl4(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_vl4
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 4, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_VL4, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_vl5(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_vl5
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 5, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_VL5, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_vl6(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_vl6
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 6, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_VL6, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_vl7(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_vl7
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 7, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_VL7, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_vl8(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_vl8
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 8, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_VL8, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_vl16(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_vl16
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 9, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_VL16, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_vl32(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_vl32
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 10, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_VL32, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_vl64(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_vl64
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 11, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_VL64, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_vl128(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_vl128
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 12, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_VL128, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_vl256(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_vl256
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 13, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_VL256, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_mul4(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_mul4
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 29, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_MUL4, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_mul3(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_mul3
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 30, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_MUL3, 16);
+}
+
+svuint16_t test_svqdech_pat_u16_all(svuint16_t op)
+{
+  // CHECK-LABEL: test_svqdech_pat_u16_all
+  // CHECK: <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %op, i32 31, i32 16)
+  // CHECK: ret
+  return svqdech_pat_u16(op, SV_ALL, 16);
+}

clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_qdech.c

+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -D__ARM_FEATURE_SVE %s
+
+#include <arm_sve.h>
+//
+// qdech
+//
+
+svint16_t test_svqdech_pat_s16(svint16_t op)
+{
+  return svqdech_pat_s16(op, SV_VL8, 0); // expected-error-re {{argument value {{[0-9]+}} is outside the valid range [1, 16]}}
+}
+
+svint16_t test_svqdech_pat_8(svint16_t op)
+{
+  return svqdech_pat(op, SV_VL8, 0); // expected-error-re {{argument value {{[0-9]+}} is outside the valid range [1, 16]}}
+}
+
+svint16_t test_svqdech_pat_s16_2(svint16_t op)
+{
+  return svqdech_pat_s16(op, SV_VL16, 17); // expected-error-re {{argument value {{[0-9]+}} is outside the valid range [1, 16]}}
+}
+
+svint16_t test_svqdech_pat_9(svint16_t op)
+{
+  return svqdech_pat(op, SV_VL16, 17); // expected-error-re {{argument value {{[0-9]+}} is outside the valid range [1, 16]}}
+}
+
+svuint16_t test_svqdech_pat_u16(svuint16_t op)
+{
+  return svqdech_pat_u16(op, SV_VL32, 0); // expected-error-re {{argument value {{[0-9]+}} is outside the valid range [1, 16]}}
+}
+
+svuint16_t test_svqdech_pat_10(svuint16_t op)
+{
+  return svqdech_pat(op, SV_VL32, 0); // expected-error-re {{argument value {{[0-9]+}} is outside the valid range [1, 16]}}
+}
+
+svuint16_t test_svqdech_pat_u16_2(svuint16_t op)
+{
+  return svqdech_pat_u16(op, SV_VL64, 17); // expected-error-re {{argument value {{[0-9]+}} is outside the valid range [1, 16]}}
+}
+
+svuint16_t test_svqdech_pat_11(svuint16_t op)
+{
+  return svqdech_pat(op, SV_VL64, 17); // expected-error-re {{argument value {{[0-9]+}} is outside the valid range [1, 16]}}
+}

clang/utils/TableGen/SveEmitter.cpp

enum ClassKind {
   ClassS,     // signed/unsigned, e.g., "_s8", "_u8" suffix
   ClassG,     // Overloaded name without type suffix
 };
 
 using TypeSpec = std::string;
 
 namespace {
 
+class ImmCheck {
+  int Arg;
+  int Kind;
+  int ElementSizeInBits;
+
+public:
+  ImmCheck(int Arg, int Kind, int ElementSizeInBits = 0)
+      : Arg(Arg), Kind(Kind), ElementSizeInBits(ElementSizeInBits) {}
+  ImmCheck(const ImmCheck &Other) = default;
+  ~ImmCheck() = default;
+
+  int getArg() const { return Arg; }
+  int getKind() const { return Kind; }
+  int getElementSizeInBits() const { return ElementSizeInBits; }
+};
+
 class SVEType {
   TypeSpec TS;
   bool Float, Signed, Immediate, Void, Constant, Pointer;
   bool DefaultType, IsScalable, Predicate, PredicatePattern, PrefetchOp;
   unsigned Bitwidth, ElementBitwidth, NumVectors;
 
 public:
   SVEType() : SVEType(TypeSpec(), 'v') {}
class Intrinsic {
   /// The types of return value [0] and parameters [1..].
   std::vector<SVEType> Types;
 
   /// The "base type", which is VarType('d', BaseTypeSpec).
   SVEType BaseType;
 
   unsigned Flags;
 
+  SmallVector<ImmCheck, 2> ImmChecks;
+
 public:
   /// The type of predication.
   enum MergeType {
     MergeNone,
     MergeAny,
     MergeOp1,
     MergeZero,
     MergeAnyExp,
     MergeZeroExp,
     MergeInvalid
   } Merge;
 
   Intrinsic(StringRef Name, StringRef Proto, int64_t MT, StringRef LLVMName,
-            unsigned Flags, TypeSpec BT, ClassKind Class, SVEEmitter &Emitter,
-            StringRef Guard)
+            unsigned Flags, ArrayRef<ImmCheck> ImmChecks, TypeSpec BT,
+            ClassKind Class, SVEEmitter &Emitter, StringRef Guard)
       : Name(Name.str()), LLVMName(LLVMName), Proto(Proto.str()),
         BaseTypeSpec(BT), Class(Class), Guard(Guard.str()), BaseType(BT, 'd'),
-        Flags(Flags), Merge(MergeType(MT)) {
-    // Types[0] is the return value.
-    for (unsigned I = 0; I < Proto.size(); ++I)
-      Types.emplace_back(BaseTypeSpec, Proto[I]);
+        Flags(Flags), ImmChecks(ImmChecks.begin(), ImmChecks.end()),
+        Merge(MergeType(MT)) {
+    initialize(Emitter);
   }
 
+  // Initialize the types for this intrinsic.
+  void initialize(const SVEEmitter &Emitter);
+
   ~Intrinsic()=default;
 
   std::string getName() const { return Name; }
   std::string getLLVMName() const { return LLVMName; }
   std::string getProto() const { return Proto; }
   TypeSpec getBaseTypeSpec() const { return BaseTypeSpec; }
   SVEType getBaseType() const { return BaseType; }
 
   StringRef getGuard() const { return Guard; }
   ClassKind getClassKind() const { return Class; }
   MergeType getMergeType() const { return Merge; }
 
   SVEType getReturnType() const { return Types[0]; }
   ArrayRef<SVEType> getTypes() const { return Types; }
   SVEType getParamType(unsigned I) const { return Types[I + 1]; }
   unsigned getNumParams() const { return Proto.size() - 1; }
 
   unsigned getFlags() const { return Flags; }
   bool isFlagSet(uint64_t Flag) const { return Flags & Flag;}
 
+  ArrayRef<ImmCheck> getImmChecks() const { return ImmChecks; }
+
   /// Return the type string for a BUILTIN() macro in Builtins.def.
   std::string getBuiltinTypeStr();
 
   /// Return the name, mangled with type information. The name is mangled for
   /// ClassS, so will add type suffixes such as _u32/_s32.
   std::string getMangledName() const { return mangleName(ClassS); }
 
   /// Returns true if the intrinsic is overloaded, in that it should also generate

 };
 
 class SVEEmitter {
 private:
   RecordKeeper &Records;
   llvm::StringMap<uint64_t> EltTypes;
   llvm::StringMap<uint64_t> MemEltTypes;
   llvm::StringMap<uint64_t> FlagTypes;
+  llvm::StringMap<uint64_t> ImmCheckTypes;
 
   unsigned getTypeFlags(const SVEType &T);
 public:
   SVEEmitter(RecordKeeper &R) : Records(R) {
     for (auto *RV : Records.getAllDerivedDefinitions("EltType"))
       EltTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
     for (auto *RV : Records.getAllDerivedDefinitions("MemEltType"))
       MemEltTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
     for (auto *RV : Records.getAllDerivedDefinitions("FlagType"))
       FlagTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+    for (auto *RV : Records.getAllDerivedDefinitions("ImmCheckType"))
+      ImmCheckTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+  }
+
+  /// Returns the enum value for the immcheck type
+  unsigned getEnumValueForImmCheck(StringRef C) const {
+    auto Res = ImmCheckTypes.find(C);
+    if (Res != ImmCheckTypes.end())
+      return Res->getValue();
+    llvm_unreachable("Unsupported imm check");
   }
 
   /// Emit arm_sve.h.
   void createHeader(raw_ostream &o);
 
   /// Emit all the __builtin prototypes and code needed by Sema.
   void createBuiltins(raw_ostream &o);
 
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGenMap(raw_ostream &o);
 
+  /// Emit all the range checks for the immediates.
+  void createRangeChecks(raw_ostream &o);
+
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream &o);
 
   /// Create intrinsic and add it to \p Out
   void createIntrinsic(Record *R, SmallVectorImpl<std::unique_ptr<Intrinsic>> &Out);
 };
 
 } // end anonymous namespace
case 'p':
     break;
   case 'P':
     Signed = true;
     Float = false;
     Predicate = true;
     Bitwidth = 16;
     ElementBitwidth = 1;
     break;
+  case 'i':
+    Predicate = false;
+    Float = false;
+    ElementBitwidth = Bitwidth = 64;
+    NumVectors = 0;
+    Signed = false;
+    Immediate = true;
+    break;
+  case 'I':
+    Predicate = false;
+    Float = false;
+    ElementBitwidth = Bitwidth = 32;
+    NumVectors = 0;
+    Signed = true;
+    Immediate = true;
+    PredicatePattern = true;
+    break;
   case 'l':
     Predicate = false;
     Signed = true;
     Float = false;
     ElementBitwidth = Bitwidth = 64;
     NumVectors = 0;
     break;
   case 'S':
void SVEType::applyModifier(char Mod) {
   }
 }
 
 
 //===----------------------------------------------------------------------===//
 // Intrinsic implementation
 //===----------------------------------------------------------------------===//
 
+void Intrinsic::initialize(const SVEEmitter &Emitter) {
+  // Types[0] is the return value.
+  for (unsigned I = 0; I < Proto.size(); ++I) {
+    SVEType T(BaseTypeSpec, Proto[I]);
+    Types.push_back(T);
+
+    // Add range checks for immediates
+    if (I > 0) {
+      if (T.isPredicatePattern())
+        ImmChecks.emplace_back(
+            I - 1, Emitter.getEnumValueForImmCheck("ImmCheckPredicatePattern"));
+    }
+  }
+}
+
 std::string Intrinsic::getBuiltinTypeStr() {
   std::string S;
 
   SVEType RetT = getReturnType();
   // Since the return value must be one type, return a vector type of the
   // appropriate width which we will bitcast.  An exception is made for
   // returning structs of 2, 3, or 4 vectors which are returned in a sret-like
   // fashion, storing them to a pointer arg.
void SVEEmitter::createIntrinsic(
     Record *R, SmallVectorImpl<std::unique_ptr<Intrinsic>> &Out) {
   StringRef Name = R->getValueAsString("Name");
   StringRef Proto = R->getValueAsString("Prototype");
   StringRef Types = R->getValueAsString("Types");
   StringRef Guard = R->getValueAsString("ArchGuard");
   StringRef LLVMName = R->getValueAsString("LLVMIntrinsic");
   int64_t Merge = R->getValueAsInt("Merge");
   std::vector<Record*> FlagsList = R->getValueAsListOfDefs("Flags");
+  std::vector<Record*> ImmCheckList = R->getValueAsListOfDefs("ImmChecks");
 
   int64_t Flags = 0;
   for (auto FlagRec : FlagsList)
     Flags |= FlagRec->getValueAsInt("Value");
   Flags |= R->getValueAsInt("MemEltType")
            << llvm::countTrailingZeros(MemEltTypes["FirstMemEltType"]);
 
   // Extract type specs from string
void SVEEmitter::createIntrinsic(
 
   // Remove duplicate type specs.
   std::sort(TypeSpecs.begin(), TypeSpecs.end());
   TypeSpecs.erase(std::unique(TypeSpecs.begin(), TypeSpecs.end()),
                   TypeSpecs.end());
 
   // Create an Intrinsic for each type spec.
   for (auto TS : TypeSpecs) {
+    // Collate a list of range/option checks for the immediates.
+    SmallVector<ImmCheck, 2> ImmChecks;
+    for (auto *R : ImmCheckList) {
+      int Arg = R->getValueAsInt("Arg");
+      int EltSizeArg = R->getValueAsInt("EltSizeArg");
+      int Kind = R->getValueAsDef("Kind")->getValueAsInt("Value");
+
+      int ElementSizeInBits = 0;
+      if (EltSizeArg >= 0)
+        ElementSizeInBits =
+            SVEType(TS, Proto[EltSizeArg + /* offset by return arg */ 1])
+                .getElementSizeInBits();
+      ImmChecks.push_back(ImmCheck(Arg, Kind, ElementSizeInBits));
+    }
+
     Out.push_back(std::make_unique<Intrinsic>(Name, Proto, Merge,
-                                              LLVMName, Flags, TS, ClassS,
-                                              *this, Guard));
+                                              LLVMName, Flags, ImmChecks, TS,
+                                              ClassS, *this, Guard));
 
     // Also generate the short-form (e.g. svadd_m) for the given type-spec.
     if (Intrinsic::isOverloadedIntrinsic(Name))
       Out.push_back(std::make_unique<Intrinsic>(
-          Name, Proto, Merge, LLVMName, Flags, TS, ClassG, *this, Guard));
+          Name, Proto, Merge, LLVMName, Flags, ImmChecks, TS, ClassG,
+          *this, Guard));
   }
 }
 
 void SVEEmitter::createHeader(raw_ostream &OS) {
   OS << "/*===---- arm_sve.h - ARM SVE intrinsics "
         "-----------------------------------===\n"
         " *\n"
         " *\n"
void SVEEmitter::createHeader(raw_ostream &OS) {
   OS << "typedef __SVUint16_t svuint16_t;\n";
   OS << "typedef __SVUint32_t svuint32_t;\n";
   OS << "typedef __SVUint64_t svuint64_t;\n";
   OS << "typedef __SVFloat16_t svfloat16_t;\n";
   OS << "typedef __SVFloat32_t svfloat32_t;\n";
   OS << "typedef __SVFloat64_t svfloat64_t;\n";
   OS << "typedef __SVBool_t  svbool_t;\n\n";
 
+  OS << "typedef enum\n";
+  OS << "{\n";
+  OS << "  SV_POW2 = 0,\n";
+  OS << "  SV_VL1 = 1,\n";
+  OS << "  SV_VL2 = 2,\n";
+  OS << "  SV_VL3 = 3,\n";
+  OS << "  SV_VL4 = 4,\n";
+  OS << "  SV_VL5 = 5,\n";
+  OS << "  SV_VL6 = 6,\n";
+  OS << "  SV_VL7 = 7,\n";
+  OS << "  SV_VL8 = 8,\n";
+  OS << "  SV_VL16 = 9,\n";
+  OS << "  SV_VL32 = 10,\n";
+  OS << "  SV_VL64 = 11,\n";
+  OS << "  SV_VL128 = 12,\n";
+  OS << "  SV_VL256 = 13,\n";
+  OS << "  SV_MUL4 = 29,\n";
+  OS << "  SV_MUL3 = 30,\n";
+  OS << "  SV_ALL = 31\n";
+  OS << "} sv_pattern;\n\n";
+
   OS << "/* Function attributes */\n";
   OS << "#define __aio static inline __attribute__((__always_inline__, "
         "__nodebug__, __overloadable__))\n\n";
 
   SmallVector<std::unique_ptr<Intrinsic>, 128> Defs;
   std::vector<Record *> RV = Records.getAllDerivedDefinitions("Inst");
   for (auto *R : RV)
     createIntrinsic(R, Defs);
if (!LLVMName.empty())
       OS << "SVEMAP1(" << Builtin << ", " << LLVMName << ", " << FlagString
          << "),\n";
     else
       OS << "SVEMAP2(" << Builtin << ", " << FlagString << "),\n";
   }
   OS << "#endif\n\n";
 }
 
+void SVEEmitter::createRangeChecks(raw_ostream &OS) {
+  std::vector<Record *> RV = Records.getAllDerivedDefinitions("Inst");
+  SmallVector<std::unique_ptr<Intrinsic>, 128> Defs;
+  for (auto *R : RV)
+    createIntrinsic(R, Defs);
+
+  // The mappings must be sorted based on BuiltinID.
+  llvm::sort(Defs, [](const std::unique_ptr<Intrinsic> &A,
+                      const std::unique_ptr<Intrinsic> &B) {
+    return A->getMangledName() < B->getMangledName();
+  });
+
+
+  OS << "#ifdef GET_SVE_IMMEDIATE_CHECK\n";
+
+  // Ensure these are only emitted once.
+  std::set<std::string> Emitted;
+
+  for (auto &Def : Defs) {
+    if (Emitted.find(Def->getMangledName()) != Emitted.end() ||
+        Def->getImmChecks().empty())
+      continue;
+
+    OS << "case SVE::BI__builtin_sve_" << Def->getMangledName() << ":\n";
+    for (auto &Check : Def->getImmChecks())
+      OS << "ImmChecks.push_back(std::make_tuple(" << Check.getArg() << ", "
+         << Check.getKind() << ", " << Check.getElementSizeInBits() << "));\n";
+    OS << "  break;\n";
+
+    Emitted.insert(Def->getMangledName());
+  }
+
+  OS << "#endif\n\n";
+}
+
 /// Create the SVETypeFlags used in CGBuiltins
 void SVEEmitter::createTypeFlags(raw_ostream &OS) {
   OS << "#ifdef LLVM_GET_SVE_TYPEFLAGS\n";
   for (auto &KV : FlagTypes)
     OS << "const uint64_t " << KV.getKey() << " = " << KV.getValue() << ";\n";
   OS << "#endif\n\n";
 
   OS << "#ifdef LLVM_GET_SVE_ELTTYPES\n";
   for (auto &KV : EltTypes)
     OS << "  " << KV.getKey() << " = " << KV.getValue() << ",\n";
   OS << "#endif\n\n";
 
   OS << "#ifdef LLVM_GET_SVE_MEMELTTYPES\n";
   for (auto &KV : MemEltTypes)
     OS << "  " << KV.getKey() << " = " << KV.getValue() << ",\n";
   OS << "#endif\n\n";
+
+  OS << "#ifdef LLVM_GET_SVE_IMMCHECKTYPES\n";
+  for (auto &KV : ImmCheckTypes)
+    OS << "  " << KV.getKey() << " = " << KV.getValue() << ",\n";
+  OS << "#endif\n\n";
 }
 
 namespace clang {
 void EmitSveHeader(RecordKeeper &Records, raw_ostream &OS) {
   SVEEmitter(Records).createHeader(OS);
 }
 
 void EmitSveBuiltins(RecordKeeper &Records, raw_ostream &OS) {
   SVEEmitter(Records).createBuiltins(OS);
 }
 
 void EmitSveBuiltinCG(RecordKeeper &Records, raw_ostream &OS) {
   SVEEmitter(Records).createCodeGenMap(OS);
 }
+
+void EmitSveRangeChecks(RecordKeeper &Records, raw_ostream &OS) {
+  SVEEmitter(Records).createRangeChecks(OS);
+}
+
 void EmitSveTypeFlags(RecordKeeper &Records, raw_ostream &OS) {
   SVEEmitter(Records).createTypeFlags(OS);
 }
 
 } // End namespace clang

clang/utils/TableGen/TableGen.cpp

enum ActionType {
   GenArmMveBuiltinDef,
   GenArmMveBuiltinSema,
   GenArmMveBuiltinCG,
   GenArmMveBuiltinAliases,
   GenArmSveHeader,
   GenArmSveBuiltins,
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
+  GenArmSveRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
   GenArmCdeBuiltinCG,
   GenArmCdeBuiltinAliases,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
cl::values(
         clEnumValN(GenArmSveHeader, "gen-arm-sve-header",
                    "Generate arm_sve.h for clang"),
         clEnumValN(GenArmSveBuiltins, "gen-arm-sve-builtins",
                    "Generate arm_sve_builtins.inc for clang"),
         clEnumValN(GenArmSveBuiltinCG, "gen-arm-sve-builtin-codegen",
                    "Generate arm_sve_builtin_cg_map.inc for clang"),
         clEnumValN(GenArmSveTypeFlags, "gen-arm-sve-typeflags",
                    "Generate arm_sve_typeflags.inc for clang"),
+        clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
+                   "Generate arm_sve_sema_rangechecks.inc for clang"),
         clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
                    "Generate arm_mve.h for clang"),
         clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
                    "Generate ARM MVE builtin definitions for clang"),
         clEnumValN(GenArmMveBuiltinSema, "gen-arm-mve-builtin-sema",
                    "Generate ARM MVE builtin sema checks for clang"),
         clEnumValN(GenArmMveBuiltinCG, "gen-arm-mve-builtin-codegen",
                    "Generate ARM MVE builtin code-generator for clang"),
case GenArmSveBuiltins:
     EmitSveBuiltins(Records, OS);
     break;
   case GenArmSveBuiltinCG:
     EmitSveBuiltinCG(Records, OS);
     break;
   case GenArmSveTypeFlags:
     EmitSveTypeFlags(Records, OS);
     break;
+  case GenArmSveRangeChecks:
+    EmitSveRangeChecks(Records, OS);
+    break;
   case GenArmCdeHeader:
     EmitCdeHeader(Records, OS);
     break;
   case GenArmCdeBuiltinDef:
     EmitCdeBuiltinDef(Records, OS);
     break;
   case GenArmCdeBuiltinSema:
     EmitCdeBuiltinSema(Records, OS);

clang/utils/TableGen/TableGenBackends.h

 void EmitNeon2(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonSema2(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonTest2(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitSveHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitSveBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitSveBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitSveTypeFlags(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitSveRangeChecks(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitMveHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinAliases(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);