- User Since
- Jul 11 2019, 4:02 AM (37 w, 3 d)
Wed, Mar 25
Fixed obsolete comments.
- Added bitmanip compressed instructions.
- Added compressed instruction emission.
- Added mc tests.
- Added assembler predicate strings to B extension and subextensions.
- Fixed typos.
- Fixed the order of the single bit instructions.
Tue, Mar 24
- Sorted the definitions of the instructions and the MC tests according to the order of the encodings in the manual.
- Improved the names of the instruction templates.
- Removed unused operand types and instruction templates.
- The features hasSideEffects, mayLoad and mayStore are now set only on the templates that need it.
- Renamed all the immediate parameters in the templates as 'shamt', for uniformity.
- Split the funct12 field of the unary instruction template into two fields of 7 and 5 bits. For conformity to the manual and for maintainability.
- Added a 4-bit immediate operand for the 32 bit shuffle.
- Added constraints on the size of the immediate operands.
- Added tests on the constraints of the immediate operands.
- Renamed most registers in the tests for uniformity.
- Removed the compressed instructions as they are still a proposal for the C extension and still cause encoding conflicts with the ones aready implemented there.
- Removed tests of compressed instructions.
Thu, Mar 19
Feb 3 2020
Added empty scheduling descriptions, just to let it build with the upstream LLVM.
Dec 3 2019
Update codegen pattern matching to RISCV BitManip v0.92:
Nov 28 2019
Nov 15 2019
Update encodings to RISCV BitManip v0.92:
Oct 2 2019
Added matching of LLVM bit manipulation instrinsics like bswap, bitreverse, fshl and fshr to the corresponding asm instructions in the RISC-V bit manipulation ISA extension. Added codegen tests accordingly. Added codegen tests for the intrinsics ctlz, cttz and ctpop, to check that they are matched with the assembly instructions clz, ctz and pcnt.
Sep 17 2019
Removed new lines and trailing spaces.
Removed new line.
Updated tests that failed due to latest commit in LLVM.
Sep 13 2019
Sep 9 2019
Sep 4 2019
Fixed immediate values of shfli/unshfli for zip/unzip pseudo instructions.
Sep 2 2019
Update the encodings to the latest version of the spec. Fix the tests and encoding conflicts.
Aug 30 2019
Added the latest updates to the encodings of the instructions, including the gorc, gorci, bfp instructions, the 'orc' pseudo instructions based on gorci and the zip/unzip pseudo instructions based on shfli/unshfli. Changed the encoding of grev and bmatxor to make space for gorc. Added the subtarget feature Zbf to support bfp. Added the necessary MC tests.
Aug 7 2019
Fixed the indentation of the tests.
Fixed typos, bad indentations and capitalization.
Added uimm6 and uimm7 riscv asm operand types in order to have more precise classes to represent the templates of the instructions with 5-bit, 6-bit and 7-bit immediate fields. The riscv asm operand uimm5 already existed.
Added missing rev pseudo instructions for riscv64.
Fixed the tests accordingly.