Hi @philipp.tomsich do you know which change is that? Has it been already upstreamed? Because as far as I see by rebasing this patch on the upstream main we still have some code size reduction and the tests still succeed

Is this still being looked at? I see that by disabling HasMultpipleConditionRegisters upstream we still get better code size with embench.

I quite agree that hasMultipleConditionRegisters seems to be intended for targets like PowerPC (only when it treats the 32 bits of the condition register as separate entities).
It also seems to me that the hook was added to RISCV as a simpler way make the RISCV backend lower select into more more logic instructions and fewer branches, as explained here: https://reviews.llvm.org/D79268
This wasn't probably very descriptive of the condition registers situation of RISCV that differs from the one of PowerPC (and AMDGPU) for which the hook was made for.
As already said, due to a previous commit, the hook hasMultipleConditionRegisters also influences (prevents) the sinking of compare instructions (sinkCmpExpression) and I found myself that by sinking them we get better code size.
I ran the benchmarks of Embench (https://github.com/embench/embench-iot) with a custom option I added (for proof of concept: https://reviews.llvm.org/D105620) and saw that by turning off that hook we achieve better code size.
I think that the idea to create another hook that is specific to the lowering of the select instructions is good. If that's preferable to overriding shouldNormalizeToSelectSequence to just return false.
(Hope you don't mind that I extracted part of your test for the test of my proof of concept: https://reviews.llvm.org/D105620, it was neat)

Fixed the test to reflect the effects of the hasMultipleConditionRegisters on the lowering of select and the sinking of icmp.

No worries.
Thank you @lewis-revill

Thank you very much @lewis-revill, very appreciated.
I haven't got commit access, can you @asb or someone else commit it for me?
Unless of course there's something else that needs immediate correction.

Added comments to inefficient tests.

Added comments to inefficient tests.

Aligned complex pattern declaration.
Clarified comment about missing 'roli' instruction.
Added comment to inefficient tests.

Making sure the changes from patch zbb are maintained.

Aligned the declarations of the complex patterns.
Added comments to inefficient tests.

Updated the test:

• the tests have been updated from the top of all the sub-patches together so that they are exactly the same as they would be if updated with the whole final patch.
• labels specific to the sub-extension have been added alongside the generic RISCVIB label (that activates all the sub-extensions) so that we can see how differently the patterns are matched with the specific subextension or with all of them together.
• the tests will probably fail if run by checking out the commit of a subextension and if updated they'll change. These tests are designed to work with the final squashed patch.

Updated the test:

• the tests have been updated from the top of all the sub-patches together so that they are exactly the same as they would be if updated with the whole final patch.
• labels specific to the sub-extension have been added alongside the generic RISCVIB label (that activates all the sub-extensions) so that we can see how differently the patterns are matched with the specific subextension or with all of them together.
• the tests will probably fail if run by checking out the commit of a subextension and if updated they'll change. These tests are designed to work with the final squashed patch.

Updated the test:

• the tests have been updated from the top of all the sub-patches together so that they are exactly the same as they would be if updated with the whole final patch.
• labels specific to the sub-extension have been added alongside the generic RISCVIB label (that activates all the sub-extensions) so that we can see how differently the patterns are matched with the specific subextension or with all of them together.
• the tests will probably fail if run by checking out the commit of a subextension and if updated they'll change. These tests are designed to work with the final squashed patch.

Updated the test:

• the tests have been updated from the top of all the sub-patches together so that they are exactly the same as they would be if updated with the whole final patch.
• labels specific to the sub-extension have been added alongside the generic RISCVIB label (that activates all the sub-extensions) so that we can see how differently the patterns are matched with the specific subextension or with all of them together.
• the tests will probably fail if run by checking out the commit of a subextension and if updated they'll change. These tests are designed to work with the final squashed patch.

Updated the test:

• the tests have been updated from the top of all the sub-patches together so that they are exactly the same as they would be if updated with the whole final patch.
• labels specific to the sub-extension have been added alongside the generic RISCVIB label (that activates all the sub-extensions) so that we can see how differently the patterns are matched with the specific subextension or with all of them together.
• the tests will probably fail if run by checking out the commit of a subextension and if updated they'll change. These tests are designed to work with the final squashed patch.

Fixed indentation.
Added architecture type control for complex pattern matching of sloiw, sroiw and slliuw.

I had to exclude the test of the pattern of sbclr_i64 on RV32 because it caused a warning of asm conflicts. Also the cross tests i64 on RV32 are quite noisy here. I'd rather keep them though as they show quite efficient results on many other instructions in other subextensions.

Added pattern-matching for sbexti, sbclrw, sbsetw, sbinvw and sbextw.
Added correspondent codegen tests.
Reorganized the tests so that both 32 and 64 bit files have both 32 and 64 bit versions of each test.
Fixed some imprecise patterns due to unnecessary constant truncations.

Added missing pattern-matching for *w instructions.
Added tests.
Added both i32 and i64 code versions to both i32 and i64 test files.
Removed NOT labels from tests.

Add missing pattern-matching for *w instructions.
Add tests.
Add both i32 and i64 code versions to both i32 and i64 test files.
Remove NOT labels from tests.

Just a clarification. I decided to split the tests into 32bit and 64bit because the 32bit code compiled on RV64 commonly produces sign-extended IR and that's when many *w instructions are selected. A version of the tests in a unique file could imply on one hand to have 32 bit IR with sign-extension compiled for RV32 (harmless but redundant), on the other hand we would have i32 code with no explicit sign-extension compiled for RV32. That is correct but it might lead to misleading selections, like pattern-matching the IR code of a 32bit SLOI on RV64 with a RV64 SLOI instead of a SLOIW (the difference is that SLOIW ignores the upper 32 bit of the result while RV64 doesn't).

Added missing pattern-matching for *w instructions.
Added codegen tests.
Added ComplexPattern instances that are crucial to pattern-match SLOI, SROI, SLOIW, SROIW and SLLIUW.
Both 32 and 64 bit test files have both 32 and 64 bit test cases of the instructions (were existing).

Sorry for the late answer.
I'm catching up with this now.

As suggested I split the patch by subextension.
You can find in order the pieces that add pattern-matching for zbb, zbp, zbbp, zbs and zbt here:

Thanks Alex.
Yes splitting it sounds reasonable. It is indeed quite a big monolithic patch and I struggle to review it myself sometimes.
Splitting it into subsets sounds a practical approach, will do.

Fixed indentation.
Regrouped/rearranged the patterns to follow the order of the instructions in the encoding table in the specs.
Removed autogenerated comments in the tests.

Fixed the order of the patterns according to follow the order in the opcode table in the specs.
Same for the tests.
Fixed the flags of the tests.
Removed duplicate patterns.
Added pattern matching for rev8.h from bswap.
Removed underscores from names of the functions in the tests.
Wrapped indentation to fit into 80 columns.

• Changed some instruction template classes so that they are not based directly on the basic RVInst.
• Changed the indentation where possible so that it fits in 80 columns.
• Fixed some obsolete comments.
• Added some runs to the Zbp tests.
• Fixed other indentation problems.

Fixed obsolete comments.

• Added bitmanip compressed instructions.
• Added compressed instruction emission.
• Added mc tests.
• Added assembler predicate strings to B extension and subextensions.
• Fixed typos.
• Fixed the order of the single bit instructions.

• Sorted the definitions of the instructions and the MC tests according to the order of the encodings in the manual.
• Improved the names of the instruction templates.
• Removed unused operand types and instruction templates.
• The features hasSideEffects, mayLoad and mayStore are now set only on the templates that need it.
• Renamed all the immediate parameters in the templates as 'shamt', for uniformity.
• Split the funct12 field of the unary instruction template into two fields of 7 and 5 bits. For conformity to the manual and for maintainability.
• Added a 4-bit immediate operand for the 32 bit shuffle.
• Added constraints on the size of the immediate operands.
• Added tests on the constraints of the immediate operands.
• Renamed most registers in the tests for uniformity.
• Removed the compressed instructions as they are still a proposal for the C extension and still cause encoding conflicts with the ones aready implemented there.
• Removed tests of compressed instructions.

Added empty scheduling descriptions, just to let it build with the upstream LLVM.

Update codegen pattern matching to RISCV BitManip v0.92:

Update encodings to RISCV BitManip v0.92:

Added matching of LLVM bit manipulation instrinsics like bswap, bitreverse, fshl and fshr to the corresponding asm instructions in the RISC-V bit manipulation ISA extension. Added codegen tests accordingly. Added codegen tests for the intrinsics ctlz, cttz and ctpop, to check that they are matched with the assembly instructions clz, ctz and pcnt.

Removed new lines and trailing spaces.

Removed new line.

Updated tests that failed due to latest commit in LLVM.

Fixed immediate values of shfli/unshfli for zip/unzip pseudo instructions.

Update the encodings to the latest version of the spec. Fix the tests and encoding conflicts.

Added the latest updates to the encodings of the instructions, including the gorc, gorci, bfp instructions, the 'orc' pseudo instructions based on gorci and the zip/unzip pseudo instructions based on shfli/unshfli. Changed the encoding of grev and bmatxor to make space for gorc. Added the subtarget feature Zbf to support bfp. Added the necessary MC tests.

Fixed the indentation of the tests.

Fixed typos, bad indentations and capitalization.
Added uimm6 and uimm7 riscv asm operand types in order to have more precise classes to represent the templates of the instructions with 5-bit, 6-bit and 7-bit immediate fields. The riscv asm operand uimm5 already existed.
Added missing rev pseudo instructions for riscv64.
Fixed the tests accordingly.
Added comments.