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craig.topper
asb
frasercrmck
Hsiang-Kai

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rG7b50c183601a: [RISCV] Codegen support for Zfhmin.

Summary

The Zfhmin subset only has FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S.
If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are also included.
Since most instructions are not included for Zfhmin, so most operations are promoted.
The patch primarily about making f16 a legal type.

RISC-V ISA info:
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions

Diff Detail

Repository: rG LLVM Github Monorepo

Unit TestsFailed
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	Time	Test
	60,030 ms	x64 debian > libFuzzer.libFuzzer::minimize_crash.test Script: -- : 'RUN: at line 1'; /var/lib/buildkite-agent/builds/llvm-project/build/./bin/clang --driver-mode=g++ -O2 -gline-tables-only -fsanitize=address,fuzzer -I/var/lib/buildkite-agent/builds/llvm-project/compiler-rt/lib/fuzzer -m64 /var/lib/buildkite-agent/builds/llvm-project/compiler-rt/test/fuzzer/NullDerefTest.cpp -o /var/lib/buildkite-agent/builds/llvm-project/build/projects/compiler-rt/test/fuzzer/X86_64DefaultLinuxConfig/Output/minimize_crash.test.tmp-NullDerefTest

Event Timeline

monkchiang created this revision.Dec 5 2022, 9:49 PM

Herald added a project: Restricted Project. · View Herald TranscriptDec 5 2022, 9:49 PM

Herald added subscribers: sunshaoce, VincentWu, vkmr and 28 others. · View Herald Transcript

monkchiang requested review of this revision.Dec 5 2022, 9:49 PM

Herald added a project: Restricted Project. · View Herald TranscriptDec 5 2022, 9:49 PM

Herald added subscribers: llvm-commits, pcwang-thead, eopXD, MaskRay. · View Herald Transcript

monkchiang added reviewers: craig.topper, asb, frasercrmck, Hsiang-Kai.Dec 5 2022, 9:53 PM

Herald added a subscriber: StephenFan. · View Herald TranscriptDec 5 2022, 9:53 PM

craig.topper added inline comments.Dec 5 2022, 10:17 PM

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
292	Can we use FSGNJ_S by changing the registers to their FR32 equivalent?
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
429	Do we need to check NotZfh too to give priority if Zfh is also enabled?

craig.topper added inline comments.Dec 5 2022, 10:29 PM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
352	What's the issue with visitFP_ROUND?

Address Craig's comment

Harbormaster completed remote builds in B201316: Diff 480374.Dec 6 2022, 6:06 AM

craig.topper added inline comments.Dec 6 2022, 3:14 PM

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
288	I think you can use `const TargetRegisterInfo *TRI = STI.getRegisterInfo()`
289	If we assigned over DstReg and SrcReg here and did `Opc = FSGNJ_S` and `IsScalableVector = false`, would the common code at the end still work?

Address comment:

Assgin over DstReg and SrcReg to generate FSJGN_S in RISCVInstrInfo::copyPhysReg()

Harbormaster completed remote builds in B201569: Diff 480716.Dec 6 2022, 5:23 PM

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
285	FFSGNJ_S -> FSGNJ_S

This revision is now accepted and ready to land.Dec 6 2022, 5:45 PM

Fix typo, FFSGNJ_S -> FSGNJ_S.

This revision was landed with ongoing or failed builds.Dec 6 2022, 10:14 PM

Closed by commit rG7b50c183601a: [RISCV] Codegen support for Zfhmin. (authored by monkchiang). · Explain Why

This revision was automatically updated to reflect the committed changes.

monkchiang added a commit: rG7b50c183601a: [RISCV] Codegen support for Zfhmin..

Harbormaster completed remote builds in B201573: Diff 480722.Dec 7 2022, 3:44 AM

[RISCV] Codegen support for Zfhmin.
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Diff 480374

llvm/lib/Target/RISCV/RISCV.td

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

llvm/lib/Target/RISCV/RISCVSubtarget.h

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

llvm/test/CodeGen/RISCV/calling-conv-half.ll

llvm/test/CodeGen/RISCV/copysign-casts.ll

llvm/test/CodeGen/RISCV/half-arith-strict.ll

llvm/test/CodeGen/RISCV/half-arith.ll

llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll

llvm/test/CodeGen/RISCV/half-br-fcmp.ll

llvm/test/CodeGen/RISCV/half-convert-strict.ll

llvm/test/CodeGen/RISCV/half-convert.ll

llvm/test/CodeGen/RISCV/half-fcmp-strict.ll

llvm/test/CodeGen/RISCV/half-fcmp.ll

llvm/test/CodeGen/RISCV/half-frem.ll

llvm/test/CodeGen/RISCV/half-imm.ll

llvm/test/CodeGen/RISCV/half-intrinsics.ll

llvm/test/CodeGen/RISCV/half-isnan.ll

llvm/test/CodeGen/RISCV/half-mem.ll

llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

llvm/test/CodeGen/RISCV/half-round-conv.ll

llvm/test/CodeGen/RISCV/half-select-fcmp.ll

llvm/test/CodeGen/RISCV/half-select-icmp.ll

llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll

llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll

llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll

llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll

llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll

llvm/test/CodeGen/RISCV/zfhmin-imm.ll

[RISCV] Codegen support for Zfhmin.ClosedPublicActions

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Diff 480374

llvm/lib/Target/RISCV/RISCV.td

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

llvm/lib/Target/RISCV/RISCVSubtarget.h

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

llvm/test/CodeGen/RISCV/calling-conv-half.ll

llvm/test/CodeGen/RISCV/copysign-casts.ll

llvm/test/CodeGen/RISCV/half-arith-strict.ll

llvm/test/CodeGen/RISCV/half-arith.ll

llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll

llvm/test/CodeGen/RISCV/half-br-fcmp.ll

llvm/test/CodeGen/RISCV/half-convert-strict.ll

llvm/test/CodeGen/RISCV/half-convert.ll

llvm/test/CodeGen/RISCV/half-fcmp-strict.ll

llvm/test/CodeGen/RISCV/half-fcmp.ll

llvm/test/CodeGen/RISCV/half-frem.ll

llvm/test/CodeGen/RISCV/half-imm.ll

llvm/test/CodeGen/RISCV/half-intrinsics.ll

llvm/test/CodeGen/RISCV/half-isnan.ll

llvm/test/CodeGen/RISCV/half-mem.ll

llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

llvm/test/CodeGen/RISCV/half-round-conv.ll

llvm/test/CodeGen/RISCV/half-select-fcmp.ll

llvm/test/CodeGen/RISCV/half-select-icmp.ll

llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll

llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll

llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll

llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll

llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll

llvm/test/CodeGen/RISCV/zfhmin-imm.ll

[RISCV] Codegen support for Zfhmin.
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