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- Nov 10 2020, 6:35 PM (124 w, 3 d)
Feb 7 2023
Feb 2 2023
Change LMULWriteRes to LMULWriteResFWRed.
Feb 1 2023
Address Michael Maitland's comment. Thanks!
Jan 12 2023
Jan 11 2023
Dec 7 2022
LGTM
Dec 6 2022
Fix typo, FFSGNJ_S -> FSGNJ_S.
Address comment:
Assgin over DstReg and SrcReg to generate FSJGN_S in RISCVInstrInfo::copyPhysReg()
Address Craig's comment
Dec 5 2022
Sep 11 2022
LGTM
Aug 16 2022
Aug 8 2022
LGTM
Aug 1 2022
LGTM
LGTM
Jul 24 2022
Jul 20 2022
Jul 12 2022
Jun 30 2022
Address comment:
- Remove ReadVLDSX from VLSEGSched, VLSEGFFSched.
- Add index vector register read for indexed segment load/store.
Fix typo
Feb 16 2022
LGTM. Thanks for adding the test case.
Feb 15 2022
LGTM, Thanks.
Dec 7 2021
LGTM.
Dec 30 2020
- Add earlyclobber constraint
- support float16 to i8 conversion for vfncvt.xu.f / vfncvt.x.f / vfncvt.rtz.xu.f / vfcvt.rtz.x.f
- Add float16 to i8 conversion test cases
- Add earlyclobber constraint
- vfwcvt.f.xu and vfwcvt.f.x support i8 to float16 conversion
- Add new test cases for vfwcvt.f.xu and vfwcvt.f.x
Dec 29 2020
address @craig.topper 's comments
Remove i64 to float in RV32 test case for fwcvt.xu.f.v/fwcvt.x.f.v/fwcvt.rtz.xu.f.v/fwcvt.rtz.x.f.v intrinsic.
Add vredsum and vredsumu test cases
Remove unneeded class, and Add several missing test cases for RV32.
All of mask test cases follow-up D93878.
Add missing float->double tests for rv32.
Dec 28 2020
address @craig.topper 's comments, and rebase the patch.
thanks!
Dec 26 2020
Dec 24 2020
Dec 23 2020
Remove redundant constraint in VPseudoReductionV_VS class
Closed by 3183add5343e5
Fix comment in IntrinsicsRISCV.td
Dec 22 2020
Dec 20 2020
Dec 17 2020
Use II->ExtendedOperand be condition for if statement.
Let ExtendOperand direct really need to extend a operand.
Correct get operands when we use it in LowerIntrinsic_W_CHAIN
Dec 16 2020
rebase main branch.