[RISCV] Codegen support for Zfhmin.

[monkchiang]

Summary

The Zfhmin subset only has FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S.
If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are also included.
Since most instructions are not included for Zfhmin, so most operations are promoted.
The patch primarily about making f16 a legal type.

RISC-V ISA info:
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

303

Can we use FSGNJ_S by changing the registers to their FR32 equivalent?

llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

429

Do we need to check NotZfh too to give priority if Zfh is also enabled?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

352

What's the issue with visitFP_ROUND?

[monkchiang]

Address Craig's comment

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

299

I think you can use const TargetRegisterInfo *TRI = STI.getRegisterInfo()

300

If we assigned over DstReg and SrcReg here and did Opc = FSGNJ_S and IsScalableVector = false, would the common code at the end still work?

[monkchiang]

Address comment:

Assgin over DstReg and SrcReg to generate FSJGN_S in RISCVInstrInfo::copyPhysReg()

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

286

FFSGNJ_S -> FSGNJ_S

[monkchiang]

Fix typo, FFSGNJ_S -> FSGNJ_S.

llvm/lib/Target/RISCV/RISCV.td

 
 def FeatureStdExtZfh
     : SubtargetFeature<"zfh", "HasStdExtZfh", "true",
                        "'Zfh' (Half-Precision Floating-Point)",
                        [FeatureStdExtF]>;
 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
                              AssemblerPredicate<(all_of FeatureStdExtZfh),
                              "'Zfh' (Half-Precision Floating-Point)">;
+def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
 
 def HasStdExtZfhOrZfhmin
     : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZfhmin()">,
                 AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin),
                                    "'Zfh' (Half-Precision Floating-Point) or "
                                    "'Zfhmin' (Half-Precision Floating-Point Minimal)">;
 
 def FeatureStdExtZfinx

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

case RISCVABI::ABI_LP64D:
     break;
   }
 
   MVT XLenVT = Subtarget.getXLenVT();
 
   // Set up the register classes.
   addRegisterClass(XLenVT, &RISCV::GPRRegClass);
 
-  if (Subtarget.hasStdExtZfh())
+  if (Subtarget.hasStdExtZfhOrZfhmin())
     addRegisterClass(MVT::f16, &RISCV::FPR16RegClass);
   if (Subtarget.hasStdExtF())
     addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
   if (Subtarget.hasStdExtD())
     addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
 
   static const MVT::SimpleValueType BoolVecVTs[] = {
       MVT::nxv1i1,  MVT::nxv2i1,  MVT::nxv4i1, MVT::nxv8i1,
static const ISD::CondCode FPCCToExpand[] = {
       ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
       ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT,
       ISD::SETGE,  ISD::SETNE,  ISD::SETO,   ISD::SETUO};
 
   static const unsigned FPOpToExpand[] = {
       ISD::FSIN, ISD::FCOS,       ISD::FSINCOS,   ISD::FPOW,
       ISD::FREM, ISD::FP16_TO_FP, ISD::FP_TO_FP16};
 
-  if (Subtarget.hasStdExtZfh())
+  if (Subtarget.hasStdExtZfhOrZfhmin())
     setOperationAction(ISD::BITCAST, MVT::i16, Custom);
 
+  if (Subtarget.hasStdExtZfhOrZfhmin()) {
     if (Subtarget.hasStdExtZfh()) {
       setOperationAction(FPLegalNodeTypes, MVT::f16, Legal);
       setOperationAction(ISD::FCEIL, MVT::f16, Custom);
       setOperationAction(ISD::FFLOOR, MVT::f16, Custom);
       setOperationAction(ISD::FTRUNC, MVT::f16, Custom);
       setOperationAction(ISD::FRINT, MVT::f16, Custom);
       setOperationAction(ISD::FROUND, MVT::f16, Custom);
       setOperationAction(ISD::FROUNDEVEN, MVT::f16, Custom);
+      setOperationAction(ISD::SELECT, MVT::f16, Custom);
+    } else {
+      static const unsigned ZfhminPromoteOps[] = {
+          ISD::FMINNUM,      ISD::FMAXNUM,       ISD::FADD,
+          ISD::FSUB,         ISD::FMUL,          ISD::FMA,
+          ISD::FDIV,         ISD::FSQRT,         ISD::FABS,
+          ISD::FNEG,         ISD::STRICT_FMA,    ISD::STRICT_FADD,
+          ISD::STRICT_FSUB,  ISD::STRICT_FMUL,   ISD::STRICT_FDIV,
+          ISD::STRICT_FSQRT, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS,
+          ISD::SETCC,        ISD::FCEIL,         ISD::FFLOOR,
+          ISD::FTRUNC,       ISD::FRINT,         ISD::FROUND,
+          ISD::FROUNDEVEN,   ISD::SELECT};
+
+      setOperationAction(ZfhminPromoteOps, MVT::f16, Promote);
+      setOperationAction({ISD::STRICT_LRINT, ISD::STRICT_LLRINT,
+                          ISD::STRICT_LROUND, ISD::STRICT_LLROUND},
+                         MVT::f16, Legal);
+      // FIXME: Need to promote f16 FCOPYSIGN to f32, but the
+      // DAGCombiner::visitFP_ROUND probably needs improvements first.
+      setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
+    }
+
     setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Legal);
     setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal);
     setCondCodeAction(FPCCToExpand, MVT::f16, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
-    setOperationAction(ISD::SELECT, MVT::f16, Custom);
     setOperationAction(ISD::BR_CC, MVT::f16, Expand);
 
     setOperationAction({ISD::FREM, ISD::FNEARBYINT, ISD::FPOW, ISD::FPOWI,
                         ISD::FCOS, ISD::FSIN, ISD::FSINCOS, ISD::FEXP,
                         ISD::FEXP2, ISD::FLOG, ISD::FLOG2, ISD::FLOG10},
                        MVT::f16, Promote);
 
     // FIXME: Need to promote f16 STRICT_* to f32 libcalls, but we don't have
if (Subtarget.useRVVForFixedLengthVectors()) {
         setOperationAction(FloatingPointVecReduceOps, VT, Custom);
 
         setOperationAction(FloatingPointVPOps, VT, Custom);
       }
 
       // Custom-legalize bitcasts from fixed-length vectors to scalar types.
       setOperationAction(ISD::BITCAST, {MVT::i8, MVT::i16, MVT::i32, MVT::i64},
                          Custom);
-      if (Subtarget.hasStdExtZfh())
+      if (Subtarget.hasStdExtZfhOrZfhmin())
         setOperationAction(ISD::BITCAST, MVT::f16, Custom);
       if (Subtarget.hasStdExtF())
         setOperationAction(ISD::BITCAST, MVT::f32, Custom);
       if (Subtarget.hasStdExtD())
         setOperationAction(ISD::BITCAST, MVT::f64, Custom);
     }
   }
 
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   if (Subtarget.hasStdExtZbb())
     setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN});
 
   if (Subtarget.hasStdExtZbs() && Subtarget.is64Bit())
     setTargetDAGCombine(ISD::TRUNCATE);
 
   if (Subtarget.hasStdExtZbkb())
     setTargetDAGCombine(ISD::BITREVERSE);
-  if (Subtarget.hasStdExtZfh())
+  if (Subtarget.hasStdExtZfhOrZfhmin())
     setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
   if (Subtarget.hasStdExtF())
     setTargetDAGCombine({ISD::ZERO_EXTEND, ISD::FP_TO_SINT, ISD::FP_TO_UINT,
                          ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT});
   if (Subtarget.hasVInstructions())
     setTargetDAGCombine({ISD::FCOPYSIGN, ISD::MGATHER, ISD::MSCATTER,
                          ISD::VP_GATHER, ISD::VP_SCATTER, ISD::SRA, ISD::SRL,
                          ISD::SHL, ISD::STORE, ISD::SPLAT_VECTOR});
bool RISCVTargetLowering::isOffsetFoldingLegal(
   // keep a separate ADD node for the global address offset instead of folding
   // it in the global address node. Later peephole optimisations may choose to
   // fold it back in when profitable.
   return false;
 }
 
 bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
                                        bool ForCodeSize) const {
-  // FIXME: Change to Zfhmin once f16 becomes a legal type with Zfhmin.
-  if (VT == MVT::f16 && !Subtarget.hasStdExtZfh())
+  if (VT == MVT::f16 && !Subtarget.hasStdExtZfhOrZfhmin())
     return false;
   if (VT == MVT::f32 && !Subtarget.hasStdExtF())
     return false;
   if (VT == MVT::f64 && !Subtarget.hasStdExtD())
     return false;
   return Imm.isZero();
 }
 
if (Index >= 32)
     return false;
 
   // TODO: We can do arbitrary slidedowns, but for now only support extracting
   // the upper half of a vector until we have more test coverage.
   return Index == 0 || Index == ResElts;
 }
 
 bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const {
-  return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) ||
+  return (VT == MVT::f16 && Subtarget.hasStdExtZfhOrZfhmin()) ||
          (VT == MVT::f32 && Subtarget.hasStdExtF()) ||
          (VT == MVT::f64 && Subtarget.hasStdExtD());
 }
 
 MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
                                                       CallingConv::ID CC,
                                                       EVT VT) const {
-  // Use f32 to pass f16 if it is legal and Zfh is not enabled.
+  // Use f32 to pass f16 if it is legal and Zfh/Zfhmin is not enabled.
   // We might still end up using a GPR but that will be decided based on ABI.
-  // FIXME: Change to Zfhmin once f16 becomes a legal type with Zfhmin.
-  if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh())
+  if (VT == MVT::f16 && Subtarget.hasStdExtF() &&
+      !Subtarget.hasStdExtZfhOrZfhmin())
     return MVT::f32;
 
   return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
 }
 
 unsigned RISCVTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
                                                            CallingConv::ID CC,
                                                            EVT VT) const {
-  // Use f32 to pass f16 if it is legal and Zfh is not enabled.
+  // Use f32 to pass f16 if it is legal and Zfh/Zfhmin is not enabled.
   // We might still end up using a GPR but that will be decided based on ABI.
-  // FIXME: Change to Zfhmin once f16 becomes a legal type with Zfhmin.
-  if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh())
+  if (VT == MVT::f16 && Subtarget.hasStdExtF() &&
+      !Subtarget.hasStdExtZfhOrZfhmin())
     return 1;
 
   return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
 }
 
 // Changes the condition code and swaps operands if necessary, so the SetCC
 // operation matches one of the comparisons supported directly by branches
 // in the RISC-V ISA. May adjust compares to favor compare with 0 over compare
SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::SRL_PARTS:
     return lowerShiftRightParts(Op, DAG, false);
   case ISD::BITCAST: {
     SDLoc DL(Op);
     EVT VT = Op.getValueType();
     SDValue Op0 = Op.getOperand(0);
     EVT Op0VT = Op0.getValueType();
     MVT XLenVT = Subtarget.getXLenVT();
-    if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) {
+    if (VT == MVT::f16 && Op0VT == MVT::i16 &&
+        Subtarget.hasStdExtZfhOrZfhmin()) {
       SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Op0);
       SDValue FPConv = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, NewOp0);
       return FPConv;
     }
     if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() &&
         Subtarget.hasStdExtF()) {
       SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
       SDValue FPConv =
case ISD::ABS: {
     return;
   }
   case ISD::BITCAST: {
     EVT VT = N->getValueType(0);
     assert(VT.isInteger() && !VT.isVector() && "Unexpected VT!");
     SDValue Op0 = N->getOperand(0);
     EVT Op0VT = Op0.getValueType();
     MVT XLenVT = Subtarget.getXLenVT();
-    if (VT == MVT::i16 && Op0VT == MVT::f16 && Subtarget.hasStdExtZfh()) {
+    if (VT == MVT::i16 && Op0VT == MVT::f16 &&
+        Subtarget.hasStdExtZfhOrZfhmin()) {
       SDValue FPConv = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenVT, Op0);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FPConv));
     } else if (VT == MVT::i32 && Op0VT == MVT::f32 && Subtarget.is64Bit() &&
                Subtarget.hasStdExtF()) {
       SDValue FPConv =
           DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv));
     } else if (!VT.isVector() && Op0VT.isFixedLengthVector() &&
RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     case 'r':
       // TODO: Support fixed vectors up to XLen for P extension?
       if (VT.isVector())
         break;
       return std::make_pair(0U, &RISCV::GPRRegClass);
     case 'f':
-      if (Subtarget.hasStdExtZfh() && VT == MVT::f16)
+      if (Subtarget.hasStdExtZfhOrZfhmin() && VT == MVT::f16)
         return std::make_pair(0U, &RISCV::FPR16RegClass);
       if (Subtarget.hasStdExtF() && VT == MVT::f32)
         return std::make_pair(0U, &RISCV::FPR32RegClass);
       if (Subtarget.hasStdExtD() && VT == MVT::f64)
         return std::make_pair(0U, &RISCV::FPR64RegClass);
       break;
     default:
       break;
if (FReg != RISCV::NoRegister) {
       assert(RISCV::F0_F <= FReg && FReg <= RISCV::F31_F && "Unknown fp-reg");
       if (Subtarget.hasStdExtD() && (VT == MVT::f64 || VT == MVT::Other)) {
         unsigned RegNo = FReg - RISCV::F0_F;
         unsigned DReg = RISCV::F0_D + RegNo;
         return std::make_pair(DReg, &RISCV::FPR64RegClass);
       }
       if (VT == MVT::f32 || VT == MVT::Other)
         return std::make_pair(FReg, &RISCV::FPR32RegClass);
-      if (Subtarget.hasStdExtZfh() && VT == MVT::f16) {
+      if (Subtarget.hasStdExtZfhOrZfhmin() && VT == MVT::f16) {
         unsigned RegNo = FReg - RISCV::F0_F;
         unsigned HReg = RISCV::F0_H + RegNo;
         return std::make_pair(HReg, &RISCV::FPR16RegClass);
       }
     }
   }
 
   if (Subtarget.hasVInstructions()) {

 
 bool RISCVTargetLowering::shouldConvertFpToSat(unsigned Op, EVT FPVT,
                                                EVT VT) const {
   if (!isOperationLegalOrCustom(Op, VT) || !FPVT.isSimple())
     return false;
 
   switch (FPVT.getSimpleVT().SimpleTy) {
   case MVT::f16:
-    return Subtarget.hasStdExtZfh();
+    return Subtarget.hasStdExtZfhOrZfhmin();
   case MVT::f32:
     return Subtarget.hasStdExtF();
   case MVT::f64:
     return Subtarget.hasStdExtD();
   default:
     return false;
   }
 }

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 
   // FPR->FPR copies and VR->VR copies.
   unsigned Opc;
   bool IsScalableVector = true;
   unsigned NF = 1;
   RISCVII::VLMUL LMul = RISCVII::LMUL_1;
   unsigned SubRegIdx = RISCV::sub_vrm1_0;
   if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) {
+    if (!STI.hasStdExtZfh() && STI.hasStdExtZfhmin()) {
+      // Zfhmin subset doesn't have FSGNJ_H, replaces FSGNJ_H with FSGNJ_S.
+      const TargetRegisterInfo *TRI = STI.getRegisterInfo();
+      DstReg = TRI->getMatchingSuperReg(DstReg, RISCV::sub_16,
+                                        &RISCV::FPR32RegClass);
+      SrcReg = TRI->getMatchingSuperReg(SrcReg, RISCV::sub_16,
+                                        &RISCV::FPR32RegClass);
+      Opc = RISCV::FSGNJ_S;
+    } else {
       Opc = RISCV::FSGNJ_H;
+    }
     IsScalableVector = false;
   } else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::FSGNJ_S;
     IsScalableVector = false;
   } else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::FSGNJ_D;
     IsScalableVector = false;
   } else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::PseudoVMV1R_V;
     LMul = RISCVII::LMUL_1;
   } else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::PseudoVMV2R_V;
     LMul = RISCVII::LMUL_2;
   } else if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::PseudoVMV4R_V;
     LMul = RISCVII::LMUL_4;

llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

 } // Predicates = [HasStdExtZhinx]
 
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZfh] in {
 
-/// Float constants
-def : Pat<(f16 (fpimm0)), (FMV_H_X X0)>;
+// Floating point constant -0.0
 def : Pat<(f16 (fpimmneg0)), (FSGNJN_H (FMV_H_X X0), (FMV_H_X X0))>;
 
 /// Float conversion operations
 
 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
 // are defined later.
 
 /// Float arithmetic operations

 /// Loads
 
 defm : LdPat<load, FLH, f16>;
 
 /// Stores
 
 defm : StPat<store, FSH, FPR16, f16>;
 
+/// Floating point constant +0.0
+def : Pat<(f16 (fpimm0)), (FMV_H_X X0)>;
+
 /// Float conversion operations
 
 // f32 -> f16, f16 -> f32
 def : Pat<(any_fpround FPR32:$rs1), (FCVT_H_S FPR32:$rs1, 0b111)>;
 def : Pat<(any_fpextend FPR16:$rs1), (FCVT_S_H FPR16:$rs1)>;
 
 // Moves (no conversion)
 def : Pat<(riscv_fmv_h_x GPR:$src), (FMV_H_X GPR:$src)>;

 def : Pat<(any_fpround FPR64:$rs1), (FCVT_H_D FPR64:$rs1, 0b111)>;
 def : Pat<(any_fpextend FPR16:$rs1), (FCVT_D_H FPR16:$rs1)>;
 
 /// Float arithmetic operations
 def : Pat<(fcopysign FPR16:$rs1, FPR64:$rs2),
           (FSGNJ_H $rs1, (FCVT_H_D $rs2, 0b111))>;
 def : Pat<(fcopysign FPR64:$rs1, FPR16:$rs2), (FSGNJ_D $rs1, (FCVT_D_H $rs2))>;
 } // Predicates = [HasStdExtZfhOrZfhmin, HasStdExtD]
+
+let Predicates = [HasStdExtZfhmin, NoStdExtZfh] in {
+// Floating point constant -0.0
+def : Pat<(f16 (fpimmneg0)), (FCVT_H_S (FSGNJN_S (FMV_W_X X0), (FMV_W_X X0)), 0b111)>;
+} // Predicates = [HasStdExtZfhmin, NoStdExtZfh]
+
+let Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV32] in {
+def : Pat<(fcopysign FPR32:$rs1, FPR16:$rs2), (FSGNJ_S $rs1, (FCVT_S_H $rs2))>;
+
+// half->[u]int. Round-to-zero must be used.
+def : Pat<(i32 (any_fp_to_sint FPR16:$rs1)), (FCVT_W_S (FCVT_S_H $rs1), 0b001)>;
+def : Pat<(i32 (any_fp_to_uint FPR16:$rs1)), (FCVT_WU_S (FCVT_S_H $rs1), 0b001)>;
+
+// half->int32 with current rounding mode.
+def : Pat<(i32 (any_lrint FPR16:$rs1)), (FCVT_W_S (FCVT_S_H $rs1), 0b111)>;
+
+// half->int32 rounded to nearest with ties rounded away from zero.
+def : Pat<(i32 (any_lround FPR16:$rs1)), (FCVT_W_S (FCVT_S_H $rs1), 0b100)>;
+
+// [u]int->half. Match GCC and default to using dynamic rounding mode.
+def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_S (FCVT_S_W $rs1, 0b111), 0b111)>;
+def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_S (FCVT_S_WU $rs1, 0b111), 0b111)>;
+
+// Saturating float->[u]int32.
+def : Pat<(i32 (riscv_fcvt_x FPR16:$rs1, timm:$frm)), (FCVT_W_S (FCVT_S_H $rs1), timm:$frm)>;
+def : Pat<(i32 (riscv_fcvt_xu FPR16:$rs1, timm:$frm)), (FCVT_WU_S (FCVT_S_H $rs1), timm:$frm)>;
+} // Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV32]
+
+let Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64] in {
+def : Pat<(fcopysign FPR32:$rs1, FPR16:$rs2), (FSGNJ_S $rs1, (FCVT_S_H $rs2))>;
+
+// half->[u]int64. Round-to-zero must be used.
+def : Pat<(i64 (any_fp_to_sint FPR16:$rs1)), (FCVT_L_S (FCVT_S_H $rs1), 0b001)>;
+def : Pat<(i64 (any_fp_to_uint FPR16:$rs1)), (FCVT_LU_S (FCVT_S_H $rs1), 0b001)>;
+
+// half->int64 with current rounding mode.
+def : Pat<(i64 (any_lrint FPR16:$rs1)), (FCVT_L_S (FCVT_S_H $rs1), 0b111)>;
+def : Pat<(i64 (any_llrint FPR16:$rs1)), (FCVT_L_S (FCVT_S_H $rs1), 0b111)>;
+
+// half->int64 rounded to nearest with ties rounded away from zero.
+def : Pat<(i64 (any_lround FPR16:$rs1)), (FCVT_L_S (FCVT_S_H $rs1), 0b100)>;
+def : Pat<(i64 (any_llround FPR16:$rs1)), (FCVT_L_S (FCVT_S_H $rs1), 0b100)>;
+
+// [u]int->fp. Match GCC and default to using dynamic rounding mode.
+def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_S (FCVT_S_L $rs1, 0b111), 0b111)>;
+def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_S (FCVT_S_LU $rs1, 0b111), 0b111)>;
+
+// Saturating float->[u]int64.
+def : Pat<(i64 (riscv_fcvt_x FPR16:$rs1, timm:$frm)), (FCVT_L_S (FCVT_S_H $rs1), timm:$frm)>;
+def : Pat<(i64 (riscv_fcvt_xu FPR16:$rs1, timm:$frm)), (FCVT_LU_S (FCVT_S_H $rs1), timm:$frm)>;
+
+def : Pat<(riscv_any_fcvt_w_rv64 FPR16:$rs1, timm:$frm),  (FCVT_W_S (FCVT_S_H $rs1), timm:$frm)>;
+def : Pat<(riscv_any_fcvt_wu_rv64 FPR16:$rs1, timm:$frm), (FCVT_WU_S (FCVT_S_H $rs1), timm:$frm)>;
+} // Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64]

llvm/lib/Target/RISCV/RISCVSubtarget.h

public:
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZca() const { return HasStdExtZca; }
   bool hasStdExtZcd() const { return HasStdExtZcd; }
   bool hasStdExtZcf() const { return HasStdExtZcf; }
   bool hasStdExtZvl() const { return ZvlLen != 0; }
   bool hasStdExtZvfh() const { return HasStdExtZvfh; }
   bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
+  bool hasStdExtZfhOrZfhmin() const { return HasStdExtZfh || HasStdExtZfhmin; }
   bool hasStdExtZfinx() const { return HasStdExtZfinx; }
   bool hasStdExtZdinx() const { return HasStdExtZdinx; }
   bool hasStdExtZhinxmin() const { return HasStdExtZhinxmin; }
   bool hasStdExtZhinx() const { return HasStdExtZhinx; }
   bool hasStdExtZbkb() const { return HasStdExtZbkb; }
   bool hasStdExtZbkc() const { return HasStdExtZbkc; }
   bool hasStdExtZbkx() const { return HasStdExtZbkx; }
   bool hasStdExtZknd() const { return HasStdExtZknd; }

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

public:
 
   unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
     if (Vector)
       return RISCVRegisterClass::VRRC;
     if (!Ty)
       return RISCVRegisterClass::GPRRC;
 
     Type *ScalarTy = Ty->getScalarType();
-    if ((ScalarTy->isHalfTy() && ST->hasStdExtZfh()) ||
+    if ((ScalarTy->isHalfTy() && ST->hasStdExtZfhOrZfhmin()) ||
         (ScalarTy->isFloatTy() && ST->hasStdExtF()) ||
         (ScalarTy->isDoubleTy() && ST->hasStdExtD())) {
       return RISCVRegisterClass::FPRRC;
     }
 
     return RISCVRegisterClass::GPRRC;
   }
 

llvm/test/CodeGen/RISCV/calling-conv-half.ll

 ; RV64-LP64F-NEXT:    addw a0, s0, a0
 ; RV64-LP64F-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-LP64F-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; RV64-LP64F-NEXT:    addi sp, sp, 16
 ; RV64-LP64F-NEXT:    ret
 ;
 ; RV32-ILP32ZFHMIN-LABEL: callee_half_in_regs:
 ; RV32-ILP32ZFHMIN:       # %bb.0:
-; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, -16
-; RV32-ILP32ZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-ILP32ZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32-ILP32ZFHMIN-NEXT:    mv s0, a0
-; RV32-ILP32ZFHMIN-NEXT:    fmv.x.w a0, fa0
-; RV32-ILP32ZFHMIN-NEXT:    call __extendhfsf2@plt
-; RV32-ILP32ZFHMIN-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32-ILP32ZFHMIN-NEXT:    add a0, s0, a0
-; RV32-ILP32ZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-ILP32ZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, 16
+; RV32-ILP32ZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32-ILP32ZFHMIN-NEXT:    fcvt.w.s a1, ft0, rtz
+; RV32-ILP32ZFHMIN-NEXT:    add a0, a0, a1
 ; RV32-ILP32ZFHMIN-NEXT:    ret
 ;
 ; RV64-LP64ZFHMIN-LABEL: callee_half_in_regs:
 ; RV64-LP64ZFHMIN:       # %bb.0:
-; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, -16
-; RV64-LP64ZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-LP64ZFHMIN-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
-; RV64-LP64ZFHMIN-NEXT:    mv s0, a0
-; RV64-LP64ZFHMIN-NEXT:    fmv.x.w a0, fa0
-; RV64-LP64ZFHMIN-NEXT:    call __extendhfsf2@plt
-; RV64-LP64ZFHMIN-NEXT:    fcvt.l.s a0, fa0, rtz
-; RV64-LP64ZFHMIN-NEXT:    addw a0, s0, a0
-; RV64-LP64ZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64-LP64ZFHMIN-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
-; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, 16
+; RV64-LP64ZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64-LP64ZFHMIN-NEXT:    fcvt.w.s a1, ft0, rtz
+; RV64-LP64ZFHMIN-NEXT:    addw a0, a0, a1
 ; RV64-LP64ZFHMIN-NEXT:    ret
   %b_fptosi = fptosi half %b to i32
   %1 = add i32 %a, %b_fptosi
   ret i32 %1
 }
 
 define i32 @caller_half_in_regs() nounwind {
 ; RV32I-LABEL: caller_half_in_regs:

 ; RV64-LP64F-NEXT:    addi sp, sp, 16
 ; RV64-LP64F-NEXT:    ret
 ;
 ; RV32-ILP32ZFHMIN-LABEL: caller_half_in_regs:
 ; RV32-ILP32ZFHMIN:       # %bb.0:
 ; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32-ILP32ZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-ILP32ZFHMIN-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32-ILP32ZFHMIN-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
+; RV32-ILP32ZFHMIN-NEXT:    flh fa0, %lo(.LCPI1_0)(a0)
 ; RV32-ILP32ZFHMIN-NEXT:    li a0, 1
 ; RV32-ILP32ZFHMIN-NEXT:    call callee_half_in_regs@plt
 ; RV32-ILP32ZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32-ILP32ZFHMIN-NEXT:    ret
 ;
 ; RV64-LP64ZFHMIN-LABEL: caller_half_in_regs:
 ; RV64-LP64ZFHMIN:       # %bb.0:
 ; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64-LP64ZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-LP64ZFHMIN-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV64-LP64ZFHMIN-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
+; RV64-LP64ZFHMIN-NEXT:    flh fa0, %lo(.LCPI1_0)(a0)
 ; RV64-LP64ZFHMIN-NEXT:    li a0, 1
 ; RV64-LP64ZFHMIN-NEXT:    call callee_half_in_regs@plt
 ; RV64-LP64ZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64-LP64ZFHMIN-NEXT:    ret
   %1 = call i32 @callee_half_in_regs(i32 1, half 2.0)
   ret i32 %1
 }

 ; RV64-LP64F-NEXT:    addw a0, s0, a0
 ; RV64-LP64F-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-LP64F-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; RV64-LP64F-NEXT:    addi sp, sp, 16
 ; RV64-LP64F-NEXT:    ret
 ;
 ; RV32-ILP32ZFHMIN-LABEL: callee_half_on_stack:
 ; RV32-ILP32ZFHMIN:       # %bb.0:
-; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, -16
-; RV32-ILP32ZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-ILP32ZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32-ILP32ZFHMIN-NEXT:    mv s0, a7
-; RV32-ILP32ZFHMIN-NEXT:    fmv.x.w a0, fa0
-; RV32-ILP32ZFHMIN-NEXT:    call __extendhfsf2@plt
-; RV32-ILP32ZFHMIN-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32-ILP32ZFHMIN-NEXT:    add a0, s0, a0
-; RV32-ILP32ZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-ILP32ZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, 16
+; RV32-ILP32ZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32-ILP32ZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32-ILP32ZFHMIN-NEXT:    add a0, a7, a0
 ; RV32-ILP32ZFHMIN-NEXT:    ret
 ;
 ; RV64-LP64ZFHMIN-LABEL: callee_half_on_stack:
 ; RV64-LP64ZFHMIN:       # %bb.0:
-; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, -16
-; RV64-LP64ZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-LP64ZFHMIN-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
-; RV64-LP64ZFHMIN-NEXT:    mv s0, a7
-; RV64-LP64ZFHMIN-NEXT:    fmv.x.w a0, fa0
-; RV64-LP64ZFHMIN-NEXT:    call __extendhfsf2@plt
-; RV64-LP64ZFHMIN-NEXT:    fcvt.l.s a0, fa0, rtz
-; RV64-LP64ZFHMIN-NEXT:    addw a0, s0, a0
-; RV64-LP64ZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64-LP64ZFHMIN-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
-; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, 16
+; RV64-LP64ZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64-LP64ZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64-LP64ZFHMIN-NEXT:    addw a0, a7, a0
 ; RV64-LP64ZFHMIN-NEXT:    ret
   %1 = fptosi half %i to i32
   %2 = add i32 %h, %1
   ret i32 %2
 }
 
 define i32 @caller_half_on_stack() nounwind {
 ; RV32I-LABEL: caller_half_on_stack:

 ; RV64-LP64F-NEXT:    addi sp, sp, 16
 ; RV64-LP64F-NEXT:    ret
 ;
 ; RV32-ILP32ZFHMIN-LABEL: caller_half_on_stack:
 ; RV32-ILP32ZFHMIN:       # %bb.0:
 ; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32-ILP32ZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-ILP32ZFHMIN-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV32-ILP32ZFHMIN-NEXT:    flw fa0, %lo(.LCPI3_0)(a0)
+; RV32-ILP32ZFHMIN-NEXT:    flh fa0, %lo(.LCPI3_0)(a0)
 ; RV32-ILP32ZFHMIN-NEXT:    li a0, 1
 ; RV32-ILP32ZFHMIN-NEXT:    li a1, 2
 ; RV32-ILP32ZFHMIN-NEXT:    li a2, 3
 ; RV32-ILP32ZFHMIN-NEXT:    li a3, 4
 ; RV32-ILP32ZFHMIN-NEXT:    li a4, 5
 ; RV32-ILP32ZFHMIN-NEXT:    li a5, 6
 ; RV32-ILP32ZFHMIN-NEXT:    li a6, 7
 ; RV32-ILP32ZFHMIN-NEXT:    li a7, 8
 ; RV32-ILP32ZFHMIN-NEXT:    call callee_half_on_stack@plt
 ; RV32-ILP32ZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32-ILP32ZFHMIN-NEXT:    ret
 ;
 ; RV64-LP64ZFHMIN-LABEL: caller_half_on_stack:
 ; RV64-LP64ZFHMIN:       # %bb.0:
 ; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64-LP64ZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-LP64ZFHMIN-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV64-LP64ZFHMIN-NEXT:    flw fa0, %lo(.LCPI3_0)(a0)
+; RV64-LP64ZFHMIN-NEXT:    flh fa0, %lo(.LCPI3_0)(a0)
 ; RV64-LP64ZFHMIN-NEXT:    li a0, 1
 ; RV64-LP64ZFHMIN-NEXT:    li a1, 2
 ; RV64-LP64ZFHMIN-NEXT:    li a2, 3
 ; RV64-LP64ZFHMIN-NEXT:    li a3, 4
 ; RV64-LP64ZFHMIN-NEXT:    li a4, 5
 ; RV64-LP64ZFHMIN-NEXT:    li a5, 6
 ; RV64-LP64ZFHMIN-NEXT:    li a6, 7
 ; RV64-LP64ZFHMIN-NEXT:    li a7, 8

 ; RV64-LP64F:       # %bb.0:
 ; RV64-LP64F-NEXT:    lui a0, %hi(.LCPI4_0)
 ; RV64-LP64F-NEXT:    flw fa0, %lo(.LCPI4_0)(a0)
 ; RV64-LP64F-NEXT:    ret
 ;
 ; RV32-ILP32ZFHMIN-LABEL: callee_half_ret:
 ; RV32-ILP32ZFHMIN:       # %bb.0:
 ; RV32-ILP32ZFHMIN-NEXT:    lui a0, %hi(.LCPI4_0)
-; RV32-ILP32ZFHMIN-NEXT:    flw fa0, %lo(.LCPI4_0)(a0)
+; RV32-ILP32ZFHMIN-NEXT:    flh fa0, %lo(.LCPI4_0)(a0)
 ; RV32-ILP32ZFHMIN-NEXT:    ret
 ;
 ; RV64-LP64ZFHMIN-LABEL: callee_half_ret:
 ; RV64-LP64ZFHMIN:       # %bb.0:
 ; RV64-LP64ZFHMIN-NEXT:    lui a0, %hi(.LCPI4_0)
-; RV64-LP64ZFHMIN-NEXT:    flw fa0, %lo(.LCPI4_0)(a0)
+; RV64-LP64ZFHMIN-NEXT:    flh fa0, %lo(.LCPI4_0)(a0)
 ; RV64-LP64ZFHMIN-NEXT:    ret
   ret half 1.0
 }
 
 define i32 @caller_half_ret() nounwind {
 ; RV32I-LABEL: caller_half_ret:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16

 ; RV64-LP64F-NEXT:    addi sp, sp, 16
 ; RV64-LP64F-NEXT:    ret
 ;
 ; RV32-ILP32ZFHMIN-LABEL: caller_half_ret:
 ; RV32-ILP32ZFHMIN:       # %bb.0:
 ; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32-ILP32ZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-ILP32ZFHMIN-NEXT:    call callee_half_ret@plt
-; RV32-ILP32ZFHMIN-NEXT:    fmv.x.w a0, fa0
-; RV32-ILP32ZFHMIN-NEXT:    call __extendhfsf2@plt
-; RV32-ILP32ZFHMIN-NEXT:    fcvt.w.s a0, fa0, rtz
+; RV32-ILP32ZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32-ILP32ZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
 ; RV32-ILP32ZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32-ILP32ZFHMIN-NEXT:    ret
 ;
 ; RV64-LP64ZFHMIN-LABEL: caller_half_ret:
 ; RV64-LP64ZFHMIN:       # %bb.0:
 ; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64-LP64ZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-LP64ZFHMIN-NEXT:    call callee_half_ret@plt
-; RV64-LP64ZFHMIN-NEXT:    fmv.x.w a0, fa0
-; RV64-LP64ZFHMIN-NEXT:    call __extendhfsf2@plt
-; RV64-LP64ZFHMIN-NEXT:    fcvt.l.s a0, fa0, rtz
+; RV64-LP64ZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64-LP64ZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
 ; RV64-LP64ZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64-LP64ZFHMIN-NEXT:    ret
   %1 = call half @callee_half_ret()
   %2 = fptosi half %1 to i32
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/copysign-casts.ll

 ; RUN:   -mattr=+zfh -target-abi ilp32f < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32IFZFH
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f -mattr=+d \
 ; RUN:   -mattr=+zfh -target-abi ilp32d < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32IFDZFH
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+f -mattr=+d \
 ; RUN:   -mattr=+zfh -target-abi lp64d < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64IFDZFH
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f \
+; RUN:   -mattr=+zfhmin -target-abi ilp32f < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IFZFHMIN
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f -mattr=+d \
+; RUN:   -mattr=+zfhmin -target-abi ilp32d < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IFDZFHMIN
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+f -mattr=+d \
+; RUN:   -mattr=+zfhmin -target-abi lp64d < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IFDZFHMIN
 
 ; Test fcopysign scenarios where the sign argument is casted to the type of the
 ; magnitude argument. Those casts can be folded away by the DAGCombiner.
 
 declare double @llvm.copysign.f64(double, double)
 declare float @llvm.copysign.f32(float, float)
 declare half @llvm.copysign.f16(half, half)
 

 ; RV32IFDZFH-NEXT:    fsgnj.d fa0, fa0, ft0
 ; RV32IFDZFH-NEXT:    ret
 ;
 ; RV64IFDZFH-LABEL: fold_promote_d_s:
 ; RV64IFDZFH:       # %bb.0:
 ; RV64IFDZFH-NEXT:    fcvt.d.s ft0, fa1
 ; RV64IFDZFH-NEXT:    fsgnj.d fa0, fa0, ft0
 ; RV64IFDZFH-NEXT:    ret
+;
+; RV32IFZFHMIN-LABEL: fold_promote_d_s:
+; RV32IFZFHMIN:       # %bb.0:
+; RV32IFZFHMIN-NEXT:    fmv.x.w a2, fa0
+; RV32IFZFHMIN-NEXT:    lui a3, 524288
+; RV32IFZFHMIN-NEXT:    and a2, a2, a3
+; RV32IFZFHMIN-NEXT:    slli a1, a1, 1
+; RV32IFZFHMIN-NEXT:    srli a1, a1, 1
+; RV32IFZFHMIN-NEXT:    or a1, a1, a2
+; RV32IFZFHMIN-NEXT:    ret
+;
+; RV32IFDZFHMIN-LABEL: fold_promote_d_s:
+; RV32IFDZFHMIN:       # %bb.0:
+; RV32IFDZFHMIN-NEXT:    fcvt.d.s ft0, fa1
+; RV32IFDZFHMIN-NEXT:    fsgnj.d fa0, fa0, ft0
+; RV32IFDZFHMIN-NEXT:    ret
+;
+; RV64IFDZFHMIN-LABEL: fold_promote_d_s:
+; RV64IFDZFHMIN:       # %bb.0:
+; RV64IFDZFHMIN-NEXT:    fcvt.d.s ft0, fa1
+; RV64IFDZFHMIN-NEXT:    fsgnj.d fa0, fa0, ft0
+; RV64IFDZFHMIN-NEXT:    ret
   %c = fpext float %b to double
   %t = call double @llvm.copysign.f64(double %a, double %c)
   ret double %t
 }
 
 define double @fold_promote_d_h(double %a, half %b) nounwind {
 ; RV32I-LABEL: fold_promote_d_h:
 ; RV32I:       # %bb.0:

 ; RV32IFDZFH-NEXT:    fsgnj.d fa0, fa0, ft0
 ; RV32IFDZFH-NEXT:    ret
 ;
 ; RV64IFDZFH-LABEL: fold_promote_d_h:
 ; RV64IFDZFH:       # %bb.0:
 ; RV64IFDZFH-NEXT:    fcvt.d.h ft0, fa1
 ; RV64IFDZFH-NEXT:    fsgnj.d fa0, fa0, ft0
 ; RV64IFDZFH-NEXT:    ret
+;
+; RV32IFZFHMIN-LABEL: fold_promote_d_h:
+; RV32IFZFHMIN:       # %bb.0:
+; RV32IFZFHMIN-NEXT:    fmv.x.h a2, fa0
+; RV32IFZFHMIN-NEXT:    lui a3, 8
+; RV32IFZFHMIN-NEXT:    and a2, a2, a3
+; RV32IFZFHMIN-NEXT:    slli a2, a2, 16
+; RV32IFZFHMIN-NEXT:    slli a1, a1, 1
+; RV32IFZFHMIN-NEXT:    srli a1, a1, 1
+; RV32IFZFHMIN-NEXT:    or a1, a1, a2
+; RV32IFZFHMIN-NEXT:    ret
+;
+; RV32IFDZFHMIN-LABEL: fold_promote_d_h:
+; RV32IFDZFHMIN:       # %bb.0:
+; RV32IFDZFHMIN-NEXT:    fcvt.d.h ft0, fa1
+; RV32IFDZFHMIN-NEXT:    fsgnj.d fa0, fa0, ft0
+; RV32IFDZFHMIN-NEXT:    ret
+;
+; RV64IFDZFHMIN-LABEL: fold_promote_d_h:
+; RV64IFDZFHMIN:       # %bb.0:
+; RV64IFDZFHMIN-NEXT:    fcvt.d.h ft0, fa1
+; RV64IFDZFHMIN-NEXT:    fsgnj.d fa0, fa0, ft0
+; RV64IFDZFHMIN-NEXT:    ret
   %c = fpext half %b to double
   %t = call double @llvm.copysign.f64(double %a, double %c)
   ret double %t
 }
 
 define float @fold_promote_f_h(float %a, half %b) nounwind {
 ; RV32I-LABEL: fold_promote_f_h:
 ; RV32I:       # %bb.0:

 ; RV32IFDZFH-NEXT:    fsgnj.s fa0, fa0, ft0
 ; RV32IFDZFH-NEXT:    ret
 ;
 ; RV64IFDZFH-LABEL: fold_promote_f_h:
 ; RV64IFDZFH:       # %bb.0:
 ; RV64IFDZFH-NEXT:    fcvt.s.h ft0, fa1
 ; RV64IFDZFH-NEXT:    fsgnj.s fa0, fa0, ft0
 ; RV64IFDZFH-NEXT:    ret
+;
+; RV32IFZFHMIN-LABEL: fold_promote_f_h:
+; RV32IFZFHMIN:       # %bb.0:
+; RV32IFZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV32IFZFHMIN-NEXT:    fsgnj.s fa0, fa0, ft0
+; RV32IFZFHMIN-NEXT:    ret
+;
+; RV32IFDZFHMIN-LABEL: fold_promote_f_h:
+; RV32IFDZFHMIN:       # %bb.0:
+; RV32IFDZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV32IFDZFHMIN-NEXT:    fsgnj.s fa0, fa0, ft0
+; RV32IFDZFHMIN-NEXT:    ret
+;
+; RV64IFDZFHMIN-LABEL: fold_promote_f_h:
+; RV64IFDZFHMIN:       # %bb.0:
+; RV64IFDZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IFDZFHMIN-NEXT:    fsgnj.s fa0, fa0, ft0
+; RV64IFDZFHMIN-NEXT:    ret
   %c = fpext half %b to float
   %t = call float @llvm.copysign.f32(float %a, float %c)
   ret float %t
 }
 
 define float @fold_demote_s_d(float %a, double %b) nounwind {
 ; RV32I-LABEL: fold_demote_s_d:
 ; RV32I:       # %bb.0:

 ; RV32IFDZFH-NEXT:    fsgnj.s fa0, fa0, ft0
 ; RV32IFDZFH-NEXT:    ret
 ;
 ; RV64IFDZFH-LABEL: fold_demote_s_d:
 ; RV64IFDZFH:       # %bb.0:
 ; RV64IFDZFH-NEXT:    fcvt.s.d ft0, fa1
 ; RV64IFDZFH-NEXT:    fsgnj.s fa0, fa0, ft0
 ; RV64IFDZFH-NEXT:    ret
+;
+; RV32IFZFHMIN-LABEL: fold_demote_s_d:
+; RV32IFZFHMIN:       # %bb.0:
+; RV32IFZFHMIN-NEXT:    fmv.w.x ft0, a1
+; RV32IFZFHMIN-NEXT:    fsgnj.s fa0, fa0, ft0
+; RV32IFZFHMIN-NEXT:    ret
+;
+; RV32IFDZFHMIN-LABEL: fold_demote_s_d:
+; RV32IFDZFHMIN:       # %bb.0:
+; RV32IFDZFHMIN-NEXT:    fcvt.s.d ft0, fa1
+; RV32IFDZFHMIN-NEXT:    fsgnj.s fa0, fa0, ft0
+; RV32IFDZFHMIN-NEXT:    ret
+;
+; RV64IFDZFHMIN-LABEL: fold_demote_s_d:
+; RV64IFDZFHMIN:       # %bb.0:
+; RV64IFDZFHMIN-NEXT:    fcvt.s.d ft0, fa1
+; RV64IFDZFHMIN-NEXT:    fsgnj.s fa0, fa0, ft0
+; RV64IFDZFHMIN-NEXT:    ret
   %c = fptrunc double %b to float
   %t = call float @llvm.copysign.f32(float %a, float %c)
   ret float %t
 }
 
 define half @fold_demote_h_s(half %a, float %b) nounwind {
 ; RV32I-LABEL: fold_demote_h_s:
 ; RV32I:       # %bb.0:

 ; RV32IFDZFH-NEXT:    fsgnj.h fa0, fa0, ft0
 ; RV32IFDZFH-NEXT:    ret
 ;
 ; RV64IFDZFH-LABEL: fold_demote_h_s:
 ; RV64IFDZFH:       # %bb.0:
 ; RV64IFDZFH-NEXT:    fcvt.h.s ft0, fa1
 ; RV64IFDZFH-NEXT:    fsgnj.h fa0, fa0, ft0
 ; RV64IFDZFH-NEXT:    ret
+;
+; RV32IFZFHMIN-LABEL: fold_demote_h_s:
+; RV32IFZFHMIN:       # %bb.0:
+; RV32IFZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IFZFHMIN-NEXT:    fsh fa0, 12(sp)
+; RV32IFZFHMIN-NEXT:    fmv.x.w a0, fa1
+; RV32IFZFHMIN-NEXT:    lbu a1, 13(sp)
+; RV32IFZFHMIN-NEXT:    lui a2, 524288
+; RV32IFZFHMIN-NEXT:    and a0, a0, a2
+; RV32IFZFHMIN-NEXT:    srli a0, a0, 24
+; RV32IFZFHMIN-NEXT:    andi a1, a1, 127
+; RV32IFZFHMIN-NEXT:    or a0, a1, a0
+; RV32IFZFHMIN-NEXT:    sb a0, 13(sp)
+; RV32IFZFHMIN-NEXT:    flh fa0, 12(sp)
+; RV32IFZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IFZFHMIN-NEXT:    ret
+;
+; RV32IFDZFHMIN-LABEL: fold_demote_h_s:
+; RV32IFDZFHMIN:       # %bb.0:
+; RV32IFDZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IFDZFHMIN-NEXT:    fsh fa0, 12(sp)
+; RV32IFDZFHMIN-NEXT:    fmv.x.w a0, fa1
+; RV32IFDZFHMIN-NEXT:    lbu a1, 13(sp)
+; RV32IFDZFHMIN-NEXT:    lui a2, 524288
+; RV32IFDZFHMIN-NEXT:    and a0, a0, a2
+; RV32IFDZFHMIN-NEXT:    srli a0, a0, 24
+; RV32IFDZFHMIN-NEXT:    andi a1, a1, 127
+; RV32IFDZFHMIN-NEXT:    or a0, a1, a0
+; RV32IFDZFHMIN-NEXT:    sb a0, 13(sp)
+; RV32IFDZFHMIN-NEXT:    flh fa0, 12(sp)
+; RV32IFDZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IFDZFHMIN-NEXT:    ret
+;
+; RV64IFDZFHMIN-LABEL: fold_demote_h_s:
+; RV64IFDZFHMIN:       # %bb.0:
+; RV64IFDZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IFDZFHMIN-NEXT:    fsw fa1, 8(sp)
+; RV64IFDZFHMIN-NEXT:    fsh fa0, 0(sp)
+; RV64IFDZFHMIN-NEXT:    lbu a0, 11(sp)
+; RV64IFDZFHMIN-NEXT:    lbu a1, 1(sp)
+; RV64IFDZFHMIN-NEXT:    andi a0, a0, 128
+; RV64IFDZFHMIN-NEXT:    andi a1, a1, 127
+; RV64IFDZFHMIN-NEXT:    or a0, a1, a0
+; RV64IFDZFHMIN-NEXT:    sb a0, 1(sp)
+; RV64IFDZFHMIN-NEXT:    flh fa0, 0(sp)
+; RV64IFDZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IFDZFHMIN-NEXT:    ret
   %c = fptrunc float %b to half
   %t = call half @llvm.copysign.f16(half %a, half %c)
   ret half %t
 }
 
 define half @fold_demote_h_d(half %a, double %b) nounwind {
 ; RV32I-LABEL: fold_demote_h_d:
 ; RV32I:       # %bb.0:

 ; RV32IFDZFH-NEXT:    fsgnj.h fa0, fa0, ft0
 ; RV32IFDZFH-NEXT:    ret
 ;
 ; RV64IFDZFH-LABEL: fold_demote_h_d:
 ; RV64IFDZFH:       # %bb.0:
 ; RV64IFDZFH-NEXT:    fcvt.h.d ft0, fa1
 ; RV64IFDZFH-NEXT:    fsgnj.h fa0, fa0, ft0
 ; RV64IFDZFH-NEXT:    ret
+;
+; RV32IFZFHMIN-LABEL: fold_demote_h_d:
+; RV32IFZFHMIN:       # %bb.0:
+; RV32IFZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IFZFHMIN-NEXT:    fsh fa0, 8(sp)
+; RV32IFZFHMIN-NEXT:    srli a1, a1, 16
+; RV32IFZFHMIN-NEXT:    fmv.h.x ft0, a1
+; RV32IFZFHMIN-NEXT:    fsh ft0, 12(sp)
+; RV32IFZFHMIN-NEXT:    lbu a0, 9(sp)
+; RV32IFZFHMIN-NEXT:    lbu a1, 13(sp)
+; RV32IFZFHMIN-NEXT:    andi a0, a0, 127
+; RV32IFZFHMIN-NEXT:    andi a1, a1, 128
+; RV32IFZFHMIN-NEXT:    or a0, a0, a1
+; RV32IFZFHMIN-NEXT:    sb a0, 9(sp)
+; RV32IFZFHMIN-NEXT:    flh fa0, 8(sp)
+; RV32IFZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IFZFHMIN-NEXT:    ret
+;
+; RV32IFDZFHMIN-LABEL: fold_demote_h_d:
+; RV32IFDZFHMIN:       # %bb.0:
+; RV32IFDZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IFDZFHMIN-NEXT:    fsd fa1, 8(sp)
+; RV32IFDZFHMIN-NEXT:    fsh fa0, 4(sp)
+; RV32IFDZFHMIN-NEXT:    lbu a0, 15(sp)
+; RV32IFDZFHMIN-NEXT:    lbu a1, 5(sp)
+; RV32IFDZFHMIN-NEXT:    andi a0, a0, 128
+; RV32IFDZFHMIN-NEXT:    andi a1, a1, 127
+; RV32IFDZFHMIN-NEXT:    or a0, a1, a0
+; RV32IFDZFHMIN-NEXT:    sb a0, 5(sp)
+; RV32IFDZFHMIN-NEXT:    flh fa0, 4(sp)
+; RV32IFDZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IFDZFHMIN-NEXT:    ret
+;
+; RV64IFDZFHMIN-LABEL: fold_demote_h_d:
+; RV64IFDZFHMIN:       # %bb.0:
+; RV64IFDZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IFDZFHMIN-NEXT:    fsh fa0, 8(sp)
+; RV64IFDZFHMIN-NEXT:    lbu a0, 9(sp)
+; RV64IFDZFHMIN-NEXT:    andi a0, a0, 127
+; RV64IFDZFHMIN-NEXT:    fmv.x.d a1, fa1
+; RV64IFDZFHMIN-NEXT:    srli a1, a1, 63
+; RV64IFDZFHMIN-NEXT:    slli a1, a1, 63
+; RV64IFDZFHMIN-NEXT:    srli a1, a1, 56
+; RV64IFDZFHMIN-NEXT:    or a0, a0, a1
+; RV64IFDZFHMIN-NEXT:    sb a0, 9(sp)
+; RV64IFDZFHMIN-NEXT:    flh fa0, 8(sp)
+; RV64IFDZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IFDZFHMIN-NEXT:    ret
   %c = fptrunc double %b to half
   %t = call half @llvm.copysign.f16(half %a, half %c)
   ret half %t
 }

llvm/test/CodeGen/RISCV/half-arith-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -disable-strictnode-mutation -target-abi ilp32f < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -disable-strictnode-mutation -target-abi lp64f < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -disable-strictnode-mutation -target-abi ilp32f < %s \
+; RUN:   | FileCheck -check-prefix=CHECK-ZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -disable-strictnode-mutation -target-abi lp64f < %s \
+; RUN:  | FileCheck -check-prefix=CHECK-ZFHMIN %s
 
 ; FIXME: We can't test without Zfh because soft promote legalization isn't
 ; implemented in SelectionDAG for STRICT nodes.
 
 define half @fadd_h(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fadd_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fadd.h fa0, fa0, fa1
 ; CHECK-NEXT:    ret
+;
+; CHECK-ZFHMIN-LABEL: fadd_h:
+; CHECK-ZFHMIN:       # %bb.0:
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECK-ZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK-ZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fadd.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fadd.f16(half, half, metadata, metadata)
 
 define half @fsub_h(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fsub_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fsub.h fa0, fa0, fa1
 ; CHECK-NEXT:    ret
+;
+; CHECK-ZFHMIN-LABEL: fsub_h:
+; CHECK-ZFHMIN:       # %bb.0:
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECK-ZFHMIN-NEXT:    fsub.s ft0, ft1, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK-ZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fsub.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fsub.f16(half, half, metadata, metadata)
 
 define half @fmul_h(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fmul_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmul.h fa0, fa0, fa1
 ; CHECK-NEXT:    ret
+;
+; CHECK-ZFHMIN-LABEL: fmul_h:
+; CHECK-ZFHMIN:       # %bb.0:
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECK-ZFHMIN-NEXT:    fmul.s ft0, ft1, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK-ZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fmul.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fmul.f16(half, half, metadata, metadata)
 
 define half @fdiv_h(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fdiv_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fdiv.h fa0, fa0, fa1
 ; CHECK-NEXT:    ret
+;
+; CHECK-ZFHMIN-LABEL: fdiv_h:
+; CHECK-ZFHMIN:       # %bb.0:
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECK-ZFHMIN-NEXT:    fdiv.s ft0, ft1, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK-ZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fdiv.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fdiv.f16(half, half, metadata, metadata)
 
 define half @fsqrt_h(half %a) nounwind strictfp {
 ; CHECK-LABEL: fsqrt_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fsqrt.h fa0, fa0
 ; CHECK-NEXT:    ret
+;
+; CHECK-ZFHMIN-LABEL: fsqrt_h:
+; CHECK-ZFHMIN:       # %bb.0:
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK-ZFHMIN-NEXT:    fsqrt.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK-ZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata)
 
 ; FIXME: fminnum/fmaxnum need libcalls to handle SNaN, but we don't have f16
 ; libcalls and don't support promotion yet.
 ;define half @fmin_h(half %a, half %b) nounwind strictfp {
 ;  %1 = call half @llvm.experimental.constrained.minnum.f16(half %a, half %b, metadata !"fpexcept.strict") strictfp
 ;  ret half %1
 ;}
 ;declare half @llvm.experimental.constrained.minnum.f16(half, half, metadata) strictfp
 ;
 ;define half @fmax_h(half %a, half %b) nounwind strictfp {
 ;  %1 = call half @llvm.experimental.constrained.maxnum.f16(half %a, half %b, metadata !"fpexcept.strict") strictfp
 ;  ret half %1
 ;}
 ;declare half @llvm.experimental.constrained.maxnum.f16(half, half, metadata) strictfp
 
 define half @fmadd_h(half %a, half %b, half %c) nounwind strictfp {
 ; CHECK-LABEL: fmadd_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmadd.h fa0, fa0, fa1, fa2
 ; CHECK-NEXT:    ret
+;
+; CHECK-ZFHMIN-LABEL: fmadd_h:
+; CHECK-ZFHMIN:       # %bb.0:
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, fa2
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECK-ZFHMIN-NEXT:    fmadd.s ft0, ft2, ft1, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK-ZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) strictfp
 
 define half @fmsub_h(half %a, half %b, half %c) nounwind strictfp {
 ; CHECK-LABEL: fmsub_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    fadd.h ft0, fa2, ft0
 ; CHECK-NEXT:    fmsub.h fa0, fa0, fa1, ft0
 ; CHECK-NEXT:    ret
+;
+; CHECK-ZFHMIN-LABEL: fmsub_h:
+; CHECK-ZFHMIN:       # %bb.0:
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, fa2
+; CHECK-ZFHMIN-NEXT:    fmv.w.x ft1, zero
+; CHECK-ZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fneg.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECK-ZFHMIN-NEXT:    fmadd.s ft0, ft2, ft1, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK-ZFHMIN-NEXT:    ret
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %negc = fneg half %c_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fnmadd_h(half %a, half %b, half %c) nounwind strictfp {
 ; CHECK-LABEL: fnmadd_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    fadd.h ft1, fa0, ft0
 ; CHECK-NEXT:    fadd.h ft0, fa2, ft0
 ; CHECK-NEXT:    fnmadd.h fa0, ft1, fa1, ft0
 ; CHECK-NEXT:    ret
+;
+; CHECK-ZFHMIN-LABEL: fnmadd_h:
+; CHECK-ZFHMIN:       # %bb.0:
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK-ZFHMIN-NEXT:    fmv.w.x ft1, zero
+; CHECK-ZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft2, fa2
+; CHECK-ZFHMIN-NEXT:    fadd.s ft1, ft2, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fneg.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECK-ZFHMIN-NEXT:    fneg.s ft1, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft2, fa1
+; CHECK-ZFHMIN-NEXT:    fmadd.s ft0, ft0, ft2, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK-ZFHMIN-NEXT:    ret
   %a_ = fadd half 0.0, %a
   %c_ = fadd half 0.0, %c
   %nega = fneg half %a_
   %negc = fneg half %c_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %nega, half %b, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fnmadd_h_2(half %a, half %b, half %c) nounwind strictfp {
 ; CHECK-LABEL: fnmadd_h_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    fadd.h ft1, fa1, ft0
 ; CHECK-NEXT:    fadd.h ft0, fa2, ft0
 ; CHECK-NEXT:    fnmadd.h fa0, ft1, fa0, ft0
 ; CHECK-NEXT:    ret
+;
+; CHECK-ZFHMIN-LABEL: fnmadd_h_2:
+; CHECK-ZFHMIN:       # %bb.0:
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECK-ZFHMIN-NEXT:    fmv.w.x ft1, zero
+; CHECK-ZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft2, fa2
+; CHECK-ZFHMIN-NEXT:    fadd.s ft1, ft2, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fneg.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECK-ZFHMIN-NEXT:    fneg.s ft1, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECK-ZFHMIN-NEXT:    fmadd.s ft0, ft2, ft0, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK-ZFHMIN-NEXT:    ret
   %b_ = fadd half 0.0, %b
   %c_ = fadd half 0.0, %c
   %negb = fneg half %b_
   %negc = fneg half %c_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %negb, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fnmsub_h(half %a, half %b, half %c) nounwind strictfp {
 ; CHECK-LABEL: fnmsub_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    fadd.h ft0, fa0, ft0
 ; CHECK-NEXT:    fnmsub.h fa0, ft0, fa1, fa2
 ; CHECK-NEXT:    ret
+;
+; CHECK-ZFHMIN-LABEL: fnmsub_h:
+; CHECK-ZFHMIN:       # %bb.0:
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK-ZFHMIN-NEXT:    fmv.w.x ft1, zero
+; CHECK-ZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fneg.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft1, fa2
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft2, fa1
+; CHECK-ZFHMIN-NEXT:    fmadd.s ft0, ft0, ft2, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK-ZFHMIN-NEXT:    ret
   %a_ = fadd half 0.0, %a
   %nega = fneg half %a_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %nega, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fnmsub_h_2(half %a, half %b, half %c) nounwind strictfp {
 ; CHECK-LABEL: fnmsub_h_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    fadd.h ft0, fa1, ft0
 ; CHECK-NEXT:    fnmsub.h fa0, ft0, fa0, fa2
 ; CHECK-NEXT:    ret
+;
+; CHECK-ZFHMIN-LABEL: fnmsub_h_2:
+; CHECK-ZFHMIN:       # %bb.0:
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECK-ZFHMIN-NEXT:    fmv.w.x ft1, zero
+; CHECK-ZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fneg.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft1, fa2
+; CHECK-ZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECK-ZFHMIN-NEXT:    fmadd.s ft0, ft2, ft0, ft1
+; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK-ZFHMIN-NEXT:    ret
   %b_ = fadd half 0.0, %b
   %negb = fneg half %b_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %negb, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }

llvm/test/CodeGen/RISCV/half-arith.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFH %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN,CHECK-RV32-FSGNJ %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi lp64f < %s | FileCheck --check-prefixes=CHECKIZFHMIN,CHECK-RV64-FSGNJ %s
 
 ; These tests are each targeted at a particular RISC-V FPU instruction.
 ; Compares and conversions can be found in half-fcmp.ll and half-convert.ll
 ; respectively. Some other half-*.ll files in this folder exercise LLVM IR
 ; instructions that don't directly match a RISC-V instruction.
 
 define half @fadd_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fadd_s:

 ; RV64I-NEXT:    call __addsf3@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fadd_s:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fadd half %a, %b
   ret half %1
 }
 
 define half @fsub_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fsub_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fsub.h fa0, fa0, fa1

 ; RV64I-NEXT:    call __subsf3@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fsub_s:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fsub.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fsub half %a, %b
   ret half %1
 }
 
 define half @fmul_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fmul_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmul.h fa0, fa0, fa1

 ; RV64I-NEXT:    call __mulsf3@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fmul_s:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fmul.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fmul half %a, %b
   ret half %1
 }
 
 define half @fdiv_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fdiv_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fdiv.h fa0, fa0, fa1

 ; RV64I-NEXT:    call __divsf3@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fdiv_s:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fdiv.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fdiv half %a, %b
   ret half %1
 }
 
 declare half @llvm.sqrt.f16(half)
 
 define half @fsqrt_s(half %a) nounwind {
 ; CHECKIZFH-LABEL: fsqrt_s:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call sqrtf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fsqrt_s:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fsqrt.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.sqrt.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.copysign.f16(half, half)
 
 define half @fsgnj_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fsgnj_s:

 ; RV64I-LABEL: fsgnj_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a2, 1048568
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    slli a0, a0, 49
 ; RV64I-NEXT:    srli a0, a0, 49
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
+;
+; CHECK-RV32-FSGNJ-LABEL: fsgnj_s:
+; CHECK-RV32-FSGNJ:       # %bb.0:
+; CHECK-RV32-FSGNJ-NEXT:    addi sp, sp, -16
+; CHECK-RV32-FSGNJ-NEXT:    fsh fa1, 12(sp)
+; CHECK-RV32-FSGNJ-NEXT:    fsh fa0, 8(sp)
+; CHECK-RV32-FSGNJ-NEXT:    lbu a0, 13(sp)
+; CHECK-RV32-FSGNJ-NEXT:    lbu a1, 9(sp)
+; CHECK-RV32-FSGNJ-NEXT:    andi a0, a0, 128
+; CHECK-RV32-FSGNJ-NEXT:    andi a1, a1, 127
+; CHECK-RV32-FSGNJ-NEXT:    or a0, a1, a0
+; CHECK-RV32-FSGNJ-NEXT:    sb a0, 9(sp)
+; CHECK-RV32-FSGNJ-NEXT:    flh fa0, 8(sp)
+; CHECK-RV32-FSGNJ-NEXT:    addi sp, sp, 16
+; CHECK-RV32-FSGNJ-NEXT:    ret
+;
+; CHECK-RV64-FSGNJ-LABEL: fsgnj_s:
+; CHECK-RV64-FSGNJ:       # %bb.0:
+; CHECK-RV64-FSGNJ-NEXT:    addi sp, sp, -16
+; CHECK-RV64-FSGNJ-NEXT:    fsh fa1, 8(sp)
+; CHECK-RV64-FSGNJ-NEXT:    fsh fa0, 0(sp)
+; CHECK-RV64-FSGNJ-NEXT:    lbu a0, 9(sp)
+; CHECK-RV64-FSGNJ-NEXT:    lbu a1, 1(sp)
+; CHECK-RV64-FSGNJ-NEXT:    andi a0, a0, 128
+; CHECK-RV64-FSGNJ-NEXT:    andi a1, a1, 127
+; CHECK-RV64-FSGNJ-NEXT:    or a0, a1, a0
+; CHECK-RV64-FSGNJ-NEXT:    sb a0, 1(sp)
+; CHECK-RV64-FSGNJ-NEXT:    flh fa0, 0(sp)
+; CHECK-RV64-FSGNJ-NEXT:    addi sp, sp, 16
+; CHECK-RV64-FSGNJ-NEXT:    ret
+; CHECKFSGNJ-LABEL: fsgnj_s:
+; CHECKFSGNJ:       # %bb.0:
+; CHECKFSGNJ-NEXT:    addi sp, sp, -16
+; CHECKFSGNJ-NEXT:    fsh fa1, 12(sp)
+; CHECKFSGNJ-NEXT:    fsh fa0, 8(sp)
+; CHECKFSGNJ-NEXT:    lbu a0, 13(sp)
+; CHECKFSGNJ-NEXT:    lbu a1, 9(sp)
+; CHECKFSGNJ-NEXT:    andi a0, a0, 128
+; CHECKFSGNJ-NEXT:    andi a1, a1, 127
+; CHECKFSGNJ-NEXT:    or a0, a1, a0
+; CHECKFSGNJ-NEXT:    sb a0, 9(sp)
+; CHECKFSGNJ-NEXT:    flh fa0, 8(sp)
+; CHECKFSGNJ-NEXT:    addi sp, sp, 16
+; CHECKFSGNJ-NEXT:    ret
+; CHECK64FSGNJ-LABEL: fsgnj_s:
+; CHECK64FSGNJ:       # %bb.0:
+; CHECK64FSGNJ-NEXT:    addi sp, sp, -16
+; CHECK64FSGNJ-NEXT:    fsh fa1, 8(sp)
+; CHECK64FSGNJ-NEXT:    fsh fa0, 0(sp)
+; CHECK64FSGNJ-NEXT:    lbu a0, 9(sp)
+; CHECK64FSGNJ-NEXT:    lbu a1, 1(sp)
+; CHECK64FSGNJ-NEXT:    andi a0, a0, 128
+; CHECK64FSGNJ-NEXT:    andi a1, a1, 127
+; CHECK64FSGNJ-NEXT:    or a0, a1, a0
+; CHECK64FSGNJ-NEXT:    sb a0, 1(sp)
+; CHECK64FSGNJ-NEXT:    flh fa0, 0(sp)
+; CHECK64FSGNJ-NEXT:    addi sp, sp, 16
+; CHECK64FSGNJ-NEXT:    ret
   %1 = call half @llvm.copysign.f16(half %a, half %b)
   ret half %1
 }
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define i32 @fneg_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fneg_s:

 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __eqsf2@plt
 ; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fneg_s:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fneg.s ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    feq.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fadd half %a, %a
   %2 = fneg half %1
   %3 = fcmp oeq half %1, %2
   %4 = zext i1 %3 to i32
   ret i32 %4
 }
 
 ; This function performs extra work to ensure that

 ; RV64I-NEXT:    or a0, s1, a0
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECK-RV32-FSGNJ-LABEL: fsgnjn_s:
+; CHECK-RV32-FSGNJ:       # %bb.0:
+; CHECK-RV32-FSGNJ-NEXT:    addi sp, sp, -16
+; CHECK-RV32-FSGNJ-NEXT:    fcvt.s.h ft0, fa1
+; CHECK-RV32-FSGNJ-NEXT:    fcvt.s.h ft1, fa0
+; CHECK-RV32-FSGNJ-NEXT:    fadd.s ft0, ft1, ft0
+; CHECK-RV32-FSGNJ-NEXT:    fcvt.h.s ft0, ft0
+; CHECK-RV32-FSGNJ-NEXT:    fcvt.s.h ft0, ft0
+; CHECK-RV32-FSGNJ-NEXT:    fneg.s ft0, ft0
+; CHECK-RV32-FSGNJ-NEXT:    fcvt.h.s ft0, ft0
+; CHECK-RV32-FSGNJ-NEXT:    fsh fa0, 8(sp)
+; CHECK-RV32-FSGNJ-NEXT:    fsh ft0, 12(sp)
+; CHECK-RV32-FSGNJ-NEXT:    lbu a0, 9(sp)
+; CHECK-RV32-FSGNJ-NEXT:    lbu a1, 13(sp)
+; CHECK-RV32-FSGNJ-NEXT:    andi a0, a0, 127
+; CHECK-RV32-FSGNJ-NEXT:    andi a1, a1, 128
+; CHECK-RV32-FSGNJ-NEXT:    or a0, a0, a1
+; CHECK-RV32-FSGNJ-NEXT:    sb a0, 9(sp)
+; CHECK-RV32-FSGNJ-NEXT:    flh fa0, 8(sp)
+; CHECK-RV32-FSGNJ-NEXT:    addi sp, sp, 16
+; CHECK-RV32-FSGNJ-NEXT:    ret
+;
+; CHECK-RV64-FSGNJ-LABEL: fsgnjn_s:
+; CHECK-RV64-FSGNJ:       # %bb.0:
+; CHECK-RV64-FSGNJ-NEXT:    addi sp, sp, -16
+; CHECK-RV64-FSGNJ-NEXT:    fcvt.s.h ft0, fa1
+; CHECK-RV64-FSGNJ-NEXT:    fcvt.s.h ft1, fa0
+; CHECK-RV64-FSGNJ-NEXT:    fadd.s ft0, ft1, ft0
+; CHECK-RV64-FSGNJ-NEXT:    fcvt.h.s ft0, ft0
+; CHECK-RV64-FSGNJ-NEXT:    fcvt.s.h ft0, ft0
+; CHECK-RV64-FSGNJ-NEXT:    fneg.s ft0, ft0
+; CHECK-RV64-FSGNJ-NEXT:    fcvt.h.s ft0, ft0
+; CHECK-RV64-FSGNJ-NEXT:    fsh fa0, 0(sp)
+; CHECK-RV64-FSGNJ-NEXT:    fsh ft0, 8(sp)
+; CHECK-RV64-FSGNJ-NEXT:    lbu a0, 1(sp)
+; CHECK-RV64-FSGNJ-NEXT:    lbu a1, 9(sp)
+; CHECK-RV64-FSGNJ-NEXT:    andi a0, a0, 127
+; CHECK-RV64-FSGNJ-NEXT:    andi a1, a1, 128
+; CHECK-RV64-FSGNJ-NEXT:    or a0, a0, a1
+; CHECK-RV64-FSGNJ-NEXT:    sb a0, 1(sp)
+; CHECK-RV64-FSGNJ-NEXT:    flh fa0, 0(sp)
+; CHECK-RV64-FSGNJ-NEXT:    addi sp, sp, 16
+; CHECK-RV64-FSGNJ-NEXT:    ret
+; CHECKFSGNJ-LABEL: fsgnjn_s:
+; CHECKFSGNJ:       # %bb.0:
+; CHECKFSGNJ-NEXT:    addi sp, sp, -16
+; CHECKFSGNJ-NEXT:    fcvt.s.h ft0, fa1
+; CHECKFSGNJ-NEXT:    fcvt.s.h ft1, fa0
+; CHECKFSGNJ-NEXT:    fadd.s ft0, ft1, ft0
+; CHECKFSGNJ-NEXT:    fcvt.h.s ft0, ft0
+; CHECKFSGNJ-NEXT:    fcvt.s.h ft0, ft0
+; CHECKFSGNJ-NEXT:    fneg.s ft0, ft0
+; CHECKFSGNJ-NEXT:    fcvt.h.s ft0, ft0
+; CHECKFSGNJ-NEXT:    fsh fa0, 8(sp)
+; CHECKFSGNJ-NEXT:    fsh ft0, 12(sp)
+; CHECKFSGNJ-NEXT:    lbu a0, 9(sp)
+; CHECKFSGNJ-NEXT:    lbu a1, 13(sp)
+; CHECKFSGNJ-NEXT:    andi a0, a0, 127
+; CHECKFSGNJ-NEXT:    andi a1, a1, 128
+; CHECKFSGNJ-NEXT:    or a0, a0, a1
+; CHECKFSGNJ-NEXT:    sb a0, 9(sp)
+; CHECKFSGNJ-NEXT:    flh fa0, 8(sp)
+; CHECKFSGNJ-NEXT:    addi sp, sp, 16
+; CHECKFSGNJ-NEXT:    ret
+; CHECK64FSGNJ-LABEL: fsgnjn_s:
+; CHECK64FSGNJ:       # %bb.0:
+; CHECK64FSGNJ-NEXT:    addi sp, sp, -16
+; CHECK64FSGNJ-NEXT:    fcvt.s.h ft0, fa1
+; CHECK64FSGNJ-NEXT:    fcvt.s.h ft1, fa0
+; CHECK64FSGNJ-NEXT:    fadd.s ft0, ft1, ft0
+; CHECK64FSGNJ-NEXT:    fcvt.h.s ft0, ft0
+; CHECK64FSGNJ-NEXT:    fcvt.s.h ft0, ft0
+; CHECK64FSGNJ-NEXT:    fneg.s ft0, ft0
+; CHECK64FSGNJ-NEXT:    fcvt.h.s ft0, ft0
+; CHECK64FSGNJ-NEXT:    fsh fa0, 0(sp)
+; CHECK64FSGNJ-NEXT:    fsh ft0, 8(sp)
+; CHECK64FSGNJ-NEXT:    lbu a0, 1(sp)
+; CHECK64FSGNJ-NEXT:    lbu a1, 9(sp)
+; CHECK64FSGNJ-NEXT:    andi a0, a0, 127
+; CHECK64FSGNJ-NEXT:    andi a1, a1, 128
+; CHECK64FSGNJ-NEXT:    or a0, a0, a1
+; CHECK64FSGNJ-NEXT:    sb a0, 1(sp)
+; CHECK64FSGNJ-NEXT:    flh fa0, 0(sp)
+; CHECK64FSGNJ-NEXT:    addi sp, sp, 16
+; CHECK64FSGNJ-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = fneg half %1
   %3 = call half @llvm.copysign.f16(half %a, half %2)
   ret half %3
 }
 
 declare half @llvm.fabs.f16(half)
 

 ; RV64I-NEXT:    call __addsf3@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fabs_s:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fabs.s ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = call half @llvm.fabs.f16(half %1)
   %3 = fadd half %2, %1
   ret half %3
 }
 
 declare half @llvm.minnum.f16(half, half)
 

 ; RV64I-NEXT:    call fminf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fmin_s:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fmin.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.minnum.f16(half %a, half %b)
   ret half %1
 }
 
 declare half @llvm.maxnum.f16(half, half)
 
 define half @fmax_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fmax_s:

 ; RV64I-NEXT:    call fmaxf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fmax_s:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fmax.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.maxnum.f16(half %a, half %b)
   ret half %1
 }
 
 declare half @llvm.fma.f16(half, half, half)
 
 define half @fmadd_s(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fmadd_s:

 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fmadd_s:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa2
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECKIZFHMIN-NEXT:    fmadd.s ft0, ft2, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
   ret half %1
 }
 
 define half @fmsub_s(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fmsub_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmv.h.x ft0, zero

 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fmsub_s:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa2
+; CHECKIZFHMIN-NEXT:    fmv.w.x ft1, zero
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fneg.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECKIZFHMIN-NEXT:    fmadd.s ft0, ft2, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %negc = fsub half -0.0, %c_
   %1 = call half @llvm.fma.f16(half %a, half %b, half %negc)
   ret half %1
 }
 
 define half @fnmadd_s(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fnmadd_s:

 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s4, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fnmadd_s:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fmv.w.x ft1, zero
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, fa2
+; CHECKIZFHMIN-NEXT:    fadd.s ft1, ft2, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fneg.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fneg.s ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, fa1
+; CHECKIZFHMIN-NEXT:    fmadd.s ft0, ft0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %a_ = fadd half 0.0, %a
   %c_ = fadd half 0.0, %c
   %nega = fsub half -0.0, %a_
   %negc = fsub half -0.0, %c_
   %1 = call half @llvm.fma.f16(half %nega, half %b, half %negc)
   ret half %1
 }
 

 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s4, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fnmadd_s_2:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fmv.w.x ft1, zero
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, fa2
+; CHECKIZFHMIN-NEXT:    fadd.s ft1, ft2, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fneg.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fneg.s ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECKIZFHMIN-NEXT:    fmadd.s ft0, ft2, ft0, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %b_ = fadd half 0.0, %b
   %c_ = fadd half 0.0, %c
   %negb = fsub half -0.0, %b_
   %negc = fsub half -0.0, %c_
   %1 = call half @llvm.fma.f16(half %a, half %negb, half %negc)
   ret half %1
 }
 

 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fnmadd_s_3:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa2
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECKIZFHMIN-NEXT:    fmadd.s ft0, ft2, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fneg.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
   %neg = fneg half %1
   ret half %neg
 }
 
 
 define half @fnmadd_nsz(half %a, half %b, half %c) nounwind {
 ; RV32IZFH-LABEL: fnmadd_nsz:

 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fnmadd_nsz:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa2
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECKIZFHMIN-NEXT:    fmadd.s ft0, ft2, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fneg.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call nsz half @llvm.fma.f16(half %a, half %b, half %c)
   %neg = fneg nsz half %1
   ret half %neg
 }
 
 define half @fnmsub_s(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fnmsub_s:
 ; CHECKIZFH:       # %bb.0:

 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fnmsub_s:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fmv.w.x ft1, zero
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fneg.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa2
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, fa1
+; CHECKIZFHMIN-NEXT:    fmadd.s ft0, ft0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %a_ = fadd half 0.0, %a
   %nega = fsub half -0.0, %a_
   %1 = call half @llvm.fma.f16(half %nega, half %b, half %c)
   ret half %1
 }
 
 define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fnmsub_s_2:

 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fnmsub_s_2:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fmv.w.x ft1, zero
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fneg.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa2
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECKIZFHMIN-NEXT:    fmadd.s ft0, ft2, ft0, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %b_ = fadd half 0.0, %b
   %negb = fsub half -0.0, %b_
   %1 = call half @llvm.fma.f16(half %a, half %negb, half %c)
   ret half %1
 }
 
 define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fmadd_s_contract:

 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fmadd_s_contract:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fmul.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa2
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fmul contract half %a, %b
   %2 = fadd contract half %1, %c
   ret half %2
 }
 
 define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fmsub_s_contract:
 ; CHECKIZFH:       # %bb.0:

 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fmsub_s_contract:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa2
+; CHECKIZFHMIN-NEXT:    fmv.w.x ft1, zero
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECKIZFHMIN-NEXT:    fmul.s ft1, ft2, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fsub.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %1 = fmul contract half %a, %b
   %2 = fsub contract half %1, %c_
   ret half %2
 }
 
 define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fnmadd_s_contract:

 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fnmadd_s_contract:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fmv.w.x ft1, zero
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, fa1
+; CHECKIZFHMIN-NEXT:    fadd.s ft2, ft2, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft2, ft2
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft3, fa2
+; CHECKIZFHMIN-NEXT:    fadd.s ft1, ft3, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, ft2
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fmul.s ft0, ft0, ft2
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fneg.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fsub.s ft0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %a_ = fadd half 0.0, %a ; avoid negation using xor
   %b_ = fadd half 0.0, %b ; avoid negation using xor
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %1 = fmul contract half %a_, %b_
   %2 = fneg half %1
   %3 = fsub contract half %2, %c_
   ret half %3
 }

 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fnmsub_s_contract:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fmv.w.x ft1, zero
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, fa1
+; CHECKIZFHMIN-NEXT:    fadd.s ft1, ft2, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fmul.s ft0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa2
+; CHECKIZFHMIN-NEXT:    fsub.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %a_ = fadd half 0.0, %a ; avoid negation using xor
   %b_ = fadd half 0.0, %b ; avoid negation using xor
   %1 = fmul contract half %a_, %b_
   %2 = fsub contract half %c, %1
   ret half %2
 }

llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefix=RV32IZFHMIN %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefix=RV64IZFHMIN %s
 
 ; This file tests cases where simple floating point operations can be
 ; profitably handled though bit manipulation if a soft-float ABI is being used
 ; (e.g. fneg implemented by XORing the sign bit). This is typically handled in
 ; DAGCombiner::visitBITCAST, but this target-independent code may not trigger
 ; in cases where we perform custom legalisation (e.g. RV64F).
 
 define half @fneg(half %a) nounwind {

 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fneg:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    lui a1, 1048568
 ; RV64IZFH-NEXT:    xor a0, a0, a1
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: fneg:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a1, 1048568
+; RV32IZFHMIN-NEXT:    xor a0, a0, a1
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: fneg:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a1, 1048568
+; RV64IZFHMIN-NEXT:    xor a0, a0, a1
+; RV64IZFHMIN-NEXT:    ret
   %1 = fneg half %a
   ret half %1
 }
 
 declare half @llvm.fabs.f16(half)
 
 define half @fabs(half %a) nounwind {
 ; RV32I-LABEL: fabs:

 ; RV64I-NEXT:    srli a0, a0, 49
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fabs:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    slli a0, a0, 49
 ; RV64IZFH-NEXT:    srli a0, a0, 49
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: fabs:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    slli a0, a0, 17
+; RV32IZFHMIN-NEXT:    srli a0, a0, 17
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: fabs:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    slli a0, a0, 49
+; RV64IZFHMIN-NEXT:    srli a0, a0, 49
+; RV64IZFHMIN-NEXT:    ret
   %1 = call half @llvm.fabs.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.copysign.f16(half, half)
 
 ; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise
 ; operations if half precision floating point isn't supported. A combine could

 ;
 ; RV64IZFH-LABEL: fcopysign_fneg:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, a1
 ; RV64IZFH-NEXT:    fmv.h.x ft1, a0
 ; RV64IZFH-NEXT:    fsgnjn.h ft0, ft1, ft0
 ; RV64IZFH-NEXT:    fmv.x.h a0, ft0
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: fcopysign_fneg:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    fmv.h.x ft0, a0
+; RV32IZFHMIN-NEXT:    fmv.h.x ft1, a1
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; RV32IZFHMIN-NEXT:    fneg.s ft1, ft1
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; RV32IZFHMIN-NEXT:    fsh ft0, 8(sp)
+; RV32IZFHMIN-NEXT:    fsh ft1, 12(sp)
+; RV32IZFHMIN-NEXT:    lbu a0, 9(sp)
+; RV32IZFHMIN-NEXT:    lbu a1, 13(sp)
+; RV32IZFHMIN-NEXT:    andi a0, a0, 127
+; RV32IZFHMIN-NEXT:    andi a1, a1, 128
+; RV32IZFHMIN-NEXT:    or a0, a0, a1
+; RV32IZFHMIN-NEXT:    sb a0, 9(sp)
+; RV32IZFHMIN-NEXT:    flh ft0, 8(sp)
+; RV32IZFHMIN-NEXT:    fmv.x.h a0, ft0
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: fcopysign_fneg:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    fmv.h.x ft0, a0
+; RV64IZFHMIN-NEXT:    fmv.h.x ft1, a1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; RV64IZFHMIN-NEXT:    fneg.s ft1, ft1
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft1, ft1
+; RV64IZFHMIN-NEXT:    fsh ft0, 0(sp)
+; RV64IZFHMIN-NEXT:    fsh ft1, 8(sp)
+; RV64IZFHMIN-NEXT:    lbu a0, 1(sp)
+; RV64IZFHMIN-NEXT:    lbu a1, 9(sp)
+; RV64IZFHMIN-NEXT:    andi a0, a0, 127
+; RV64IZFHMIN-NEXT:    andi a1, a1, 128
+; RV64IZFHMIN-NEXT:    or a0, a0, a1
+; RV64IZFHMIN-NEXT:    sb a0, 1(sp)
+; RV64IZFHMIN-NEXT:    flh ft0, 0(sp)
+; RV64IZFHMIN-NEXT:    fmv.x.h a0, ft0
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = fneg half %b
   %2 = call half @llvm.copysign.f16(half %a, half %1)
   ret half %2
 }

llvm/test/CodeGen/RISCV/half-br-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFHMIN %s
 
 declare void @abort()
 declare void @exit(i32)
 declare half @dummy(half)
 
 define void @br_fcmp_false(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: br_fcmp_false:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:    li a0, 1
 ; RV64IZFH-NEXT:    bnez a0, .LBB0_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.then
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB0_2: # %if.else
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_false:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    li a0, 1
+; RV32IZFHMIN-NEXT:    bnez a0, .LBB0_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.then
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB0_2: # %if.else
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_false:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    li a0, 1
+; RV64IZFHMIN-NEXT:    bnez a0, .LBB0_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.then
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB0_2: # %if.else
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp false half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.then:
   ret void
 if.else:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    bnez a0, .LBB1_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB1_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_oeq:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV32IZFHMIN-NEXT:    feq.s a0, ft1, ft0
+; RV32IZFHMIN-NEXT:    bnez a0, .LBB1_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB1_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_oeq:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV64IZFHMIN-NEXT:    feq.s a0, ft1, ft0
+; RV64IZFHMIN-NEXT:    bnez a0, .LBB1_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB1_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp oeq half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    bnez a0, .LBB2_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB2_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_oeq_alt:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV32IZFHMIN-NEXT:    feq.s a0, ft1, ft0
+; RV32IZFHMIN-NEXT:    bnez a0, .LBB2_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB2_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_oeq_alt:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV64IZFHMIN-NEXT:    feq.s a0, ft1, ft0
+; RV64IZFHMIN-NEXT:    bnez a0, .LBB2_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB2_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp oeq half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.then:
   tail call void @abort()
   unreachable
 if.else:
   ret void
 }

 ; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
 ; RV64IZFH-NEXT:    bnez a0, .LBB3_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB3_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_ogt:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; RV32IZFHMIN-NEXT:    flt.s a0, ft1, ft0
+; RV32IZFHMIN-NEXT:    bnez a0, .LBB3_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB3_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_ogt:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; RV64IZFHMIN-NEXT:    flt.s a0, ft1, ft0
+; RV64IZFHMIN-NEXT:    bnez a0, .LBB3_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB3_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp ogt half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
 ; RV64IZFH-NEXT:    bnez a0, .LBB4_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB4_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_oge:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; RV32IZFHMIN-NEXT:    fle.s a0, ft1, ft0
+; RV32IZFHMIN-NEXT:    bnez a0, .LBB4_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB4_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_oge:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; RV64IZFHMIN-NEXT:    fle.s a0, ft1, ft0
+; RV64IZFHMIN-NEXT:    bnez a0, .LBB4_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB4_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp oge half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    bnez a0, .LBB5_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB5_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_olt:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft1, ft0
+; RV32IZFHMIN-NEXT:    bnez a0, .LBB5_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB5_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_olt:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft1, ft0
+; RV64IZFHMIN-NEXT:    bnez a0, .LBB5_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB5_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp olt half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    bnez a0, .LBB6_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB6_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_ole:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV32IZFHMIN-NEXT:    fle.s a0, ft1, ft0
+; RV32IZFHMIN-NEXT:    bnez a0, .LBB6_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB6_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_ole:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV64IZFHMIN-NEXT:    fle.s a0, ft1, ft0
+; RV64IZFHMIN-NEXT:    bnez a0, .LBB6_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB6_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp ole half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    or a0, a1, a0
 ; RV64IZFH-NEXT:    bnez a0, .LBB7_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB7_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_one:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft1, ft0
+; RV32IZFHMIN-NEXT:    flt.s a1, ft0, ft1
+; RV32IZFHMIN-NEXT:    or a0, a1, a0
+; RV32IZFHMIN-NEXT:    bnez a0, .LBB7_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB7_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_one:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft1, ft0
+; RV64IZFHMIN-NEXT:    flt.s a1, ft0, ft1
+; RV64IZFHMIN-NEXT:    or a0, a1, a0
+; RV64IZFHMIN-NEXT:    bnez a0, .LBB7_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB7_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp one half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    bnez a0, .LBB8_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB8_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_ord:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV32IZFHMIN-NEXT:    feq.s a0, ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV32IZFHMIN-NEXT:    and a0, a1, a0
+; RV32IZFHMIN-NEXT:    bnez a0, .LBB8_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB8_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_ord:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    feq.s a0, ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    and a0, a1, a0
+; RV64IZFHMIN-NEXT:    bnez a0, .LBB8_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB8_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp ord half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    or a0, a1, a0
 ; RV64IZFH-NEXT:    beqz a0, .LBB9_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB9_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_ueq:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft1, ft0
+; RV32IZFHMIN-NEXT:    flt.s a1, ft0, ft1
+; RV32IZFHMIN-NEXT:    or a0, a1, a0
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB9_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB9_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_ueq:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft1, ft0
+; RV64IZFHMIN-NEXT:    flt.s a1, ft0, ft1
+; RV64IZFHMIN-NEXT:    or a0, a1, a0
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB9_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB9_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp ueq half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    beqz a0, .LBB10_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB10_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_ugt:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV32IZFHMIN-NEXT:    fle.s a0, ft1, ft0
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB10_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB10_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_ugt:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV64IZFHMIN-NEXT:    fle.s a0, ft1, ft0
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB10_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB10_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp ugt half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    beqz a0, .LBB11_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB11_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_uge:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft1, ft0
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB11_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB11_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_uge:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft1, ft0
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB11_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB11_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp uge half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
 ; RV64IZFH-NEXT:    beqz a0, .LBB12_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB12_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_ult:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; RV32IZFHMIN-NEXT:    fle.s a0, ft1, ft0
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB12_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB12_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_ult:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; RV64IZFHMIN-NEXT:    fle.s a0, ft1, ft0
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB12_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB12_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp ult half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
 ; RV64IZFH-NEXT:    beqz a0, .LBB13_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB13_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_ule:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; RV32IZFHMIN-NEXT:    flt.s a0, ft1, ft0
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB13_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB13_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_ule:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; RV64IZFHMIN-NEXT:    flt.s a0, ft1, ft0
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB13_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB13_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp ule half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    beqz a0, .LBB14_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB14_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_une:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV32IZFHMIN-NEXT:    feq.s a0, ft1, ft0
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB14_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB14_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_une:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV64IZFHMIN-NEXT:    feq.s a0, ft1, ft0
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB14_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB14_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp une half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    beqz a0, .LBB15_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB15_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_uno:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV32IZFHMIN-NEXT:    feq.s a0, ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV32IZFHMIN-NEXT:    and a0, a1, a0
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB15_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB15_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_uno:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    feq.s a0, ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    and a0, a1, a0
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB15_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB15_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp uno half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    li a0, 1
 ; RV64IZFH-NEXT:    bnez a0, .LBB16_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB16_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
+;
+; RV32IZFHMIN-LABEL: br_fcmp_true:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    li a0, 1
+; RV32IZFHMIN-NEXT:    bnez a0, .LBB16_2
+; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZFHMIN-NEXT:    ret
+; RV32IZFHMIN-NEXT:  .LBB16_2: # %if.then
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    call abort@plt
+;
+; RV64IZFHMIN-LABEL: br_fcmp_true:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    li a0, 1
+; RV64IZFHMIN-NEXT:    bnez a0, .LBB16_2
+; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZFHMIN-NEXT:    ret
+; RV64IZFHMIN-NEXT:  .LBB16_2: # %if.then
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    call abort@plt
   %1 = fcmp true half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

llvm/test/CodeGen/RISCV/half-convert-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32d -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IDZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64d -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IDZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32f -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefixes=CHECK32-IZFHMIN,RV32IFZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi lp64f -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefixes=CHECK64-IZFHMIN,RV64IFZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32d -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefixes=CHECK32-IZFHMIN,RV32IDZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi lp64d -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefixes=CHECK64-IZFHMIN,RV64IDZFHMIN %s
 
 ; NOTE: The rounding mode metadata does not effect which instruction is
 ; selected. Dynamic rounding mode is always used for operations that
 ; support rounding mode.
 
 define i16 @fcvt_si_h(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_si_h:
 ; RV32IZFH:       # %bb.0:

 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_si_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_si_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_si_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call i16 @llvm.experimental.constrained.fptosi.i16.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i16 %1
 }
 declare i16 @llvm.experimental.constrained.fptosi.i16.f16(half, metadata)
 
 define i16 @fcvt_ui_h(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_ui_h:
 ; RV32IZFH:       # %bb.0:

 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_ui_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_ui_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_ui_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call i16 @llvm.experimental.constrained.fptoui.i16.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i16 %1
 }
 declare i16 @llvm.experimental.constrained.fptoui.i16.f16(half, metadata)
 
 define i32 @fcvt_w_h(half %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_w_h:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_w_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_w_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_w_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_w_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptosi.i32.f16(half, metadata)
 
 define i32 @fcvt_wu_h(half %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_wu_h:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_wu_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_wu_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_wu_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_wu_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptoui.i32.f16(half, metadata)
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 ; FIXME: We should not have an fcvt.wu.h and an fcvt.lu.h.

 ; RV64IDZFH-LABEL: fcvt_wu_h_multiple_use:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    bnez a0, .LBB4_2
 ; RV64IDZFH-NEXT:  # %bb.1:
 ; RV64IDZFH-NEXT:    li a0, 1
 ; RV64IDZFH-NEXT:  .LBB4_2:
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_wu_h_multiple_use:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    bnez a0, .LBB4_2
+; CHECK32-IZFHMIN-NEXT:  # %bb.1:
+; CHECK32-IZFHMIN-NEXT:    li a0, 1
+; CHECK32-IZFHMIN-NEXT:  .LBB4_2:
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_wu_h_multiple_use:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    bnez a0, .LBB4_2
+; CHECK64-IZFHMIN-NEXT:  # %bb.1:
+; CHECK64-IZFHMIN-NEXT:    li a0, 1
+; CHECK64-IZFHMIN-NEXT:  .LBB4_2:
+; CHECK64-IZFHMIN-NEXT:    ret
   %a = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %x, metadata !"fpexcept.strict") strictfp
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i64 @fcvt_l_h(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_l_h:

 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_l_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_l_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZFHMIN-NEXT:    call __fixhfdi@plt
+; CHECK32-IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_l_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call i64 @llvm.experimental.constrained.fptosi.i64.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i64 %1
 }
 declare i64 @llvm.experimental.constrained.fptosi.i64.f16(half, metadata)
 
 define i64 @fcvt_lu_h(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_lu_h:
 ; RV32IZFH:       # %bb.0:

 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_lu_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_lu_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZFHMIN-NEXT:    call __fixunshfdi@plt
+; CHECK32-IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_lu_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call i64 @llvm.experimental.constrained.fptoui.i64.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i64 %1
 }
 declare i64 @llvm.experimental.constrained.fptoui.i64.f16(half, metadata)
 
 define half @fcvt_h_si(i16 %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_h_si:
 ; RV32IZFH:       # %bb.0:

 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_si:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    slli a0, a0, 48
 ; RV64IDZFH-NEXT:    srai a0, a0, 48
 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_si:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    slli a0, a0, 16
+; CHECK32-IZFHMIN-NEXT:    srai a0, a0, 16
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.w ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_si:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 48
+; CHECK64-IZFHMIN-NEXT:    srai a0, a0, 48
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.sitofp.f16.i16(i16, metadata, metadata)
 
 define half @fcvt_h_si_signext(i16 signext %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_h_si_signext:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_si_signext:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_si_signext:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_si_signext:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.w ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_si_signext:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fcvt_h_ui(i16 %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_h_ui:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    slli a0, a0, 16

 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_ui:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    slli a0, a0, 48
 ; RV64IDZFH-NEXT:    srli a0, a0, 48
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_ui:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    slli a0, a0, 16
+; CHECK32-IZFHMIN-NEXT:    srli a0, a0, 16
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_ui:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 48
+; CHECK64-IZFHMIN-NEXT:    srli a0, a0, 48
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.uitofp.f16.i16(i16, metadata, metadata)
 
 define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_h_ui_zeroext:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.wu fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_ui_zeroext:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_ui_zeroext:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_ui_zeroext:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fcvt_h_w(i32 %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_h_w:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_w:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_w:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.w ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_w:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    sext.w a0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.sitofp.f16.i32(i32, metadata, metadata)
 
 define half @fcvt_h_w_load(i32* %p) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_h_w_load:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    lw a0, 0(a0)
 ; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_w_load:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    lw a0, 0(a0)
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w_load:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    lw a0, 0(a0)
 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_w_load:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    lw a0, 0(a0)
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.w ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_w_load:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    lw a0, 0(a0)
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %a = load i32, i32* %p
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fcvt_h_wu(i32 %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_h_wu:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.wu fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_wu:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_wu:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_wu:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_wu:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 32
+; CHECK64-IZFHMIN-NEXT:    srli a0, a0, 32
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.uitofp.f16.i32(i32, metadata, metadata)
 
 define half @fcvt_h_wu_load(i32* %p) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_h_wu_load:
 ; RV32IZFH:       # %bb.0:

 ; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_wu_load:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    lwu a0, 0(a0)
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_wu_load:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    lw a0, 0(a0)
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_wu_load:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    lwu a0, 0(a0)
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %a = load i32, i32* %p
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fcvt_h_l(i64 %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_h_l:
 ; RV32IZFH:       # %bb.0:

 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_l:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.l fa0, a0
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_l:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZFHMIN-NEXT:    call __floatdihf@plt
+; CHECK32-IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_l:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.sitofp.f16.i64(i64, metadata, metadata)
 
 define half @fcvt_h_lu(i64 %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_h_lu:
 ; RV32IZFH:       # %bb.0:

 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_lu:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.lu fa0, a0
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_lu:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZFHMIN-NEXT:    call __floatundihf@plt
+; CHECK32-IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_lu:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.uitofp.f16.i64(i64, metadata, metadata)
 
 define half @fcvt_h_s(float %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_h_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.s fa0, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_s:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_s:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_s:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_s:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fptrunc.f16.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret half %1
 }
 declare half @llvm.experimental.constrained.fptrunc.f16.f32(float, metadata, metadata)
 
 define float @fcvt_s_h(half %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_s_h:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.s.h fa0, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_s_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_s_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_s_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_s_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fpext.f32.f16(half %a, metadata !"fpexcept.strict")
   ret float %1
 }
 declare float @llvm.experimental.constrained.fpext.f32.f16(half, metadata)
 
 define half @fcvt_h_d(double %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_h_d:
 ; RV32IZFH:       # %bb.0:

 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.d fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_d:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.d fa0, fa0
 ; RV64IDZFH-NEXT:    ret
+;
+; RV32IFZFHMIN-LABEL: fcvt_h_d:
+; RV32IFZFHMIN:       # %bb.0:
+; RV32IFZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IFZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFZFHMIN-NEXT:    call __truncdfhf2@plt
+; RV32IFZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IFZFHMIN-NEXT:    ret
+;
+; RV64IFZFHMIN-LABEL: fcvt_h_d:
+; RV64IFZFHMIN:       # %bb.0:
+; RV64IFZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IFZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFZFHMIN-NEXT:    call __truncdfhf2@plt
+; RV64IFZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IFZFHMIN-NEXT:    ret
+;
+; RV32IDZFHMIN-LABEL: fcvt_h_d:
+; RV32IDZFHMIN:       # %bb.0:
+; RV32IDZFHMIN-NEXT:    fcvt.h.d fa0, fa0
+; RV32IDZFHMIN-NEXT:    ret
+;
+; RV64IDZFHMIN-LABEL: fcvt_h_d:
+; RV64IDZFHMIN:       # %bb.0:
+; RV64IDZFHMIN-NEXT:    fcvt.h.d fa0, fa0
+; RV64IDZFHMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fptrunc.f16.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret half %1
 }
 declare half @llvm.experimental.constrained.fptrunc.f16.f64(double, metadata, metadata)
 
 define double @fcvt_d_h(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_d_h:
 ; RV32IZFH:       # %bb.0:

 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.d.h fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_d_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.d.h fa0, fa0
 ; RV64IDZFH-NEXT:    ret
+;
+; RV32IFZFHMIN-LABEL: fcvt_d_h:
+; RV32IFZFHMIN:       # %bb.0:
+; RV32IFZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IFZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IFZFHMIN-NEXT:    call __extendsfdf2@plt
+; RV32IFZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IFZFHMIN-NEXT:    ret
+;
+; RV64IFZFHMIN-LABEL: fcvt_d_h:
+; RV64IFZFHMIN:       # %bb.0:
+; RV64IFZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IFZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IFZFHMIN-NEXT:    call __extendsfdf2@plt
+; RV64IFZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IFZFHMIN-NEXT:    ret
+;
+; RV32IDZFHMIN-LABEL: fcvt_d_h:
+; RV32IDZFHMIN:       # %bb.0:
+; RV32IDZFHMIN-NEXT:    fcvt.d.h fa0, fa0
+; RV32IDZFHMIN-NEXT:    ret
+;
+; RV64IDZFHMIN-LABEL: fcvt_d_h:
+; RV64IDZFHMIN:       # %bb.0:
+; RV64IDZFHMIN-NEXT:    fcvt.d.h fa0, fa0
+; RV64IDZFHMIN-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.fpext.f64.f16(half %a, metadata !"fpexcept.strict")
   ret double %1
 }
 declare double @llvm.experimental.constrained.fpext.f64.f16(half, metadata)
 
 ; Make sure we select W version of addi on RV64.
 define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) {
 ; RV32IZFH-LABEL: fcvt_h_w_demanded_bits:

 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    addiw a0, a0, 1
 ; RV64IDZFH-NEXT:    fcvt.h.w ft0, a0
 ; RV64IDZFH-NEXT:    fsh ft0, 0(a1)
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_w_demanded_bits:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    addi a0, a0, 1
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.w ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK32-IZFHMIN-NEXT:    fsh ft0, 0(a1)
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_w_demanded_bits:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    addiw a0, a0, 1
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK64-IZFHMIN-NEXT:    fsh ft0, 0(a1)
+; CHECK64-IZFHMIN-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   store half %4, half* %1, align 2
   ret i32 %3
 }
 
 ; Make sure we select W version of addi on RV64.
 define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) {

 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    addiw a0, a0, 1
 ; RV64IDZFH-NEXT:    fcvt.h.wu ft0, a0
 ; RV64IDZFH-NEXT:    fsh ft0, 0(a1)
 ; RV64IDZFH-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_wu_demanded_bits:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    addi a0, a0, 1
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK32-IZFHMIN-NEXT:    fsh ft0, 0(a1)
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_wu_demanded_bits:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    addiw a0, a0, 1
+; CHECK64-IZFHMIN-NEXT:    slli a2, a0, 32
+; CHECK64-IZFHMIN-NEXT:    srli a2, a2, 32
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu ft0, a2
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK64-IZFHMIN-NEXT:    fsh ft0, 0(a1)
+; CHECK64-IZFHMIN-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   store half %4, half* %1, align 2
   ret i32 %3
 }

llvm/test/CodeGen/RISCV/half-convert.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32d < %s | FileCheck -check-prefix=RV32IDZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64d < %s | FileCheck -check-prefix=RV64IDZFH %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECK32-IZFHMIN,RV32IFZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECK64-IZFHMIN,RV64IFZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32d < %s | FileCheck -check-prefixes=CHECK32-IZFHMIN,RV32IDZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi lp64d < %s | FileCheck -check-prefixes=CHECK64-IZFHMIN,RV64IDZFHMIN %s
 
 define i16 @fcvt_si_h(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_si_h:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_si_h:

 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call __fixsfdi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_si_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_si_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = fptosi half %a to i16
   ret i16 %1
 }
 
 define i16 @fcvt_si_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_si_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI1_0)

 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_si_h_sat:
+; CHECK32-IZFHMIN:       # %bb.0: # %start
+; CHECK32-IZFHMIN-NEXT:    lui a0, %hi(.LCPI1_0)
+; CHECK32-IZFHMIN-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
+; CHECK32-IZFHMIN-NEXT:    lui a0, %hi(.LCPI1_1)
+; CHECK32-IZFHMIN-NEXT:    flw ft1, %lo(.LCPI1_1)(a0)
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECK32-IZFHMIN-NEXT:    fmax.s ft0, ft2, ft0
+; CHECK32-IZFHMIN-NEXT:    fmin.s ft0, ft0, ft1
+; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    feq.s a1, ft2, ft2
+; CHECK32-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK32-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK32-IZFHMIN-NEXT:    and a0, a1, a0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_si_h_sat:
+; CHECK64-IZFHMIN:       # %bb.0: # %start
+; CHECK64-IZFHMIN-NEXT:    lui a0, %hi(.LCPI1_0)
+; CHECK64-IZFHMIN-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
+; CHECK64-IZFHMIN-NEXT:    lui a0, %hi(.LCPI1_1)
+; CHECK64-IZFHMIN-NEXT:    flw ft1, %lo(.LCPI1_1)(a0)
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECK64-IZFHMIN-NEXT:    fmax.s ft0, ft2, ft0
+; CHECK64-IZFHMIN-NEXT:    fmin.s ft0, ft0, ft1
+; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    feq.s a1, ft2, ft2
+; CHECK64-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK64-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK64-IZFHMIN-NEXT:    and a0, a1, a0
+; CHECK64-IZFHMIN-NEXT:    ret
 start:
   %0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a)
   ret i16 %0
 }
 declare i16 @llvm.fptosi.sat.i16.f16(half)
 
 define i16 @fcvt_ui_h(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_ui_h:

 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call __fixunssfdi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_ui_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_ui_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = fptoui half %a to i16
   ret i16 %1
 }
 
 define i16 @fcvt_ui_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_ui_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI3_0)

 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_ui_h_sat:
+; CHECK32-IZFHMIN:       # %bb.0: # %start
+; CHECK32-IZFHMIN-NEXT:    lui a0, %hi(.LCPI3_0)
+; CHECK32-IZFHMIN-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECK32-IZFHMIN-NEXT:    fmv.w.x ft2, zero
+; CHECK32-IZFHMIN-NEXT:    fmax.s ft1, ft1, ft2
+; CHECK32-IZFHMIN-NEXT:    fmin.s ft0, ft1, ft0
+; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_ui_h_sat:
+; CHECK64-IZFHMIN:       # %bb.0: # %start
+; CHECK64-IZFHMIN-NEXT:    lui a0, %hi(.LCPI3_0)
+; CHECK64-IZFHMIN-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECK64-IZFHMIN-NEXT:    fmv.w.x ft2, zero
+; CHECK64-IZFHMIN-NEXT:    fmax.s ft1, ft1, ft2
+; CHECK64-IZFHMIN-NEXT:    fmin.s ft0, ft1, ft0
+; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
 start:
   %0 = tail call i16 @llvm.fptoui.sat.i16.f16(half %a)
   ret i16 %0
 }
 declare i16 @llvm.fptoui.sat.i16.f16(half)
 
 define i32 @fcvt_w_h(half %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_w_h:

 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call __fixsfdi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_w_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_w_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = fptosi half %a to i32
   ret i32 %1
 }
 
 define i32 @fcvt_w_h_sat(half %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_w_h_sat:
 ; CHECKIZFH:       # %bb.0: # %start
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz

 ; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_w_h_sat:
+; CHECK32-IZFHMIN:       # %bb.0: # %start
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECK32-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK32-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK32-IZFHMIN-NEXT:    and a0, a1, a0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_w_h_sat:
+; CHECK64-IZFHMIN:       # %bb.0: # %start
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECK64-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK64-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK64-IZFHMIN-NEXT:    and a0, a1, a0
+; CHECK64-IZFHMIN-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %0
 }
 declare i32 @llvm.fptosi.sat.i32.f16(half)
 
 define i32 @fcvt_wu_h(half %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_wu_h:

 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call __fixunssfdi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_wu_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_wu_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = fptoui half %a to i32
   ret i32 %1
 }
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) nounwind {
 ; CHECKIZFH-LABEL: fcvt_wu_h_multiple_use:

 ; RV64I-NEXT:    call __fixunssfdi@plt
 ; RV64I-NEXT:    bnez a0, .LBB7_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:  .LBB7_2:
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_wu_h_multiple_use:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    bnez a0, .LBB7_2
+; CHECK32-IZFHMIN-NEXT:  # %bb.1:
+; CHECK32-IZFHMIN-NEXT:    li a0, 1
+; CHECK32-IZFHMIN-NEXT:  .LBB7_2:
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_wu_h_multiple_use:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    bnez a0, .LBB7_2
+; CHECK64-IZFHMIN-NEXT:  # %bb.1:
+; CHECK64-IZFHMIN-NEXT:    li a0, 1
+; CHECK64-IZFHMIN-NEXT:  .LBB7_2:
+; CHECK64-IZFHMIN-NEXT:    ret
   %a = fptoui half %x to i32
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i32 @fcvt_wu_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_wu_h_sat:

 ; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:  .LBB8_3: # %start
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_wu_h_sat:
+; CHECK32-IZFHMIN:       # %bb.0: # %start
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECK32-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK32-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK32-IZFHMIN-NEXT:    and a0, a1, a0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_wu_h_sat:
+; CHECK64-IZFHMIN:       # %bb.0: # %start
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECK64-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK64-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK64-IZFHMIN-NEXT:    and a0, a0, a1
+; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 32
+; CHECK64-IZFHMIN-NEXT:    srli a0, a0, 32
+; CHECK64-IZFHMIN-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %0
 }
 declare i32 @llvm.fptoui.sat.i32.f16(half)
 
 define i64 @fcvt_l_h(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_l_h:

 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call __fixsfdi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_l_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZFHMIN-NEXT:    call __fixhfdi@plt
+; CHECK32-IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_l_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = fptosi half %a to i64
   ret i64 %1
 }
 
 define i64 @fcvt_l_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_l_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    addi sp, sp, -16

 ; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; RV32IFZFHMIN-LABEL: fcvt_l_h_sat:
+; RV32IFZFHMIN:       # %bb.0: # %start
+; RV32IFZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IFZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IFZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IFZFHMIN-NEXT:    lui a0, %hi(.LCPI10_0)
+; RV32IFZFHMIN-NEXT:    flw ft0, %lo(.LCPI10_0)(a0)
+; RV32IFZFHMIN-NEXT:    fcvt.s.h fs0, fa0
+; RV32IFZFHMIN-NEXT:    fle.s s0, ft0, fs0
+; RV32IFZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IFZFHMIN-NEXT:    call __fixsfdi@plt
+; RV32IFZFHMIN-NEXT:    lui a3, 524288
+; RV32IFZFHMIN-NEXT:    bnez s0, .LBB10_2
+; RV32IFZFHMIN-NEXT:  # %bb.1: # %start
+; RV32IFZFHMIN-NEXT:    lui a1, 524288
+; RV32IFZFHMIN-NEXT:  .LBB10_2: # %start
+; RV32IFZFHMIN-NEXT:    lui a2, %hi(.LCPI10_1)
+; RV32IFZFHMIN-NEXT:    flw ft0, %lo(.LCPI10_1)(a2)
+; RV32IFZFHMIN-NEXT:    flt.s a2, ft0, fs0
+; RV32IFZFHMIN-NEXT:    beqz a2, .LBB10_4
+; RV32IFZFHMIN-NEXT:  # %bb.3:
+; RV32IFZFHMIN-NEXT:    addi a1, a3, -1
+; RV32IFZFHMIN-NEXT:  .LBB10_4: # %start
+; RV32IFZFHMIN-NEXT:    feq.s a3, fs0, fs0
+; RV32IFZFHMIN-NEXT:    seqz a3, a3
+; RV32IFZFHMIN-NEXT:    addi a3, a3, -1
+; RV32IFZFHMIN-NEXT:    and a1, a3, a1
+; RV32IFZFHMIN-NEXT:    neg a2, a2
+; RV32IFZFHMIN-NEXT:    neg a4, s0
+; RV32IFZFHMIN-NEXT:    and a0, a4, a0
+; RV32IFZFHMIN-NEXT:    or a0, a2, a0
+; RV32IFZFHMIN-NEXT:    and a0, a3, a0
+; RV32IFZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IFZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IFZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IFZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_l_h_sat:
+; CHECK64-IZFHMIN:       # %bb.0: # %start
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECK64-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK64-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK64-IZFHMIN-NEXT:    and a0, a1, a0
+; CHECK64-IZFHMIN-NEXT:    ret
+;
+; RV32IDZFHMIN-LABEL: fcvt_l_h_sat:
+; RV32IDZFHMIN:       # %bb.0: # %start
+; RV32IDZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IDZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IDZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IDZFHMIN-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
+; RV32IDZFHMIN-NEXT:    lui a0, %hi(.LCPI10_0)
+; RV32IDZFHMIN-NEXT:    flw ft0, %lo(.LCPI10_0)(a0)
+; RV32IDZFHMIN-NEXT:    fcvt.s.h fs0, fa0
+; RV32IDZFHMIN-NEXT:    fle.s s0, ft0, fs0
+; RV32IDZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IDZFHMIN-NEXT:    call __fixsfdi@plt
+; RV32IDZFHMIN-NEXT:    lui a3, 524288
+; RV32IDZFHMIN-NEXT:    bnez s0, .LBB10_2
+; RV32IDZFHMIN-NEXT:  # %bb.1: # %start
+; RV32IDZFHMIN-NEXT:    lui a1, 524288
+; RV32IDZFHMIN-NEXT:  .LBB10_2: # %start
+; RV32IDZFHMIN-NEXT:    lui a2, %hi(.LCPI10_1)
+; RV32IDZFHMIN-NEXT:    flw ft0, %lo(.LCPI10_1)(a2)
+; RV32IDZFHMIN-NEXT:    flt.s a2, ft0, fs0
+; RV32IDZFHMIN-NEXT:    beqz a2, .LBB10_4
+; RV32IDZFHMIN-NEXT:  # %bb.3:
+; RV32IDZFHMIN-NEXT:    addi a1, a3, -1
+; RV32IDZFHMIN-NEXT:  .LBB10_4: # %start
+; RV32IDZFHMIN-NEXT:    feq.s a3, fs0, fs0
+; RV32IDZFHMIN-NEXT:    seqz a3, a3
+; RV32IDZFHMIN-NEXT:    addi a3, a3, -1
+; RV32IDZFHMIN-NEXT:    and a1, a3, a1
+; RV32IDZFHMIN-NEXT:    neg a2, a2
+; RV32IDZFHMIN-NEXT:    neg a4, s0
+; RV32IDZFHMIN-NEXT:    and a0, a4, a0
+; RV32IDZFHMIN-NEXT:    or a0, a2, a0
+; RV32IDZFHMIN-NEXT:    and a0, a3, a0
+; RV32IDZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IDZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IDZFHMIN-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
+; RV32IDZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IDZFHMIN-NEXT:    ret
 start:
   %0 = tail call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %0
 }
 declare i64 @llvm.fptosi.sat.i64.f16(half)
 
 define i64 @fcvt_lu_h(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_lu_h:

 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call __fixunssfdi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_lu_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZFHMIN-NEXT:    call __fixunshfdi@plt
+; CHECK32-IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_lu_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = fptoui half %a to i64
   ret i64 %1
 }
 
 define i64 @fcvt_lu_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_lu_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    addi sp, sp, -16

 ; RV64I-NEXT:    and a0, s2, a0
 ; RV64I-NEXT:    or a0, s1, a0
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_lu_h_sat:
+; CHECK32-IZFHMIN:       # %bb.0: # %start
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; CHECK32-IZFHMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; CHECK32-IZFHMIN-NEXT:    lui a0, %hi(.LCPI12_0)
+; CHECK32-IZFHMIN-NEXT:    flw ft0, %lo(.LCPI12_0)(a0)
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; CHECK32-IZFHMIN-NEXT:    flt.s a0, ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    neg s0, a0
+; CHECK32-IZFHMIN-NEXT:    fmv.w.x ft0, zero
+; CHECK32-IZFHMIN-NEXT:    fle.s a0, ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    neg s1, a0
+; CHECK32-IZFHMIN-NEXT:    call __fixunssfdi@plt
+; CHECK32-IZFHMIN-NEXT:    and a0, s1, a0
+; CHECK32-IZFHMIN-NEXT:    or a0, s0, a0
+; CHECK32-IZFHMIN-NEXT:    and a1, s1, a1
+; CHECK32-IZFHMIN-NEXT:    or a1, s0, a1
+; CHECK32-IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; CHECK32-IZFHMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_lu_h_sat:
+; CHECK64-IZFHMIN:       # %bb.0: # %start
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECK64-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK64-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK64-IZFHMIN-NEXT:    and a0, a1, a0
+; CHECK64-IZFHMIN-NEXT:    ret
 start:
   %0 = tail call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %0
 }
 declare i64 @llvm.fptoui.sat.i64.f16(half)
 
 define half @fcvt_h_si(i16 %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_si:

 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srai a0, a0, 48
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_si:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    slli a0, a0, 16
+; CHECK32-IZFHMIN-NEXT:    srai a0, a0, 16
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.w ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_si:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 48
+; CHECK64-IZFHMIN-NEXT:    srai a0, a0, 48
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = sitofp i16 %a to half
   ret half %1
 }
 
 define half @fcvt_h_si_signext(i16 signext %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_h_si_signext:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_si_signext:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.w ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_si_signext:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = sitofp i16 %a to half
   ret half %1
 }
 
 define half @fcvt_h_ui(i16 %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_ui:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    slli a0, a0, 16

 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __floatunsisf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_ui:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    slli a0, a0, 16
+; CHECK32-IZFHMIN-NEXT:    srli a0, a0, 16
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_ui:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 48
+; CHECK64-IZFHMIN-NEXT:    srli a0, a0, 48
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = uitofp i16 %a to half
   ret half %1
 }
 
 define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_h_ui_zeroext:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.wu fa0, a0

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatunsisf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_ui_zeroext:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_ui_zeroext:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = uitofp i16 %a to half
   ret half %1
 }
 
 define half @fcvt_h_w(i32 %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_h_w:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0

 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_w:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.w ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_w:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    sext.w a0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = sitofp i32 %a to half
   ret half %1
 }
 
 define half @fcvt_h_w_load(i32* %p) nounwind {
 ; CHECKIZFH-LABEL: fcvt_h_w_load:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    lw a0, 0(a0)

 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_w_load:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    lw a0, 0(a0)
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.w ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_w_load:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    lw a0, 0(a0)
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %a = load i32, i32* %p
   %1 = sitofp i32 %a to half
   ret half %1
 }
 
 define half @fcvt_h_wu(i32 %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_h_wu:
 ; CHECKIZFH:       # %bb.0:

 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    call __floatunsisf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_wu:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_wu:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 32
+; CHECK64-IZFHMIN-NEXT:    srli a0, a0, 32
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = uitofp i32 %a to half
   ret half %1
 }
 
 define half @fcvt_h_wu_load(i32* %p) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_wu_load:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    lw a0, 0(a0)

 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    call __floatunsisf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_wu_load:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    lw a0, 0(a0)
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_wu_load:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    lwu a0, 0(a0)
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %a = load i32, i32* %p
   %1 = uitofp i32 %a to half
   ret half %1
 }
 
 define half @fcvt_h_l(i64 %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_l:
 ; RV32IZFH:       # %bb.0:

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatdisf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_l:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZFHMIN-NEXT:    call __floatdihf@plt
+; CHECK32-IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_l:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = sitofp i64 %a to half
   ret half %1
 }
 
 define half @fcvt_h_lu(i64 %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_lu:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatundisf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_lu:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZFHMIN-NEXT:    call __floatundihf@plt
+; CHECK32-IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_lu:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = uitofp i64 %a to half
   ret half %1
 }
 
 define half @fcvt_h_s(float %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_h_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.s fa0, fa0

 ; RV64I-LABEL: fcvt_h_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_s:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_s:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = fptrunc float %a to half
   ret half %1
 }
 
 define float @fcvt_s_h(half %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_s_h:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.s.h fa0, fa0

 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_s_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_s_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = fpext half %a to float
   ret float %1
 }
 
 define half @fcvt_h_d(double %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_d:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16

 ; RV64I-LABEL: fcvt_h_d:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __truncdfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32IFZFHMIN-LABEL: fcvt_h_d:
+; RV32IFZFHMIN:       # %bb.0:
+; RV32IFZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IFZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFZFHMIN-NEXT:    call __truncdfhf2@plt
+; RV32IFZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IFZFHMIN-NEXT:    ret
+;
+; RV64IFZFHMIN-LABEL: fcvt_h_d:
+; RV64IFZFHMIN:       # %bb.0:
+; RV64IFZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IFZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFZFHMIN-NEXT:    call __truncdfhf2@plt
+; RV64IFZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IFZFHMIN-NEXT:    ret
+;
+; RV32IDZFHMIN-LABEL: fcvt_h_d:
+; RV32IDZFHMIN:       # %bb.0:
+; RV32IDZFHMIN-NEXT:    fcvt.h.d fa0, fa0
+; RV32IDZFHMIN-NEXT:    ret
+;
+; RV64IDZFHMIN-LABEL: fcvt_h_d:
+; RV64IDZFHMIN:       # %bb.0:
+; RV64IDZFHMIN-NEXT:    fcvt.h.d fa0, fa0
+; RV64IDZFHMIN-NEXT:    ret
   %1 = fptrunc double %a to half
   ret half %1
 }
 
 define double @fcvt_d_h(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_d_h:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16

 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    call __extendsfdf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32IFZFHMIN-LABEL: fcvt_d_h:
+; RV32IFZFHMIN:       # %bb.0:
+; RV32IFZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IFZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IFZFHMIN-NEXT:    call __extendsfdf2@plt
+; RV32IFZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IFZFHMIN-NEXT:    ret
+;
+; RV64IFZFHMIN-LABEL: fcvt_d_h:
+; RV64IFZFHMIN:       # %bb.0:
+; RV64IFZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IFZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IFZFHMIN-NEXT:    call __extendsfdf2@plt
+; RV64IFZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IFZFHMIN-NEXT:    ret
+;
+; RV32IDZFHMIN-LABEL: fcvt_d_h:
+; RV32IDZFHMIN:       # %bb.0:
+; RV32IDZFHMIN-NEXT:    fcvt.d.h fa0, fa0
+; RV32IDZFHMIN-NEXT:    ret
+;
+; RV64IDZFHMIN-LABEL: fcvt_d_h:
+; RV64IDZFHMIN:       # %bb.0:
+; RV64IDZFHMIN-NEXT:    fcvt.d.h fa0, fa0
+; RV64IDZFHMIN-NEXT:    ret
   %1 = fpext half %a to double
   ret double %1
 }
 
 define half @bitcast_h_i16(i16 %a) nounwind {
 ; CHECKIZFH-LABEL: bitcast_h_i16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmv.h.x fa0, a0

 ;
 ; RV32I-LABEL: bitcast_h_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: bitcast_h_i16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: bitcast_h_i16:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fmv.h.x fa0, a0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: bitcast_h_i16:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fmv.h.x fa0, a0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = bitcast i16 %a to half
   ret half %1
 }
 
 define i16 @bitcast_i16_h(half %a) nounwind {
 ; CHECKIZFH-LABEL: bitcast_i16_h:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmv.x.h a0, fa0

 ;
 ; RV32I-LABEL: bitcast_i16_h:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: bitcast_i16_h:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: bitcast_i16_h:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fmv.x.h a0, fa0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: bitcast_i16_h:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fmv.x.h a0, fa0
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = bitcast half %a to i16
   ret i16 %1
 }
 
 ; Make sure we select W version of addi on RV64.
 define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV32IZFH:       # %bb.0:

 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    sh a0, 0(s0)
 ; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_w_demanded_bits:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    addi a0, a0, 1
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.w ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK32-IZFHMIN-NEXT:    fsh ft0, 0(a1)
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_w_demanded_bits:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    addiw a0, a0, 1
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK64-IZFHMIN-NEXT:    fsh ft0, 0(a1)
+; CHECK64-IZFHMIN-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = sitofp i32 %3 to half
   store half %4, half* %1, align 2
   ret i32 %3
 }
 
 ; Make sure we select W version of addi on RV64.
 define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) nounwind {

 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    sh a0, 0(s0)
 ; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_h_wu_demanded_bits:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    addi a0, a0, 1
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu ft0, a0
+; CHECK32-IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK32-IZFHMIN-NEXT:    fsh ft0, 0(a1)
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_h_wu_demanded_bits:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    addiw a0, a0, 1
+; CHECK64-IZFHMIN-NEXT:    slli a2, a0, 32
+; CHECK64-IZFHMIN-NEXT:    srli a2, a2, 32
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu ft0, a2
+; CHECK64-IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECK64-IZFHMIN-NEXT:    fsh ft0, 0(a1)
+; CHECK64-IZFHMIN-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = uitofp i32 %3 to half
   store half %4, half* %1, align 2
   ret i32 %3
 }
 
 define signext i16 @fcvt_w_s_i16(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_w_s_i16:

 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call __fixsfdi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_w_s_i16:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_w_s_i16:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = fptosi half %a to i16
   ret i16 %1
 }
 
 define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_w_s_sat_i16:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI32_0)

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srai a0, a0, 48
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_w_s_sat_i16:
+; CHECK32-IZFHMIN:       # %bb.0: # %start
+; CHECK32-IZFHMIN-NEXT:    lui a0, %hi(.LCPI32_0)
+; CHECK32-IZFHMIN-NEXT:    flw ft0, %lo(.LCPI32_0)(a0)
+; CHECK32-IZFHMIN-NEXT:    lui a0, %hi(.LCPI32_1)
+; CHECK32-IZFHMIN-NEXT:    flw ft1, %lo(.LCPI32_1)(a0)
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECK32-IZFHMIN-NEXT:    fmax.s ft0, ft2, ft0
+; CHECK32-IZFHMIN-NEXT:    fmin.s ft0, ft0, ft1
+; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    feq.s a1, ft2, ft2
+; CHECK32-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK32-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK32-IZFHMIN-NEXT:    and a0, a1, a0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_w_s_sat_i16:
+; CHECK64-IZFHMIN:       # %bb.0: # %start
+; CHECK64-IZFHMIN-NEXT:    lui a0, %hi(.LCPI32_0)
+; CHECK64-IZFHMIN-NEXT:    flw ft0, %lo(.LCPI32_0)(a0)
+; CHECK64-IZFHMIN-NEXT:    lui a0, %hi(.LCPI32_1)
+; CHECK64-IZFHMIN-NEXT:    flw ft1, %lo(.LCPI32_1)(a0)
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECK64-IZFHMIN-NEXT:    fmax.s ft0, ft2, ft0
+; CHECK64-IZFHMIN-NEXT:    fmin.s ft0, ft0, ft1
+; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    feq.s a1, ft2, ft2
+; CHECK64-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK64-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK64-IZFHMIN-NEXT:    and a0, a1, a0
+; CHECK64-IZFHMIN-NEXT:    ret
 start:
   %0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a)
   ret i16 %0
 }
 
 define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_wu_s_i16:
 ; RV32IZFH:       # %bb.0:

 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call __fixunssfdi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_wu_s_i16:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_wu_s_i16:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = fptoui half %a to i16
   ret i16 %1
 }
 
 define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_wu_s_sat_i16:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI34_0)

 ; RV64I-NEXT:    and a0, a0, s3
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_wu_s_sat_i16:
+; CHECK32-IZFHMIN:       # %bb.0: # %start
+; CHECK32-IZFHMIN-NEXT:    lui a0, %hi(.LCPI34_0)
+; CHECK32-IZFHMIN-NEXT:    flw ft0, %lo(.LCPI34_0)(a0)
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECK32-IZFHMIN-NEXT:    fmv.w.x ft2, zero
+; CHECK32-IZFHMIN-NEXT:    fmax.s ft1, ft1, ft2
+; CHECK32-IZFHMIN-NEXT:    fmin.s ft0, ft1, ft0
+; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_wu_s_sat_i16:
+; CHECK64-IZFHMIN:       # %bb.0: # %start
+; CHECK64-IZFHMIN-NEXT:    lui a0, %hi(.LCPI34_0)
+; CHECK64-IZFHMIN-NEXT:    flw ft0, %lo(.LCPI34_0)(a0)
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECK64-IZFHMIN-NEXT:    fmv.w.x ft2, zero
+; CHECK64-IZFHMIN-NEXT:    fmax.s ft1, ft1, ft2
+; CHECK64-IZFHMIN-NEXT:    fmin.s ft0, ft1, ft0
+; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
 start:
   %0 = tail call i16 @llvm.fptoui.sat.i16.f16(half %a)
   ret i16 %0
 }
 
 define signext i8 @fcvt_w_s_i8(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_w_s_i8:
 ; RV32IZFH:       # %bb.0:

 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call __fixsfdi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_w_s_i8:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_w_s_i8:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = fptosi half %a to i8
   ret i8 %1
 }
 
 define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_w_s_sat_i8:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI36_0)

 ; RV64I-NEXT:    slli a0, a0, 56
 ; RV64I-NEXT:    srai a0, a0, 56
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_w_s_sat_i8:
+; CHECK32-IZFHMIN:       # %bb.0: # %start
+; CHECK32-IZFHMIN-NEXT:    lui a0, %hi(.LCPI36_0)
+; CHECK32-IZFHMIN-NEXT:    flw ft0, %lo(.LCPI36_0)(a0)
+; CHECK32-IZFHMIN-NEXT:    lui a0, %hi(.LCPI36_1)
+; CHECK32-IZFHMIN-NEXT:    flw ft1, %lo(.LCPI36_1)(a0)
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECK32-IZFHMIN-NEXT:    fmax.s ft0, ft2, ft0
+; CHECK32-IZFHMIN-NEXT:    fmin.s ft0, ft0, ft1
+; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    feq.s a1, ft2, ft2
+; CHECK32-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK32-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK32-IZFHMIN-NEXT:    and a0, a1, a0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_w_s_sat_i8:
+; CHECK64-IZFHMIN:       # %bb.0: # %start
+; CHECK64-IZFHMIN-NEXT:    lui a0, %hi(.LCPI36_0)
+; CHECK64-IZFHMIN-NEXT:    flw ft0, %lo(.LCPI36_0)(a0)
+; CHECK64-IZFHMIN-NEXT:    lui a0, %hi(.LCPI36_1)
+; CHECK64-IZFHMIN-NEXT:    flw ft1, %lo(.LCPI36_1)(a0)
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECK64-IZFHMIN-NEXT:    fmax.s ft0, ft2, ft0
+; CHECK64-IZFHMIN-NEXT:    fmin.s ft0, ft0, ft1
+; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    feq.s a1, ft2, ft2
+; CHECK64-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK64-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK64-IZFHMIN-NEXT:    and a0, a1, a0
+; CHECK64-IZFHMIN-NEXT:    ret
 start:
   %0 = tail call i8 @llvm.fptosi.sat.i8.f16(half %a)
   ret i8 %0
 }
 declare i8 @llvm.fptosi.sat.i8.f16(half)
 
 define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_wu_s_i8:

 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call __fixunssfdi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_wu_s_i8:
+; CHECK32-IZFHMIN:       # %bb.0:
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_wu_s_i8:
+; CHECK64-IZFHMIN:       # %bb.0:
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
   %1 = fptoui half %a to i8
   ret i8 %1
 }
 
 define zeroext i8 @fcvt_wu_s_sat_i8(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_wu_s_sat_i8:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI38_0)

 ; RV64I-NEXT:  .LBB38_3: # %start
 ; RV64I-NEXT:    andi a0, a0, 255
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_wu_s_sat_i8:
+; CHECK32-IZFHMIN:       # %bb.0: # %start
+; CHECK32-IZFHMIN-NEXT:    lui a0, %hi(.LCPI38_0)
+; CHECK32-IZFHMIN-NEXT:    flw ft0, %lo(.LCPI38_0)(a0)
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECK32-IZFHMIN-NEXT:    fmv.w.x ft2, zero
+; CHECK32-IZFHMIN-NEXT:    fmax.s ft1, ft1, ft2
+; CHECK32-IZFHMIN-NEXT:    fmin.s ft0, ft1, ft0
+; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_wu_s_sat_i8:
+; CHECK64-IZFHMIN:       # %bb.0: # %start
+; CHECK64-IZFHMIN-NEXT:    lui a0, %hi(.LCPI38_0)
+; CHECK64-IZFHMIN-NEXT:    flw ft0, %lo(.LCPI38_0)(a0)
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECK64-IZFHMIN-NEXT:    fmv.w.x ft2, zero
+; CHECK64-IZFHMIN-NEXT:    fmax.s ft1, ft1, ft2
+; CHECK64-IZFHMIN-NEXT:    fmin.s ft0, ft1, ft0
+; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    ret
 start:
   %0 = tail call i8 @llvm.fptoui.sat.i8.f16(half %a)
   ret i8 %0
 }
 declare i8 @llvm.fptoui.sat.i8.f16(half)
 
 define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_wu_h_sat_zext:

 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_wu_h_sat_zext:
+; CHECK32-IZFHMIN:       # %bb.0: # %start
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECK32-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK32-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK32-IZFHMIN-NEXT:    and a0, a1, a0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_wu_h_sat_zext:
+; CHECK64-IZFHMIN:       # %bb.0: # %start
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECK64-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK64-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK64-IZFHMIN-NEXT:    and a0, a0, a1
+; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 32
+; CHECK64-IZFHMIN-NEXT:    srli a0, a0, 32
+; CHECK64-IZFHMIN-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %0
 }
 
 define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_w_h_sat_sext:
 ; CHECKIZFH:       # %bb.0: # %start

 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECK32-IZFHMIN-LABEL: fcvt_w_h_sat_sext:
+; CHECK32-IZFHMIN:       # %bb.0: # %start
+; CHECK32-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK32-IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECK32-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK32-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK32-IZFHMIN-NEXT:    and a0, a1, a0
+; CHECK32-IZFHMIN-NEXT:    ret
+;
+; CHECK64-IZFHMIN-LABEL: fcvt_w_h_sat_sext:
+; CHECK64-IZFHMIN:       # %bb.0: # %start
+; CHECK64-IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECK64-IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECK64-IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECK64-IZFHMIN-NEXT:    seqz a1, a1
+; CHECK64-IZFHMIN-NEXT:    addi a1, a1, -1
+; CHECK64-IZFHMIN-NEXT:    and a0, a1, a0
+; CHECK64-IZFHMIN-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %0
 }

llvm/test/CodeGen/RISCV/half-fcmp-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f -disable-strictnode-mutation < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f -disable-strictnode-mutation < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
+; RUN:   -target-abi ilp32f -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefix=CHECKIZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
+; RUN:   -target-abi lp64f -disable-strictnode-mutation < %s  \
+; RUN:   | FileCheck -check-prefix=CHECKIZFHMIN %s
 
 define i32 @fcmp_oeq(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_oeq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_oeq:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    feq.h a0, fa0, fa1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 declare i1 @llvm.experimental.constrained.fcmp.f16(half, half, metadata, metadata)
 
 define i32 @fcmp_ogt(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_ogt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a1
 ; CHECK-NEXT:    flt.h a0, fa1, fa0
 ; CHECK-NEXT:    fsflags a1
 ; CHECK-NEXT:    feq.h zero, fa1, fa0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_ogt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    frflags a1
+; CHECKIZFHMIN-NEXT:    flt.h a0, fa1, fa0
+; CHECKIZFHMIN-NEXT:    fsflags a1
+; CHECKIZFHMIN-NEXT:    feq.h zero, fa1, fa0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_oge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a1
 ; CHECK-NEXT:    fle.h a0, fa1, fa0
 ; CHECK-NEXT:    fsflags a1
 ; CHECK-NEXT:    feq.h zero, fa1, fa0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_oge:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    frflags a1
+; CHECKIZFHMIN-NEXT:    fle.h a0, fa1, fa0
+; CHECKIZFHMIN-NEXT:    fsflags a1
+; CHECKIZFHMIN-NEXT:    feq.h zero, fa1, fa0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_olt(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_olt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a1
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    fsflags a1
 ; CHECK-NEXT:    feq.h zero, fa0, fa1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_olt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    frflags a1
+; CHECKIZFHMIN-NEXT:    flt.h a0, fa0, fa1
+; CHECKIZFHMIN-NEXT:    fsflags a1
+; CHECKIZFHMIN-NEXT:    feq.h zero, fa0, fa1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ole(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_ole:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a1
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
 ; CHECK-NEXT:    fsflags a1
 ; CHECK-NEXT:    feq.h zero, fa0, fa1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_ole:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    frflags a1
+; CHECKIZFHMIN-NEXT:    fle.h a0, fa0, fa1
+; CHECKIZFHMIN-NEXT:    fsflags a1
+; CHECKIZFHMIN-NEXT:    feq.h zero, fa0, fa1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 ; FIXME: We only need one frflags before the two flts and one fsflags after the
 ; two flts.
 define i32 @fcmp_one(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_one:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    flt.h a1, fa0, fa1
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    feq.h zero, fa0, fa1
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    flt.h a2, fa1, fa0
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    or a0, a2, a1
 ; CHECK-NEXT:    feq.h zero, fa1, fa0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_one:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    frflags a0
+; CHECKIZFHMIN-NEXT:    flt.h a1, fa0, fa1
+; CHECKIZFHMIN-NEXT:    fsflags a0
+; CHECKIZFHMIN-NEXT:    feq.h zero, fa0, fa1
+; CHECKIZFHMIN-NEXT:    frflags a0
+; CHECKIZFHMIN-NEXT:    flt.h a2, fa1, fa0
+; CHECKIZFHMIN-NEXT:    fsflags a0
+; CHECKIZFHMIN-NEXT:    or a0, a2, a1
+; CHECKIZFHMIN-NEXT:    feq.h zero, fa1, fa0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"one", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ord(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_ord:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa1, fa1
 ; CHECK-NEXT:    feq.h a1, fa0, fa0
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_ord:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    feq.h a0, fa1, fa1
+; CHECKIZFHMIN-NEXT:    feq.h a1, fa0, fa0
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 ; FIXME: We only need one frflags before the two flts and one fsflags after the
 ; two flts.
 define i32 @fcmp_ueq(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_ueq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    flt.h a1, fa0, fa1
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    feq.h zero, fa0, fa1
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    flt.h a2, fa1, fa0
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    or a1, a2, a1
 ; CHECK-NEXT:    xori a0, a1, 1
 ; CHECK-NEXT:    feq.h zero, fa1, fa0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_ueq:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    frflags a0
+; CHECKIZFHMIN-NEXT:    flt.h a1, fa0, fa1
+; CHECKIZFHMIN-NEXT:    fsflags a0
+; CHECKIZFHMIN-NEXT:    feq.h zero, fa0, fa1
+; CHECKIZFHMIN-NEXT:    frflags a0
+; CHECKIZFHMIN-NEXT:    flt.h a2, fa1, fa0
+; CHECKIZFHMIN-NEXT:    fsflags a0
+; CHECKIZFHMIN-NEXT:    or a1, a2, a1
+; CHECKIZFHMIN-NEXT:    xori a0, a1, 1
+; CHECKIZFHMIN-NEXT:    feq.h zero, fa1, fa0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_ugt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    fle.h a1, fa0, fa1
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    xori a0, a1, 1
 ; CHECK-NEXT:    feq.h zero, fa0, fa1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_ugt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    frflags a0
+; CHECKIZFHMIN-NEXT:    fle.h a1, fa0, fa1
+; CHECKIZFHMIN-NEXT:    fsflags a0
+; CHECKIZFHMIN-NEXT:    xori a0, a1, 1
+; CHECKIZFHMIN-NEXT:    feq.h zero, fa0, fa1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_uge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    flt.h a1, fa0, fa1
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    xori a0, a1, 1
 ; CHECK-NEXT:    feq.h zero, fa0, fa1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_uge:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    frflags a0
+; CHECKIZFHMIN-NEXT:    flt.h a1, fa0, fa1
+; CHECKIZFHMIN-NEXT:    fsflags a0
+; CHECKIZFHMIN-NEXT:    xori a0, a1, 1
+; CHECKIZFHMIN-NEXT:    feq.h zero, fa0, fa1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_ult:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    fle.h a1, fa1, fa0
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    xori a0, a1, 1
 ; CHECK-NEXT:    feq.h zero, fa1, fa0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_ult:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    frflags a0
+; CHECKIZFHMIN-NEXT:    fle.h a1, fa1, fa0
+; CHECKIZFHMIN-NEXT:    fsflags a0
+; CHECKIZFHMIN-NEXT:    xori a0, a1, 1
+; CHECKIZFHMIN-NEXT:    feq.h zero, fa1, fa0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_ule:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    flt.h a1, fa1, fa0
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    xori a0, a1, 1
 ; CHECK-NEXT:    feq.h zero, fa1, fa0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_ule:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    frflags a0
+; CHECKIZFHMIN-NEXT:    flt.h a1, fa1, fa0
+; CHECKIZFHMIN-NEXT:    fsflags a0
+; CHECKIZFHMIN-NEXT:    xori a0, a1, 1
+; CHECKIZFHMIN-NEXT:    feq.h zero, fa1, fa0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_une:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa1
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_une:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    feq.h a0, fa0, fa1
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"une", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uno(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_uno:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa1, fa1
 ; CHECK-NEXT:    feq.h a1, fa0, fa0
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_uno:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    feq.h a0, fa1, fa1
+; CHECKIZFHMIN-NEXT:    feq.h a1, fa0, fa0
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"uno", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oeq(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_oeq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa0
 ; CHECK-NEXT:    fle.h a1, fa0, fa1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmps_oeq:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fle.h a0, fa1, fa0
+; CHECKIZFHMIN-NEXT:    fle.h a1, fa0, fa1
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 declare i1 @llvm.experimental.constrained.fcmps.f16(half, half, metadata, metadata)
 
 define i32 @fcmps_ogt(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_ogt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa1, fa0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmps_ogt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    flt.h a0, fa1, fa0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oge(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_oge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmps_oge:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fle.h a0, fa1, fa0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_olt(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_olt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmps_olt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    flt.h a0, fa0, fa1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ole(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_ole:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmps_ole:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fle.h a0, fa0, fa1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_one(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_one:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    flt.h a1, fa1, fa0
 ; CHECK-NEXT:    or a0, a1, a0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmps_one:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    flt.h a0, fa0, fa1
+; CHECKIZFHMIN-NEXT:    flt.h a1, fa1, fa0
+; CHECKIZFHMIN-NEXT:    or a0, a1, a0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"one", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ord(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_ord:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa1
 ; CHECK-NEXT:    fle.h a1, fa0, fa0
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmps_ord:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fle.h a0, fa1, fa1
+; CHECKIZFHMIN-NEXT:    fle.h a1, fa0, fa0
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ueq(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_ueq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    flt.h a1, fa1, fa0
 ; CHECK-NEXT:    or a0, a1, a0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmps_ueq:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    flt.h a0, fa0, fa1
+; CHECKIZFHMIN-NEXT:    flt.h a1, fa1, fa0
+; CHECKIZFHMIN-NEXT:    or a0, a1, a0
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ugt(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_ugt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmps_ugt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fle.h a0, fa0, fa1
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_uge(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_uge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmps_uge:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    flt.h a0, fa0, fa1
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ult(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_ult:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmps_ult:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fle.h a0, fa1, fa0
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ule(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_ule:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa1, fa0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmps_ule:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    flt.h a0, fa1, fa0
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_une(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_une:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa0
 ; CHECK-NEXT:    fle.h a1, fa0, fa1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmps_une:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fle.h a0, fa1, fa0
+; CHECKIZFHMIN-NEXT:    fle.h a1, fa0, fa1
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"une", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_uno(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_uno:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa1
 ; CHECK-NEXT:    fle.h a1, fa0, fa0
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmps_uno:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fle.h a0, fa1, fa1
+; CHECKIZFHMIN-NEXT:    fle.h a1, fa0, fa0
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"uno", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/half-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFHMIN-ILP32F-LP64F %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFHMIN-ILP32F-LP64F %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefix=CHECKIZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefix=CHECKIZFHMIN %s
 
 define i32 @fcmp_false(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_false:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    li a0, 0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_false:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_false:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 0
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_false:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    li a0, 0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_false:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    li a0, 0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp false half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oeq(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_oeq:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    feq.h a0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    feq.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_oeq:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    feq.h a0, ft1, ft0
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_oeq:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    feq.s a0, ft1, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_oeq:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft0, a0
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft1, a1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    feq.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp oeq half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ogt(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ogt:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    flt.h a0, fa1, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a0
 ; RV32I-NEXT:    fmv.h.x ft1, a1
 ; RV32I-NEXT:    flt.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ogt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a0
 ; RV64I-NEXT:    fmv.h.x ft1, a1
 ; RV64I-NEXT:    flt.h a0, ft1, ft0
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ogt:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    flt.s a0, ft1, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_ogt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft0, a1
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft1, a0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ogt half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_oge:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fle.h a0, fa1, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a0
 ; RV32I-NEXT:    fmv.h.x ft1, a1
 ; RV32I-NEXT:    fle.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_oge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a0
 ; RV64I-NEXT:    fmv.h.x ft1, a1
 ; RV64I-NEXT:    fle.h a0, ft1, ft0
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_oge:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fle.s a0, ft1, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_oge:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft0, a1
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft1, a0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fle.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp oge half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_olt(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_olt:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    flt.h a0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    flt.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_olt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    flt.h a0, ft1, ft0
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_olt:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    flt.s a0, ft1, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_olt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft0, a0
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft1, a1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp olt half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ole(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ole:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fle.h a0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    fle.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ole:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    fle.h a0, ft1, ft0
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ole:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fle.s a0, ft1, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_ole:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft0, a0
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft1, a1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fle.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ole half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_one(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_one:
 ; CHECKIZFH:       # %bb.0:

 ; RV64I-LABEL: fcmp_one:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    flt.h a0, ft1, ft0
 ; RV64I-NEXT:    flt.h a1, ft0, ft1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_one:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    flt.s a0, ft1, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    flt.s a1, ft0, ft1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    or a0, a1, a0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_one:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft0, a0
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft1, a1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    flt.s a1, ft1, ft0
+; CHECKIZFHMIN-NEXT:    or a0, a1, a0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp one half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ord(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ord:
 ; CHECKIZFH:       # %bb.0:

 ; RV64I-LABEL: fcmp_ord:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a0
 ; RV64I-NEXT:    fmv.h.x ft1, a1
 ; RV64I-NEXT:    feq.h a0, ft1, ft1
 ; RV64I-NEXT:    feq.h a1, ft0, ft0
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ord:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    feq.s a0, ft0, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    feq.s a1, ft0, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_ord:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft0, a0
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft1, a1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    feq.s a0, ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ord half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ueq(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ueq:
 ; CHECKIZFH:       # %bb.0:

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    flt.h a0, ft1, ft0
 ; RV64I-NEXT:    flt.h a1, ft0, ft1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ueq:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    flt.s a0, ft1, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    flt.s a1, ft0, ft1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    or a0, a1, a0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_ueq:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft0, a0
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft1, a1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    flt.s a1, ft1, ft0
+; CHECKIZFHMIN-NEXT:    or a0, a1, a0
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ueq half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ugt:
 ; CHECKIZFH:       # %bb.0:

 ;
 ; RV64I-LABEL: fcmp_ugt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    fle.h a0, ft1, ft0
 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ugt:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fle.s a0, ft1, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_ugt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft0, a0
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft1, a1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fle.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_uge:
 ; CHECKIZFH:       # %bb.0:

 ;
 ; RV64I-LABEL: fcmp_uge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    flt.h a0, ft1, ft0
 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_uge:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    flt.s a0, ft1, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_uge:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft0, a0
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft1, a1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp uge half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ult:
 ; CHECKIZFH:       # %bb.0:

 ;
 ; RV64I-LABEL: fcmp_ult:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a0
 ; RV64I-NEXT:    fmv.h.x ft1, a1
 ; RV64I-NEXT:    fle.h a0, ft1, ft0
 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ult:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fle.s a0, ft1, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_ult:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft0, a1
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft1, a0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fle.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ult half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ule:
 ; CHECKIZFH:       # %bb.0:

 ;
 ; RV64I-LABEL: fcmp_ule:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a0
 ; RV64I-NEXT:    fmv.h.x ft1, a1
 ; RV64I-NEXT:    flt.h a0, ft1, ft0
 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ule:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    flt.s a0, ft1, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_ule:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft0, a1
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft1, a0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ule half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_une:
 ; CHECKIZFH:       # %bb.0:

 ;
 ; RV64I-LABEL: fcmp_une:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    feq.h a0, ft1, ft0
 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_une:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    feq.s a0, ft1, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_une:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft0, a0
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft1, a1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    feq.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp une half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uno(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_uno:
 ; CHECKIZFH:       # %bb.0:

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a0
 ; RV64I-NEXT:    fmv.h.x ft1, a1
 ; RV64I-NEXT:    feq.h a0, ft1, ft1
 ; RV64I-NEXT:    feq.h a1, ft0, ft0
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_uno:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    feq.s a0, ft0, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    feq.s a1, ft0, ft0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_uno:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft0, a0
+; CHECKIZFHMIN-NEXT:    fmv.h.x ft1, a1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    feq.s a0, ft1, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp uno half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_true(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_true:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    li a0, 1
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_true:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_true:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_true:
+; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    li a0, 1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fcmp_true:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    li a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp true half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/half-frem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32f < %s \
+; RUN:   | FileCheck -check-prefix=RV32IZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi lp64f < %s \
+; RUN:   | FileCheck -check-prefix=RV64IZFHMIN %s
 
 define half @frem_f16(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: frem_f16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    fcvt.s.h fa1, fa1

 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    fcvt.s.h fa1, fa1
 ; RV64IZFH-NEXT:    call fmodf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: frem_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa1, fa1
+; RV32IZFHMIN-NEXT:    call fmodf@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: frem_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa1, fa1
+; RV64IZFHMIN-NEXT:    call fmodf@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = frem half %a, %b
   ret half %1
 }

llvm/test/CodeGen/RISCV/half-imm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
 
 ; TODO: constant pool shouldn't be necessary for RV32IZfh and RV64IZfh
 define half @half_imm() nounwind {
 ; CHECK-LABEL: half_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI0_0)
 ; CHECK-NEXT:    flh fa0, %lo(.LCPI0_0)(a0)
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: half_imm:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI0_0)
+; CHECKIZFHMIN-NEXT:    flh fa0, %lo(.LCPI0_0)(a0)
+; CHECKIZFHMIN-NEXT:    ret
   ret half 3.0
 }
 
 define half @half_imm_op(half %a) nounwind {
 ; CHECK-LABEL: half_imm_op:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI1_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI1_0)(a0)
 ; CHECK-NEXT:    fadd.h fa0, fa0, ft0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: half_imm_op:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI1_0)
+; CHECKIZFHMIN-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fadd half %a, 1.0
   ret half %1
 }

llvm/test/CodeGen/RISCV/half-intrinsics.ll

 ; RUN:   FileCheck -check-prefixes=CHECKIZFH,RV64IZFH,RV64IDZFH %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
 ; RUN:   -verify-machineinstrs | \
 ; RUN:   FileCheck -check-prefix=RV32I %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
 ; RUN:   -verify-machineinstrs | \
 ; RUN:   FileCheck -check-prefix=RV64I %s
 
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfhmin \
+; RUN:   -verify-machineinstrs -target-abi ilp32f | \
+; RUN:   FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN,RV32IFZFHMIN %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfhmin \
+; RUN:   -verify-machineinstrs -target-abi lp64f | \
+; RUN:   FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN,RV64IFZFHMIN %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
+; RUN:   -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32d | \
+; RUN:   FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN,RV32IDZFHMIN %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
+; RUN:   -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d | \
+; RUN:   FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN,RV64IDZFHMIN %s
+
 declare half @llvm.sqrt.f16(half)
 
 define half @sqrt_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: sqrt_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fsqrt.h fa0, fa0
 ; CHECKIZFH-NEXT:    ret
 ;

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call sqrtf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: sqrt_f16:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fsqrt.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.sqrt.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.powi.f16.i32(half, i32)
 
 define half @powi_f16(half %a, i32 %b) nounwind {
 ; RV32IZFH-LABEL: powi_f16:

 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    sext.w a1, s0
 ; RV64I-NEXT:    call __powisf2@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: powi_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call __powisf2@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: powi_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    sext.w a0, a0
+; RV64IZFHMIN-NEXT:    call __powisf2@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = call half @llvm.powi.f16.i32(half %a, i32 %b)
   ret half %1
 }
 
 declare half @llvm.sin.f16(half)
 
 define half @sin_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: sin_f16:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call sinf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: sin_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call sinf@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: sin_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call sinf@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = call half @llvm.sin.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.cos.f16(half)
 
 define half @cos_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: cos_f16:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call cosf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: cos_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call cosf@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: cos_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call cosf@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = call half @llvm.cos.f16(half %a)
   ret half %1
 }
 
 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
 define half @sincos_f16(half %a) nounwind {
 ; RV32IFZFH-LABEL: sincos_f16:
 ; RV32IFZFH:       # %bb.0:

 ; RV64I-NEXT:    call __addsf3@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; RV32IFZFHMIN-LABEL: sincos_f16:
+; RV32IFZFHMIN:       # %bb.0:
+; RV32IFZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IFZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFZFHMIN-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
+; RV32IFZFHMIN-NEXT:    fsw fs1, 4(sp) # 4-byte Folded Spill
+; RV32IFZFHMIN-NEXT:    fcvt.s.h fs0, fa0
+; RV32IFZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IFZFHMIN-NEXT:    call sinf@plt
+; RV32IFZFHMIN-NEXT:    fcvt.h.s fs1, fa0
+; RV32IFZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IFZFHMIN-NEXT:    call cosf@plt
+; RV32IFZFHMIN-NEXT:    fcvt.h.s ft0, fa0
+; RV32IFZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IFZFHMIN-NEXT:    fcvt.s.h ft1, fs1
+; RV32IFZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IFZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IFZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFZFHMIN-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
+; RV32IFZFHMIN-NEXT:    flw fs1, 4(sp) # 4-byte Folded Reload
+; RV32IFZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IFZFHMIN-NEXT:    ret
+;
+; RV64IFZFHMIN-LABEL: sincos_f16:
+; RV64IFZFHMIN:       # %bb.0:
+; RV64IFZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IFZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV64IFZFHMIN-NEXT:    fsw fs1, 0(sp) # 4-byte Folded Spill
+; RV64IFZFHMIN-NEXT:    fcvt.s.h fs0, fa0
+; RV64IFZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV64IFZFHMIN-NEXT:    call sinf@plt
+; RV64IFZFHMIN-NEXT:    fcvt.h.s fs1, fa0
+; RV64IFZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV64IFZFHMIN-NEXT:    call cosf@plt
+; RV64IFZFHMIN-NEXT:    fcvt.h.s ft0, fa0
+; RV64IFZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IFZFHMIN-NEXT:    fcvt.s.h ft1, fs1
+; RV64IFZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IFZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IFZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV64IFZFHMIN-NEXT:    flw fs1, 0(sp) # 4-byte Folded Reload
+; RV64IFZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IFZFHMIN-NEXT:    ret
+;
+; RV32IDZFHMIN-LABEL: sincos_f16:
+; RV32IDZFHMIN:       # %bb.0:
+; RV32IDZFHMIN-NEXT:    addi sp, sp, -32
+; RV32IDZFHMIN-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
+; RV32IDZFHMIN-NEXT:    fsd fs0, 16(sp) # 8-byte Folded Spill
+; RV32IDZFHMIN-NEXT:    fsd fs1, 8(sp) # 8-byte Folded Spill
+; RV32IDZFHMIN-NEXT:    fcvt.s.h fs0, fa0
+; RV32IDZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IDZFHMIN-NEXT:    call sinf@plt
+; RV32IDZFHMIN-NEXT:    fcvt.h.s fs1, fa0
+; RV32IDZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IDZFHMIN-NEXT:    call cosf@plt
+; RV32IDZFHMIN-NEXT:    fcvt.h.s ft0, fa0
+; RV32IDZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IDZFHMIN-NEXT:    fcvt.s.h ft1, fs1
+; RV32IDZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IDZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IDZFHMIN-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
+; RV32IDZFHMIN-NEXT:    fld fs0, 16(sp) # 8-byte Folded Reload
+; RV32IDZFHMIN-NEXT:    fld fs1, 8(sp) # 8-byte Folded Reload
+; RV32IDZFHMIN-NEXT:    addi sp, sp, 32
+; RV32IDZFHMIN-NEXT:    ret
+;
+; RV64IDZFHMIN-LABEL: sincos_f16:
+; RV64IDZFHMIN:       # %bb.0:
+; RV64IDZFHMIN-NEXT:    addi sp, sp, -32
+; RV64IDZFHMIN-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64IDZFHMIN-NEXT:    fsd fs0, 16(sp) # 8-byte Folded Spill
+; RV64IDZFHMIN-NEXT:    fsd fs1, 8(sp) # 8-byte Folded Spill
+; RV64IDZFHMIN-NEXT:    fcvt.s.h fs0, fa0
+; RV64IDZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV64IDZFHMIN-NEXT:    call sinf@plt
+; RV64IDZFHMIN-NEXT:    fcvt.h.s fs1, fa0
+; RV64IDZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV64IDZFHMIN-NEXT:    call cosf@plt
+; RV64IDZFHMIN-NEXT:    fcvt.h.s ft0, fa0
+; RV64IDZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IDZFHMIN-NEXT:    fcvt.s.h ft1, fs1
+; RV64IDZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IDZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IDZFHMIN-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64IDZFHMIN-NEXT:    fld fs0, 16(sp) # 8-byte Folded Reload
+; RV64IDZFHMIN-NEXT:    fld fs1, 8(sp) # 8-byte Folded Reload
+; RV64IDZFHMIN-NEXT:    addi sp, sp, 32
+; RV64IDZFHMIN-NEXT:    ret
   %1 = call half @llvm.sin.f16(half %a)
   %2 = call half @llvm.cos.f16(half %a)
   %3 = fadd half %1, %2
   ret half %3
 }
 
 declare half @llvm.pow.f16(half, half)
 

 ; RV64I-NEXT:    call powf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: pow_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa1, fa1
+; RV32IZFHMIN-NEXT:    call powf@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: pow_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa1, fa1
+; RV64IZFHMIN-NEXT:    call powf@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = call half @llvm.pow.f16(half %a, half %b)
   ret half %1
 }
 
 declare half @llvm.exp.f16(half)
 
 define half @exp_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: exp_f16:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call expf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: exp_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call expf@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: exp_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call expf@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = call half @llvm.exp.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.exp2.f16(half)
 
 define half @exp2_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: exp2_f16:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call exp2f@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: exp2_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call exp2f@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: exp2_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call exp2f@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = call half @llvm.exp2.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.log.f16(half)
 
 define half @log_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: log_f16:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call logf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: log_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call logf@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: log_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call logf@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = call half @llvm.log.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.log10.f16(half)
 
 define half @log10_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: log10_f16:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call log10f@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: log10_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call log10f@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: log10_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call log10f@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = call half @llvm.log10.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.log2.f16(half)
 
 define half @log2_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: log2_f16:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call log2f@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: log2_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call log2f@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: log2_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call log2f@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = call half @llvm.log2.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.fma.f16(half, half, half)
 
 define half @fma_f16(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fma_f16:

 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fma_f16:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa2
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft2, fa0
+; CHECKIZFHMIN-NEXT:    fmadd.s ft0, ft2, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
   ret half %1
 }
 
 declare half @llvm.fmuladd.f16(half, half, half)
 
 define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fmuladd_f16:

 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fmuladd_f16:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fmul.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa2
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
   ret half %1
 }
 
 declare half @llvm.fabs.f16(half)
 
 define half @fabs_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: fabs_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fabs.h fa0, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fabs_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 17
 ; RV32I-NEXT:    srli a0, a0, 17
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fabs_f16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 49
 ; RV64I-NEXT:    srli a0, a0, 49
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fabs_f16:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.fabs.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.minnum.f16(half, half)
 
 define half @minnum_f16(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: minnum_f16:

 ; RV64I-NEXT:    call fminf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: minnum_f16:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fmin.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.minnum.f16(half %a, half %b)
   ret half %1
 }
 
 declare half @llvm.maxnum.f16(half, half)
 
 define half @maxnum_f16(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: maxnum_f16:

 ; RV64I-NEXT:    call fmaxf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: maxnum_f16:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fmax.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.maxnum.f16(half %a, half %b)
   ret half %1
 }
 
 ; TODO: FMINNAN and FMAXNAN aren't handled in
 ; SelectionDAGLegalize::ExpandNode.
 
 ; declare half @llvm.minimum.f16(half, half)

 ; RV64I-LABEL: copysign_f16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a2, 1048568
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    slli a0, a0, 49
 ; RV64I-NEXT:    srli a0, a0, 49
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: copysign_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    fsh fa1, 12(sp)
+; RV32IZFHMIN-NEXT:    fsh fa0, 8(sp)
+; RV32IZFHMIN-NEXT:    lbu a0, 13(sp)
+; RV32IZFHMIN-NEXT:    lbu a1, 9(sp)
+; RV32IZFHMIN-NEXT:    andi a0, a0, 128
+; RV32IZFHMIN-NEXT:    andi a1, a1, 127
+; RV32IZFHMIN-NEXT:    or a0, a1, a0
+; RV32IZFHMIN-NEXT:    sb a0, 9(sp)
+; RV32IZFHMIN-NEXT:    flh fa0, 8(sp)
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: copysign_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    fsh fa1, 8(sp)
+; RV64IZFHMIN-NEXT:    fsh fa0, 0(sp)
+; RV64IZFHMIN-NEXT:    lbu a0, 9(sp)
+; RV64IZFHMIN-NEXT:    lbu a1, 1(sp)
+; RV64IZFHMIN-NEXT:    andi a0, a0, 128
+; RV64IZFHMIN-NEXT:    andi a1, a1, 127
+; RV64IZFHMIN-NEXT:    or a0, a1, a0
+; RV64IZFHMIN-NEXT:    sb a0, 1(sp)
+; RV64IZFHMIN-NEXT:    flh fa0, 0(sp)
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = call half @llvm.copysign.f16(half %a, half %b)
   ret half %1
 }
 
 declare half @llvm.floor.f16(half)
 
 define half @floor_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: floor_f16:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call floorf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: floor_f16:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI17_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI17_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB17_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB17_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.floor.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.ceil.f16(half)
 
 define half @ceil_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: ceil_f16:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call ceilf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: ceil_f16:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI18_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI18_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB18_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB18_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.ceil.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.trunc.f16(half)
 
 define half @trunc_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: trunc_f16:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call truncf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: trunc_f16:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI19_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI19_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB19_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB19_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.trunc.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.rint.f16(half)
 
 define half @rint_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: rint_f16:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call rintf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: rint_f16:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI20_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI20_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB20_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB20_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.rint.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.nearbyint.f16(half)
 
 define half @nearbyint_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: nearbyint_f16:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call nearbyintf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: nearbyint_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call nearbyintf@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: nearbyint_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call nearbyintf@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = call half @llvm.nearbyint.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.round.f16(half)
 
 define half @round_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: round_f16:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call roundf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: round_f16:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI22_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI22_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB22_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB22_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.round.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.roundeven.f16(half)
 
 define half @roundeven_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: roundeven_f16:

 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call roundevenf@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: roundeven_f16:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI23_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI23_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB23_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB23_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = call half @llvm.roundeven.f16(half %a)
   ret half %1
 }

llvm/test/CodeGen/RISCV/half-isnan.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
 
 define zeroext i1 @half_is_nan(half %a) nounwind {
 ; CHECK-LABEL: half_is_nan:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: half_is_nan:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    feq.s a0, ft0, ft0
+; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp uno half %a, 0.000000e+00
   ret i1 %1
 }
 
 define zeroext i1 @half_not_nan(half %a) nounwind {
 ; CHECK-LABEL: half_not_nan:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: half_not_nan:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    feq.s a0, ft0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ord half %a, 0.000000e+00
   ret i1 %1
 }

llvm/test/CodeGen/RISCV/half-mem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN %s
 
 define half @flh(half *%a) nounwind {
 ; CHECKIZFH-LABEL: flh:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    flh ft0, 0(a0)
 ; CHECKIZFH-NEXT:    flh ft1, 6(a0)
 ; CHECKIZFH-NEXT:    fadd.h fa0, ft0, ft1
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: flh:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    flh ft0, 6(a0)
+; CHECKIZFHMIN-NEXT:    flh ft1, 0(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = load half, half* %a
   %2 = getelementptr half, half* %a, i32 3
   %3 = load half, half* %2
 ; Use both loaded values in an FP op to ensure an flh is used, even for the
 ; soft half ABI
   %4 = fadd half %1, %3
   ret half %4
 }
 
 define dso_local void @fsh(half *%a, half %b, half %c) nounwind {
 ; Use %b and %c in an FP op to ensure half precision floating point registers
 ; are used, even for the soft half ABI
 ; CHECKIZFH-LABEL: fsh:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fadd.h ft0, fa0, fa1
 ; CHECKIZFH-NEXT:    fsh ft0, 0(a0)
 ; CHECKIZFH-NEXT:    fsh ft0, 16(a0)
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: fsh:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fsh ft0, 0(a0)
+; CHECKIZFHMIN-NEXT:    fsh ft0, 16(a0)
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fadd half %b, %c
   store half %1, half* %a
   %2 = getelementptr half, half* %a, i32 8
   store half %1, half* %2
   ret void
 }
 
 ; Check load and store to a global
 @G = dso_local global half 0.0
 
 define half @flh_fsh_global(half %a, half %b) nounwind {
 ; Use %a and %b in an FP op to ensure half precision floating point registers
 ; are used, even for the soft half ABI
 ; CHECKIZFH-LABEL: flh_fsh_global:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fadd.h fa0, fa0, fa1
 ; CHECKIZFH-NEXT:    lui a0, %hi(G)
 ; CHECKIZFH-NEXT:    flh ft0, %lo(G)(a0)
 ; CHECKIZFH-NEXT:    addi a1, a0, %lo(G)
 ; CHECKIZFH-NEXT:    fsh fa0, %lo(G)(a0)
 ; CHECKIZFH-NEXT:    flh ft0, 18(a1)
 ; CHECKIZFH-NEXT:    fsh fa0, 18(a1)
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: flh_fsh_global:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(G)
+; CHECKIZFHMIN-NEXT:    flh ft0, %lo(G)(a0)
+; CHECKIZFHMIN-NEXT:    addi a1, a0, %lo(G)
+; CHECKIZFHMIN-NEXT:    fsh fa0, %lo(G)(a0)
+; CHECKIZFHMIN-NEXT:    flh ft0, 18(a1)
+; CHECKIZFHMIN-NEXT:    fsh fa0, 18(a1)
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = load volatile half, half* @G
   store half %1, half* @G
   %3 = getelementptr half, half* @G, i32 9
   %4 = load volatile half, half* %3
   store half %1, half* %3
   ret half %1
 }

 ; RV64IZFH-LABEL: flh_fsh_constant:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    lui a0, 228023
 ; RV64IZFH-NEXT:    slli a0, a0, 2
 ; RV64IZFH-NEXT:    flh ft0, -273(a0)
 ; RV64IZFH-NEXT:    fadd.h fa0, fa0, ft0
 ; RV64IZFH-NEXT:    fsh fa0, -273(a0)
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: flh_fsh_constant:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, 912092
+; RV32IZFHMIN-NEXT:    flh ft0, -273(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IZFHMIN-NEXT:    fsh fa0, -273(a0)
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: flh_fsh_constant:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, 228023
+; RV64IZFHMIN-NEXT:    slli a0, a0, 2
+; RV64IZFHMIN-NEXT:    flh ft0, -273(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    fsh fa0, -273(a0)
+; RV64IZFHMIN-NEXT:    ret
   %1 = inttoptr i32 3735928559 to half*
   %2 = load volatile half, half* %1
   %3 = fadd half %a, %2
   store half %3, half* %1
   ret half %3
 }
 
 declare void @notdead(i8*)

 ; RV64IZFH-NEXT:    mv a0, sp
 ; RV64IZFH-NEXT:    call notdead@plt
 ; RV64IZFH-NEXT:    flh ft0, 0(sp)
 ; RV64IZFH-NEXT:    fadd.h fa0, ft0, fs0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: flh_stack:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fmv.s fs0, fa0
+; RV32IZFHMIN-NEXT:    addi a0, sp, 4
+; RV32IZFHMIN-NEXT:    call notdead@plt
+; RV32IZFHMIN-NEXT:    flh ft0, 4(sp)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fs0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: flh_stack:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fmv.s fs0, fa0
+; RV64IZFHMIN-NEXT:    mv a0, sp
+; RV64IZFHMIN-NEXT:    call notdead@plt
+; RV64IZFHMIN-NEXT:    flh ft0, 0(sp)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fs0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = alloca half, align 4
   %2 = bitcast half* %1 to i8*
   call void @notdead(i8* %2)
   %3 = load half, half* %1
   %4 = fadd half %3, %a ; force load in to FPR16
   ret half %4
 }
 

 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa1
 ; RV64IZFH-NEXT:    fsh ft0, 4(sp)
 ; RV64IZFH-NEXT:    addi a0, sp, 4
 ; RV64IZFH-NEXT:    call notdead@plt
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: fsh_stack:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV32IZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fsh ft0, 8(sp)
+; RV32IZFHMIN-NEXT:    addi a0, sp, 8
+; RV32IZFHMIN-NEXT:    call notdead@plt
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: fsh_stack:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV64IZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fsh ft0, 4(sp)
+; RV64IZFHMIN-NEXT:    addi a0, sp, 4
+; RV64IZFHMIN-NEXT:    call notdead@plt
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
   %1 = fadd half %a, %b ; force store from FPR16
   %2 = alloca half, align 4
   store half %1, half* %2
   %3 = bitcast half* %2 to i8*
   call void @notdead(i8* %3)
   ret void
 }

llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN %s
 
 define signext i32 @test_floor_si32(half %x) {
 ; CHECKIZFH-LABEL: test_floor_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rdn
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_floor_si32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI0_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI0_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB0_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB0_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECKIZFHMIN-NEXT:    seqz a1, a1
+; CHECKIZFHMIN-NEXT:    addi a1, a1, -1
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_floor_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_floor_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-LABEL: test_floor_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_floor_si64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI1_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB1_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB1_2:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI1_1)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI1_1)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFHMIN-NEXT:    fle.s s0, ft1, fs0
+; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IZFHMIN-NEXT:    call __fixsfdi@plt
+; RV32IZFHMIN-NEXT:    lui a3, 524288
+; RV32IZFHMIN-NEXT:    bnez s0, .LBB1_4
+; RV32IZFHMIN-NEXT:  # %bb.3:
+; RV32IZFHMIN-NEXT:    lui a1, 524288
+; RV32IZFHMIN-NEXT:  .LBB1_4:
+; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI1_2)
+; RV32IZFHMIN-NEXT:    flw ft0, %lo(.LCPI1_2)(a2)
+; RV32IZFHMIN-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFHMIN-NEXT:    beqz a2, .LBB1_6
+; RV32IZFHMIN-NEXT:  # %bb.5:
+; RV32IZFHMIN-NEXT:    addi a1, a3, -1
+; RV32IZFHMIN-NEXT:  .LBB1_6:
+; RV32IZFHMIN-NEXT:    feq.s a3, fs0, fs0
+; RV32IZFHMIN-NEXT:    seqz a3, a3
+; RV32IZFHMIN-NEXT:    addi a3, a3, -1
+; RV32IZFHMIN-NEXT:    and a1, a3, a1
+; RV32IZFHMIN-NEXT:    neg a4, s0
+; RV32IZFHMIN-NEXT:    and a0, a4, a0
+; RV32IZFHMIN-NEXT:    neg a2, a2
+; RV32IZFHMIN-NEXT:    or a0, a2, a0
+; RV32IZFHMIN-NEXT:    and a0, a3, a0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_floor_si64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI1_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB1_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB1_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a1, a0
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_floor_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_floor_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_floor_ui32:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI2_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI2_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB2_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB2_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV32IZFHMIN-NEXT:    seqz a1, a1
+; RV32IZFHMIN-NEXT:    addi a1, a1, -1
+; RV32IZFHMIN-NEXT:    and a0, a1, a0
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_floor_ui32:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI2_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI2_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB2_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB2_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a0, a1
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_floor_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-LABEL: test_floor_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_floor_ui64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI3_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI3_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB3_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB3_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFHMIN-NEXT:    fmv.w.x ft0, zero
+; RV32IZFHMIN-NEXT:    fle.s a0, ft0, fs0
+; RV32IZFHMIN-NEXT:    neg s0, a0
+; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IZFHMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI3_1)
+; RV32IZFHMIN-NEXT:    flw ft0, %lo(.LCPI3_1)(a2)
+; RV32IZFHMIN-NEXT:    and a0, s0, a0
+; RV32IZFHMIN-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFHMIN-NEXT:    neg a2, a2
+; RV32IZFHMIN-NEXT:    or a0, a2, a0
+; RV32IZFHMIN-NEXT:    and a1, s0, a1
+; RV32IZFHMIN-NEXT:    or a1, a2, a1
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_floor_ui64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI3_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI3_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB3_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB3_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a1, a0
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_si32(half %x) {
 ; CHECKIZFH-LABEL: test_ceil_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rup
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_ceil_si32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI4_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI4_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB4_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB4_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECKIZFHMIN-NEXT:    seqz a1, a1
+; CHECKIZFHMIN-NEXT:    addi a1, a1, -1
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_ceil_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-LABEL: test_ceil_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_ceil_si64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI5_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI5_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB5_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB5_2:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI5_1)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI5_1)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFHMIN-NEXT:    fle.s s0, ft1, fs0
+; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IZFHMIN-NEXT:    call __fixsfdi@plt
+; RV32IZFHMIN-NEXT:    lui a3, 524288
+; RV32IZFHMIN-NEXT:    bnez s0, .LBB5_4
+; RV32IZFHMIN-NEXT:  # %bb.3:
+; RV32IZFHMIN-NEXT:    lui a1, 524288
+; RV32IZFHMIN-NEXT:  .LBB5_4:
+; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI5_2)
+; RV32IZFHMIN-NEXT:    flw ft0, %lo(.LCPI5_2)(a2)
+; RV32IZFHMIN-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFHMIN-NEXT:    beqz a2, .LBB5_6
+; RV32IZFHMIN-NEXT:  # %bb.5:
+; RV32IZFHMIN-NEXT:    addi a1, a3, -1
+; RV32IZFHMIN-NEXT:  .LBB5_6:
+; RV32IZFHMIN-NEXT:    feq.s a3, fs0, fs0
+; RV32IZFHMIN-NEXT:    seqz a3, a3
+; RV32IZFHMIN-NEXT:    addi a3, a3, -1
+; RV32IZFHMIN-NEXT:    and a1, a3, a1
+; RV32IZFHMIN-NEXT:    neg a4, s0
+; RV32IZFHMIN-NEXT:    and a0, a4, a0
+; RV32IZFHMIN-NEXT:    neg a2, a2
+; RV32IZFHMIN-NEXT:    or a0, a2, a0
+; RV32IZFHMIN-NEXT:    and a0, a3, a0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_ceil_si64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI5_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI5_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB5_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB5_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a1, a0
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_ceil_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rup
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_ceil_ui32:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI6_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI6_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB6_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB6_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV32IZFHMIN-NEXT:    seqz a1, a1
+; RV32IZFHMIN-NEXT:    addi a1, a1, -1
+; RV32IZFHMIN-NEXT:    and a0, a1, a0
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_ceil_ui32:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI6_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI6_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB6_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB6_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a0, a1
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_ceil_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-LABEL: test_ceil_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_ceil_ui64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI7_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI7_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB7_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB7_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFHMIN-NEXT:    fmv.w.x ft0, zero
+; RV32IZFHMIN-NEXT:    fle.s a0, ft0, fs0
+; RV32IZFHMIN-NEXT:    neg s0, a0
+; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IZFHMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI7_1)
+; RV32IZFHMIN-NEXT:    flw ft0, %lo(.LCPI7_1)(a2)
+; RV32IZFHMIN-NEXT:    and a0, s0, a0
+; RV32IZFHMIN-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFHMIN-NEXT:    neg a2, a2
+; RV32IZFHMIN-NEXT:    or a0, a2, a0
+; RV32IZFHMIN-NEXT:    and a1, s0, a1
+; RV32IZFHMIN-NEXT:    or a1, a2, a1
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_ceil_ui64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI7_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI7_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB7_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB7_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a1, a0
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_si32(half %x) {
 ; CHECKIZFH-LABEL: test_trunc_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_trunc_si32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI8_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI8_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB8_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB8_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECKIZFHMIN-NEXT:    seqz a1, a1
+; CHECKIZFHMIN-NEXT:    addi a1, a1, -1
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_trunc_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-LABEL: test_trunc_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_trunc_si64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI9_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI9_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB9_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB9_2:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI9_1)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI9_1)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFHMIN-NEXT:    fle.s s0, ft1, fs0
+; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IZFHMIN-NEXT:    call __fixsfdi@plt
+; RV32IZFHMIN-NEXT:    lui a3, 524288
+; RV32IZFHMIN-NEXT:    bnez s0, .LBB9_4
+; RV32IZFHMIN-NEXT:  # %bb.3:
+; RV32IZFHMIN-NEXT:    lui a1, 524288
+; RV32IZFHMIN-NEXT:  .LBB9_4:
+; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI9_2)
+; RV32IZFHMIN-NEXT:    flw ft0, %lo(.LCPI9_2)(a2)
+; RV32IZFHMIN-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFHMIN-NEXT:    beqz a2, .LBB9_6
+; RV32IZFHMIN-NEXT:  # %bb.5:
+; RV32IZFHMIN-NEXT:    addi a1, a3, -1
+; RV32IZFHMIN-NEXT:  .LBB9_6:
+; RV32IZFHMIN-NEXT:    feq.s a3, fs0, fs0
+; RV32IZFHMIN-NEXT:    seqz a3, a3
+; RV32IZFHMIN-NEXT:    addi a3, a3, -1
+; RV32IZFHMIN-NEXT:    and a1, a3, a1
+; RV32IZFHMIN-NEXT:    neg a4, s0
+; RV32IZFHMIN-NEXT:    and a0, a4, a0
+; RV32IZFHMIN-NEXT:    neg a2, a2
+; RV32IZFHMIN-NEXT:    or a0, a2, a0
+; RV32IZFHMIN-NEXT:    and a0, a3, a0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_trunc_si64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI9_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI9_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB9_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB9_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a1, a0
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_trunc_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_trunc_ui32:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI10_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI10_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB10_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB10_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV32IZFHMIN-NEXT:    seqz a1, a1
+; RV32IZFHMIN-NEXT:    addi a1, a1, -1
+; RV32IZFHMIN-NEXT:    and a0, a1, a0
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_trunc_ui32:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI10_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI10_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB10_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB10_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a0, a1
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_trunc_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-LABEL: test_trunc_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_trunc_ui64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI11_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI11_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB11_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB11_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFHMIN-NEXT:    fmv.w.x ft0, zero
+; RV32IZFHMIN-NEXT:    fle.s a0, ft0, fs0
+; RV32IZFHMIN-NEXT:    neg s0, a0
+; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IZFHMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI11_1)
+; RV32IZFHMIN-NEXT:    flw ft0, %lo(.LCPI11_1)(a2)
+; RV32IZFHMIN-NEXT:    and a0, s0, a0
+; RV32IZFHMIN-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFHMIN-NEXT:    neg a2, a2
+; RV32IZFHMIN-NEXT:    or a0, a2, a0
+; RV32IZFHMIN-NEXT:    and a1, s0, a1
+; RV32IZFHMIN-NEXT:    or a1, a2, a1
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_trunc_ui64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI11_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI11_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB11_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB11_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a1, a0
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_si32(half %x) {
 ; CHECKIZFH-LABEL: test_round_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_round_si32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI12_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI12_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB12_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB12_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECKIZFHMIN-NEXT:    seqz a1, a1
+; CHECKIZFHMIN-NEXT:    addi a1, a1, -1
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_round_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_round_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-LABEL: test_round_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_round_si64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI13_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI13_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB13_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB13_2:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI13_1)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI13_1)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFHMIN-NEXT:    fle.s s0, ft1, fs0
+; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IZFHMIN-NEXT:    call __fixsfdi@plt
+; RV32IZFHMIN-NEXT:    lui a3, 524288
+; RV32IZFHMIN-NEXT:    bnez s0, .LBB13_4
+; RV32IZFHMIN-NEXT:  # %bb.3:
+; RV32IZFHMIN-NEXT:    lui a1, 524288
+; RV32IZFHMIN-NEXT:  .LBB13_4:
+; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI13_2)
+; RV32IZFHMIN-NEXT:    flw ft0, %lo(.LCPI13_2)(a2)
+; RV32IZFHMIN-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFHMIN-NEXT:    beqz a2, .LBB13_6
+; RV32IZFHMIN-NEXT:  # %bb.5:
+; RV32IZFHMIN-NEXT:    addi a1, a3, -1
+; RV32IZFHMIN-NEXT:  .LBB13_6:
+; RV32IZFHMIN-NEXT:    feq.s a3, fs0, fs0
+; RV32IZFHMIN-NEXT:    seqz a3, a3
+; RV32IZFHMIN-NEXT:    addi a3, a3, -1
+; RV32IZFHMIN-NEXT:    and a1, a3, a1
+; RV32IZFHMIN-NEXT:    neg a4, s0
+; RV32IZFHMIN-NEXT:    and a0, a4, a0
+; RV32IZFHMIN-NEXT:    neg a2, a2
+; RV32IZFHMIN-NEXT:    or a0, a2, a0
+; RV32IZFHMIN-NEXT:    and a0, a3, a0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_round_si64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI13_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI13_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB13_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB13_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a1, a0
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_round_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_round_ui32:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI14_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI14_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB14_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB14_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV32IZFHMIN-NEXT:    seqz a1, a1
+; RV32IZFHMIN-NEXT:    addi a1, a1, -1
+; RV32IZFHMIN-NEXT:    and a0, a1, a0
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_round_ui32:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI14_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI14_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB14_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB14_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a0, a1
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_round_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_round_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-LABEL: test_round_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_round_ui64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI15_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI15_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB15_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB15_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFHMIN-NEXT:    fmv.w.x ft0, zero
+; RV32IZFHMIN-NEXT:    fle.s a0, ft0, fs0
+; RV32IZFHMIN-NEXT:    neg s0, a0
+; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IZFHMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI15_1)
+; RV32IZFHMIN-NEXT:    flw ft0, %lo(.LCPI15_1)(a2)
+; RV32IZFHMIN-NEXT:    and a0, s0, a0
+; RV32IZFHMIN-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFHMIN-NEXT:    neg a2, a2
+; RV32IZFHMIN-NEXT:    or a0, a2, a0
+; RV32IZFHMIN-NEXT:    and a1, s0, a1
+; RV32IZFHMIN-NEXT:    or a1, a2, a1
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_round_ui64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI15_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI15_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB15_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB15_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a1, a0
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_si32(half %x) {
 ; CHECKIZFH-LABEL: test_roundeven_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rne
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_roundeven_si32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI16_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI16_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB16_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB16_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; CHECKIZFHMIN-NEXT:    seqz a1, a1
+; CHECKIZFHMIN-NEXT:    addi a1, a1, -1
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_roundeven_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-LABEL: test_roundeven_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_roundeven_si64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI17_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI17_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB17_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB17_2:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI17_1)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI17_1)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFHMIN-NEXT:    fle.s s0, ft1, fs0
+; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IZFHMIN-NEXT:    call __fixsfdi@plt
+; RV32IZFHMIN-NEXT:    lui a3, 524288
+; RV32IZFHMIN-NEXT:    bnez s0, .LBB17_4
+; RV32IZFHMIN-NEXT:  # %bb.3:
+; RV32IZFHMIN-NEXT:    lui a1, 524288
+; RV32IZFHMIN-NEXT:  .LBB17_4:
+; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI17_2)
+; RV32IZFHMIN-NEXT:    flw ft0, %lo(.LCPI17_2)(a2)
+; RV32IZFHMIN-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFHMIN-NEXT:    beqz a2, .LBB17_6
+; RV32IZFHMIN-NEXT:  # %bb.5:
+; RV32IZFHMIN-NEXT:    addi a1, a3, -1
+; RV32IZFHMIN-NEXT:  .LBB17_6:
+; RV32IZFHMIN-NEXT:    feq.s a3, fs0, fs0
+; RV32IZFHMIN-NEXT:    seqz a3, a3
+; RV32IZFHMIN-NEXT:    addi a3, a3, -1
+; RV32IZFHMIN-NEXT:    and a1, a3, a1
+; RV32IZFHMIN-NEXT:    neg a4, s0
+; RV32IZFHMIN-NEXT:    and a0, a4, a0
+; RV32IZFHMIN-NEXT:    neg a2, a2
+; RV32IZFHMIN-NEXT:    or a0, a2, a0
+; RV32IZFHMIN-NEXT:    and a0, a3, a0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_roundeven_si64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI17_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI17_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB17_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB17_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a1, a0
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_roundeven_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rne
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_roundeven_ui32:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI18_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI18_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB18_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB18_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV32IZFHMIN-NEXT:    seqz a1, a1
+; RV32IZFHMIN-NEXT:    addi a1, a1, -1
+; RV32IZFHMIN-NEXT:    and a0, a1, a0
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_roundeven_ui32:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI18_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI18_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB18_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB18_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a0, a1
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_roundeven_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-LABEL: test_roundeven_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_roundeven_ui64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI19_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI19_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB19_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB19_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFHMIN-NEXT:    fmv.w.x ft0, zero
+; RV32IZFHMIN-NEXT:    fle.s a0, ft0, fs0
+; RV32IZFHMIN-NEXT:    neg s0, a0
+; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
+; RV32IZFHMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI19_1)
+; RV32IZFHMIN-NEXT:    flw ft0, %lo(.LCPI19_1)(a2)
+; RV32IZFHMIN-NEXT:    and a0, s0, a0
+; RV32IZFHMIN-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFHMIN-NEXT:    neg a2, a2
+; RV32IZFHMIN-NEXT:    or a0, a2, a0
+; RV32IZFHMIN-NEXT:    and a1, s0, a1
+; RV32IZFHMIN-NEXT:    or a1, a2, a1
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_roundeven_ui64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI19_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI19_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB19_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB19_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    feq.s a1, ft0, ft0
+; RV64IZFHMIN-NEXT:    seqz a1, a1
+; RV64IZFHMIN-NEXT:    addi a1, a1, -1
+; RV64IZFHMIN-NEXT:    and a0, a1, a0
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 declare half @llvm.floor.f16(half)
 declare half @llvm.ceil.f16(half)
 declare half @llvm.trunc.f16(half)
 declare half @llvm.round.f16(half)
 declare half @llvm.roundeven.f16(half)
 declare i32 @llvm.fptosi.sat.i32.f16(half)
 declare i64 @llvm.fptosi.sat.i64.f16(half)
 declare i32 @llvm.fptoui.sat.i32.f16(half)
 declare i64 @llvm.fptoui.sat.i64.f16(half)

llvm/test/CodeGen/RISCV/half-round-conv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN %s
 
 define signext i8 @test_floor_si8(half %x) {
 ; RV32IZFH-LABEL: test_floor_si8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_si8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_floor_si8:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI0_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI0_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB0_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB0_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_floor_si8:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI0_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI0_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB0_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB0_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptosi half %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_floor_si16(half %x) {
 ; RV32IZFH-LABEL: test_floor_si16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_si16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_floor_si16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI1_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB1_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB1_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_floor_si16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI1_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB1_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB1_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_floor_si32(half %x) {
 ; CHECKIZFH-LABEL: test_floor_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rdn
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_floor_si32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI2_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI2_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB2_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB2_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_floor_si64(half %x) {
 ; RV32IZFH-LABEL: test_floor_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_floor_si64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI3_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI3_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB3_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB3_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IZFHMIN-NEXT:    call __fixhfdi@plt
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_floor_si64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI3_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI3_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB3_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB3_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptosi half %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_floor_ui8(half %x) {
 ; RV32IZFH-LABEL: test_floor_ui8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_ui8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_floor_ui8:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI4_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI4_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB4_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB4_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_floor_ui8:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI4_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI4_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB4_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB4_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptoui half %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_floor_ui16(half %x) {
 ; RV32IZFH-LABEL: test_floor_ui16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_ui16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_floor_ui16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI5_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI5_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB5_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB5_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_floor_ui16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI5_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI5_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB5_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB5_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_floor_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_floor_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_floor_ui32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI6_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI6_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB6_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB6_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(half %x) {
 ; RV32IZFH-LABEL: test_floor_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_floor_ui64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI7_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI7_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB7_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB7_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IZFHMIN-NEXT:    call __fixunshfdi@plt
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_floor_ui64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI7_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI7_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB7_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB7_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptoui half %a to i64
   ret i64 %b
 }
 
 define signext i8 @test_ceil_si8(half %x) {
 ; RV32IZFH-LABEL: test_ceil_si8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rup
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_si8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_ceil_si8:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI8_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI8_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB8_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB8_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_ceil_si8:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI8_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI8_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB8_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB8_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptosi half %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_ceil_si16(half %x) {
 ; RV32IZFH-LABEL: test_ceil_si16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rup
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_si16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_ceil_si16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI9_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI9_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB9_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB9_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_ceil_si16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI9_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI9_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB9_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB9_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_ceil_si32(half %x) {
 ; CHECKIZFH-LABEL: test_ceil_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rup
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_ceil_si32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI10_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI10_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB10_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB10_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(half %x) {
 ; RV32IZFH-LABEL: test_ceil_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_ceil_si64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI11_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI11_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB11_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB11_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IZFHMIN-NEXT:    call __fixhfdi@plt
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_ceil_si64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI11_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI11_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB11_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB11_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptosi half %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_ceil_ui8(half %x) {
 ; RV32IZFH-LABEL: test_ceil_ui8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rup
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_ui8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_ceil_ui8:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI12_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI12_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB12_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB12_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_ceil_ui8:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI12_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI12_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB12_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB12_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptoui half %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_ceil_ui16(half %x) {
 ; RV32IZFH-LABEL: test_ceil_ui16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rup
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_ui16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_ceil_ui16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI13_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI13_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB13_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB13_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_ceil_ui16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI13_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI13_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB13_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB13_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_ceil_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_ceil_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rup
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_ceil_ui32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI14_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI14_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB14_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB14_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(half %x) {
 ; RV32IZFH-LABEL: test_ceil_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_ceil_ui64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI15_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI15_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB15_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB15_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IZFHMIN-NEXT:    call __fixunshfdi@plt
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_ceil_ui64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI15_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI15_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB15_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB15_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptoui half %a to i64
   ret i64 %b
 }
 
 define signext i8 @test_trunc_si8(half %x) {
 ; RV32IZFH-LABEL: test_trunc_si8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_si8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_trunc_si8:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI16_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI16_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB16_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB16_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_trunc_si8:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI16_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI16_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB16_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB16_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptosi half %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_trunc_si16(half %x) {
 ; RV32IZFH-LABEL: test_trunc_si16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_si16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_trunc_si16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI17_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI17_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB17_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB17_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_trunc_si16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI17_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI17_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB17_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB17_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_trunc_si32(half %x) {
 ; CHECKIZFH-LABEL: test_trunc_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_trunc_si32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI18_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI18_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB18_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB18_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(half %x) {
 ; RV32IZFH-LABEL: test_trunc_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_trunc_si64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI19_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI19_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB19_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB19_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IZFHMIN-NEXT:    call __fixhfdi@plt
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_trunc_si64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI19_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI19_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB19_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB19_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptosi half %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_trunc_ui8(half %x) {
 ; RV32IZFH-LABEL: test_trunc_ui8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_ui8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_trunc_ui8:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI20_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI20_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB20_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB20_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_trunc_ui8:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI20_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI20_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB20_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB20_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptoui half %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_trunc_ui16(half %x) {
 ; RV32IZFH-LABEL: test_trunc_ui16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_ui16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_trunc_ui16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI21_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI21_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB21_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB21_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_trunc_ui16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI21_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI21_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB21_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB21_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_trunc_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_trunc_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_trunc_ui32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI22_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI22_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB22_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB22_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(half %x) {
 ; RV32IZFH-LABEL: test_trunc_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_trunc_ui64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI23_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI23_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB23_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB23_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IZFHMIN-NEXT:    call __fixunshfdi@plt
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_trunc_ui64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI23_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI23_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB23_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB23_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptoui half %a to i64
   ret i64 %b
 }
 
 define signext i8 @test_round_si8(half %x) {
 ; RV32IZFH-LABEL: test_round_si8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_si8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_round_si8:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI24_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI24_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB24_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB24_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_round_si8:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI24_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI24_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB24_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB24_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptosi half %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_round_si16(half %x) {
 ; RV32IZFH-LABEL: test_round_si16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_si16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_round_si16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI25_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI25_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB25_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB25_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_round_si16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI25_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI25_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB25_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB25_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_round_si32(half %x) {
 ; CHECKIZFH-LABEL: test_round_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_round_si32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI26_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI26_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB26_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB26_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_round_si64(half %x) {
 ; RV32IZFH-LABEL: test_round_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_round_si64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI27_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI27_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB27_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB27_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IZFHMIN-NEXT:    call __fixhfdi@plt
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_round_si64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI27_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI27_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB27_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB27_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptosi half %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_round_ui8(half %x) {
 ; RV32IZFH-LABEL: test_round_ui8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_ui8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_round_ui8:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI28_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI28_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB28_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB28_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_round_ui8:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI28_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI28_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB28_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB28_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptoui half %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_round_ui16(half %x) {
 ; RV32IZFH-LABEL: test_round_ui16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_ui16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_round_ui16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI29_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI29_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB29_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB29_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_round_ui16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI29_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI29_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB29_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB29_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_round_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_round_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_round_ui32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI30_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI30_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB30_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB30_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_round_ui64(half %x) {
 ; RV32IZFH-LABEL: test_round_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_round_ui64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI31_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI31_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB31_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB31_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IZFHMIN-NEXT:    call __fixunshfdi@plt
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_round_ui64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI31_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI31_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB31_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB31_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptoui half %a to i64
   ret i64 %b
 }
 
 define signext i8 @test_roundeven_si8(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_si8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_si8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_roundeven_si8:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI32_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI32_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB32_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB32_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_roundeven_si8:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI32_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI32_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB32_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB32_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptosi half %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_roundeven_si16(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_si16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_si16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_roundeven_si16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI33_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI33_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB33_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB33_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_roundeven_si16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI33_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI33_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB33_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB33_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_roundeven_si32(half %x) {
 ; CHECKIZFH-LABEL: test_roundeven_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rne
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_roundeven_si32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI34_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI34_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB34_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB34_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_roundeven_si64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI35_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI35_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB35_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB35_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IZFHMIN-NEXT:    call __fixhfdi@plt
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_roundeven_si64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI35_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI35_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB35_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB35_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptosi half %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_roundeven_ui8(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_ui8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_ui8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_roundeven_ui8:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI36_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI36_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB36_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB36_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_roundeven_ui8:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI36_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI36_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB36_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB36_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptoui half %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_roundeven_ui16(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_ui16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_ui16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_roundeven_ui16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI37_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI37_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB37_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB37_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_roundeven_ui16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI37_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI37_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB37_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB37_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_roundeven_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_roundeven_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rne
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_roundeven_ui32:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI38_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI38_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB38_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB38_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZFHMIN-LABEL: test_roundeven_ui64:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZFHMIN-NEXT:    lui a0, %hi(.LCPI39_0)
+; RV32IZFHMIN-NEXT:    flw ft1, %lo(.LCPI39_0)(a0)
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV32IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV32IZFHMIN-NEXT:    beqz a0, .LBB39_2
+; RV32IZFHMIN-NEXT:  # %bb.1:
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV32IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV32IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV32IZFHMIN-NEXT:  .LBB39_2:
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IZFHMIN-NEXT:    call __fixunshfdi@plt
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: test_roundeven_ui64:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    lui a0, %hi(.LCPI39_0)
+; RV64IZFHMIN-NEXT:    flw ft1, %lo(.LCPI39_0)(a0)
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fabs.s ft2, ft0
+; RV64IZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; RV64IZFHMIN-NEXT:    beqz a0, .LBB39_2
+; RV64IZFHMIN-NEXT:  # %bb.1:
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; RV64IZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; RV64IZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:  .LBB39_2:
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptoui half %a to i64
   ret i64 %b
 }
 
 define half @test_floor_half(half %x) {
 ; RV32IFD-LABEL: test_floor_half:
 ; RV32IFD:       # %bb.0:

 ; CHECKIZFH-NEXT:    flt.h a0, ft1, ft0
 ; CHECKIZFH-NEXT:    beqz a0, .LBB40_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rdn
 ; CHECKIZFH-NEXT:    fcvt.h.w ft0, a0, rdn
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, ft0, fa0
 ; CHECKIZFH-NEXT:  .LBB40_2:
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_floor_half:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI40_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI40_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB40_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rdn
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rdn
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB40_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   ret half %a
 }
 
 define half @test_ceil_half(half %x) {
 ; RV32IFD-LABEL: test_ceil_half:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16

 ; CHECKIZFH-NEXT:    flt.h a0, ft1, ft0
 ; CHECKIZFH-NEXT:    beqz a0, .LBB41_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rup
 ; CHECKIZFH-NEXT:    fcvt.h.w ft0, a0, rup
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, ft0, fa0
 ; CHECKIZFH-NEXT:  .LBB41_2:
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_ceil_half:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI41_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI41_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB41_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rup
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rup
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB41_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   ret half %a
 }
 
 define half @test_trunc_half(half %x) {
 ; RV32IFD-LABEL: test_trunc_half:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16

 ; CHECKIZFH-NEXT:    flt.h a0, ft1, ft0
 ; CHECKIZFH-NEXT:    beqz a0, .LBB42_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    fcvt.h.w ft0, a0, rtz
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, ft0, fa0
 ; CHECKIZFH-NEXT:  .LBB42_2:
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_trunc_half:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI42_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI42_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB42_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rtz
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB42_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   ret half %a
 }
 
 define half @test_round_half(half %x) {
 ; RV32IFD-LABEL: test_round_half:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16

 ; CHECKIZFH-NEXT:    flt.h a0, ft1, ft0
 ; CHECKIZFH-NEXT:    beqz a0, .LBB43_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; CHECKIZFH-NEXT:    fcvt.h.w ft0, a0, rmm
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, ft0, fa0
 ; CHECKIZFH-NEXT:  .LBB43_2:
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_round_half:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI43_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI43_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB43_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rmm
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB43_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   ret half %a
 }
 
 define half @test_roundeven_half(half %x) {
 ; RV32IFD-LABEL: test_roundeven_half:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16

 ; CHECKIZFH-NEXT:    flt.h a0, ft1, ft0
 ; CHECKIZFH-NEXT:    beqz a0, .LBB44_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rne
 ; CHECKIZFH-NEXT:    fcvt.h.w ft0, a0, rne
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, ft0, fa0
 ; CHECKIZFH-NEXT:  .LBB44_2:
 ; CHECKIZFH-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: test_roundeven_half:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI44_0)
+; CHECKIZFHMIN-NEXT:    flw ft1, %lo(.LCPI44_0)(a0)
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fabs.s ft2, ft0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft2, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB44_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, ft0, rne
+; CHECKIZFHMIN-NEXT:    fcvt.s.w ft1, a0, rne
+; CHECKIZFHMIN-NEXT:    fsgnj.s ft0, ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB44_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   ret half %a
 }
 
 declare half @llvm.floor.f16(half)
 declare half @llvm.ceil.f16(half)
 declare half @llvm.trunc.f16(half)
 declare half @llvm.round.f16(half)
 declare half @llvm.roundeven.f16(half)

llvm/test/CodeGen/RISCV/half-select-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=CHECKIZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64f | FileCheck -check-prefix=CHECKIZFHMIN %s
 
 define half @select_fcmp_false(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_false:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_false:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fmv.s fa0, fa1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp false half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_oeq(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_oeq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa1
 ; CHECK-NEXT:    bnez a0, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_oeq:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    feq.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    bnez a0, .LBB1_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fmv.s ft0, ft1
+; CHECKIZFHMIN-NEXT:  .LBB1_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp oeq half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ogt(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ogt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa1, fa0
 ; CHECK-NEXT:    bnez a0, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB2_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_ogt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    bnez a0, .LBB2_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fmv.s ft0, ft1
+; CHECKIZFHMIN-NEXT:  .LBB2_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ogt half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_oge(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_oge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa0
 ; CHECK-NEXT:    bnez a0, .LBB3_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB3_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_oge:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fle.s a0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    bnez a0, .LBB3_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fmv.s ft0, ft1
+; CHECKIZFHMIN-NEXT:  .LBB3_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp oge half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_olt(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_olt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    bnez a0, .LBB4_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB4_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_olt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    bnez a0, .LBB4_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fmv.s ft0, ft1
+; CHECKIZFHMIN-NEXT:  .LBB4_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp olt half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ole(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ole:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
 ; CHECK-NEXT:    bnez a0, .LBB5_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB5_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_ole:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fle.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    bnez a0, .LBB5_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fmv.s ft0, ft1
+; CHECKIZFHMIN-NEXT:  .LBB5_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ole half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_one(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_one:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    flt.h a1, fa1, fa0
 ; CHECK-NEXT:    or a0, a1, a0
 ; CHECK-NEXT:    bnez a0, .LBB6_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB6_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_one:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    flt.s a1, ft1, ft0
+; CHECKIZFHMIN-NEXT:    or a0, a1, a0
+; CHECKIZFHMIN-NEXT:    bnez a0, .LBB6_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fmv.s ft0, ft1
+; CHECKIZFHMIN-NEXT:  .LBB6_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp one half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ord(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ord:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa1, fa1
 ; CHECK-NEXT:    feq.h a1, fa0, fa0
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    bnez a0, .LBB7_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB7_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_ord:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    feq.s a0, ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    feq.s a1, ft1, ft1
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    bnez a0, .LBB7_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fmv.s ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB7_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ord half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ueq(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ueq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    flt.h a1, fa1, fa0
 ; CHECK-NEXT:    or a0, a1, a0
 ; CHECK-NEXT:    beqz a0, .LBB8_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB8_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_ueq:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    flt.s a1, ft1, ft0
+; CHECKIZFHMIN-NEXT:    or a0, a1, a0
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB8_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fmv.s ft0, ft1
+; CHECKIZFHMIN-NEXT:  .LBB8_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ueq half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ugt(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ugt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
 ; CHECK-NEXT:    beqz a0, .LBB9_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB9_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_ugt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fle.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB9_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fmv.s ft0, ft1
+; CHECKIZFHMIN-NEXT:  .LBB9_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_uge(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    beqz a0, .LBB10_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB10_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_uge:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB10_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fmv.s ft0, ft1
+; CHECKIZFHMIN-NEXT:  .LBB10_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp uge half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ult(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ult:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa0
 ; CHECK-NEXT:    beqz a0, .LBB11_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB11_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_ult:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fle.s a0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB11_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fmv.s ft0, ft1
+; CHECKIZFHMIN-NEXT:  .LBB11_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ult half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ule(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ule:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa1, fa0
 ; CHECK-NEXT:    beqz a0, .LBB12_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB12_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_ule:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    flt.s a0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB12_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fmv.s ft0, ft1
+; CHECKIZFHMIN-NEXT:  .LBB12_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ule half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_une(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_une:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa1
 ; CHECK-NEXT:    beqz a0, .LBB13_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB13_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_une:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    feq.s a0, ft0, ft1
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB13_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fmv.s ft0, ft1
+; CHECKIZFHMIN-NEXT:  .LBB13_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp une half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_uno(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uno:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa1, fa1
 ; CHECK-NEXT:    feq.h a1, fa0, fa0
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    beqz a0, .LBB14_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB14_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_uno:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    feq.s a0, ft0, ft0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    feq.s a1, ft1, ft1
+; CHECKIZFHMIN-NEXT:    and a0, a1, a0
+; CHECKIZFHMIN-NEXT:    beqz a0, .LBB14_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fmv.s ft1, ft0
+; CHECKIZFHMIN-NEXT:  .LBB14_2:
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp uno half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_true(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_true:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_true:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp true half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 ; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
 define i32 @i32_select_fcmp_oeq(half %a, half %b, i32 %c, i32 %d) nounwind {
 ; CHECK-LABEL: i32_select_fcmp_oeq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a2, fa0, fa1
 ; CHECK-NEXT:    bnez a2, .LBB16_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a0, a1
 ; CHECK-NEXT:  .LBB16_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: i32_select_fcmp_oeq:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    feq.s a2, ft1, ft0
+; CHECKIZFHMIN-NEXT:    bnez a2, .LBB16_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    mv a0, a1
+; CHECKIZFHMIN-NEXT:  .LBB16_2:
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp oeq half %a, %b
   %2 = select i1 %1, i32 %c, i32 %d
   ret i32 %2
 }
 
 define i32 @select_fcmp_oeq_1_2(half %a, half %b) {
 ; CHECK-LABEL: select_fcmp_oeq_1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa1
 ; CHECK-NEXT:    li a1, 2
 ; CHECK-NEXT:    sub a0, a1, a0
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_oeq_1_2:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    feq.s a0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    li a1, 2
+; CHECKIZFHMIN-NEXT:    sub a0, a1, a0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp fast oeq half %a, %b
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_negone_zero(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_negone_zero:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
 ; CHECK-NEXT:    addi a0, a0, -1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_uge_negone_zero:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fle.s a0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    addi a0, a0, -1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = select i1 %1, i32 -1, i32 0
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_1_2(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_fcmp_uge_1_2:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; CHECKIZFHMIN-NEXT:    fle.s a0, ft1, ft0
+; CHECKIZFHMIN-NEXT:    addi a0, a0, 1
+; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/half-select-icmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=CHECKIZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64f | FileCheck -check-prefix=CHECKIZFHMIN %s
 
 define half @select_icmp_eq(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_eq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    beq a0, a1, .LBB0_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_icmp_eq:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    beq a0, a1, .LBB0_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZFHMIN-NEXT:  .LBB0_2:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = icmp eq i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_ne(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_ne:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bne a0, a1, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_icmp_ne:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    bne a0, a1, .LBB1_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZFHMIN-NEXT:  .LBB1_2:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = icmp ne i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_ugt(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_ugt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bltu a1, a0, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB2_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_icmp_ugt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    bltu a1, a0, .LBB2_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZFHMIN-NEXT:  .LBB2_2:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = icmp ugt i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_uge(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_uge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bgeu a0, a1, .LBB3_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB3_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_icmp_uge:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    bgeu a0, a1, .LBB3_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZFHMIN-NEXT:  .LBB3_2:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = icmp uge i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_ult(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_ult:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bltu a0, a1, .LBB4_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB4_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_icmp_ult:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    bltu a0, a1, .LBB4_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZFHMIN-NEXT:  .LBB4_2:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = icmp ult i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_ule(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_ule:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bgeu a1, a0, .LBB5_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB5_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_icmp_ule:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    bgeu a1, a0, .LBB5_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZFHMIN-NEXT:  .LBB5_2:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = icmp ule i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_sgt(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_sgt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    blt a1, a0, .LBB6_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB6_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_icmp_sgt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    blt a1, a0, .LBB6_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZFHMIN-NEXT:  .LBB6_2:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = icmp sgt i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_sge(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_sge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bge a0, a1, .LBB7_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB7_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_icmp_sge:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    bge a0, a1, .LBB7_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZFHMIN-NEXT:  .LBB7_2:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = icmp sge i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_slt(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_slt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    blt a0, a1, .LBB8_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB8_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_icmp_slt:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    blt a0, a1, .LBB8_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZFHMIN-NEXT:  .LBB8_2:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = icmp slt i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_sle(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_sle:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bge a1, a0, .LBB9_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB9_2:
 ; CHECK-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_icmp_sle:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    bge a1, a0, .LBB9_2
+; CHECKIZFHMIN-NEXT:  # %bb.1:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZFHMIN-NEXT:  .LBB9_2:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; CHECKIZFHMIN-NEXT:    ret
   %1 = icmp sle i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }

llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi lp64f -disable-strictnode-mutation < %s | \
+; RUN:   FileCheck %s -check-prefix=RV64IZFHMIN
+
+; This file exhaustively checks half<->i32 conversions.
+
+define i32 @aext_fptosi(half %a) nounwind {
+; RV64IZFHMIN-LABEL: aext_fptosi:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
+  ret i32 %1
+}
+declare i32 @llvm.experimental.constrained.fptosi.i32.f16(half, metadata)
+
+define signext i32 @sext_fptosi(half %a) nounwind {
+; RV64IZFHMIN-LABEL: sext_fptosi:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
+  ret i32 %1
+}
+
+define zeroext i32 @zext_fptosi(half %a) nounwind {
+; RV64IZFHMIN-LABEL: zext_fptosi:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    slli a0, a0, 32
+; RV64IZFHMIN-NEXT:    srli a0, a0, 32
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
+  ret i32 %1
+}
+
+define i32 @aext_fptoui(half %a) nounwind {
+; RV64IZFHMIN-LABEL: aext_fptoui:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
+  ret i32 %1
+}
+declare i32 @llvm.experimental.constrained.fptoui.i32.f16(half, metadata)
+
+define signext i32 @sext_fptoui(half %a) nounwind {
+; RV64IZFHMIN-LABEL: sext_fptoui:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
+  ret i32 %1
+}
+
+define zeroext i32 @zext_fptoui(half %a) nounwind {
+; RV64IZFHMIN-LABEL: zext_fptoui:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
+  ret i32 %1
+}
+
+define half @uitofp_aext_i32_to_f16(i32 %a) nounwind {
+; RV64IZFHMIN-LABEL: uitofp_aext_i32_to_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    slli a0, a0, 32
+; RV64IZFHMIN-NEXT:    srli a0, a0, 32
+; RV64IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+  ret half %1
+}
+declare half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata, metadata)
+
+define half @uitofp_sext_i32_to_f16(i32 signext %a) nounwind {
+; RV64IZFHMIN-LABEL: uitofp_sext_i32_to_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    slli a0, a0, 32
+; RV64IZFHMIN-NEXT:    srli a0, a0, 32
+; RV64IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+  ret half %1
+}
+
+define half @uitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
+; RV64IZFHMIN-LABEL: uitofp_zext_i32_to_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+  ret half %1
+}
+
+define half @sitofp_aext_i32_to_f16(i32 %a) nounwind {
+; RV64IZFHMIN-LABEL: sitofp_aext_i32_to_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    sext.w a0, a0
+; RV64IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+  ret half %1
+}
+declare half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata, metadata)
+
+define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind {
+; RV64IZFHMIN-LABEL: sitofp_sext_i32_to_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+  ret half %1
+}
+
+define half @sitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
+; RV64IZFHMIN-LABEL: sitofp_zext_i32_to_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    sext.w a0, a0
+; RV64IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+  ret half %1
+}

llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
+; RUN:   -target-abi lp64f < %s | FileCheck %s -check-prefix=RV64IZFHMIN
+
+; This file exhaustively checks half<->i32 conversions.
+
+define i32 @aext_fptosi(half %a) nounwind {
+; RV64IZFHMIN-LABEL: aext_fptosi:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
+  %1 = fptosi half %a to i32
+  ret i32 %1
+}
+
+define signext i32 @sext_fptosi(half %a) nounwind {
+; RV64IZFHMIN-LABEL: sext_fptosi:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
+  %1 = fptosi half %a to i32
+  ret i32 %1
+}
+
+define zeroext i32 @zext_fptosi(half %a) nounwind {
+; RV64IZFHMIN-LABEL: zext_fptosi:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    slli a0, a0, 32
+; RV64IZFHMIN-NEXT:    srli a0, a0, 32
+; RV64IZFHMIN-NEXT:    ret
+  %1 = fptosi half %a to i32
+  ret i32 %1
+}
+
+define i32 @aext_fptoui(half %a) nounwind {
+; RV64IZFHMIN-LABEL: aext_fptoui:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
+  %1 = fptoui half %a to i32
+  ret i32 %1
+}
+
+define signext i32 @sext_fptoui(half %a) nounwind {
+; RV64IZFHMIN-LABEL: sext_fptoui:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
+  %1 = fptoui half %a to i32
+  ret i32 %1
+}
+
+define zeroext i32 @zext_fptoui(half %a) nounwind {
+; RV64IZFHMIN-LABEL: zext_fptoui:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IZFHMIN-NEXT:    ret
+  %1 = fptoui half %a to i32
+  ret i32 %1
+}
+
+define i16 @bcvt_f16_to_aext_i16(half %a, half %b) nounwind {
+; RV64IZFHMIN-LABEL: bcvt_f16_to_aext_i16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV64IZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fmv.x.h a0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = fadd half %a, %b
+  %2 = bitcast half %1 to i16
+  ret i16 %2
+}
+
+define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind {
+; RV64IZFHMIN-LABEL: bcvt_f16_to_sext_i16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV64IZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fmv.x.h a0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = fadd half %a, %b
+  %2 = bitcast half %1 to i16
+  ret i16 %2
+}
+
+define zeroext i16 @bcvt_f16_to_zext_i16(half %a, half %b) nounwind {
+; RV64IZFHMIN-LABEL: bcvt_f16_to_zext_i16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, fa0
+; RV64IZFHMIN-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IZFHMIN-NEXT:    fcvt.h.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fmv.x.h a0, ft0
+; RV64IZFHMIN-NEXT:    slli a0, a0, 48
+; RV64IZFHMIN-NEXT:    srli a0, a0, 48
+; RV64IZFHMIN-NEXT:    ret
+  %1 = fadd half %a, %b
+  %2 = bitcast half %1 to i16
+  ret i16 %2
+}
+
+define half @bcvt_i64_to_f16_via_i16(i64 %a, i64 %b) nounwind {
+; RV64IZFHMIN-LABEL: bcvt_i64_to_f16_via_i16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fmv.h.x ft0, a0
+; RV64IZFHMIN-NEXT:    fmv.h.x ft1, a1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, ft1
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, ft0
+; RV64IZFHMIN-NEXT:    fadd.s ft0, ft0, ft1
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = trunc i64 %a to i16
+  %2 = trunc i64 %b to i16
+  %3 = bitcast i16 %1 to half
+  %4 = bitcast i16 %2 to half
+  %5 = fadd half %3, %4
+  ret half %5
+}
+
+define half @uitofp_aext_i32_to_f16(i32 %a) nounwind {
+; RV64IZFHMIN-LABEL: uitofp_aext_i32_to_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    slli a0, a0, 32
+; RV64IZFHMIN-NEXT:    srli a0, a0, 32
+; RV64IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = uitofp i32 %a to half
+  ret half %1
+}
+
+define half @uitofp_sext_i32_to_f16(i32 signext %a) nounwind {
+; RV64IZFHMIN-LABEL: uitofp_sext_i32_to_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    slli a0, a0, 32
+; RV64IZFHMIN-NEXT:    srli a0, a0, 32
+; RV64IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = uitofp i32 %a to half
+  ret half %1
+}
+
+define half @uitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
+; RV64IZFHMIN-LABEL: uitofp_zext_i32_to_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.lu ft0, a0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = uitofp i32 %a to half
+  ret half %1
+}
+
+define half @sitofp_aext_i32_to_f16(i32 %a) nounwind {
+; RV64IZFHMIN-LABEL: sitofp_aext_i32_to_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    sext.w a0, a0
+; RV64IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = sitofp i32 %a to half
+  ret half %1
+}
+
+define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind {
+; RV64IZFHMIN-LABEL: sitofp_sext_i32_to_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = sitofp i32 %a to half
+  ret half %1
+}
+
+define half @sitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
+; RV64IZFHMIN-LABEL: sitofp_zext_i32_to_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    sext.w a0, a0
+; RV64IZFHMIN-NEXT:    fcvt.s.l ft0, a0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = sitofp i32 %a to half
+  ret half %1
+}

llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+zfhmin \
+; RUN:   -verify-machineinstrs -target-abi lp64f | \
+; RUN:   FileCheck -check-prefix=CHECKIZFHMIN %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+d \
+; RUN:   -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d | \
+; RUN:   FileCheck -check-prefix=CHECKIZFHMIN %s
+
+; These intrinsics require half and i64 to be legal types.
+
+declare i64 @llvm.llrint.i64.f16(half)
+
+define i64 @llrint_f16(half %a) nounwind {
+; CHECKIZFHMIN-LABEL: llrint_f16:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.l.s a0, ft0
+; CHECKIZFHMIN-NEXT:    ret
+  %1 = call i64 @llvm.llrint.i64.f16(half %a)
+  ret i64 %1
+}
+
+declare i64 @llvm.llround.i64.f16(half)
+
+define i64 @llround_f16(half %a) nounwind {
+; CHECKIZFHMIN-LABEL: llround_f16:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.l.s a0, ft0, rmm
+; CHECKIZFHMIN-NEXT:    ret
+  %1 = call i64 @llvm.llround.i64.f16(half %a)
+  ret i64 %1
+}

llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfhmin \
+; RUN:   -verify-machineinstrs -target-abi ilp32f -disable-strictnode-mutation \
+; RUN:   | FileCheck -check-prefix=RV32IZFHMIN %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfhmin \
+; RUN:   -verify-machineinstrs -target-abi lp64f -disable-strictnode-mutation \
+; RUN:   | FileCheck -check-prefix=RV64IZFHMIN %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
+; RUN:   -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32d \
+; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32IZFHMIN %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
+; RUN:   -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d \
+; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64IZFHMIN %s
+
+declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata)
+
+define half @sqrt_f16(half %a) nounwind strictfp {
+; RV32IZFHMIN-LABEL: sqrt_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fsqrt.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: sqrt_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fsqrt.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+  ret half %1
+}
+
+declare half @llvm.experimental.constrained.floor.f16(half, metadata)
+
+define half @floor_f16(half %a) nounwind strictfp {
+; RV32IZFHMIN-LABEL: floor_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call floorf@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: floor_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call floorf@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call half @llvm.experimental.constrained.floor.f16(half %a, metadata !"fpexcept.strict") strictfp
+  ret half %1
+}
+
+declare half @llvm.experimental.constrained.ceil.f16(half, metadata)
+
+define half @ceil_f16(half %a) nounwind strictfp {
+; RV32IZFHMIN-LABEL: ceil_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call ceilf@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: ceil_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call ceilf@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call half @llvm.experimental.constrained.ceil.f16(half %a, metadata !"fpexcept.strict") strictfp
+  ret half %1
+}
+
+declare half @llvm.experimental.constrained.trunc.f16(half, metadata)
+
+define half @trunc_f16(half %a) nounwind strictfp {
+; RV32IZFHMIN-LABEL: trunc_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call truncf@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: trunc_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call truncf@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call half @llvm.experimental.constrained.trunc.f16(half %a, metadata !"fpexcept.strict") strictfp
+  ret half %1
+}
+
+declare half @llvm.experimental.constrained.rint.f16(half, metadata, metadata)
+
+define half @rint_f16(half %a) nounwind strictfp {
+; RV32IZFHMIN-LABEL: rint_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call rintf@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: rint_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call rintf@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call half @llvm.experimental.constrained.rint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+  ret half %1
+}
+
+declare half @llvm.experimental.constrained.nearbyint.f16(half, metadata, metadata)
+
+define half @nearbyint_f16(half %a) nounwind strictfp {
+; RV32IZFHMIN-LABEL: nearbyint_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call nearbyintf@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: nearbyint_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call nearbyintf@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call half @llvm.experimental.constrained.nearbyint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+  ret half %1
+}
+
+declare half @llvm.experimental.constrained.round.f16(half, metadata)
+
+define half @round_f16(half %a) nounwind strictfp {
+; RV32IZFHMIN-LABEL: round_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call roundf@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: round_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call roundf@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call half @llvm.experimental.constrained.round.f16(half %a, metadata !"fpexcept.strict") strictfp
+  ret half %1
+}
+
+declare half @llvm.experimental.constrained.roundeven.f16(half, metadata)
+
+define half @roundeven_f16(half %a) nounwind strictfp {
+; RV32IZFHMIN-LABEL: roundeven_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call roundevenf@plt
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: roundeven_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    addi sp, sp, -16
+; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT:    call roundevenf@plt
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT:    addi sp, sp, 16
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call half @llvm.experimental.constrained.roundeven.f16(half %a, metadata !"fpexcept.strict") strictfp
+  ret half %1
+}
+
+declare iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half, metadata, metadata)
+
+define iXLen @lrint_f16(half %a) nounwind strictfp {
+; RV32IZFHMIN-LABEL: lrint_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: lrint_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+  ret iXLen %1
+}
+
+declare iXLen @llvm.experimental.constrained.lround.iXLen.f16(half, metadata)
+
+define iXLen @lround_f16(half %a) nounwind strictfp {
+; RV32IZFHMIN-LABEL: lround_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: lround_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rmm
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f16(half %a, metadata !"fpexcept.strict") strictfp
+  ret iXLen %1
+}
+
+declare i64 @llvm.experimental.constrained.llrint.i64.f16(half, metadata, metadata)
+
+define i64 @llrint_f16(half %a) nounwind strictfp {
+; RV32IZFHMIN-LABEL: llrint_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call llrintf@plt
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: llrint_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call i64 @llvm.experimental.constrained.llrint.i64.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+  ret i64 %1
+}
+
+declare i64 @llvm.experimental.constrained.llround.i64.f16(half, metadata)
+
+define i64 @llround_f16(half %a) nounwind strictfp {
+; RV32IZFHMIN-LABEL: llround_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    addi sp, sp, -16
+; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT:    call llroundf@plt
+; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    addi sp, sp, 16
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: llround_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rmm
+; RV64IZFHMIN-NEXT:    ret
+  %1 = call i64 @llvm.experimental.constrained.llround.i64.f16(half %a, metadata !"fpexcept.strict") strictfp
+  ret i64 %1
+}

llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfhmin \
+; RUN:   -verify-machineinstrs -target-abi ilp32f | \
+; RUN:   FileCheck -check-prefix=RV32IZFHMIN %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfhmin \
+; RUN:   -verify-machineinstrs -target-abi lp64f | \
+; RUN:   FileCheck -check-prefix=RV64IZFHMIN %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
+; RUN:   -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32d | \
+; RUN:   FileCheck -check-prefix=RV32IDZFHMIN %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
+; RUN:   -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d | \
+; RUN:   FileCheck -check-prefix=RV64IDZFHMIN %s
+
+; These intrinsics require half to be a legal type.
+
+declare iXLen @llvm.lrint.iXLen.f16(half)
+
+define iXLen @lrint_f16(half %a) nounwind {
+; RV32IZFHMIN-LABEL: lrint_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: lrint_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0
+; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IDZFHMIN-LABEL: lrint_f16:
+; RV32IDZFHMIN:       # %bb.0:
+; RV32IDZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IDZFHMIN-NEXT:    fcvt.w.s a0, ft0
+; RV32IDZFHMIN-NEXT:    ret
+;
+; RV64IDZFHMIN-LABEL: lrint_f16:
+; RV64IDZFHMIN:       # %bb.0:
+; RV64IDZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IDZFHMIN-NEXT:    fcvt.l.s a0, ft0
+; RV64IDZFHMIN-NEXT:    ret
+  %1 = call iXLen @llvm.lrint.iXLen.f16(half %a)
+  ret iXLen %1
+}
+
+declare iXLen @llvm.lround.iXLen.f16(half)
+
+define iXLen @lround_f16(half %a) nounwind {
+; RV32IZFHMIN-LABEL: lround_f16:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: lround_f16:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IZFHMIN-NEXT:    fcvt.l.s a0, ft0, rmm
+; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IDZFHMIN-LABEL: lround_f16:
+; RV32IDZFHMIN:       # %bb.0:
+; RV32IDZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV32IDZFHMIN-NEXT:    fcvt.w.s a0, ft0, rmm
+; RV32IDZFHMIN-NEXT:    ret
+;
+; RV64IDZFHMIN-LABEL: lround_f16:
+; RV64IDZFHMIN:       # %bb.0:
+; RV64IDZFHMIN-NEXT:    fcvt.s.h ft0, fa0
+; RV64IDZFHMIN-NEXT:    fcvt.l.s a0, ft0, rmm
+; RV64IDZFHMIN-NEXT:    ret
+  %1 = call iXLen @llvm.lround.iXLen.f16(half %a)
+  ret iXLen %1
+}

llvm/test/CodeGen/RISCV/zfhmin-imm.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfhmin < %s \
+; RUN:     | FileCheck --check-prefix=RV32IZFHMIN %s
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zfhmin,+d < %s \
+; RUN:     | FileCheck --check-prefix=RV32IDZFHMIN %s
+; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfhmin < %s \
+; RUN:     | FileCheck --check-prefix=RV64IZFHMIN %s
+; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+zfhmin,+d < %s \
+; RUN:     | FileCheck --check-prefix=RV64IDZFHMIN %s
+
+define half @f16_positive_zero(half *%pf) nounwind {
+; RV32IZFHMIN-LABEL: f16_positive_zero:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fmv.h.x fa0, zero
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV32IDZFHMIN-LABEL: f16_positive_zero:
+; RV32IDZFHMIN:       # %bb.0:
+; RV32IDZFHMIN-NEXT:    fmv.h.x fa0, zero
+; RV32IDZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: f16_positive_zero:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fmv.h.x fa0, zero
+; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IDZFHMIN-LABEL: f16_positive_zero:
+; RV64IDZFHMIN:       # %bb.0:
+; RV64IDZFHMIN-NEXT:    fmv.h.x fa0, zero
+; RV64IDZFHMIN-NEXT:    ret
+  ret half 0.0
+}
+
+define half @f16_negative_zero(half *%pf) nounwind {
+; RV32IZFHMIN-LABEL: f16_negative_zero:
+; RV32IZFHMIN:       # %bb.0:
+; RV32IZFHMIN-NEXT:    fmv.w.x ft0, zero
+; RV32IZFHMIN-NEXT:    fneg.s ft0, ft0
+; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IZFHMIN-NEXT:    ret
+;
+; RV32IDZFHMIN-LABEL: f16_negative_zero:
+; RV32IDZFHMIN:       # %bb.0:
+; RV32IDZFHMIN-NEXT:    fmv.w.x ft0, zero
+; RV32IDZFHMIN-NEXT:    fneg.s ft0, ft0
+; RV32IDZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV32IDZFHMIN-NEXT:    ret
+;
+; RV64IZFHMIN-LABEL: f16_negative_zero:
+; RV64IZFHMIN:       # %bb.0:
+; RV64IZFHMIN-NEXT:    fmv.w.x ft0, zero
+; RV64IZFHMIN-NEXT:    fneg.s ft0, ft0
+; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IDZFHMIN-LABEL: f16_negative_zero:
+; RV64IDZFHMIN:       # %bb.0:
+; RV64IDZFHMIN-NEXT:    fmv.w.x ft0, zero
+; RV64IDZFHMIN-NEXT:    fneg.s ft0, ft0
+; RV64IDZFHMIN-NEXT:    fcvt.h.s fa0, ft0
+; RV64IDZFHMIN-NEXT:    ret
+  ret half -0.0
+}