[RISCV][CodeGen] Support Zfinx,Zdinx,Zhinx,Zhinxmin codegen

[sunshaoce]

Summary

Co-Author: @liaolucy @realqhc

[sunshaoce]

Support float-arith in RV64 Zfinx

[sunshaoce]

Add abi info in test files

[sunshaoce]

Rebase

[hughperkins]

Note: I get a crash when I try to compile some LLVM IR. Crash trace:

$ bin/llc --march riscv32 -mattr +zfinx test.ll
LLVM ERROR: Cannot select: t8: ch = store<(store (s32) into %ir.4)> t7, t4, t6, undef:i32
  t4: f32,ch = load<(dereferenceable load (s32) from %ir.2)> t0, FrameIndex:i32<1>, undef:i32
    t1: i32 = FrameIndex<1>
    t3: i32 = undef
  t6: i32,ch = load<(dereferenceable load (s32) from %ir.1, align 8)> t0, FrameIndex:i32<0>, undef:i32
    t5: i32 = FrameIndex<0>
    t3: i32 = undef
  t3: i32 = undef
In function: _Z10sum_floatsPfjS_
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.	Program arguments: bin/llc --march riscv32 -mattr +zfinx test.ll
1.	Running pass 'Function Pass Manager' on module 'test.ll'.
2.	Running pass 'RISCV DAG->DAG Pattern Instruction Selection' on function '@_Z10sum_floatsPfjS_'
Stack dump without symbol names (ensure you have llvm-symbolizer in your PATH or set the environment var `LLVM_SYMBOLIZER_PATH` to point to it):
0  llc                      0x000000010974962d llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) + 61
1  llc                      0x0000000109749bdb PrintStackTraceSignalHandler(void*) + 27
2  llc                      0x000000010974785b llvm::sys::RunSignalHandlers() + 139
3  llc                      0x000000010974b7d8 SignalHandler(int) + 232
4  libsystem_platform.dylib 0x00007fff206e5d7d _sigtramp + 29
5  libsystem_platform.dylib 000000000000000000 _sigtramp + 18446603339972059808
6  libsystem_c.dylib        0x00007fff205f5406 abort + 125
7  llc                      0x00000001095aae4a llvm::report_fatal_error(llvm::Twine const&, bool) + 394
8  llc                      0x0000000109432305 llvm::SelectionDAGISel::CannotYetSelect(llvm::SDNode*) + 725
9  llc                      0x000000010942dd72 llvm::SelectionDAGISel::SelectCodeCommon(llvm::SDNode*, unsigned char const*, unsigned int) + 26690
10 llc                      0x0000000106faec6c llvm::RISCVDAGToDAGISel::SelectCode(llvm::SDNode*) + 44
11 llc                      0x0000000106fade73 llvm::RISCVDAGToDAGISel::Select(llvm::SDNode*) + 31299
12 llc                      0x000000010941e7fd llvm::SelectionDAGISel::DoInstructionSelection() + 1629
13 llc                      0x000000010941cf4d llvm::SelectionDAGISel::CodeGenAndEmitDAG() + 6205
14 llc                      0x000000010941b56f llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::Instruction, true, false, void>, false, true>, llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::Instruction, true, false, void>, false, true>, bool&) + 399
15 llc                      0x0000000109419649 llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) + 6329
16 llc                      0x0000000109415d2c llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) + 2268
17 llc                      0x0000000106fb0668 llvm::RISCVDAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&) + 56
18 llc                      0x0000000107cc0dcd llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 541
19 llc                      0x0000000108645dbc llvm::FPPassManager::runOnFunction(llvm::Function&) + 700
20 llc                      0x000000010864dce5 llvm::FPPassManager::runOnModule(llvm::Module&) + 117
21 llc                      0x0000000108646784 (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) + 772
22 llc                      0x00000001086462a8 llvm::legacy::PassManagerImpl::run(llvm::Module&) + 296
23 llc                      0x000000010864e081 llvm::legacy::PassManager::run(llvm::Module&) + 33
24 llc                      0x0000000106eeba16 compileModule(char**, llvm::LLVMContext&) + 6742
25 llc                      0x0000000106ee977d main + 1501
26 libdyld.dylib            0x00007fff206bbf3d start + 1
27 libdyld.dylib            0x0000000000000006 start + 18446603339972231370
Abort trap: 6

Corresponding LLVM IR:

define dso_local void @_Z10sum_floatsPfjS_() #0 {
  %1 = alloca float*, align 8
  %2 = alloca float, align 4
  %3 = load float, float* %2, align 4
  %4 = load float*, float** %1, align 8
  store float %3, float* %4, align 4
  ret void
}

(Note that it compiles just fine with +f (but using float registers...), or with nothing (but uses softwawre emulation for the fadd)

(Edited to shorten llvm ir code a lot :) )

[hughperkins]

Ok, I've since learned that this PR doesnt handle load/store. Only arithmetic.

However note that immediate float arithmetic also seems to be missing, e.g. the following crashes

define noundef float @_Z4funcf(float noundef %0) #0 {
  %2 = fadd float %0, 3.000000e+00
  ret float %2
}

Compiled with:

bin/llc --march riscv32 -mattr +zfinx test_fadd_imm.ll

Gives:

LLVM ERROR: Cannot select: t15: f32,ch = load<(load (s32) from constant-pool)> t0, t19, undef:i32
  t19: i32 = ADDI t18, TargetConstantPool:i32<float 3.000000e+00> 0 [TF=3]
    t18: i32 = LUI TargetConstantPool:i32<float 3.000000e+00> 0 [TF=4]
      t16: i32 = TargetConstantPool<float 3.000000e+00> 0 [TF=4]
    t17: i32 = TargetConstantPool<float 3.000000e+00> 0 [TF=3]
  t14: i32 = undef
In function: _Z4funcf

(but compiles ok with +f)

[hughperkins]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

544

I think it's confusing that FINX in this context means F and F_INX. I feel it might be good to make more explicit that FINX includes F. How to do that is an open question. I'd suggest FFINX, but FFINX is already taken to mean FF with FF_INX. Maybe we need an explicit acronym to mean 'F and F_INX', like e.g. 'ALLF'. Or perhaps use a verbose form like 'F_AND_FINX'? (If it was my own decision I'd go for the explicit F_AND_FINX)

[hughperkins]

Also, not really part of this PR, but I don't know where else to put this. This code:

def FF        : ExtInfo_rr<FExt,       FPR32,    FPR32>;
def FF_INX    : ExtInfo_rr<ZfinxExt,   FPR32INX, FPR32INX>;
def FX        : ExtInfo_rr<FExt,       FPR32,    GPR>;
def FX_INX    : ExtInfo_rr<ZfinxExt,   FPR32INX, GPR>;
def FX_64     : ExtInfo_rr<F64Ext,     FPR32,    GPR>;
def FX_INX_64 : ExtInfo_rr<Zfinx64Ext, FPR32INX, GPR>;
def XF        : ExtInfo_rr<FExt,       GPR,      FPR32>;
def XF_64     : ExtInfo_rr<F64Ext,     GPR,      FPR32>;
def XF_INX    : ExtInfo_rr<ZfinxExt,   GPR,      FPR32INX>;
def XF_INX_64 : ExtInfo_rr<Zfinx64Ext, GPR,      FPR32INX>;

... I feel it would be good to add a docstring explaining what this is, like e.g. something like:

Each of these definitions represents a single combination of register spaces.
For example, `FX` means that the destination register is a float register (`FPR32`), e.g. `ft1`,
and that the source register is a general `x` register (`GPR`), e.g. `x1`.
The `_INX` versions are for the `+zfinx` extension. In this case, `FPR32INX` is effectively a synonym in practice
for `GPR`. At least `FPR32INX` are emitted as general `x` registers, even though they 'look like' float registers
for much of the tablegen process.

[sunshaoce]

In D122918#3447845, @hughperkins wrote:

Ok, I've since learned that this PR doesnt handle load/store. Only arithmetic.

However note that immediate float arithmetic also seems to be missing, e.g. the following crashes

define noundef float @_Z4funcf(float noundef %0) #0 {
  %2 = fadd float %0, 3.000000e+00
  ret float %2
}

Compiled with:

bin/llc --march riscv32 -mattr +zfinx test_fadd_imm.ll

Gives:

LLVM ERROR: Cannot select: t15: f32,ch = load<(load (s32) from constant-pool)> t0, t19, undef:i32
  t19: i32 = ADDI t18, TargetConstantPool:i32<float 3.000000e+00> 0 [TF=3]
    t18: i32 = LUI TargetConstantPool:i32<float 3.000000e+00> 0 [TF=4]
      t16: i32 = TargetConstantPool<float 3.000000e+00> 0 [TF=4]
    t17: i32 = TargetConstantPool<float 3.000000e+00> 0 [TF=3]
  t14: i32 = undef
In function: _Z4funcf

(but compiles ok with +f)

Thanks, I'll try to fix it.

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

544

Your suggestion is very good, but I think FINX should be replaced with a shorter name because it appears as a parameter, eg F_INX. And consider changing the name of F_INX to FprINX. Would you like to submit a new patch about this?

[hughperkins]

In D122918#3447973, @sunshaoce wrote:

Thanks, I'll try to fix it.

Awesome :) Thank you :)

[hughperkins]

As a general comment, after thinking about this whilst brushing my teeth, I kind of feel that it might be clearer and simpler for everyone, both F people and Zfinx people, if we decoupled F and Zfinx into two separate files. This way F people don't have to figure out what is Zfinx. They just keep their clean separate F file. and Zfinx people dont have to think about how our bits mangle with F bits. Yes involves a bit of duplication, but if it's clearer/cleaner for everyone, maybe it might be a good approach?

After all, Zfinx is not an extension of F. It's a separate, mutually incompatible extension. And it's a fairly niche extension, I feel.

[hughperkins]

(Conversely, if we feel that zfinx is a non-niche extension, then it should have a shorter name I feel, eg maybe U for untyped registers)

[asb]

In D122918#3448001, @hughperkins wrote:

As a general comment, after thinking about this whilst brushing my teeth, I kind of feel that it might be clearer and simpler for everyone, both F people and Zfinx people, if we decoupled F and Zfinx into two separate files. This way F people don't have to figure out what is Zfinx. They just keep their clean separate F file. and Zfinx people dont have to think about how our bits mangle with F bits. Yes involves a bit of duplication, but if it's clearer/cleaner for everyone, maybe it might be a good approach?

After all, Zfinx is not an extension of F. It's a separate, mutually incompatible extension. And it's a fairly niche extension, I feel.

Hi Hugh, and welcome! The naming of the extension is outside of our control I'm afraid.

I see your point, though the main reasoning about keeping F and Zfinx together is that they are largely the same instructions, and the hope is to define instructions and patterns together where feasible.

[hughperkins]

In D122918#3448555, @asb wrote:

I see your point, though the main reasoning about keeping F and Zfinx together is that they are largely the same instructions, and the hope is to define instructions and patterns together where feasible.

Yeah, I totally understand that. And when I first looked at this PR, I thought that made total sense. But then I saw how challenging it is to try to combine the two.

As far as the general principle of 'lets keep things together with similar patterns', the same argument can be levied against the pair of F and D, and yet they are in separate files, and I currently feel putting F and D in separate files is likely a reasonable idea. Despite their apparent similarities (32 vs 64 bits...), it is simpler and easier to keep D and F separate. Compared to D vs F, F vs Zfinx are I feel more different, and there is more reason to keep them apart. But even if they were the same difference as D and F, I feel keeping Zfinx and F apart coudl be a good idea:

• Zfinx is fairly niche, and seems unfair to 'pollute' F with it?
• I suspect Zfinx might be easier to implement if it is kept separaet fomr F.

Anyway, I seem likely to at least dabble in creating a decoupled version of Zfinx. I sort of have a hunch it will be eiaser. If it's not, well, I will come back, and say "well, yes, you were right, it is good to keep Zfinx and F together because ... [reasons X, Y, Z]".

[asb]

@hughperkins: You make good points. It's not immediately obvious what kind of splitting would be better, and at what point the added complexity of trying to have piggy-back zfinx on current F/D patterns hampers readability and maintainability rather than enhance it. If you have time to play around with some options, I'd be really interested in hearing what you come up with.

[sunshaoce]

Fix crash

[hughperkins]

Oooo. you've made load and store work :) Taht's fantastic :) Thank you :)

[sunshaoce]

Fully support zfinx codegen

[hughperkins]

By the way, whilst I remember, since @sunshaoce has implemented all the functionality I need (for now), so I'm not intending to spend any time on working on this. Everything I tested in this PR worked great for me :)

[sunshaoce]

Fix errors

[sunshaoce]

ping

[sunshaoce]

Support zdinx,zhinx codegen

[sunshaoce]

Rebase

[sunshaoce]

Ping

[reames]

A couple of very high level review comments.

1. This patch commingles the assembler/disassembly support and the pattern matching required for IR lowering. The typical process for an extension is to start with a patch specific to the MC layer (i.e. assembler/disassembler), and then move to codegen support in a later patch. I strongly strongly recommend you split if you want meaningful chance of review.

2. You don't appear to have any assembler tests. That's a show stopper right there.

3. On the MC part, please try to get the new extension as separate as possible from the existing floating point ones. I realize there's some potential for code savings, but the change will be lower risk if it touches as little as possible. Once it's in, and tested, changes to share code incrementally would be reasonable.

I strongly recommend you address these points. This patch is unlikely to get meaningful review without them addressed.

[craig.topper]

Assembler and disassembler support was already commited in https://reviews.llvm.org/D93298

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

105 ↗

(On Diff #456908)

Is this something that should have been in the MC layer patch?

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

105 ↗

(On Diff #456908)

No. These don't exist. From the spec:

Load-pair and store-pair instructions are not provided, so transferring
double-precision operands in RV32Zdinx from or to memory requires
two loads or stores.

[reames]

In D122918#3762537, @craig.topper wrote:

Assembler and disassembler support was already commited in https://reviews.llvm.org/D93298

Then why does this contain what look to be MC related changes to .td files? Looking closer, I do see that something has already landed, but there's definitely MC pieces in this. Confusing to say the least.

[craig.topper]

In D122918#3762574, @reames wrote:

In D122918#3762537, @craig.topper wrote:

Assembler and disassembler support was already commited in https://reviews.llvm.org/D93298

Then why does this contain what look to be MC related changes to .td files? Looking closer, I do see that something has already landed, but there's definitely MC pieces in this. Confusing to say the least.

Can you point to a specific example?

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

105 ↗

(On Diff #456908)

Are these expanded somewhere that I'm not seeing?

[craig.topper]

llvm/test/CodeGen/RISCV/double-mem.ll

22 ↗

(On Diff #456908)

This seems to be emitting an ld instruction in rv32 which is illegal.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

105 ↗

(On Diff #456908)

Nope, you can see them in the test output for the RV32Zdinx tests... it's just wrong. Whether these should be pseudos or we should be teaching the legaliser that f64 is legal except for loads/stores I don't know; the latter would be nice, but the interaction with spills sounds bad.

I had a similar issue downstream in CHERI-LLVM where, depending on the mode and pointer address space, there is no FLD/FSD available (when the pointer address space doesn't match the default for the encoding mode used for the current ABI). I used BuildPairF64Pseudo on loading from the address and loading from adding 4 to the address in the TableGen patterns, and added new (Cheri)SplitStoreF64Pseudo's for the store side that do SplitF64Pseudo plus storing to additional addresses. Presumably some of that could be reused if adopting that approach rather than legalisation, though if there's a nicer way without going to legalisation I'd be interested to see it as it's rather ugly (and the only user I can see of (KILL ...) in TableGen patterns themselves...). https://github.com/CTSRD-CHERI/llvm-project/pull/635/files, for what it's worth.

[sunshaoce]

Replace ld with lw in RV32 Zdinx

[reames]

In D122918#3762609, @craig.topper wrote:

In D122918#3762574, @reames wrote:

In D122918#3762537, @craig.topper wrote:

Assembler and disassembler support was already commited in https://reviews.llvm.org/D93298

Then why does this contain what look to be MC related changes to .td files? Looking closer, I do see that something has already landed, but there's definitely MC pieces in this. Confusing to say the least.

Can you point to a specific example?

I think I was seeing the FLD_IN32X definition from the Aug 28th version of the patch. This has since been removed, and even at the time of my comment, I must have been looking at a stale diff. Sorry for the noise.

Two minor optional style comments.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

11721

This pattern repeats a lot. Maybe worth introducing a "Subtarget.hasStdExtZfhorZhinx()" cover?

Also for corresponding F/D variants.

llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

474 ↗

(On Diff #459306)

For the rounding modes, defining symbolic constant names would make the code easier to read. I see that this pattern exists in the current code, so this is a non-blocking suggestion.

[sunshaoce]

Address @reames's comment

[sunshaoce]

Ping

[jrtc27]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

53 ↗

(On Diff #463574)

Way too generic a name that also isn't correctly capitalised

93 ↗

(On Diff #463574)

Is that guaranteed to be 0?

102 ↗

(On Diff #463574)

Think about whether this is actually safe, please...

[sunshaoce]

Address comment

[jrtc27]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

53–56 ↗

(On Diff #464557)

These still are not consistently named

[sunshaoce]

Rebase

[sunshaoce]

Address @jrtc27's comments

[jrtc27]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

102 ↗

(On Diff #463574)

I don't know why you've marked this as done; the line in question (which is now the line below) is not correct, the immediate could be 0x7f[cdef] at which point the arithmetic here will wrap to 0x80[0123] (which the machine verifier probably catches as out of range due to the immediate being signed?..). That is:

void
foo(void *p, double d)
{
    *(double *)((char *)p + 0x7fc) = d;
}

will be miscompiled, surely.

[jrtc27]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

102 ↗

(On Diff #463574)

Note this doesn't have to mean the store is to an unaligned location, either, p could be unaligned and then the addition of 0x7fc results in a well-aligned location. Though we want to support unaligned accesses anyway so that shouldn't be relevant.

[sunshaoce]

We plan to split this patch into the following four parts:

• zfinx
• zdinx on rv32
• zdinx on rv64
• zhinx, zhinxmin

And, we will address Jessica’s comments in the new patch. Thanks!

[asb]

In D122918#4285895, @sunshaoce wrote:

We plan to split this patch into the following four parts:

• zfinx
• zdinx on rv32
• zdinx on rv64
• zhinx, zhinxmin

And, we will address Jessica’s comments in the new patch. Thanks!

Thank you - I think this is a piece of work where you need to have implemented everything to be sure that your approach works, but splitting to allow reviewing it in smaller chunks will be much better.

[sunshaoce]

In D122918#4287273, @asb wrote:

In D122918#4285895, @sunshaoce wrote:

We plan to split this patch into the following four parts:

• zfinx
• zdinx on rv32
• zdinx on rv64
• zhinx, zhinxmin

And, we will address Jessica’s comments in the new patch. Thanks!

Thank you - I think this is a piece of work where you need to have implemented everything to be sure that your approach works, but splitting to allow reviewing it in smaller chunks will be much better.

Thanks, we will make sure to do it well.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   addRegisterClass(XLenVT, &RISCV::GPRRegClass);
 
   if (Subtarget.hasStdExtZfh())
     addRegisterClass(MVT::f16, &RISCV::FPR16RegClass);
   if (Subtarget.hasStdExtF())
     addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
   if (Subtarget.hasStdExtD())
     addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
+  if (Subtarget.hasStdExtZfinx())
+    addRegisterClass(MVT::f32, &RISCV::GPRF32RegClass);
 
   static const MVT::SimpleValueType BoolVecVTs[] = {
       MVT::nxv1i1,  MVT::nxv2i1,  MVT::nxv4i1, MVT::nxv8i1,
       MVT::nxv16i1, MVT::nxv32i1, MVT::nxv64i1};
   static const MVT::SimpleValueType IntVecVTs[] = {
       MVT::nxv1i8,  MVT::nxv2i8,   MVT::nxv4i8,   MVT::nxv8i8,  MVT::nxv16i8,
       MVT::nxv32i8, MVT::nxv64i8,  MVT::nxv1i16,  MVT::nxv2i16, MVT::nxv4i16,
       MVT::nxv8i16, MVT::nxv16i16, MVT::nxv32i16, MVT::nxv1i32, MVT::nxv2i32,
if (Subtarget.hasStdExtZfh()) {
     // FIXME: Need to promote f16 STRICT_* to f32 libcalls, but we don't have
     // complete support for all operations in LegalizeDAG.
 
     // We need to custom promote this.
     if (Subtarget.is64Bit())
       setOperationAction(ISD::FPOWI, MVT::i32, Custom);
   }
 
-  if (Subtarget.hasStdExtF()) {
+  if (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) {
     for (auto NT : FPLegalNodeTypes)
       setOperationAction(NT, MVT::f32, Legal);
     for (auto CC : FPCCToExpand)
       setCondCodeAction(CC, MVT::f32, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
     setOperationAction(ISD::SELECT, MVT::f32, Custom);
     setOperationAction(ISD::BR_CC, MVT::f32, Expand);
     for (auto Op : FPOpToExpand)
       setOperationAction(Op, MVT::f32, Expand);
     setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
     setTruncStoreAction(MVT::f32, MVT::f16, Expand);
   }
 
-  if (Subtarget.hasStdExtF() && Subtarget.is64Bit())
+  if ((Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) &&
+      Subtarget.is64Bit())
     setOperationAction(ISD::BITCAST, MVT::i32, Custom);
 
   if (Subtarget.hasStdExtD()) {
     for (auto NT : FPLegalNodeTypes)
       setOperationAction(NT, MVT::f64, Legal);
     setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
     setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal);
     for (auto CC : FPCCToExpand)
if (Subtarget.hasStdExtD()) {
     setTruncStoreAction(MVT::f64, MVT::f16, Expand);
   }
 
   if (Subtarget.is64Bit())
     setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT,
                         ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT},
                        MVT::i32, Custom);
 
-  if (Subtarget.hasStdExtF()) {
+  if (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) {
     setOperationAction({ISD::FP_TO_UINT_SAT, ISD::FP_TO_SINT_SAT}, XLenVT,
                        Custom);
 
     setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT,
                         ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP},
                        XLenVT, Legal);
 
     setOperationAction(ISD::FLT_ROUNDS_, XLenVT, Custom);
if (Subtarget.useRVVForFixedLengthVectors()) {
           setOperationAction(VPOpc, VT, Custom);
       }
 
       // Custom-legalize bitcasts from fixed-length vectors to scalar types.
       setOperationAction(ISD::BITCAST, {MVT::i8, MVT::i16, MVT::i32, MVT::i64},
                          Custom);
       if (Subtarget.hasStdExtZfh())
         setOperationAction(ISD::BITCAST, MVT::f16, Custom);
-      if (Subtarget.hasStdExtF())
+      if (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx())
         setOperationAction(ISD::BITCAST, MVT::f32, Custom);
       if (Subtarget.hasStdExtD())
         setOperationAction(ISD::BITCAST, MVT::f64, Custom);
     }
   }
 
   // Function alignments.
   const Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4);
   setMinFunctionAlignment(FunctionAlignment);
   setPrefFunctionAlignment(FunctionAlignment);
 
   setMinimumJumpTableEntries(5);
 
   // Jumps are expensive, compared to logic
   setJumpIsExpensive();
 
   setTargetDAGCombine({ISD::INTRINSIC_WO_CHAIN, ISD::ADD, ISD::SUB, ISD::AND,
                        ISD::OR, ISD::XOR});
 
-  if (Subtarget.hasStdExtF())
+  if (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx())
     setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM});
 
   if (Subtarget.hasStdExtZbp())
     setTargetDAGCombine({ISD::ROTL, ISD::ROTR});
 
   if (Subtarget.hasStdExtZbb())
     setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN});
 
   if (Subtarget.hasStdExtZbkb())
     setTargetDAGCombine(ISD::BITREVERSE);
   if (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZbb())
     setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
-  if (Subtarget.hasStdExtF())
+  if (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx())
     setTargetDAGCombine({ISD::ZERO_EXTEND, ISD::FP_TO_SINT, ISD::FP_TO_UINT,
                          ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT});
   if (Subtarget.hasVInstructions())
     setTargetDAGCombine({ISD::FCOPYSIGN, ISD::MGATHER, ISD::MSCATTER,
                          ISD::VP_GATHER, ISD::VP_SCATTER, ISD::SRA, ISD::SRL,
                          ISD::SHL, ISD::STORE, ISD::SPLAT_VECTOR});
 
   setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
bool RISCVTargetLowering::shouldSinkOperands(
   return true;
 }
 
 bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
                                        bool ForCodeSize) const {
   // FIXME: Change to Zfhmin once f16 becomes a legal type with Zfhmin.
   if (VT == MVT::f16 && !Subtarget.hasStdExtZfh())
     return false;
-  if (VT == MVT::f32 && !Subtarget.hasStdExtF())
+  if (VT == MVT::f32 && !Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfinx())
     return false;
   if (VT == MVT::f64 && !Subtarget.hasStdExtD())
     return false;
   return Imm.isZero();
 }
 
 bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const {
   return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) ||
-         (VT == MVT::f32 && Subtarget.hasStdExtF()) ||
+         (VT == MVT::f32 &&
+          (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx())) ||
          (VT == MVT::f64 && Subtarget.hasStdExtD());
 }
 
 MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
                                                       CallingConv::ID CC,
                                                       EVT VT) const {
   // Use f32 to pass f16 if it is legal and Zfh is not enabled.
   // We might still end up using a GPR but that will be decided based on ABI.
   // FIXME: Change to Zfhmin once f16 becomes a legal type with Zfhmin.
-  if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh())
+  if (VT == MVT::f16 &&
+      (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) &&
+      !Subtarget.hasStdExtZfh())
     return MVT::f32;
 
   return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
 }
 
 unsigned RISCVTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
                                                            CallingConv::ID CC,
                                                            EVT VT) const {
   // Use f32 to pass f16 if it is legal and Zfh is not enabled.
   // We might still end up using a GPR but that will be decided based on ABI.
   // FIXME: Change to Zfhmin once f16 becomes a legal type with Zfhmin.
-  if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh())
+  if (VT == MVT::f16 &&
+      (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) &&
+      !Subtarget.hasStdExtZfh())
     return 1;
 
   return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
 }
 
 // Changes the condition code and swaps operands if necessary, so the SetCC
 // operation matches one of the comparisons supported directly by branches
 // in the RISC-V ISA. May adjust compares to favor compare with 0 over compare
if (!VT.isVector() && Op0VT.isFixedLengthVector()) {
                          DAG.getConstant(0, DL, XLenVT));
     }
     if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) {
       SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Op0);
       SDValue FPConv = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, NewOp0);
       return FPConv;
     }
     if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() &&
-        Subtarget.hasStdExtF()) {
+        (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx())) {
       SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
       SDValue FPConv =
           DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0);
       return FPConv;
     }
     return SDValue();
   }
   case ISD::INTRINSIC_WO_CHAIN:
case ISD::BITCAST: {
     assert(VT.isInteger() && !VT.isVector() && "Unexpected VT!");
     SDValue Op0 = N->getOperand(0);
     EVT Op0VT = Op0.getValueType();
     MVT XLenVT = Subtarget.getXLenVT();
     if (VT == MVT::i16 && Op0VT == MVT::f16 && Subtarget.hasStdExtZfh()) {
       SDValue FPConv = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenVT, Op0);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FPConv));
     } else if (VT == MVT::i32 && Op0VT == MVT::f32 && Subtarget.is64Bit() &&
-               Subtarget.hasStdExtF()) {
+               (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx())) {
       SDValue FPConv =
           DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv));
     } else if (!VT.isVector() && Op0VT.isFixedLengthVector() &&
                isTypeLegal(Op0VT)) {
       // Custom-legalize bitcasts from fixed-length vector types to illegal
       // scalar types in order to improve codegen. Bitcast the vector to a
       // one-element vector type whose element type is the same as the result

 
 static bool isSelectPseudo(MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default:
     return false;
   case RISCV::Select_GPR_Using_CC_GPR:
   case RISCV::Select_FPR16_Using_CC_GPR:
   case RISCV::Select_FPR32_Using_CC_GPR:
+  case RISCV::Select_FPR32INX_Using_CC_GPR:
   case RISCV::Select_FPR64_Using_CC_GPR:
     return true;
   }
 }
 
 static MachineBasicBlock *emitQuietFCMP(MachineInstr &MI, MachineBasicBlock *BB,
                                         unsigned RelOpcode, unsigned EqOpcode,
                                         const RISCVSubtarget &Subtarget) {
default:
     llvm_unreachable("Unexpected instr type to insert");
   case RISCV::ReadCycleWide:
     assert(!Subtarget.is64Bit() &&
            "ReadCycleWrite is only to be used on riscv32");
     return emitReadCycleWidePseudo(MI, BB);
   case RISCV::Select_GPR_Using_CC_GPR:
   case RISCV::Select_FPR16_Using_CC_GPR:
   case RISCV::Select_FPR32_Using_CC_GPR:
+  case RISCV::Select_FPR32INX_Using_CC_GPR:
   case RISCV::Select_FPR64_Using_CC_GPR:
     return emitSelectPseudo(MI, BB, Subtarget);
   case RISCV::BuildPairF64Pseudo:
     return emitBuildPairF64Pseudo(MI, BB);
   case RISCV::SplitF64Pseudo:
     return emitSplitF64Pseudo(MI, BB);
   case RISCV::PseudoQuietFLE_H:
     return emitQuietFCMP(MI, BB, RISCV::FLE_H, RISCV::FEQ_H, Subtarget);
   case RISCV::PseudoQuietFLT_H:
     return emitQuietFCMP(MI, BB, RISCV::FLT_H, RISCV::FEQ_H, Subtarget);
   case RISCV::PseudoQuietFLE_S:
     return emitQuietFCMP(MI, BB, RISCV::FLE_S, RISCV::FEQ_S, Subtarget);
+  case RISCV::PseudoQuietFLE_S_INX:
+    return emitQuietFCMP(MI, BB, RISCV::FLE_S_INX, RISCV::FEQ_S_INX, Subtarget);
   case RISCV::PseudoQuietFLT_S:
     return emitQuietFCMP(MI, BB, RISCV::FLT_S, RISCV::FEQ_S, Subtarget);
+  case RISCV::PseudoQuietFLT_S_INX:
+    return emitQuietFCMP(MI, BB, RISCV::FLT_S_INX, RISCV::FEQ_S_INX, Subtarget);
   case RISCV::PseudoQuietFLE_D:
     return emitQuietFCMP(MI, BB, RISCV::FLE_D, RISCV::FEQ_D, Subtarget);
   case RISCV::PseudoQuietFLT_D:
     return emitQuietFCMP(MI, BB, RISCV::FLT_D, RISCV::FEQ_D, Subtarget);
   }
 }
 
 void RISCVTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
if (Constraint.size() == 1) {
     case 'r':
       // TODO: Support fixed vectors up to XLen for P extension?
       if (VT.isVector())
         break;
       return std::make_pair(0U, &RISCV::GPRRegClass);
     case 'f':
       if (Subtarget.hasStdExtZfh() && VT == MVT::f16)
         return std::make_pair(0U, &RISCV::FPR16RegClass);
-      if (Subtarget.hasStdExtF() && VT == MVT::f32)
+      if ((Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) &&
+          VT == MVT::f32)
         return std::make_pair(0U, &RISCV::FPR32RegClass);
       if (Subtarget.hasStdExtD() && VT == MVT::f64)
         return std::make_pair(0U, &RISCV::FPR64RegClass);
       break;
     default:
       break;
     }
   } else if (Constraint == "vr") {
bool RISCVTargetLowering::shouldConvertFpToSat(unsigned Op, EVT FPVT,
                                                EVT VT) const {
   if (!isOperationLegalOrCustom(Op, VT) || !FPVT.isSimple())
     return false;
 
   switch (FPVT.getSimpleVT().SimpleTy) {
   case MVT::f16:
     return Subtarget.hasStdExtZfh();
   case MVT::f32:
-    return Subtarget.hasStdExtF();
+    return Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx();
   case MVT::f64:
     return Subtarget.hasStdExtD();
   default:
     return false;
   }
 }
 
 unsigned RISCVTargetLowering::getJumpTableEncoding() const {
bool RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
                                                      EVT VT) const {
   VT = VT.getScalarType();
 
   if (!VT.isSimple())
     return false;
 
   switch (VT.getSimpleVT().SimpleTy) {
   case MVT::f16:
     return Subtarget.hasStdExtZfh();
   case MVT::f32:
-    return Subtarget.hasStdExtF();
+    return Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx();
   case MVT::f64:
     return Subtarget.hasStdExtD();
   default:
     break;
   }
 
   return false;
 }

llvm/lib/Target/RISCV/RISCVInstrFormats.td

 
 // Pseudo instructions
 class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
     : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
 
-class PseudoQuietFCMP<RegisterClass Ty>
+class PseudoQuietFCMP<DAGOperand Ty>
     : Pseudo<(outs GPR:$rd), (ins Ty:$rs1, Ty:$rs2), []> {
   let hasSideEffects = 1;
   let mayLoad = 0;
   let mayStore = 0;
 }
 
 // Pseudo load instructions.
 class PseudoLoad<string opcodestr, RegisterClass rdty = GPR>

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

 
 bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
   const unsigned Opcode = MI.getOpcode();
   switch (Opcode) {
   default:
     break;
   case RISCV::FSGNJ_D:
   case RISCV::FSGNJ_S:
+  case RISCV::FSGNJ_S_INX:
   case RISCV::FSGNJ_H:
     // The canonical floating-point move is fsgnj rd, rs, rs.
     return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
            MI.getOperand(1).getReg() == MI.getOperand(2).getReg();
   case RISCV::ADDI:
   case RISCV::ORI:
   case RISCV::XORI:
     return (MI.getOperand(1).isReg() &&
RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
   case RISCV::ADDI:
     // Operand 1 can be a frameindex but callers expect registers
     if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
         MI.getOperand(2).getImm() == 0)
       return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
     break;
   case RISCV::FSGNJ_D:
   case RISCV::FSGNJ_S:
+  case RISCV::FSGNJ_S_INX:
   case RISCV::FSGNJ_H:
     // The canonical floating-point move is fsgnj rd, rs, rs.
     if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
         MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
       return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
     break;
   }
   return None;

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 def riscv_selectcc_frag : PatFrag<(ops node:$lhs, node:$rhs, node:$cc,
                                        node:$truev, node:$falsev),
                                   (riscv_selectcc node:$lhs, node:$rhs,
                                                   node:$cc, node:$truev,
                                                   node:$falsev), [{}],
                                   IntCCtoRISCVCC>;
 
 let usesCustomInserter = 1 in
-class SelectCC_rrirr<RegisterClass valty, RegisterClass cmpty>
+class SelectCC_rrirr<DAGOperand valty, RegisterClass cmpty>
     : Pseudo<(outs valty:$dst),
              (ins cmpty:$lhs, cmpty:$rhs, ixlenimm:$imm,
               valty:$truev, valty:$falsev),
              [(set valty:$dst,
                (riscv_selectcc_frag:$imm cmpty:$lhs, cmpty:$rhs, cond,
                                          valty:$truev, valty:$falsev))]>;
 
 def Select_GPR_Using_CC_GPR : SelectCC_rrirr<GPR, GPR>;

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

 let Predicates = [HasStdExtZfinx] in {
 def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S_INX FPR32INX:$rd, FPR32INX:$rs, FPR32INX:$rs)>;
 def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S_INX FPR32INX:$rd, FPR32INX:$rs, FPR32INX:$rs)>;
 
 def : InstAlias<"fgt.s $rd, $rs, $rt",
                 (FLT_S_INX GPR:$rd, FPR32INX:$rt, FPR32INX:$rs), 0>;
 def : InstAlias<"fge.s $rd, $rs, $rt",
                 (FLE_S_INX GPR:$rd, FPR32INX:$rt, FPR32INX:$rs), 0>;
+
+// frsr, fssr are obsolete aliases replaced by frcsr, fscsr, so give them
+// zero weight.
+def : InstAlias<"frsr $rd",       (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 0>;
+def : InstAlias<"fssr $rd, $rs",  (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs), 0>;
+def : InstAlias<"fssr $rs",       (CSRRW      X0, SysRegFCSR.Encoding, GPR:$rs), 0>;
+
+def : InstAlias<"frrm $rd",        (CSRRS  GPR:$rd, SysRegFRM.Encoding, X0), 2>;
+def : InstAlias<"fsrm $rd, $rs",   (CSRRW  GPR:$rd, SysRegFRM.Encoding, GPR:$rs)>;
+def : InstAlias<"fsrm $rs",        (CSRRW       X0, SysRegFRM.Encoding, GPR:$rs), 2>;
+def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, SysRegFRM.Encoding, uimm5:$imm)>;
+def : InstAlias<"fsrmi $imm",      (CSRRWI      X0, SysRegFRM.Encoding, uimm5:$imm), 2>;
+
+def : InstAlias<"frflags $rd",        (CSRRS  GPR:$rd, SysRegFFLAGS.Encoding, X0), 2>;
+def : InstAlias<"fsflags $rd, $rs",   (CSRRW  GPR:$rd, SysRegFFLAGS.Encoding, GPR:$rs)>;
+def : InstAlias<"fsflags $rs",        (CSRRW       X0, SysRegFFLAGS.Encoding, GPR:$rs), 2>;
+def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, SysRegFFLAGS.Encoding, uimm5:$imm)>;
+def : InstAlias<"fsflagsi $imm",      (CSRRWI      X0, SysRegFFLAGS.Encoding, uimm5:$imm), 2>;
+
+let usesCustomInserter = 1 in {
+def PseudoQuietFLE_S_INX : PseudoQuietFCMP<FPR32INX>;
+def PseudoQuietFLT_S_INX : PseudoQuietFCMP<FPR32INX>;
+}
 } // Predicates = [HasStdExtZfinx]
 
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
 /// Floating point constants
 def fpimm0    : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
 def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>;
 
 /// Generic pattern classes
-class PatSetCC<RegisterClass Ty, SDPatternOperator OpNode, CondCode Cond, RVInst Inst>
+class PatSetCC<DAGOperand Ty, SDPatternOperator OpNode, CondCode Cond,
+               RVInst Inst>
     : Pat<(OpNode Ty:$rs1, Ty:$rs2, Cond), (Inst $rs1, $rs2)>;
+multiclass PatSetCC_m<SDPatternOperator OpNode, CondCode Cond,
+                      RVInst Inst, list<ExtInfo_r> Exts> {
+  foreach Ext = Exts in
+    let Predicates = Ext.Predicates in
+    def Ext.Suffix : PatSetCC<Ext.Reg, OpNode, Cond, 
+                              !cast<RVInst>(Inst#Ext.Suffix)>;
+}
 
 class PatFprFpr<SDPatternOperator OpNode, RVInstR Inst,
-                RegisterClass RegTy>
+                DAGOperand RegTy>
     : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2)>;
+multiclass PatFprFpr_m<SDPatternOperator OpNode, RVInstR Inst,
+                       list<ExtInfo_r> Exts> {
+  foreach Ext = Exts in
+    let Predicates = Ext.Predicates in
+    def Ext.Suffix : PatFprFpr<OpNode, !cast<RVInstR>(Inst#Ext.Suffix),
+                               Ext.Reg>;
+}
 
 class PatFprFprDynFrm<SDPatternOperator OpNode, RVInstRFrm Inst,
-                      RegisterClass RegTy>
+                      DAGOperand RegTy>
     : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2, 0b111)>;
+multiclass PatFprFprDynFrm_m<SDPatternOperator OpNode, RVInstRFrm Inst,
+                             list<ExtInfo_r> Exts> {
+  foreach Ext = Exts in
+    let Predicates = Ext.Predicates in
+    def Ext.Suffix : PatFprFprDynFrm<OpNode,
+                                     !cast<RVInstRFrm>(Inst#Ext.Suffix),
+                                     Ext.Reg>;
+}
 
 let Predicates = [HasStdExtF] in {
-
 /// Float constants
 def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>;
 def : Pat<(f32 (fpimmneg0)), (FSGNJN_S (FMV_W_X X0), (FMV_W_X X0))>;
+} // Predicates = [HasStdExtF]
+
+let Predicates = [HasStdExtZfinx] in {
+def : Pat<(f32 (fpimm0)), (COPY (f32 X0))>;
+def : Pat<(f32 (fpimmneg0)), (FSGNJN_S_INX (COPY (f32 X0)), (COPY (f32 X0)))>;
+} // Predicates = [HasStdExtZfinx]
 
 /// Float conversion operations
 
 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
 // are defined later.
 
 /// Float arithmetic operations
+defm : PatFprFprDynFrm_m<any_fadd, FADD_S, FINX>;
+defm : PatFprFprDynFrm_m<any_fsub, FSUB_S, FINX>;
+defm : PatFprFprDynFrm_m<any_fmul, FMUL_S, FINX>;
+defm : PatFprFprDynFrm_m<any_fdiv, FDIV_S, FINX>;
 
-def : PatFprFprDynFrm<any_fadd, FADD_S, FPR32>;
-def : PatFprFprDynFrm<any_fsub, FSUB_S, FPR32>;
-def : PatFprFprDynFrm<any_fmul, FMUL_S, FPR32>;
-def : PatFprFprDynFrm<any_fdiv, FDIV_S, FPR32>;
-
+let Predicates = [HasStdExtF] in {
 def : Pat<(any_fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>;
 
 def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>;
 def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>;
+} // Predicates = [HasStdExtF]
+
+let Predicates = [HasStdExtZfinx] in {
+def : Pat<(any_fsqrt FPR32INX:$rs1), (FSQRT_S_INX FPR32INX:$rs1, 0b111)>;
+
+def : Pat<(fneg FPR32INX:$rs1), (FSGNJN_S_INX $rs1, $rs1)>;
+def : Pat<(fabs FPR32INX:$rs1), (FSGNJX_S_INX $rs1, $rs1)>;
+} // Predicates = [HasStdExtZfinx]
+
+defm : PatFprFpr_m<fcopysign, FSGNJ_S, FINX>;
 
-def : PatFprFpr<fcopysign, FSGNJ_S, FPR32>;
+let Predicates = [HasStdExtF] in {
 def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>;
 
 // fmadd: rs1 * rs2 + rs3
 def : Pat<(any_fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3),
           (FMADD_S $rs1, $rs2, $rs3, 0b111)>;
 
 // fmsub: rs1 * rs2 - rs3
 def : Pat<(any_fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)),
           (FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
 
 // fnmsub: -rs1 * rs2 + rs3
 def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3),
           (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
 
 // fnmadd: -rs1 * rs2 - rs3
 def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)),
           (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
+} // Predicates = [HasStdExtF]
+
+let Predicates = [HasStdExtZfinx] in {
+def : Pat<(fcopysign FPR32INX:$rs1, (fneg FPR32INX:$rs2)), (FSGNJN_S_INX $rs1, $rs2)>;
+
+// fmadd: rs1 * rs2 + rs3
+def : Pat<(any_fma FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3),
+          (FMADD_S_INX $rs1, $rs2, $rs3, 0b111)>;
+
+// fmsub: rs1 * rs2 - rs3
+def : Pat<(any_fma FPR32INX:$rs1, FPR32INX:$rs2, (fneg FPR32INX:$rs3)),
+          (FMSUB_S_INX FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3, 0b111)>;
+
+// fnmsub: -rs1 * rs2 + rs3
+def : Pat<(any_fma (fneg FPR32INX:$rs1), FPR32INX:$rs2, FPR32INX:$rs3),
+          (FNMSUB_S_INX FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3, 0b111)>;
+
+// fnmadd: -rs1 * rs2 - rs3
+def : Pat<(any_fma (fneg FPR32INX:$rs1), FPR32INX:$rs2, (fneg FPR32INX:$rs3)),
+          (FNMADD_S_INX FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3, 0b111)>;
+} // Predicates = [HasStdExtZfinx]
 
 // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
 // LLVM's fminnum and fmaxnum
 // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
-def : PatFprFpr<fminnum, FMIN_S, FPR32>;
-def : PatFprFpr<fmaxnum, FMAX_S, FPR32>;
+defm : PatFprFpr_m<fminnum, FMIN_S, FINX>;
+defm : PatFprFpr_m<fmaxnum, FMAX_S, FINX>;
 
 /// Setcc
 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
 // strict versions of those.
 
 // Match non-signaling FEQ_S
-def : PatSetCC<FPR32, any_fsetcc, SETEQ, FEQ_S>;
-def : PatSetCC<FPR32, any_fsetcc, SETOEQ, FEQ_S>;
-def : PatSetCC<FPR32, strict_fsetcc, SETLT, PseudoQuietFLT_S>;
-def : PatSetCC<FPR32, strict_fsetcc, SETOLT, PseudoQuietFLT_S>;
-def : PatSetCC<FPR32, strict_fsetcc, SETLE, PseudoQuietFLE_S>;
-def : PatSetCC<FPR32, strict_fsetcc, SETOLE, PseudoQuietFLE_S>;
+defm : PatSetCC_m<any_fsetcc, SETEQ,  FEQ_S, FINX>;
+defm : PatSetCC_m<any_fsetcc, SETOEQ, FEQ_S, FINX>;
+defm : PatSetCC_m<strict_fsetcc, SETLT,  PseudoQuietFLT_S, FINX>;
+defm : PatSetCC_m<strict_fsetcc, SETOLT, PseudoQuietFLT_S, FINX>;
+defm : PatSetCC_m<strict_fsetcc, SETLE,  PseudoQuietFLE_S, FINX>;
+defm : PatSetCC_m<strict_fsetcc, SETOLE, PseudoQuietFLE_S, FINX>;
 
+let Predicates = [HasStdExtF] in {
 // Match signaling FEQ_S
 def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ),
           (AND (FLE_S $rs1, $rs2),
                (FLE_S $rs2, $rs1))>;
 def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETOEQ),
           (AND (FLE_S $rs1, $rs2),
                (FLE_S $rs2, $rs1))>;
 // If both operands are the same, use a single FLE.
 def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETEQ),
           (FLE_S $rs1, $rs1)>;
 def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETOEQ),
           (FLE_S $rs1, $rs1)>;
+} // Predicates = [HasStdExtF]
+
+let Predicates = [HasStdExtZfinx] in {
+// Match signaling FEQ_S
+def : Pat<(strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs2, SETEQ),
+          (AND (FLE_S_INX $rs1, $rs2),
+               (FLE_S_INX $rs2, $rs1))>;
+def : Pat<(strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs2, SETOEQ),
+          (AND (FLE_S_INX $rs1, $rs2),
+               (FLE_S_INX $rs2, $rs1))>;
+// If both operands are the same, use a single FLE.
+def : Pat<(strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs1, SETEQ),
+          (FLE_S_INX $rs1, $rs1)>;
+def : Pat<(strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs1, SETOEQ),
+          (FLE_S_INX $rs1, $rs1)>;
+} // Predicates = [HasStdExtZfinx]
 
-def : PatSetCC<FPR32, any_fsetccs, SETLT, FLT_S>;
-def : PatSetCC<FPR32, any_fsetccs, SETOLT, FLT_S>;
-def : PatSetCC<FPR32, any_fsetccs, SETLE, FLE_S>;
-def : PatSetCC<FPR32, any_fsetccs, SETOLE, FLE_S>;
+defm : PatSetCC_m<any_fsetccs, SETLT,  FLT_S, FINX>;
+defm : PatSetCC_m<any_fsetccs, SETOLT, FLT_S, FINX>;
+defm : PatSetCC_m<any_fsetccs, SETLE,  FLE_S, FINX>;
+defm : PatSetCC_m<any_fsetccs, SETOLE, FLE_S, FINX>;
 
+
+let Predicates = [HasStdExtF] in {
 def Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>;
 
 /// Loads
 
 defm : LdPat<load, FLW, f32>;
 
 /// Stores
 
 defm : StPat<store, FSW, FPR32, f32>;
 
 } // Predicates = [HasStdExtF]
 
+let Predicates = [HasStdExtZfinx] in {
+def Select_FPR32INX_Using_CC_GPR : SelectCC_rrirr<FPR32INX, GPR>;
+
+/// Loads
+def : Pat<(f32 (load BaseAddr:$rs1)), (COPY (LW BaseAddr:$rs1, 0))>;
+
+/// Stores
+def : Pat<(store (f32 FPR32INX:$rs2), BaseAddr:$rs1),
+          (SW (COPY FPR32INX:$rs2), BaseAddr:$rs1, 0)>;
+}
+
 let Predicates = [HasStdExtF, IsRV32] in {
 // Moves (no conversion)
 def : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_W_X GPR:$rs1)>;
 def : Pat<(i32 (bitconvert FPR32:$rs1)), (FMV_X_W FPR32:$rs1)>;
+} // Predicates = [HasStdExtF, IsRV32]
 
+let Predicates = [HasStdExtZfinx, IsRV32] in {
+// Moves (no conversion)
+def : Pat<(f32 (bitconvert (i32 GPR:$rs1))), (COPY GPR:$rs1)>;
+def : Pat<(i32 (bitconvert FPR32INX:$rs1)), (COPY FPR32INX:$rs1)>;
+} // Predicates = [HasStdExtZfinx, IsRV32]
+
+let Predicates = [HasStdExtF, IsRV32] in {
 // float->[u]int. Round-to-zero must be used.
 def : Pat<(i32 (any_fp_to_sint FPR32:$rs1)), (FCVT_W_S $rs1, 0b001)>;
 def : Pat<(i32 (any_fp_to_uint FPR32:$rs1)), (FCVT_WU_S $rs1, 0b001)>;
 
 // Saturating float->[u]int32.
 def : Pat<(i32 (riscv_fcvt_x FPR32:$rs1, timm:$frm)), (FCVT_W_S $rs1, timm:$frm)>;
 def : Pat<(i32 (riscv_fcvt_xu FPR32:$rs1, timm:$frm)), (FCVT_WU_S $rs1, timm:$frm)>;
 
 // float->int32 with current rounding mode.
 def : Pat<(i32 (any_lrint FPR32:$rs1)), (FCVT_W_S $rs1, 0b111)>;
 
 // float->int32 rounded to nearest with ties rounded away from zero.
 def : Pat<(i32 (any_lround FPR32:$rs1)), (FCVT_W_S $rs1, 0b100)>;
 
 // [u]int->float. Match GCC and default to using dynamic rounding mode.
 def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W $rs1, 0b111)>;
 def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>;
 } // Predicates = [HasStdExtF, IsRV32]
 
+let Predicates = [HasStdExtZfinx, IsRV32] in {
+// float->[u]int. Round-to-zero must be used.
+def : Pat<(i32 (any_fp_to_sint FPR32INX:$rs1)), (FCVT_W_S_INX $rs1, 0b001)>;
+def : Pat<(i32 (any_fp_to_uint FPR32INX:$rs1)), (FCVT_WU_S_INX $rs1, 0b001)>;
+
+// Saturating float->[u]int32.
+def : Pat<(i32 (riscv_fcvt_x FPR32INX:$rs1, timm:$frm)), (FCVT_W_S_INX $rs1, timm:$frm)>;
+def : Pat<(i32 (riscv_fcvt_xu FPR32INX:$rs1, timm:$frm)), (FCVT_WU_S_INX $rs1, timm:$frm)>;
+
+// float->int32 with current rounding mode.
+def : Pat<(i32 (any_lrint FPR32INX:$rs1)), (FCVT_W_S_INX $rs1, 0b111)>;
+
+// float->int32 rounded to nearest with ties rounded away from zero.
+def : Pat<(i32 (any_lround FPR32INX:$rs1)), (FCVT_W_S_INX $rs1, 0b100)>;
+
+// [u]int->float. Match GCC and default to using dynamic rounding mode.
+def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W_INX $rs1, 0b111)>;
+def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU_INX $rs1, 0b111)>;
+} // Predicates = [HasStdExtZfinx, IsRV32]
+
 let Predicates = [HasStdExtF, IsRV64] in {
 // Moves (no conversion)
 def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>;
 def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>;
 def : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 FPR32:$src), i32),
           (FMV_X_W FPR32:$src)>;
 
 // Use target specific isd nodes to help us remember the result is sign

 def : Pat<(i64 (any_llround FPR32:$rs1)), (FCVT_L_S $rs1, 0b100)>;
 
 // [u]int->fp. Match GCC and default to using dynamic rounding mode.
 def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_S_W $rs1, 0b111)>;
 def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_S_WU $rs1, 0b111)>;
 def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_S_L $rs1, 0b111)>;
 def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_S_LU $rs1, 0b111)>;
 } // Predicates = [HasStdExtF, IsRV64]
+
+let Predicates = [HasStdExtZfinx, IsRV64] in {
+// Moves (no conversion)
+def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (COPY GPR:$src)>;
+def : Pat<(riscv_fmv_x_anyextw_rv64 GPRF32:$src), (COPY GPRF32:$src)>;
+def : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 GPRF32:$src), i32),
+          (COPY GPRF32:$src)>;
+
+// Use target specific isd nodes to help us remember the result is sign
+// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be
+// duplicated if it has another user that didn't need the sign_extend.
+def : Pat<(riscv_any_fcvt_w_rv64 FPR32INX:$rs1, timm:$frm),  (FCVT_W_S_INX $rs1, timm:$frm)>;
+def : Pat<(riscv_any_fcvt_wu_rv64 FPR32INX:$rs1, timm:$frm), (FCVT_WU_S_INX $rs1, timm:$frm)>;
+
+// float->[u]int64. Round-to-zero must be used.
+def : Pat<(i64 (any_fp_to_sint FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, 0b001)>;
+def : Pat<(i64 (any_fp_to_uint FPR32INX:$rs1)), (FCVT_LU_S_INX $rs1, 0b001)>;
+
+// Saturating float->[u]int64.
+def : Pat<(i64 (riscv_fcvt_x FPR32INX:$rs1, timm:$frm)), (FCVT_L_S_INX $rs1, timm:$frm)>;
+def : Pat<(i64 (riscv_fcvt_xu FPR32INX:$rs1, timm:$frm)), (FCVT_LU_S_INX $rs1, timm:$frm)>;
+
+// float->int64 with current rounding mode.
+def : Pat<(i64 (any_lrint FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, 0b111)>;
+def : Pat<(i64 (any_llrint FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, 0b111)>;
+
+// float->int64 rounded to neartest with ties rounded away from zero.
+def : Pat<(i64 (any_lround FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, 0b100)>;
+def : Pat<(i64 (any_llround FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, 0b100)>;
+
+// [u]int->fp. Match GCC and default to using dynamic rounding mode.
+def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_S_W_INX $rs1, 0b111)>;
+def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_S_WU_INX $rs1, 0b111)>;
+def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_S_L_INX $rs1, 0b111)>;
+def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_S_LU_INX $rs1, 0b111)>;
+} // Predicates = [HasStdExtZfinx, IsRV64]

llvm/test/CodeGen/RISCV/float-arith-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=lp64f \
-; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK,RV64IF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -disable-strictnode-mutation -target-abi=ilp32 \
+; RUN:   | FileCheck -check-prefixes=CHECKZFINX,RV32IZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -disable-strictnode-mutation -target-abi=lp64 \
+; RUN:   | FileCheck -check-prefixes=CHECKZFINX,RV64IZFINX %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
 
 define float @fadd_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fadd_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fadd_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fadd_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __addsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fadd.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)
 
 define float @fsub_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsub.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsub.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fsub_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsub.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fsub_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fsub.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __subsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsub_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __subsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fsub.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata)
 
 define float @fmul_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fmul_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmul.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmul_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmul.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmul_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmul.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fmul_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fmul.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fmul_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __mulsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmul_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __mulsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fmul.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata)
 
 define float @fdiv_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fdiv_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fdiv.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fdiv_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fdiv.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fdiv_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fdiv.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fdiv_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fdiv.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fdiv_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __divsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fdiv_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __divsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fdiv.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata)
 
 define float @fsqrt_s(float %a) nounwind strictfp {
-; RV32IF-LABEL: fsqrt_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsqrt.s fa0, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsqrt_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsqrt.s fa0, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fsqrt_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsqrt.s fa0, fa0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fsqrt_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fsqrt.s a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fsqrt_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sqrtf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call fminf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fmin_s:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call fminf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fmin_s:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call fminf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fmin_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fminf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call fmaxf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fmax_s:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call fmaxf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fmax_s:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call fmaxf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fmax_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaxf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmax_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call fmaxf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.maxnum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.maxnum.f32(float, float, metadata) strictfp
 
 define float @fmadd_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fmadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmadd_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fmadd_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmadd_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call fmaf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) strictfp
 
 define float @fmsub_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fmsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmsub_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fmsub.s fa0, fa0, fa1, ft0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fmsub_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a2, a2, zero
+; CHECKZFINX-NEXT:    fmsub.s a0, a0, a1, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %negc = fneg float %c_
   %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmadd_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft1, fa0, ft0
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fnmadd_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a0, a0, zero
+; CHECKZFINX-NEXT:    fadd.s a2, a2, zero
+; CHECKZFINX-NEXT:    fnmadd.s a0, a0, a1, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c
   %nega = fneg float %a_
   %negc = fneg float %c_
   %1 = call float @llvm.experimental.constrained.fma.f32(float %nega, float %b, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmadd_s_2:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa1, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s_2:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa1, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmadd_s_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft1, fa1, ft0
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fnmadd_s_2:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a1, a1, zero
+; CHECKZFINX-NEXT:    fadd.s a2, a2, zero
+; CHECKZFINX-NEXT:    fnmadd.s a0, a1, a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c
   %negb = fneg float %b_
   %negc = fneg float %c_
   %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %negb, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fnmsub_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa0, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa0, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmsub_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft0, fa0, ft0
+; CHECK-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fnmsub_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a0, a0, zero
+; CHECKZFINX-NEXT:    fnmsub.s a0, a0, a1, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2

 ; RV64I-NEXT:    ret
   %a_ = fadd float 0.0, %a
   %nega = fneg float %a_
   %1 = call float @llvm.experimental.constrained.fma.f32(float %nega, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fnmsub_s_2(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmsub_s_2:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s_2:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmsub_s_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft0, fa1, ft0
+; CHECK-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fnmsub_s_2:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a1, a1, zero
+; CHECKZFINX-NEXT:    fnmsub.s a0, a1, a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2

llvm/test/CodeGen/RISCV/float-arith.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECK %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefixes=CHECKZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefixes=CHECKZFINX %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 ; These tests are each targeted at a particular RISC-V FPU instruction.
 ; Compares and conversions can be found in float-fcmp.ll and float-convert.ll
 ; respectively. Some other float-*.ll files in this folder exercise LLVM IR
 ; instructions that don't directly match a RISC-V instruction.
 
 define float @fadd_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fadd_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fadd_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fadd_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __addsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fadd float %a, %b
   ret float %1
 }
 
 define float @fsub_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsub.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsub.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fsub_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsub.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fsub_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fsub.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __subsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsub_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __subsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fsub float %a, %b
   ret float %1
 }
 
 define float @fmul_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmul_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmul.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmul_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmul.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmul_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmul.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fmul_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fmul.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fmul_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __mulsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmul_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __mulsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fmul float %a, %b
   ret float %1
 }
 
 define float @fdiv_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fdiv_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fdiv.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fdiv_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fdiv.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fdiv_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fdiv.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fdiv_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fdiv.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fdiv_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __divsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = fdiv float %a, %b
   ret float %1
 }
 
 declare float @llvm.sqrt.f32(float)
 
 define float @fsqrt_s(float %a) nounwind {
-; RV32IF-LABEL: fsqrt_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsqrt.s fa0, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsqrt_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsqrt.s fa0, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fsqrt_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsqrt.s fa0, fa0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fsqrt_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fsqrt.s a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fsqrt_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sqrtf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.sqrt.f32(float %a)
   ret float %1
 }
 
 declare float @llvm.copysign.f32(float, float)
 
 define float @fsgnj_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fsgnj_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsgnj.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsgnj_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsgnj.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fsgnj_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsgnj.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fsgnj_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fsgnj.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fsgnj_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a2, 524288
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsgnj_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a2, 524288
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    slli a0, a0, 33
 ; RV64I-NEXT:    srli a0, a0, 33
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.copysign.f32(float %a, float %b)
   ret float %1
 }
 
-; This function performs extra work to ensure that
-; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define i32 @fneg_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fneg_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa0
-; RV32IF-NEXT:    fneg.s ft1, ft0
-; RV32IF-NEXT:    feq.s a0, ft0, ft1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fneg_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa0
-; RV64IF-NEXT:    fneg.s ft1, ft0
-; RV64IF-NEXT:    feq.s a0, ft0, ft1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fneg_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s ft0, fa0, fa0
+; CHECK-NEXT:    fneg.s ft1, ft0
+; CHECK-NEXT:    feq.s a0, ft0, ft1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fneg_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a0, a0, a0
+; CHECKZFINX-NEXT:    fneg.s a1, a0
+; CHECKZFINX-NEXT:    feq.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fneg_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lui a1, 524288

 ; RV64I-NEXT:    ret
   %1 = fadd float %a, %a
   %2 = fneg float %1
   %3 = fcmp oeq float %1, %2
   %4 = zext i1 %3 to i32
   ret i32 %4
 }
 
-; This function performs extra work to ensure that
-; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define float @fsgnjn_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fsgnjn_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV32IF-NEXT:    fsgnjn.s fa0, fa0, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsgnjn_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV64IF-NEXT:    fsgnjn.s fa0, fa0, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fsgnjn_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s ft0, fa0, fa1
+; CHECK-NEXT:    fsgnjn.s fa0, fa0, ft0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fsgnjn_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a1, a0, a1
+; CHECKZFINX-NEXT:    fsgnjn.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fsgnjn_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    call __addsf3@plt
; RV64I-NEXT:    ret
   %1 = fadd float %a, %b
   %2 = fneg float %1
   %3 = call float @llvm.copysign.f32(float %a, float %2)
   ret float %3
 }
 
 declare float @llvm.fabs.f32(float)
 
-; This function performs extra work to ensure that
-; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
 define float @fabs_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fabs_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV32IF-NEXT:    fabs.s ft1, ft0
-; RV32IF-NEXT:    fadd.s fa0, ft1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fabs_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV64IF-NEXT:    fabs.s ft1, ft0
-; RV64IF-NEXT:    fadd.s fa0, ft1, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fabs_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s ft0, fa0, fa1
+; CHECK-NEXT:    fabs.s ft1, ft0
+; CHECK-NEXT:    fadd.s fa0, ft1, ft0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fabs_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a0, a0, a1
+; CHECKZFINX-NEXT:    fabs.s a1, a0
+; CHECKZFINX-NEXT:    fadd.s a0, a1, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fabs_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    slli a0, a0, 1
; RV64I-NEXT:    ret
   %2 = call float @llvm.fabs.f32(float %1)
   %3 = fadd float %2, %1
   ret float %3
 }
 
 declare float @llvm.minnum.f32(float, float)
 
 define float @fmin_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmin_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmin.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmin_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmin.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmin_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmin.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fmin_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fmin.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fmin_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fminf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.minnum.f32(float %a, float %b)
   ret float %1
 }
 
 declare float @llvm.maxnum.f32(float, float)
 
 define float @fmax_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmax_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmax.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmax_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmax.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmax_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmax.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fmax_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fmax.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fmax_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaxf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.maxnum.f32(float %a, float %b)
   ret float %1
 }
 
 declare float @llvm.fma.f32(float, float, float)
 
 define float @fmadd_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmadd_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fmadd_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmadd_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call fmaf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
   ret float %1
 }
 
 define float @fmsub_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmsub_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fmsub.s fa0, fa0, fa1, ft0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fmsub_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a2, a2, zero
+; CHECKZFINX-NEXT:    fmsub.s a0, a0, a1, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call fmaf@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
-  %c_ = fadd float 0.0, %c ; avoid negation using xor
-  %negc = fsub float -0.0, %c_
+  %c_ = fadd float 0.0, %c   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
   ret float %1
 }
 
 define float @fnmadd_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmadd_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft1, fa0, ft0
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fnmadd_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a0, a0, zero
+; CHECKZFINX-NEXT:    fadd.s a2, a2, zero
+; CHECKZFINX-NEXT:    fnmadd.s a0, a0, a1, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c
   %nega = fsub float -0.0, %a_
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)
   ret float %1
 }
 
 define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmadd_s_2:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa1, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s_2:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa1, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmadd_s_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft1, fa1, ft0
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fnmadd_s_2:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a1, a1, zero
+; CHECKZFINX-NEXT:    fadd.s a2, a2, zero
+; CHECKZFINX-NEXT:    fnmadd.s a0, a1, a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c
   %negb = fsub float -0.0, %b_
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %a, float %negb, float %negc)
   ret float %1
 }
 
 define float @fnmsub_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa0, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa0, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmsub_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft0, fa0, ft0
+; CHECK-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fnmsub_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a0, a0, zero
+; CHECKZFINX-NEXT:    fnmsub.s a0, a0, a1, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2

 ; RV64I-NEXT:    ret
   %a_ = fadd float 0.0, %a
   %nega = fsub float -0.0, %a_
   %1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
   ret float %1
 }
 
 define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmsub_s_2:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s_2:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmsub_s_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft0, fa1, ft0
+; CHECK-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fnmsub_s_2:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a1, a1, zero
+; CHECKZFINX-NEXT:    fnmsub.s a0, a1, a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2

 ; RV64I-NEXT:    ret
   %b_ = fadd float 0.0, %b
   %negb = fsub float -0.0, %b_
   %1 = call float @llvm.fma.f32(float %a, float %negb, float %c)
   ret float %1
 }
 
 define float @fmadd_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmadd_s_contract:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmadd_s_contract:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmadd_s_contract:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fmadd_s_contract:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fmadd_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    call __mulsf3@plt

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fmul contract float %a, %b
   %2 = fadd contract float %1, %c
   ret float %2
 }
 
 define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmsub_s_contract:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmsub_s_contract:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmsub_s_contract:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fmsub.s fa0, fa0, fa1, ft0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fmsub_s_contract:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a2, a2, zero
+; CHECKZFINX-NEXT:    fmsub.s a0, a0, a1, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fmsub_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    call __subsf3@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
-  %c_ = fadd float 0.0, %c ; avoid negation using xor
-  %1 = fmul contract float %a, %b
+  %c_ = fadd float 0.0, %c   %1 = fmul contract float %a, %b
   %2 = fsub contract float %1, %c_
   ret float %2
 }
 
 define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmadd_s_contract:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV32IF-NEXT:    fadd.s ft2, fa1, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, ft2, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s_contract:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV64IF-NEXT:    fadd.s ft2, fa1, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, ft2, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmadd_s_contract:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft1, fa0, ft0
+; CHECK-NEXT:    fadd.s ft2, fa1, ft0
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fnmadd.s fa0, ft1, ft2, ft0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fnmadd_s_contract:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a0, a0, zero
+; CHECKZFINX-NEXT:    fadd.s a1, a1, zero
+; CHECKZFINX-NEXT:    fadd.s a2, a2, zero
+; CHECKZFINX-NEXT:    fnmadd.s a0, a0, a1, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __subsf3@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
-  %a_ = fadd float 0.0, %a ; avoid negation using xor
-  %b_ = fadd float 0.0, %b ; avoid negation using xor
-  %c_ = fadd float 0.0, %c ; avoid negation using xor
-  %1 = fmul contract float %a_, %b_
+  %a_ = fadd float 0.0, %a   %b_ = fadd float 0.0, %b   %c_ = fadd float 0.0, %c   %1 = fmul contract float %a_, %b_
   %2 = fneg float %1
   %3 = fsub contract float %2, %c_
   ret float %3
 }
 
 define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmsub_s_contract:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft1, ft0, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s_contract:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft1, ft0, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmsub_s_contract:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft1, fa0, ft0
+; CHECK-NEXT:    fadd.s ft0, fa1, ft0
+; CHECK-NEXT:    fnmsub.s fa0, ft1, ft0, fa2
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fnmsub_s_contract:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a0, a0, zero
+; CHECKZFINX-NEXT:    fadd.s a1, a1, zero
+; CHECKZFINX-NEXT:    fnmsub.s a0, a0, a1, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __subsf3@plt
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
-  %a_ = fadd float 0.0, %a ; avoid negation using xor
-  %b_ = fadd float 0.0, %b ; avoid negation using xor
-  %1 = fmul contract float %a_, %b_
+  %a_ = fadd float 0.0, %a   %b_ = fadd float 0.0, %b   %1 = fmul contract float %a_, %b_
   %2 = fsub contract float %c, %1
   ret float %2
 }

llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IZFINX %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64IZFINX %s
 
 ; This file tests cases where simple floating point operations can be
 ; profitably handled though bit manipulation if a soft-float ABI is being used
 ; (e.g. fneg implemented by XORing the sign bit). This is typically handled in
 ; DAGCombiner::visitBITCAST, but this target-independent code may not trigger
 ; in cases where we perform custom legalisation (e.g. RV64F).
 
 define float @fneg(float %a) nounwind {
 ; RV32I-LABEL: fneg:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fneg:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    lui a1, 524288
 ; RV32IF-NEXT:    xor a0, a0, a1
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fneg:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    lui a1, 524288
+; RV32IZFINX-NEXT:    xor a0, a0, a1
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64I-LABEL: fneg:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 524288
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IF-LABEL: fneg:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    lui a1, 524288
 ; RV64IF-NEXT:    xor a0, a0, a1
 ; RV64IF-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fneg:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    lui a1, 524288
+; RV64IZFINX-NEXT:    xor a0, a0, a1
+; RV64IZFINX-NEXT:    ret
   %1 = fneg float %a
   ret float %1
 }
 
 declare float @llvm.fabs.f32(float)
 
 define float @fabs(float %a) nounwind {
 ; RV32I-LABEL: fabs:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fabs:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    slli a0, a0, 1
 ; RV32IF-NEXT:    srli a0, a0, 1
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fabs:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    slli a0, a0, 1
+; RV32IZFINX-NEXT:    srli a0, a0, 1
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64I-LABEL: fabs:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 33
 ; RV64I-NEXT:    srli a0, a0, 33
 ; RV64I-NEXT:    ret
 ;
 ; RV64IF-LABEL: fabs:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    slli a0, a0, 33
 ; RV64IF-NEXT:    srli a0, a0, 33
 ; RV64IF-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fabs:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    slli a0, a0, 33
+; RV64IZFINX-NEXT:    srli a0, a0, 33
+; RV64IZFINX-NEXT:    ret
   %1 = call float @llvm.fabs.f32(float %a)
   ret float %1
 }
 
 declare float @llvm.copysign.f32(float, float)
 
 ; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise
 ; operations if floating point isn't supported. A combine could be written to

 ; RV32IF-NEXT:    lui a2, 524288
 ; RV32IF-NEXT:    xor a1, a1, a2
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fsgnj.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcopysign_fneg:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    lui a2, 524288
+; RV32IZFINX-NEXT:    xor a1, a1, a2
+; RV32IZFINX-NEXT:    fsgnj.s a0, a0, a1
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64I-LABEL: fcopysign_fneg:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a1, a1
 ; RV64I-NEXT:    lui a2, 524288
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    slli a0, a0, 33
 ; RV64I-NEXT:    srli a0, a0, 33
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcopysign_fneg:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fsgnjn.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcopysign_fneg:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fsgnjn.s a0, a0, a1
+; RV64IZFINX-NEXT:    ret
   %1 = fneg float %b
   %2 = call float @llvm.copysign.f32(float %a, float %1)
   ret float %2
 }

llvm/test/CodeGen/RISCV/float-br-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefix=RV32IZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefix=RV64IZFINX %s
 
 declare void @abort()
 declare void @exit(i32)
 declare float @dummy(float)
 
 define void @br_fcmp_false(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_false:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:    li a0, 1
 ; RV64IF-NEXT:    bnez a0, .LBB0_2
 ; RV64IF-NEXT:  # %bb.1: # %if.then
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB0_2: # %if.else
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_false:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    li a0, 1
+; RV32IZFINX-NEXT:    bnez a0, .LBB0_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.then
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB0_2: # %if.else
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_false:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    li a0, 1
+; RV64IZFINX-NEXT:    bnez a0, .LBB0_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.then
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB0_2: # %if.else
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp false float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.then:
   ret void
 if.else:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    feq.s a0, fa0, fa1
 ; RV64IF-NEXT:    bnez a0, .LBB1_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB1_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_oeq:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    feq.s a0, a0, a1
+; RV32IZFINX-NEXT:    bnez a0, .LBB1_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB1_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_oeq:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    feq.s a0, a0, a1
+; RV64IZFINX-NEXT:    bnez a0, .LBB1_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB1_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp oeq float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    feq.s a0, fa0, fa1
 ; RV64IF-NEXT:    bnez a0, .LBB2_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB2_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_oeq_alt:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    feq.s a0, a0, a1
+; RV32IZFINX-NEXT:    bnez a0, .LBB2_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB2_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_oeq_alt:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    feq.s a0, a0, a1
+; RV64IZFINX-NEXT:    bnez a0, .LBB2_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB2_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp oeq float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.then:
   tail call void @abort()
   unreachable
 if.else:
   ret void
 }

 ; RV64IF-NEXT:    flt.s a0, fa1, fa0
 ; RV64IF-NEXT:    bnez a0, .LBB3_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB3_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_ogt:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    flt.s a0, a1, a0
+; RV32IZFINX-NEXT:    bnez a0, .LBB3_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB3_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_ogt:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    flt.s a0, a1, a0
+; RV64IZFINX-NEXT:    bnez a0, .LBB3_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB3_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp ogt float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    fle.s a0, fa1, fa0
 ; RV64IF-NEXT:    bnez a0, .LBB4_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB4_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_oge:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    fle.s a0, a1, a0
+; RV32IZFINX-NEXT:    bnez a0, .LBB4_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB4_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_oge:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    fle.s a0, a1, a0
+; RV64IZFINX-NEXT:    bnez a0, .LBB4_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB4_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp oge float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    flt.s a0, fa0, fa1
 ; RV64IF-NEXT:    bnez a0, .LBB5_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB5_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_olt:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    flt.s a0, a0, a1
+; RV32IZFINX-NEXT:    bnez a0, .LBB5_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB5_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_olt:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    flt.s a0, a0, a1
+; RV64IZFINX-NEXT:    bnez a0, .LBB5_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB5_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp olt float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    fle.s a0, fa0, fa1
 ; RV64IF-NEXT:    bnez a0, .LBB6_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB6_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_ole:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    fle.s a0, a0, a1
+; RV32IZFINX-NEXT:    bnez a0, .LBB6_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB6_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_ole:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    fle.s a0, a0, a1
+; RV64IZFINX-NEXT:    bnez a0, .LBB6_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB6_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp ole float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    or a0, a1, a0
 ; RV64IF-NEXT:    bnez a0, .LBB7_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB7_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_one:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    flt.s a2, a0, a1
+; RV32IZFINX-NEXT:    flt.s a0, a1, a0
+; RV32IZFINX-NEXT:    or a0, a0, a2
+; RV32IZFINX-NEXT:    bnez a0, .LBB7_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB7_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_one:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    flt.s a2, a0, a1
+; RV64IZFINX-NEXT:    flt.s a0, a1, a0
+; RV64IZFINX-NEXT:    or a0, a0, a2
+; RV64IZFINX-NEXT:    bnez a0, .LBB7_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB7_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp one float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    bnez a0, .LBB8_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB8_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_ord:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    feq.s a1, a1, a1
+; RV32IZFINX-NEXT:    feq.s a0, a0, a0
+; RV32IZFINX-NEXT:    and a0, a0, a1
+; RV32IZFINX-NEXT:    bnez a0, .LBB8_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB8_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_ord:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    feq.s a1, a1, a1
+; RV64IZFINX-NEXT:    feq.s a0, a0, a0
+; RV64IZFINX-NEXT:    and a0, a0, a1
+; RV64IZFINX-NEXT:    bnez a0, .LBB8_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB8_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp ord float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    or a0, a1, a0
 ; RV64IF-NEXT:    beqz a0, .LBB9_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB9_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_ueq:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    flt.s a2, a0, a1
+; RV32IZFINX-NEXT:    flt.s a0, a1, a0
+; RV32IZFINX-NEXT:    or a0, a0, a2
+; RV32IZFINX-NEXT:    beqz a0, .LBB9_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB9_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_ueq:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    flt.s a2, a0, a1
+; RV64IZFINX-NEXT:    flt.s a0, a1, a0
+; RV64IZFINX-NEXT:    or a0, a0, a2
+; RV64IZFINX-NEXT:    beqz a0, .LBB9_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB9_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp ueq float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    fle.s a0, fa0, fa1
 ; RV64IF-NEXT:    beqz a0, .LBB10_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB10_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_ugt:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    fle.s a0, a0, a1
+; RV32IZFINX-NEXT:    beqz a0, .LBB10_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB10_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_ugt:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    fle.s a0, a0, a1
+; RV64IZFINX-NEXT:    beqz a0, .LBB10_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB10_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp ugt float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    flt.s a0, fa0, fa1
 ; RV64IF-NEXT:    beqz a0, .LBB11_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB11_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_uge:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    flt.s a0, a0, a1
+; RV32IZFINX-NEXT:    beqz a0, .LBB11_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB11_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_uge:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    flt.s a0, a0, a1
+; RV64IZFINX-NEXT:    beqz a0, .LBB11_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB11_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp uge float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    fle.s a0, fa1, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB12_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB12_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_ult:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    fle.s a0, a1, a0
+; RV32IZFINX-NEXT:    beqz a0, .LBB12_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB12_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_ult:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    fle.s a0, a1, a0
+; RV64IZFINX-NEXT:    beqz a0, .LBB12_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB12_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp ult float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    flt.s a0, fa1, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB13_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB13_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_ule:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    flt.s a0, a1, a0
+; RV32IZFINX-NEXT:    beqz a0, .LBB13_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB13_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_ule:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    flt.s a0, a1, a0
+; RV64IZFINX-NEXT:    beqz a0, .LBB13_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB13_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp ule float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    feq.s a0, fa0, fa1
 ; RV64IF-NEXT:    beqz a0, .LBB14_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB14_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_une:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    feq.s a0, a0, a1
+; RV32IZFINX-NEXT:    beqz a0, .LBB14_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB14_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_une:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    feq.s a0, a0, a1
+; RV64IZFINX-NEXT:    beqz a0, .LBB14_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB14_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp une float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    beqz a0, .LBB15_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB15_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_uno:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    feq.s a1, a1, a1
+; RV32IZFINX-NEXT:    feq.s a0, a0, a0
+; RV32IZFINX-NEXT:    and a0, a0, a1
+; RV32IZFINX-NEXT:    beqz a0, .LBB15_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB15_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_uno:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    feq.s a1, a1, a1
+; RV64IZFINX-NEXT:    feq.s a0, a0, a0
+; RV64IZFINX-NEXT:    and a0, a0, a1
+; RV64IZFINX-NEXT:    beqz a0, .LBB15_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB15_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp uno float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:    li a0, 1
 ; RV64IF-NEXT:    bnez a0, .LBB16_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB16_2: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_true:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    li a0, 1
+; RV32IZFINX-NEXT:    bnez a0, .LBB16_2
+; RV32IZFINX-NEXT:  # %bb.1: # %if.else
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB16_2: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_true:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    li a0, 1
+; RV64IZFINX-NEXT:    bnez a0, .LBB16_2
+; RV64IZFINX-NEXT:  # %bb.1: # %if.else
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB16_2: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp true float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IF-NEXT:  # %bb.2: # %if.end4
 ; RV64IF-NEXT:    li a0, 0
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB17_3: # %if.then
 ; RV64IF-NEXT:    call abort@plt
+;
+; RV32IZFINX-LABEL: br_fcmp_store_load_stack_slot:
+; RV32IZFINX:       # %bb.0: # %entry
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    li a0, 0
+; RV32IZFINX-NEXT:    call dummy@plt
+; RV32IZFINX-NEXT:    feq.s a0, a0, zero
+; RV32IZFINX-NEXT:    beqz a0, .LBB17_3
+; RV32IZFINX-NEXT:  # %bb.1: # %if.end
+; RV32IZFINX-NEXT:    li a0, 0
+; RV32IZFINX-NEXT:    call dummy@plt
+; RV32IZFINX-NEXT:    feq.s a0, a0, zero
+; RV32IZFINX-NEXT:    beqz a0, .LBB17_3
+; RV32IZFINX-NEXT:  # %bb.2: # %if.end4
+; RV32IZFINX-NEXT:    li a0, 0
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB17_3: # %if.then
+; RV32IZFINX-NEXT:    call abort@plt
+;
+; RV64IZFINX-LABEL: br_fcmp_store_load_stack_slot:
+; RV64IZFINX:       # %bb.0: # %entry
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    call dummy@plt
+; RV64IZFINX-NEXT:    feq.s a0, a0, zero
+; RV64IZFINX-NEXT:    beqz a0, .LBB17_3
+; RV64IZFINX-NEXT:  # %bb.1: # %if.end
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    call dummy@plt
+; RV64IZFINX-NEXT:    feq.s a0, a0, zero
+; RV64IZFINX-NEXT:    beqz a0, .LBB17_3
+; RV64IZFINX-NEXT:  # %bb.2: # %if.end4
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB17_3: # %if.then
+; RV64IZFINX-NEXT:    call abort@plt
 entry:
   %call = call float @dummy(float 0.000000e+00)
   %cmp = fcmp une float %call, 0.000000e+00
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   call void @abort()
   unreachable

llvm/test/CodeGen/RISCV/float-convert-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=lp64f \
-; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK,RV64IF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -disable-strictnode-mutation -target-abi=ilp32 \
+; RUN:   | FileCheck -check-prefixes=CHECKZFINX,RV32IZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -disable-strictnode-mutation -target-abi=lp64 \
+; RUN:   | FileCheck -check-prefixes=CHECKZFINX,RV64IZFINX %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
 
 ; NOTE: The rounding mode metadata does not effect which instruction is
 ; selected. Dynamic rounding mode is always used for operations that
 ; support rounding mode.
 
 define i32 @fcvt_w_s(float %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_w_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_w_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_w_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rtz
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_w_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixsfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixsfsi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
 
 define i32 @fcvt_wu_s(float %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_wu_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_wu_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_wu_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
; RV64I-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
-; RV32IF-LABEL: fcvt_wu_s_multiple_use:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV32IF-NEXT:    li a0, 1
-; RV32IF-NEXT:    beqz a1, .LBB2_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    mv a0, a1
-; RV32IF-NEXT:  .LBB2_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s_multiple_use:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV64IF-NEXT:    li a0, 1
-; RV64IF-NEXT:    beqz a1, .LBB2_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    mv a0, a1
-; RV64IF-NEXT:  .LBB2_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_wu_s_multiple_use:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.wu.s a1, fa0, rtz
+; CHECK-NEXT:    li a0, 1
+; CHECK-NEXT:    beqz a1, .LBB2_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:  .LBB2_2:
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_wu_s_multiple_use:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.wu.s a1, a0, rtz
+; CHECKZFINX-NEXT:    li a0, 1
+; CHECKZFINX-NEXT:    beqz a1, .LBB2_2
+; CHECKZFINX-NEXT:  # %bb.1:
+; CHECKZFINX-NEXT:    mv a0, a1
+; CHECKZFINX-NEXT:  .LBB2_2:
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_multiple_use:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    li a0, 1

 ; RV64I-NEXT:    ret
   %a = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %x, metadata !"fpexcept.strict") strictfp
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define float @fcvt_s_w(i32 %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_s_w:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.s.w a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata)
 
 define float @fcvt_s_w_load(i32* %p) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w_load:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lw a0, 0(a0)
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_load:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lw a0, 0(a0)
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w_load:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lw a0, 0(a0)
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_s_w_load:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    lw a0, 0(a0)
+; CHECKZFINX-NEXT:    fcvt.s.w a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_load:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = load i32, i32* %p
   %1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fcvt_s_wu(i32 %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_wu:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_wu:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.wu fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_s_wu:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.s.wu a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_s_wu_load:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    lwu a0, 0(a0)
 ; RV64IF-NEXT:    fcvt.s.wu fa0, a0
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_s_wu_load:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    lw a0, 0(a0)
+; RV32IZFINX-NEXT:    fcvt.s.wu a0, a0
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_s_wu_load:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    lwu a0, 0(a0)
+; RV64IZFINX-NEXT:    fcvt.s.wu a0, a0
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_s_wu_load:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_l_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_l_s:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call __fixsfdi@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_l_s:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_l_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixsfdi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_lu_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_lu_s:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call __fixunssfdi@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_lu_s:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_lu_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfdi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_s_l:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.s.l fa0, a0
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_s_l:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call __floatdisf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_s_l:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.s.l a0, a0
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_s_l:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatdisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_s_lu:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.s.lu fa0, a0
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_s_lu:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call __floatundisf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_s_lu:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.s.lu a0, a0
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_s_lu:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatundisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_lu:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatundisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.uitofp.f32.i64(i64, metadata, metadata)
 
 define float @fcvt_s_w_i8(i8 signext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w_i8:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_i8:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_s_w_i8:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.s.w a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.sitofp.f32.i8(i8 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.sitofp.f32.i8(i8, metadata, metadata)
 
 define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_wu_i8:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i8:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_wu_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.wu fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_s_wu_i8:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.s.wu a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_wu_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatunsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.uitofp.f32.i8(i8 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret float %1
 }
 declare float @llvm.experimental.constrained.uitofp.f32.i8(i8, metadata, metadata)
 
 define float @fcvt_s_w_i16(i16 signext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w_i16:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_i16:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_s_w_i16:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.s.w a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w_i16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.sitofp.f32.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.sitofp.f32.i16(i16, metadata, metadata)
 
 define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_wu_i16:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i16:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_wu_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.wu fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_s_wu_i16:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.s.wu a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ;
 ; RV64IF-LABEL: fcvt_s_w_demanded_bits:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addiw a0, a0, 1
 ; RV64IF-NEXT:    fcvt.s.w ft0, a0
 ; RV64IF-NEXT:    fsw ft0, 0(a1)
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_s_w_demanded_bits:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi a0, a0, 1
+; RV32IZFINX-NEXT:    fcvt.s.w a2, a0
+; RV32IZFINX-NEXT:    sw a2, 0(a1)
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_s_w_demanded_bits:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addiw a2, a0, 1
+; RV64IZFINX-NEXT:    addi a0, a0, 1
+; RV64IZFINX-NEXT:    fcvt.s.w a0, a0
+; RV64IZFINX-NEXT:    sw a0, 0(a1)
+; RV64IZFINX-NEXT:    mv a0, a2
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_s_w_demanded_bits:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1
 ; RV32I-NEXT:    addi s1, a0, 1

 ;
 ; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addiw a0, a0, 1
 ; RV64IF-NEXT:    fcvt.s.wu ft0, a0
 ; RV64IF-NEXT:    fsw ft0, 0(a1)
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_s_wu_demanded_bits:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi a0, a0, 1
+; RV32IZFINX-NEXT:    fcvt.s.wu a2, a0
+; RV32IZFINX-NEXT:    sw a2, 0(a1)
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_s_wu_demanded_bits:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addiw a0, a0, 1
+; RV64IZFINX-NEXT:    fcvt.s.wu a2, a0
+; RV64IZFINX-NEXT:    sw a2, 0(a1)
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_s_wu_demanded_bits:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1
 ; RV32I-NEXT:    addi s1, a0, 1

llvm/test/CodeGen/RISCV/float-convert.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECK,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECK,RV64IF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefixes=CHECKZFINX,RV32IZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefixes=CHECKZFINX,RV64IZFINX %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcvt_w_s(float %a) nounwind {
-; RV32IF-LABEL: fcvt_w_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_w_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_w_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rtz
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_w_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixsfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixsfsi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fptosi float %a to i32
   ret i32 %1
 }
 
 define i32 @fcvt_w_s_sat(float %a) nounwind {
-; RV32IF-LABEL: fcvt_w_s_sat:
-; RV32IF:       # %bb.0: # %start
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB1_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT:  .LBB1_2: # %start
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_w_s_sat:
-; RV64IF:       # %bb.0: # %start
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB1_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:  .LBB1_2: # %start
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_w_s_sat:
+; CHECK:       # %bb.0: # %start
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB1_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rtz
+; CHECK-NEXT:  .LBB1_2: # %start
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_w_s_sat:
+; CHECKZFINX:       # %bb.0: # %start
+; CHECKZFINX-NEXT:    feq.s a1, a0, a0
+; CHECKZFINX-NEXT:    bnez a1, .LBB1_2
+; CHECKZFINX-NEXT:  # %bb.1: # %start
+; CHECKZFINX-NEXT:    li a0, 0
+; CHECKZFINX-NEXT:    ret
+; CHECKZFINX-NEXT:  .LBB1_2:
+; CHECKZFINX-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %0
 }
 declare i32 @llvm.fptosi.sat.i32.f32(float)
 
 define i32 @fcvt_wu_s(float %a) nounwind {
-; RV32IF-LABEL: fcvt_wu_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_wu_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_wu_s:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = fptoui float %a to i32
   ret i32 %1
 }
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
-; RV32IF-LABEL: fcvt_wu_s_multiple_use:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV32IF-NEXT:    li a0, 1
-; RV32IF-NEXT:    beqz a1, .LBB3_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    mv a0, a1
-; RV32IF-NEXT:  .LBB3_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s_multiple_use:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV64IF-NEXT:    li a0, 1
-; RV64IF-NEXT:    beqz a1, .LBB3_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    mv a0, a1
-; RV64IF-NEXT:  .LBB3_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_wu_s_multiple_use:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.wu.s a1, fa0, rtz
+; CHECK-NEXT:    li a0, 1
+; CHECK-NEXT:    beqz a1, .LBB3_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:  .LBB3_2:
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_wu_s_multiple_use:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.wu.s a1, a0, rtz
+; CHECKZFINX-NEXT:    li a0, 1
+; CHECKZFINX-NEXT:    beqz a1, .LBB3_2
+; CHECKZFINX-NEXT:  # %bb.1:
+; CHECKZFINX-NEXT:    mv a0, a1
+; CHECKZFINX-NEXT:  .LBB3_2:
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_multiple_use:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    li a0, 1

 ; RV64I-NEXT:    ret
   %a = fptoui float %x to i32
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i32 @fcvt_wu_s_sat(float %a) nounwind {
-; RV32IF-LABEL: fcvt_wu_s_sat:
-; RV32IF:       # %bb.0: # %start
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB4_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT:  .LBB4_2: # %start
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s_sat:
-; RV64IF:       # %bb.0: # %start
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB4_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT:  .LBB4_2: # %start
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_wu_s_sat:
+; CHECK:       # %bb.0: # %start
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB4_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECK-NEXT:  .LBB4_2: # %start
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_wu_s_sat:
+; CHECKZFINX:       # %bb.0: # %start
+; CHECKZFINX-NEXT:    feq.s a1, a0, a0
+; CHECKZFINX-NEXT:    bnez a1, .LBB4_2
+; CHECKZFINX-NEXT:  # %bb.1: # %start
+; CHECKZFINX-NEXT:    li a0, 0
+; CHECKZFINX-NEXT:    ret
+; CHECKZFINX-NEXT:  .LBB4_2:
+; CHECKZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %0
 }
 declare i32 @llvm.fptoui.sat.i32.f32(float)
 
 define i32 @fmv_x_w(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmv_x_w:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV32IF-NEXT:    fmv.x.w a0, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmv_x_w:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV64IF-NEXT:    fmv.x.w a0, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmv_x_w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s ft0, fa0, fa1
+; CHECK-NEXT:    fmv.x.w a0, ft0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fmv_x_w:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fmv_x_w:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
 ; Ensure fmv.x.w is generated even for a soft float calling convention
   %1 = fadd float %a, %b
   %2 = bitcast float %1 to i32
   ret i32 %2
 }
 
 define float @fcvt_s_w(i32 %a) nounwind {
-; RV32IF-LABEL: fcvt_s_w:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_s_w:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.s.w a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = sitofp i32 %a to float
   ret float %1
 }
 
 define float @fcvt_s_w_load(i32* %p) nounwind {
-; RV32IF-LABEL: fcvt_s_w_load:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lw a0, 0(a0)
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_load:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lw a0, 0(a0)
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w_load:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lw a0, 0(a0)
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_s_w_load:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    lw a0, 0(a0)
+; CHECKZFINX-NEXT:    fcvt.s.w a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_load:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = load i32, i32* %p
   %1 = sitofp i32 %a to float
   ret float %1
 }
 
 define float @fcvt_s_wu(i32 %a) nounwind {
-; RV32IF-LABEL: fcvt_s_wu:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_wu:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.wu fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_s_wu:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.s.wu a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_s_wu_load:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    lwu a0, 0(a0)
 ; RV64IF-NEXT:    fcvt.s.wu fa0, a0
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_s_wu_load:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    lw a0, 0(a0)
+; RV32IZFINX-NEXT:    fcvt.s.wu a0, a0
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_s_wu_load:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    lwu a0, 0(a0)
+; RV64IZFINX-NEXT:    fcvt.s.wu a0, a0
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_s_wu_load:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = load i32, i32* %p
   %1 = uitofp i32 %a to float
   ret float %1
 }
 
 define float @fmv_w_x(i32 %a, i32 %b) nounwind {
-; RV32IF-LABEL: fmv_w_x:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, a0
-; RV32IF-NEXT:    fmv.w.x ft1, a1
-; RV32IF-NEXT:    fadd.s fa0, ft0, ft1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmv_w_x:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, a0
-; RV64IF-NEXT:    fmv.w.x ft1, a1
-; RV64IF-NEXT:    fadd.s fa0, ft0, ft1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmv_w_x:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    fmv.w.x ft1, a1
+; CHECK-NEXT:    fadd.s fa0, ft0, ft1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fmv_w_x:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fmv_w_x:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_l_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_l_s:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call __fixsfdi@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_l_s:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_l_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixsfdi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0: # %start
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB12_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
 ; RV64IF-NEXT:  .LBB12_2: # %start
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_l_s_sat:
+; RV32IZFINX:       # %bb.0: # %start
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    lui a1, %hi(.LCPI12_0)
+; RV32IZFINX-NEXT:    lw a1, %lo(.LCPI12_0)(a1)
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    fle.s s1, a1, a0
+; RV32IZFINX-NEXT:    call __fixsfdi@plt
+; RV32IZFINX-NEXT:    mv a2, a0
+; RV32IZFINX-NEXT:    bnez s1, .LBB12_2
+; RV32IZFINX-NEXT:  # %bb.1: # %start
+; RV32IZFINX-NEXT:    li a2, 0
+; RV32IZFINX-NEXT:  .LBB12_2: # %start
+; RV32IZFINX-NEXT:    lui a0, %hi(.LCPI12_1)
+; RV32IZFINX-NEXT:    lw a0, %lo(.LCPI12_1)(a0)
+; RV32IZFINX-NEXT:    flt.s a3, a0, s0
+; RV32IZFINX-NEXT:    li a0, -1
+; RV32IZFINX-NEXT:    beqz a3, .LBB12_9
+; RV32IZFINX-NEXT:  # %bb.3: # %start
+; RV32IZFINX-NEXT:    feq.s a2, s0, s0
+; RV32IZFINX-NEXT:    beqz a2, .LBB12_10
+; RV32IZFINX-NEXT:  .LBB12_4: # %start
+; RV32IZFINX-NEXT:    lui a4, 524288
+; RV32IZFINX-NEXT:    beqz s1, .LBB12_11
+; RV32IZFINX-NEXT:  .LBB12_5: # %start
+; RV32IZFINX-NEXT:    bnez a3, .LBB12_12
+; RV32IZFINX-NEXT:  .LBB12_6: # %start
+; RV32IZFINX-NEXT:    bnez a2, .LBB12_8
+; RV32IZFINX-NEXT:  .LBB12_7: # %start
+; RV32IZFINX-NEXT:    li a1, 0
+; RV32IZFINX-NEXT:  .LBB12_8: # %start
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB12_9: # %start
+; RV32IZFINX-NEXT:    mv a0, a2
+; RV32IZFINX-NEXT:    feq.s a2, s0, s0
+; RV32IZFINX-NEXT:    bnez a2, .LBB12_4
+; RV32IZFINX-NEXT:  .LBB12_10: # %start
+; RV32IZFINX-NEXT:    li a0, 0
+; RV32IZFINX-NEXT:    lui a4, 524288
+; RV32IZFINX-NEXT:    bnez s1, .LBB12_5
+; RV32IZFINX-NEXT:  .LBB12_11: # %start
+; RV32IZFINX-NEXT:    lui a1, 524288
+; RV32IZFINX-NEXT:    beqz a3, .LBB12_6
+; RV32IZFINX-NEXT:  .LBB12_12:
+; RV32IZFINX-NEXT:    addi a1, a4, -1
+; RV32IZFINX-NEXT:    beqz a2, .LBB12_7
+; RV32IZFINX-NEXT:    j .LBB12_8
+;
+; RV64IZFINX-LABEL: fcvt_l_s_sat:
+; RV64IZFINX:       # %bb.0: # %start
+; RV64IZFINX-NEXT:    feq.s a1, a0, a0
+; RV64IZFINX-NEXT:    bnez a1, .LBB12_2
+; RV64IZFINX-NEXT:  # %bb.1: # %start
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB12_2:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_l_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_lu_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_lu_s:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call __fixunssfdi@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_lu_s:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_lu_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfdi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0: # %start
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB14_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
 ; RV64IF-NEXT:  .LBB14_2: # %start
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_lu_s_sat:
+; RV32IZFINX:       # %bb.0: # %start
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    fle.s s1, zero, a0
+; RV32IZFINX-NEXT:    call __fixunssfdi@plt
+; RV32IZFINX-NEXT:    mv a3, a0
+; RV32IZFINX-NEXT:    bnez s1, .LBB14_2
+; RV32IZFINX-NEXT:  # %bb.1: # %start
+; RV32IZFINX-NEXT:    li a3, 0
+; RV32IZFINX-NEXT:  .LBB14_2: # %start
+; RV32IZFINX-NEXT:    lui a0, %hi(.LCPI14_0)
+; RV32IZFINX-NEXT:    lw a0, %lo(.LCPI14_0)(a0)
+; RV32IZFINX-NEXT:    flt.s a4, a0, s0
+; RV32IZFINX-NEXT:    li a2, -1
+; RV32IZFINX-NEXT:    li a0, -1
+; RV32IZFINX-NEXT:    beqz a4, .LBB14_7
+; RV32IZFINX-NEXT:  # %bb.3: # %start
+; RV32IZFINX-NEXT:    beqz s1, .LBB14_8
+; RV32IZFINX-NEXT:  .LBB14_4: # %start
+; RV32IZFINX-NEXT:    bnez a4, .LBB14_6
+; RV32IZFINX-NEXT:  .LBB14_5: # %start
+; RV32IZFINX-NEXT:    mv a2, a1
+; RV32IZFINX-NEXT:  .LBB14_6: # %start
+; RV32IZFINX-NEXT:    mv a1, a2
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB14_7: # %start
+; RV32IZFINX-NEXT:    mv a0, a3
+; RV32IZFINX-NEXT:    bnez s1, .LBB14_4
+; RV32IZFINX-NEXT:  .LBB14_8: # %start
+; RV32IZFINX-NEXT:    li a1, 0
+; RV32IZFINX-NEXT:    beqz a4, .LBB14_5
+; RV32IZFINX-NEXT:    j .LBB14_6
+;
+; RV64IZFINX-LABEL: fcvt_lu_s_sat:
+; RV64IZFINX:       # %bb.0: # %start
+; RV64IZFINX-NEXT:    feq.s a1, a0, a0
+; RV64IZFINX-NEXT:    bnez a1, .LBB14_2
+; RV64IZFINX-NEXT:  # %bb.1: # %start
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB14_2:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_lu_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_s_l:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.s.l fa0, a0
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_s_l:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call __floatdisf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_s_l:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.s.l a0, a0
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_s_l:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatdisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_s_lu:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.s.lu fa0, a0
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_s_lu:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call __floatundisf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_s_lu:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.s.lu a0, a0
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_s_lu:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatundisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_lu:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatundisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = uitofp i64 %a to float
   ret float %1
 }
 
 define float @fcvt_s_w_i8(i8 signext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_w_i8:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_i8:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_s_w_i8:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.s.w a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = sitofp i8 %a to float
   ret float %1
 }
 
 define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_wu_i8:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i8:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_wu_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.wu fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_s_wu_i8:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.s.wu a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_wu_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatunsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = uitofp i8 %a to float
   ret float %1
 }
 
 define float @fcvt_s_w_i16(i16 signext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_w_i16:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_i16:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_s_w_i16:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.s.w a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w_i16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = sitofp i16 %a to float
   ret float %1
 }
 
 define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_wu_i16:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i16:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_wu_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.wu fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcvt_s_wu_i16:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.s.wu a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ;
 ; RV64IF-LABEL: fcvt_s_w_demanded_bits:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addiw a0, a0, 1
 ; RV64IF-NEXT:    fcvt.s.w ft0, a0
 ; RV64IF-NEXT:    fsw ft0, 0(a1)
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_s_w_demanded_bits:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi a0, a0, 1
+; RV32IZFINX-NEXT:    fcvt.s.w a2, a0
+; RV32IZFINX-NEXT:    sw a2, 0(a1)
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_s_w_demanded_bits:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addiw a2, a0, 1
+; RV64IZFINX-NEXT:    addi a0, a0, 1
+; RV64IZFINX-NEXT:    fcvt.s.w a0, a0
+; RV64IZFINX-NEXT:    sw a0, 0(a1)
+; RV64IZFINX-NEXT:    mv a0, a2
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_s_w_demanded_bits:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1
 ; RV32I-NEXT:    addi s1, a0, 1

 ;
 ; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addiw a0, a0, 1
 ; RV64IF-NEXT:    fcvt.s.wu ft0, a0
 ; RV64IF-NEXT:    fsw ft0, 0(a1)
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_s_wu_demanded_bits:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi a0, a0, 1
+; RV32IZFINX-NEXT:    fcvt.s.wu a2, a0
+; RV32IZFINX-NEXT:    sw a2, 0(a1)
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_s_wu_demanded_bits:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addiw a0, a0, 1
+; RV64IZFINX-NEXT:    fcvt.s.wu a2, a0
+; RV64IZFINX-NEXT:    sw a2, 0(a1)
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_s_wu_demanded_bits:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1
 ; RV32I-NEXT:    addi s1, a0, 1

 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_w_s_i16:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_w_s_i16:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_w_s_i16:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_w_s_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixsfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF-NEXT:    lui a0, %hi(.LCPI24_1)
 ; RV64IF-NEXT:    flw ft1, %lo(.LCPI24_1)(a0)
 ; RV64IF-NEXT:    fmax.s ft0, fa0, ft0
 ; RV64IF-NEXT:    fmin.s ft0, ft0, ft1
 ; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
 ; RV64IF-NEXT:  .LBB24_2: # %start
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_w_s_sat_i16:
+; RV32IZFINX:       # %bb.0: # %start
+; RV32IZFINX-NEXT:    feq.s a1, a0, a0
+; RV32IZFINX-NEXT:    bnez a1, .LBB24_2
+; RV32IZFINX-NEXT:  # %bb.1: # %start
+; RV32IZFINX-NEXT:    li a0, 0
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB24_2:
+; RV32IZFINX-NEXT:    lui a1, %hi(.LCPI24_0)
+; RV32IZFINX-NEXT:    lw a1, %lo(.LCPI24_0)(a1)
+; RV32IZFINX-NEXT:    lui a2, %hi(.LCPI24_1)
+; RV32IZFINX-NEXT:    lw a2, %lo(.LCPI24_1)(a2)
+; RV32IZFINX-NEXT:    fmax.s a0, a0, a1
+; RV32IZFINX-NEXT:    fmin.s a0, a0, a2
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_w_s_sat_i16:
+; RV64IZFINX:       # %bb.0: # %start
+; RV64IZFINX-NEXT:    feq.s a1, a0, a0
+; RV64IZFINX-NEXT:    bnez a1, .LBB24_2
+; RV64IZFINX-NEXT:  # %bb.1: # %start
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB24_2:
+; RV64IZFINX-NEXT:    lui a1, %hi(.LCPI24_0)
+; RV64IZFINX-NEXT:    lw a1, %lo(.LCPI24_0)(a1)
+; RV64IZFINX-NEXT:    lui a2, %hi(.LCPI24_1)
+; RV64IZFINX-NEXT:    lw a2, %lo(.LCPI24_1)(a2)
+; RV64IZFINX-NEXT:    fmax.s a0, a0, a1
+; RV64IZFINX-NEXT:    fmin.s a0, a0, a2
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_w_s_sat_i16:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_wu_s_i16:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_wu_s_i16:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_wu_s_i16:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_wu_s_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF-NEXT:    lui a0, %hi(.LCPI26_0)
 ; RV64IF-NEXT:    flw ft0, %lo(.LCPI26_0)(a0)
 ; RV64IF-NEXT:    fmv.w.x ft1, zero
 ; RV64IF-NEXT:    fmax.s ft1, fa0, ft1
 ; RV64IF-NEXT:    fmin.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fcvt.lu.s a0, ft0, rtz
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_wu_s_sat_i16:
+; RV32IZFINX:       # %bb.0: # %start
+; RV32IZFINX-NEXT:    lui a1, %hi(.LCPI26_0)
+; RV32IZFINX-NEXT:    lw a1, %lo(.LCPI26_0)(a1)
+; RV32IZFINX-NEXT:    fmax.s a0, a0, zero
+; RV32IZFINX-NEXT:    fmin.s a0, a0, a1
+; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_wu_s_sat_i16:
+; RV64IZFINX:       # %bb.0: # %start
+; RV64IZFINX-NEXT:    lui a1, %hi(.LCPI26_0)
+; RV64IZFINX-NEXT:    lw a1, %lo(.LCPI26_0)(a1)
+; RV64IZFINX-NEXT:    fmax.s a0, a0, zero
+; RV64IZFINX-NEXT:    fmin.s a0, a0, a1
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_wu_s_sat_i16:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0

 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_w_s_i8:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_w_s_i8:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_w_s_i8:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_w_s_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixsfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF-NEXT:    lui a0, %hi(.LCPI28_1)
 ; RV64IF-NEXT:    flw ft1, %lo(.LCPI28_1)(a0)
 ; RV64IF-NEXT:    fmax.s ft0, fa0, ft0
 ; RV64IF-NEXT:    fmin.s ft0, ft0, ft1
 ; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
 ; RV64IF-NEXT:  .LBB28_2: # %start
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_w_s_sat_i8:
+; RV32IZFINX:       # %bb.0: # %start
+; RV32IZFINX-NEXT:    feq.s a1, a0, a0
+; RV32IZFINX-NEXT:    bnez a1, .LBB28_2
+; RV32IZFINX-NEXT:  # %bb.1: # %start
+; RV32IZFINX-NEXT:    li a0, 0
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB28_2:
+; RV32IZFINX-NEXT:    lui a1, %hi(.LCPI28_0)
+; RV32IZFINX-NEXT:    lw a1, %lo(.LCPI28_0)(a1)
+; RV32IZFINX-NEXT:    lui a2, %hi(.LCPI28_1)
+; RV32IZFINX-NEXT:    lw a2, %lo(.LCPI28_1)(a2)
+; RV32IZFINX-NEXT:    fmax.s a0, a0, a1
+; RV32IZFINX-NEXT:    fmin.s a0, a0, a2
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_w_s_sat_i8:
+; RV64IZFINX:       # %bb.0: # %start
+; RV64IZFINX-NEXT:    feq.s a1, a0, a0
+; RV64IZFINX-NEXT:    bnez a1, .LBB28_2
+; RV64IZFINX-NEXT:  # %bb.1: # %start
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB28_2:
+; RV64IZFINX-NEXT:    lui a1, %hi(.LCPI28_0)
+; RV64IZFINX-NEXT:    lw a1, %lo(.LCPI28_0)(a1)
+; RV64IZFINX-NEXT:    lui a2, %hi(.LCPI28_1)
+; RV64IZFINX-NEXT:    lw a2, %lo(.LCPI28_1)(a2)
+; RV64IZFINX-NEXT:    fmax.s a0, a0, a1
+; RV64IZFINX-NEXT:    fmin.s a0, a0, a2
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_w_s_sat_i8:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_wu_s_i8:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_wu_s_i8:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_wu_s_i8:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_wu_s_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF-NEXT:    lui a0, %hi(.LCPI30_0)
 ; RV64IF-NEXT:    flw ft0, %lo(.LCPI30_0)(a0)
 ; RV64IF-NEXT:    fmv.w.x ft1, zero
 ; RV64IF-NEXT:    fmax.s ft1, fa0, ft1
 ; RV64IF-NEXT:    fmin.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fcvt.lu.s a0, ft0, rtz
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fcvt_wu_s_sat_i8:
+; RV32IZFINX:       # %bb.0: # %start
+; RV32IZFINX-NEXT:    lui a1, %hi(.LCPI30_0)
+; RV32IZFINX-NEXT:    lw a1, %lo(.LCPI30_0)(a1)
+; RV32IZFINX-NEXT:    fmax.s a0, a0, zero
+; RV32IZFINX-NEXT:    fmin.s a0, a0, a1
+; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fcvt_wu_s_sat_i8:
+; RV64IZFINX:       # %bb.0: # %start
+; RV64IZFINX-NEXT:    lui a1, %hi(.LCPI30_0)
+; RV64IZFINX-NEXT:    lw a1, %lo(.LCPI30_0)(a1)
+; RV64IZFINX-NEXT:    fmax.s a0, a0, zero
+; RV64IZFINX-NEXT:    fmin.s a0, a0, a1
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_wu_s_sat_i8:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0

llvm/test/CodeGen/RISCV/float-fcmp-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=lp64f \
-; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -disable-strictnode-mutation -target-abi=ilp32 \
+; RUN:   | FileCheck -check-prefixes=CHECKZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -disable-strictnode-mutation -target-abi=lp64 \
+; RUN:   | FileCheck -check-prefixes=CHECKZFINX %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcmp_oeq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_oeq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_oeq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_oeq:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __eqsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata)
 
 define i32 @fcmp_ogt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ogt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a1
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    fsflags a1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ogt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a1
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    fsflags a1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ogt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a1
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    fsflags a1
+; CHECK-NEXT:    feq.s zero, fa1, fa0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_ogt:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    frflags a3
+; CHECKZFINX-NEXT:    flt.s a2, a1, a0
+; CHECKZFINX-NEXT:    fsflags a3
+; CHECKZFINX-NEXT:    feq.s zero, a1, a0
+; CHECKZFINX-NEXT:    mv a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_oge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a1
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    fsflags a1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_oge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a1
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    fsflags a1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_oge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a1
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    fsflags a1
+; CHECK-NEXT:    feq.s zero, fa1, fa0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_oge:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    frflags a3
+; CHECKZFINX-NEXT:    fle.s a2, a1, a0
+; CHECKZFINX-NEXT:    fsflags a3
+; CHECKZFINX-NEXT:    feq.s zero, a1, a0
+; CHECKZFINX-NEXT:    mv a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_olt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_olt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a1
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    fsflags a1
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_olt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a1
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    fsflags a1
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_olt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a1
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    fsflags a1
+; CHECK-NEXT:    feq.s zero, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_olt:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    frflags a3
+; CHECKZFINX-NEXT:    flt.s a2, a0, a1
+; CHECKZFINX-NEXT:    fsflags a3
+; CHECKZFINX-NEXT:    feq.s zero, a0, a1
+; CHECKZFINX-NEXT:    mv a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ole(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ole:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a1
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    fsflags a1
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ole:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a1
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    fsflags a1
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ole:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a1
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    fsflags a1
+; CHECK-NEXT:    feq.s zero, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_ole:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    frflags a3
+; CHECKZFINX-NEXT:    fle.s a2, a0, a1
+; CHECKZFINX-NEXT:    fsflags a3
+; CHECKZFINX-NEXT:    feq.s zero, a0, a1
+; CHECKZFINX-NEXT:    mv a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 ; FIXME: We only need one frflags before the two flts and one fsflags after the
 ; two flts.
 define i32 @fcmp_one(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_one:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a1, fa0, fa1
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a2, fa1, fa0
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    or a0, a2, a1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_one:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a1, fa0, fa1
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a2, fa1, fa0
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    or a0, a2, a1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.s a1, fa0, fa1
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    feq.s zero, fa0, fa1
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.s a2, fa1, fa0
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    or a0, a2, a1
+; CHECK-NEXT:    feq.s zero, fa1, fa0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_one:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    frflags a2
+; CHECKZFINX-NEXT:    flt.s a3, a0, a1
+; CHECKZFINX-NEXT:    fsflags a2
+; CHECKZFINX-NEXT:    feq.s zero, a0, a1
+; CHECKZFINX-NEXT:    frflags a2
+; CHECKZFINX-NEXT:    flt.s a4, a1, a0
+; CHECKZFINX-NEXT:    fsflags a2
+; CHECKZFINX-NEXT:    or a2, a4, a3
+; CHECKZFINX-NEXT:    feq.s zero, a1, a0
+; CHECKZFINX-NEXT:    mv a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"one", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ord(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ord:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ord:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ord:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa1, fa1
+; CHECK-NEXT:    feq.s a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_ord:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a1, a1, a1
+; CHECKZFINX-NEXT:    feq.s a0, a0, a0
+; CHECKZFINX-NEXT:    and a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 ; FIXME: We only need one frflags before the two flts and one fsflags after the
 ; two flts.
 define i32 @fcmp_ueq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ueq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a1, fa0, fa1
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a2, fa1, fa0
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    or a0, a2, a1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ueq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a1, fa0, fa1
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a2, fa1, fa0
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    or a0, a2, a1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ueq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.s a1, fa0, fa1
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    feq.s zero, fa0, fa1
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.s a2, fa1, fa0
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    or a0, a2, a1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    feq.s zero, fa1, fa0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_ueq:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    frflags a2
+; CHECKZFINX-NEXT:    flt.s a3, a0, a1
+; CHECKZFINX-NEXT:    fsflags a2
+; CHECKZFINX-NEXT:    feq.s zero, a0, a1
+; CHECKZFINX-NEXT:    frflags a2
+; CHECKZFINX-NEXT:    flt.s a4, a1, a0
+; CHECKZFINX-NEXT:    fsflags a2
+; CHECKZFINX-NEXT:    or a2, a4, a3
+; CHECKZFINX-NEXT:    xori a2, a2, 1
+; CHECKZFINX-NEXT:    feq.s zero, a1, a0
+; CHECKZFINX-NEXT:    mv a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ugt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    fle.s a1, fa0, fa1
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    xori a0, a1, 1
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ugt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    fle.s a1, fa0, fa1
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    xori a0, a1, 1
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ugt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    fle.s a1, fa0, fa1
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    xori a0, a1, 1
+; CHECK-NEXT:    feq.s zero, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_ugt:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    frflags a2
+; CHECKZFINX-NEXT:    fle.s a3, a0, a1
+; CHECKZFINX-NEXT:    fsflags a2
+; CHECKZFINX-NEXT:    xori a2, a3, 1
+; CHECKZFINX-NEXT:    feq.s zero, a0, a1
+; CHECKZFINX-NEXT:    mv a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_uge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a1, fa0, fa1
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    xori a0, a1, 1
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_uge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a1, fa0, fa1
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    xori a0, a1, 1
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_uge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.s a1, fa0, fa1
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    xori a0, a1, 1
+; CHECK-NEXT:    feq.s zero, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_uge:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    frflags a2
+; CHECKZFINX-NEXT:    flt.s a3, a0, a1
+; CHECKZFINX-NEXT:    fsflags a2
+; CHECKZFINX-NEXT:    xori a2, a3, 1
+; CHECKZFINX-NEXT:    feq.s zero, a0, a1
+; CHECKZFINX-NEXT:    mv a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ult:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    fle.s a1, fa1, fa0
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    xori a0, a1, 1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ult:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    fle.s a1, fa1, fa0
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    xori a0, a1, 1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ult:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    fle.s a1, fa1, fa0
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    xori a0, a1, 1
+; CHECK-NEXT:    feq.s zero, fa1, fa0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_ult:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    frflags a2
+; CHECKZFINX-NEXT:    fle.s a3, a1, a0
+; CHECKZFINX-NEXT:    fsflags a2
+; CHECKZFINX-NEXT:    xori a2, a3, 1
+; CHECKZFINX-NEXT:    feq.s zero, a1, a0
+; CHECKZFINX-NEXT:    mv a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ule:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    xori a0, a1, 1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ule:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    xori a0, a1, 1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ule:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.s a1, fa1, fa0
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    xori a0, a1, 1
+; CHECK-NEXT:    feq.s zero, fa1, fa0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_ule:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    frflags a2
+; CHECKZFINX-NEXT:    flt.s a3, a1, a0
+; CHECKZFINX-NEXT:    fsflags a2
+; CHECKZFINX-NEXT:    xori a2, a3, 1
+; CHECKZFINX-NEXT:    feq.s zero, a1, a0
+; CHECKZFINX-NEXT:    mv a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_une:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_une:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_une:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_une:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a0, a0, a1
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __nesf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"une", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uno(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_uno:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_uno:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_uno:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa1, fa1
+; CHECK-NEXT:    feq.s a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_uno:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a1, a1, a1
+; CHECKZFINX-NEXT:    feq.s a0, a0, a0
+; CHECKZFINX-NEXT:    and a0, a0, a1
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"uno", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oeq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_oeq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    fle.s a1, fa0, fa1
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_oeq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    fle.s a1, fa0, fa1
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    fle.s a1, fa0, fa1
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmps_oeq:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fle.s a2, a1, a0
+; CHECKZFINX-NEXT:    fle.s a0, a0, a1
+; CHECKZFINX-NEXT:    and a0, a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __eqsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 declare i1 @llvm.experimental.constrained.fcmps.f32(float, float, metadata, metadata)
 
 define i32 @fcmps_ogt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ogt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ogt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_ogt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmps_ogt:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    flt.s a0, a1, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_oge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_oge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_oge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmps_oge:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fle.s a0, a1, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_olt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_olt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_olt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_olt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmps_olt:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    flt.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ole(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ole:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ole:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_ole:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmps_ole:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fle.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_one(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_one:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_one:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    flt.s a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmps_one:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    flt.s a2, a0, a1
+; CHECKZFINX-NEXT:    flt.s a0, a1, a0
+; CHECKZFINX-NEXT:    or a0, a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"one", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ord(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ord:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa1
-; RV32IF-NEXT:    fle.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ord:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa1
-; RV64IF-NEXT:    fle.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_ord:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa1
+; CHECK-NEXT:    fle.s a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmps_ord:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fle.s a1, a1, a1
+; CHECKZFINX-NEXT:    fle.s a0, a0, a0
+; CHECKZFINX-NEXT:    and a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ueq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ueq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ueq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_ueq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    flt.s a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmps_ueq:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    flt.s a2, a0, a1
+; CHECKZFINX-NEXT:    flt.s a0, a1, a0
+; CHECKZFINX-NEXT:    or a0, a0, a2
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ugt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ugt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ugt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_ugt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmps_ugt:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fle.s a0, a0, a1
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_uge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_uge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_uge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_uge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmps_uge:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    flt.s a0, a0, a1
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ult(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ult:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ult:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_ult:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmps_ult:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fle.s a0, a1, a0
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ule(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ule:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ule:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_ule:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmps_ule:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    flt.s a0, a1, a0
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_une(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_une:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    fle.s a1, fa0, fa1
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_une:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    fle.s a1, fa0, fa1
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_une:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    fle.s a1, fa0, fa1
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmps_une:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fle.s a2, a1, a0
+; CHECKZFINX-NEXT:    fle.s a0, a0, a1
+; CHECKZFINX-NEXT:    and a0, a0, a2
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __nesf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"une", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_uno(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_uno:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa1
-; RV32IF-NEXT:    fle.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_uno:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa1
-; RV64IF-NEXT:    fle.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_uno:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa1
+; CHECK-NEXT:    fle.s a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmps_uno:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fle.s a1, a1, a1
+; CHECKZFINX-NEXT:    fle.s a0, a0, a0
+; CHECKZFINX-NEXT:    and a0, a0, a1
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

llvm/test/CodeGen/RISCV/float-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECK %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefixes=CHECKZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefixes=CHECKZFINX %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcmp_false(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_false:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_false:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_false:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_false:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    li a0, 0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_false:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_false:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 0
 ; RV64I-NEXT:    ret
   %1 = fcmp false float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oeq(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_oeq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_oeq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_oeq:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __eqsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp oeq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ogt(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ogt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ogt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ogt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_ogt:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    flt.s a0, a1, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ogt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_oge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_oge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_oge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_oge:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fle.s a0, a1, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp oge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_olt(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_olt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_olt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_olt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_olt:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    flt.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp olt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ole(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ole:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ole:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ole:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_ole:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fle.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ole float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_one(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_one:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_one:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    flt.s a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_one:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    flt.s a2, a0, a1
+; CHECKZFINX-NEXT:    flt.s a0, a1, a0
+; CHECKZFINX-NEXT:    or a0, a0, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = fcmp one float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ord(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ord:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ord:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ord:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa1, fa1
+; CHECK-NEXT:    feq.s a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_ord:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a1, a1, a1
+; CHECKZFINX-NEXT:    feq.s a0, a0, a0
+; CHECKZFINX-NEXT:    and a0, a0, a1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ord float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ueq(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ueq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ueq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ueq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    flt.s a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_ueq:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    flt.s a2, a0, a1
+; CHECKZFINX-NEXT:    flt.s a0, a1, a0
+; CHECKZFINX-NEXT:    or a0, a0, a2
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = fcmp ueq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ugt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ugt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ugt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_ugt:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fle.s a0, a0, a1
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ugt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_uge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_uge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_uge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_uge:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    flt.s a0, a0, a1
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp uge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ult:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ult:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ult:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_ult:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fle.s a0, a1, a0
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ult float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ule:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ule:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ule:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_ule:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    flt.s a0, a1, a0
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ule float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_une:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_une:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_une:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_une:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a0, a0, a1
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __nesf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp une float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uno(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_uno:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_uno:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_uno:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa1, fa1
+; CHECK-NEXT:    feq.s a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_uno:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a1, a1, a1
+; CHECKZFINX-NEXT:    feq.s a0, a0, a0
+; CHECKZFINX-NEXT:    and a0, a0, a1
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp uno float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_true(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_true:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    li a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_true:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    li a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_true:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 1
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fcmp_true:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    li a0, 1
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_true:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_true:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp true float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/float-frem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64IZFINX %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 define float @frem_f32(float %a, float %b) nounwind {
 ; RV32IF-LABEL: frem_f32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call fmodf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: frem_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call fmodf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: frem_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call fmodf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: frem_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call fmodf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: frem_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmodf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

llvm/test/CodeGen/RISCV/float-imm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECK %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefixes=CHECKZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefixes=CHECKZFINX %s
 
 ; TODO: constant pool shouldn't be necessary for RV64IF.
 define float @float_imm() nounwind {
-; RV32IF-LABEL: float_imm:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lui a0, %hi(.LCPI0_0)
-; RV32IF-NEXT:    flw fa0, %lo(.LCPI0_0)(a0)
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: float_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI0_0)
+; CHECK-NEXT:    flw fa0, %lo(.LCPI0_0)(a0)
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: float_imm:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lui a0, %hi(.LCPI0_0)
-; RV64IF-NEXT:    flw fa0, %lo(.LCPI0_0)(a0)
-; RV64IF-NEXT:    ret
+; RV32IZFINX-LABEL: float_imm:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    lui a0, 263313
+; RV32IZFINX-NEXT:    addi a0, a0, -37
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: float_imm:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    lui a0, %hi(.LCPI0_0)
+; RV64IZFINX-NEXT:    lw a0, %lo(.LCPI0_0)(a0)
+; RV64IZFINX-NEXT:    ret
   ret float 3.14159274101257324218750
 }
 
 define float @float_imm_op(float %a) nounwind {
-; RV32IF-LABEL: float_imm_op:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
-; RV32IF-NEXT:    fadd.s fa0, fa0, ft0
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: float_imm_op:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI1_0)
+; CHECK-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
+; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: float_imm_op:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV64IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
-; RV64IF-NEXT:    fadd.s fa0, fa0, ft0
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: float_imm_op:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    lui a1, %hi(.LCPI1_0)
+; CHECKZFINX-NEXT:    lw a1, %lo(.LCPI1_0)(a1)
+; CHECKZFINX-NEXT:    fadd.s a0, a0, a1
+; CHECKZFINX-NEXT:    ret
   %1 = fadd float %a, 1.0
   ret float %1
 }

llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK,RV32IF %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64f \
-; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK,RV64IF %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx \
+; RUN:   -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32 \
+; RUN:   | FileCheck -check-prefixes=CHECKZFINX,RV32IZFINX %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx \
+; RUN:   -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64 \
+; RUN:   | FileCheck -check-prefixes=CHECKZFINX,RV64IZFINX %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata)
 
 define float @sqrt_f32(float %a) nounwind strictfp {
-; RV32IF-LABEL: sqrt_f32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsqrt.s fa0, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: sqrt_f32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsqrt.s fa0, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: sqrt_f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsqrt.s fa0, fa0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: sqrt_f32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fsqrt.s a0, a0
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: sqrt_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sqrtf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    sext.w a0, a0
 ; RV64IF-NEXT:    call __powisf2@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: powi_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call __powisf2@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: powi_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    sext.w a1, a1
+; RV64IZFINX-NEXT:    call __powisf2@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: powi_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __powisf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call sinf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: sin_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call sinf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: sin_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call sinf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: sin_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sinf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call cosf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: cos_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call cosf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: cos_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call cosf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: cos_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call cosf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF-NEXT:    call cosf@plt
 ; RV64IF-NEXT:    fadd.s fa0, fs1, fa0
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV64IF-NEXT:    flw fs1, 0(sp) # 4-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: sincos_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    call sinf@plt
+; RV32IZFINX-NEXT:    mv s1, a0
+; RV32IZFINX-NEXT:    mv a0, s0
+; RV32IZFINX-NEXT:    call cosf@plt
+; RV32IZFINX-NEXT:    fadd.s a0, s1, a0
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: sincos_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -32
+; RV64IZFINX-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    mv s0, a0
+; RV64IZFINX-NEXT:    call sinf@plt
+; RV64IZFINX-NEXT:    mv s1, a0
+; RV64IZFINX-NEXT:    mv a0, s0
+; RV64IZFINX-NEXT:    call cosf@plt
+; RV64IZFINX-NEXT:    fadd.s a0, s1, a0
+; RV64IZFINX-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 32
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: sincos_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    call sinf@plt

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call powf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: pow_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call powf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: pow_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call powf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: pow_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call powf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call expf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: exp_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call expf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: exp_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call expf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: exp_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call expf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call exp2f@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: exp2_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call exp2f@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: exp2_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call exp2f@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: exp2_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call exp2f@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call logf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: log_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call logf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: log_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call logf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: log_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call logf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call log10f@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: log10_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call log10f@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: log10_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call log10f@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: log10_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call log10f@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call log2f@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: log2_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call log2f@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: log2_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call log2f@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: log2_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call log2f@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: log2_f32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call log2f@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.log2.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata)
 
 define float @fma_f32(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fma_f32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fma_f32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fma_f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fma_f32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fma_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 declare float @llvm.experimental.constrained.fmuladd.f32(float, float, float, metadata, metadata)
 
 define float @fmuladd_f32(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fmuladd_f32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmuladd_f32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmuladd_f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: fmuladd_f32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECKZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fmuladd_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    call __mulsf3@plt

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call fminf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: minnum_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call fminf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: minnum_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call fminf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: minnum_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fminf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call fmaxf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: maxnum_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call fmaxf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: maxnum_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call fmaxf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: maxnum_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaxf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call floorf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: floor_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call floorf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: floor_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call floorf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: floor_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call floorf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call ceilf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: ceil_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call ceilf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: ceil_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call ceilf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: ceil_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call ceilf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call truncf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: trunc_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call truncf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: trunc_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call truncf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: trunc_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call truncf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call rintf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: rint_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call rintf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: rint_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call rintf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: rint_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call rintf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call nearbyintf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: nearbyint_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call nearbyintf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: nearbyint_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call nearbyintf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: nearbyint_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call nearbyintf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call roundf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: round_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call roundf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: round_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call roundf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: round_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call roundf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call roundevenf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: roundeven_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call roundevenf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: roundeven_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call roundevenf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: roundeven_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call roundevenf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF-NEXT:    fcvt.w.s a0, fa0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: lrint_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: lrint_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: lrint_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: lrint_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call lrintf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: lround_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: lround_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rmm
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: lround_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: lround_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call lroundf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: llrint_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: llrint_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call llrintf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: llrint_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: llrint_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call llrintf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: llround_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
 ; RV64IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: llround_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call llroundf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: llround_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: llround_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call llroundf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

llvm/test/CodeGen/RISCV/float-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \
 ; RUN:   -verify-machineinstrs -target-abi=ilp32f \
 ; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx \
+; RUN:   -verify-machineinstrs -target-abi=ilp32 \
+; RUN:   | FileCheck -check-prefix=RV32IZFINX %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
 ; RUN:   -verify-machineinstrs -target-abi=ilp32f \
 ; RUN:   | FileCheck -check-prefix=RV32IF %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \
 ; RUN:   -verify-machineinstrs -target-abi=lp64f \
 ; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx \
+; RUN:   -verify-machineinstrs -target-abi=lp64 \
+; RUN:   | FileCheck -check-prefix=RV64IZFINX %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
 ; RUN:   -verify-machineinstrs -target-abi=lp64d \
 ; RUN:   | FileCheck -check-prefix=RV64IF %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
 ; RUN:   -verify-machineinstrs | FileCheck -check-prefix=RV32I %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
 ; RUN:   -verify-machineinstrs | FileCheck -check-prefix=RV64I %s
 
 declare float @llvm.sqrt.f32(float)
 
 define float @sqrt_f32(float %a) nounwind {
 ; RV32IF-LABEL: sqrt_f32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fsqrt.s fa0, fa0
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: sqrt_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fsqrt.s a0, a0
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: sqrt_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fsqrt.s fa0, fa0
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: sqrt_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fsqrt.s a0, a0
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: sqrt_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sqrtf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call __powisf2@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: powi_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call __powisf2@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: powi_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    sext.w a0, a0
 ; RV64IF-NEXT:    call __powisf2@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: powi_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    sext.w a1, a1
+; RV64IZFINX-NEXT:    call __powisf2@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: powi_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __powisf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call sinf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: sin_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call sinf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: sin_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call sinf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: sin_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call sinf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: sin_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sinf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call cosf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: cos_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call cosf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: cos_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call cosf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: cos_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call cosf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: cos_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call cosf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF-NEXT:    call cosf@plt
 ; RV32IF-NEXT:    fadd.s fa0, fs1, fa0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs1, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: sincos_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    call sinf@plt
+; RV32IZFINX-NEXT:    mv s1, a0
+; RV32IZFINX-NEXT:    mv a0, s0
+; RV32IZFINX-NEXT:    call cosf@plt
+; RV32IZFINX-NEXT:    fadd.s a0, s1, a0
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: sincos_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -32
+; RV64IZFINX-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    mv s0, a0
+; RV64IZFINX-NEXT:    call sinf@plt
+; RV64IZFINX-NEXT:    mv s1, a0
+; RV64IZFINX-NEXT:    mv a0, s0
+; RV64IZFINX-NEXT:    call cosf@plt
+; RV64IZFINX-NEXT:    fadd.s a0, s1, a0
+; RV64IZFINX-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 32
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: sincos_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    call sinf@plt

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call powf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: pow_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call powf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: pow_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call powf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: pow_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call powf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: pow_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call powf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call expf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: exp_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call expf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: exp_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call expf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: exp_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call expf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: exp_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call expf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call exp2f@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: exp2_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call exp2f@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: exp2_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call exp2f@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: exp2_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call exp2f@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: exp2_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call exp2f@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call logf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: log_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call logf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: log_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call logf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: log_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call logf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: log_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call logf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call log10f@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: log10_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call log10f@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: log10_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call log10f@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: log10_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call log10f@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: log10_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call log10f@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call log2f@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: log2_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call log2f@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: log2_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call log2f@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: log2_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call log2f@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: log2_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call log2f@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 declare float @llvm.fma.f32(float, float, float)
 
 define float @fma_f32(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fma_f32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fma_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fmadd.s a0, a0, a1, a2
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: fma_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: fma_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fmadd.s a0, a0, a1, a2
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fma_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 declare float @llvm.fmuladd.f32(float, float, float)
 
 define float @fmuladd_f32(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fmuladd_f32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fmuladd_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fmadd.s a0, a0, a1, a2
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: fmuladd_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: fmuladd_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fmadd.s a0, a0, a1, a2
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fmuladd_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    call __mulsf3@plt
 ; RV32I-NEXT:    mv a1, s0

 declare float @llvm.fabs.f32(float)
 
 define float @fabs_f32(float %a) nounwind {
 ; RV32IF-LABEL: fabs_f32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fabs.s fa0, fa0
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: fabs_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    slli a0, a0, 1
+; RV32IZFINX-NEXT:    srli a0, a0, 1
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: fabs_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fabs.s fa0, fa0
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: fabs_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    slli a0, a0, 33
+; RV64IZFINX-NEXT:    srli a0, a0, 33
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fabs_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fabs_f32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 33
 ; RV64I-NEXT:    srli a0, a0, 33
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.fabs.f32(float %a)
   ret float %1
 }
 
 declare float @llvm.minnum.f32(float, float)
 
 define float @minnum_f32(float %a, float %b) nounwind {
 ; RV32IF-LABEL: minnum_f32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmin.s fa0, fa0, fa1
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: minnum_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fmin.s a0, a0, a1
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: minnum_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmin.s fa0, fa0, fa1
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: minnum_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fmin.s a0, a0, a1
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: minnum_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fminf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 declare float @llvm.maxnum.f32(float, float)
 
 define float @maxnum_f32(float %a, float %b) nounwind {
 ; RV32IF-LABEL: maxnum_f32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmax.s fa0, fa0, fa1
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: maxnum_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fmax.s a0, a0, a1
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: maxnum_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmax.s fa0, fa0, fa1
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: maxnum_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fmax.s a0, a0, a1
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: maxnum_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaxf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 declare float @llvm.copysign.f32(float, float)
 
 define float @copysign_f32(float %a, float %b) nounwind {
 ; RV32IF-LABEL: copysign_f32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fsgnj.s fa0, fa0, fa1
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: copysign_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fsgnj.s a0, a0, a1
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: copysign_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fsgnj.s fa0, fa0, fa1
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: copysign_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fsgnj.s a0, a0, a1
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: copysign_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a2, 524288
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call floorf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: floor_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call floorf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: floor_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call floorf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: floor_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call floorf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: floor_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call floorf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call ceilf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: ceil_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call ceilf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: ceil_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call ceilf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: ceil_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call ceilf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: ceil_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call ceilf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call truncf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: trunc_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call truncf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: trunc_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call truncf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: trunc_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call truncf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: trunc_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call truncf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call rintf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: rint_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call rintf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: rint_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call rintf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: rint_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call rintf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: rint_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call rintf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call nearbyintf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: nearbyint_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call nearbyintf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: nearbyint_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call nearbyintf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: nearbyint_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call nearbyintf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: nearbyint_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call nearbyintf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call roundf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: round_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call roundf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: round_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call roundf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: round_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call roundf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: round_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call roundf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call roundevenf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: roundeven_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call roundevenf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: roundeven_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call roundevenf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: roundeven_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    call roundevenf@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: roundeven_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call roundevenf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 declare iXLen @llvm.lrint.iXLen.f32(float)
 
 define iXLen @lrint_f32(float %a) nounwind {
 ; RV32IF-LABEL: lrint_f32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: lrint_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: lrint_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: lrint_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: lrint_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call lrintf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 declare iXLen @llvm.lround.iXLen.f32(float)
 
 define iXLen @lround_f32(float %a) nounwind {
 ; RV32IF-LABEL: lround_f32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: lround_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rmm
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: lround_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: lround_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: lround_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call lroundf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call llrintf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: llrint_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call llrintf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: llrint_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: llrint_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: llrint_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call llrintf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call llroundf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
+; RV32IZFINX-LABEL: llround_f32:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call llroundf@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
 ; RV64IF-LABEL: llround_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
 ; RV64IF-NEXT:    ret
 ;
+; RV64IZFINX-LABEL: llround_f32:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
+; RV64IZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: llround_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call llroundf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

llvm/test/CodeGen/RISCV/float-isnan.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \
-; RUN:   < %s | FileCheck -check-prefix=RV32IF %s
+; RUN:   < %s | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \
-; RUN:   < %s | FileCheck -check-prefix=RV64IF %s
+; RUN:   < %s | FileCheck -check-prefixes=CHECK %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -target-abi ilp32 -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefixes=CHECKZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -target-abi lp64 -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefixes=CHECKZFINX %s
 
 define zeroext i1 @float_is_nan(float %a) nounwind {
-; RV32IF-LABEL: float_is_nan:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: float_is_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: float_is_nan:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: float_is_nan:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a0, a0, a0
+; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    ret
   %1 = fcmp uno float %a, 0.000000e+00
   ret i1 %1
 }
 
 define zeroext i1 @float_not_nan(float %a) nounwind {
-; RV32IF-LABEL: float_not_nan:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: float_not_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: float_not_nan:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: float_not_nan:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a0, a0, a0
+; CHECKZFINX-NEXT:    ret
   %1 = fcmp ord float %a, 0.000000e+00
   ret i1 %1
 }

llvm/test/CodeGen/RISCV/float-mem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECK,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECK,RV64IF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefixes=CHECKZFINX,RV32IZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefixes=CHECKZFINX,RV64IZFINX %s
 
 define dso_local float @flw(float *%a) nounwind {
-; RV32IF-LABEL: flw:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flw ft0, 0(a0)
-; RV32IF-NEXT:    flw ft1, 12(a0)
-; RV32IF-NEXT:    fadd.s fa0, ft0, ft1
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: flw:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flw ft0, 0(a0)
+; CHECK-NEXT:    flw ft1, 12(a0)
+; CHECK-NEXT:    fadd.s fa0, ft0, ft1
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: flw:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flw ft0, 0(a0)
-; RV64IF-NEXT:    flw ft1, 12(a0)
-; RV64IF-NEXT:    fadd.s fa0, ft0, ft1
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: flw:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    lw a1, 0(a0)
+; CHECKZFINX-NEXT:    lw a0, 12(a0)
+; CHECKZFINX-NEXT:    fadd.s a0, a1, a0
+; CHECKZFINX-NEXT:    ret
   %1 = load float, float* %a
   %2 = getelementptr float, float* %a, i32 3
   %3 = load float, float* %2
 ; Use both loaded values in an FP op to ensure an flw is used, even for the
 ; soft float ABI
   %4 = fadd float %1, %3
   ret float %4
 }
 
 define dso_local void @fsw(float *%a, float %b, float %c) nounwind {
 ; Use %b and %c in an FP op to ensure floating point registers are used, even
 ; for the soft float ABI
-; RV32IF-LABEL: fsw:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV32IF-NEXT:    fsw ft0, 0(a0)
-; RV32IF-NEXT:    fsw ft0, 32(a0)
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: fsw:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s ft0, fa0, fa1
+; CHECK-NEXT:    fsw ft0, 0(a0)
+; CHECK-NEXT:    fsw ft0, 32(a0)
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: fsw:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV64IF-NEXT:    fsw ft0, 0(a0)
-; RV64IF-NEXT:    fsw ft0, 32(a0)
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: fsw:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a1, a1, a2
+; CHECKZFINX-NEXT:    sw a1, 0(a0)
+; CHECKZFINX-NEXT:    sw a1, 32(a0)
+; CHECKZFINX-NEXT:    ret
   %1 = fadd float %b, %c
   store float %1, float* %a
   %2 = getelementptr float, float* %a, i32 8
   store float %1, float* %2
   ret void
 }
 
 ; Check load and store to a global
 @G = dso_local global float 0.0
 
 define dso_local float @flw_fsw_global(float %a, float %b) nounwind {
 ; Use %a and %b in an FP op to ensure floating point registers are used, even
 ; for the soft float ABI
-; RV32IF-LABEL: flw_fsw_global:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV32IF-NEXT:    lui a0, %hi(G)
-; RV32IF-NEXT:    flw ft0, %lo(G)(a0)
-; RV32IF-NEXT:    fsw fa0, %lo(G)(a0)
-; RV32IF-NEXT:    addi a0, a0, %lo(G)
-; RV32IF-NEXT:    flw ft0, 36(a0)
-; RV32IF-NEXT:    fsw fa0, 36(a0)
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: flw_fsw_global:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s fa0, fa0, fa1
+; CHECK-NEXT:    lui a0, %hi(G)
+; CHECK-NEXT:    flw ft0, %lo(G)(a0)
+; CHECK-NEXT:    fsw fa0, %lo(G)(a0)
+; CHECK-NEXT:    addi a0, a0, %lo(G)
+; CHECK-NEXT:    flw ft0, 36(a0)
+; CHECK-NEXT:    fsw fa0, 36(a0)
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: flw_fsw_global:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV64IF-NEXT:    lui a0, %hi(G)
-; RV64IF-NEXT:    flw ft0, %lo(G)(a0)
-; RV64IF-NEXT:    fsw fa0, %lo(G)(a0)
-; RV64IF-NEXT:    addi a0, a0, %lo(G)
-; RV64IF-NEXT:    flw ft0, 36(a0)
-; RV64IF-NEXT:    fsw fa0, 36(a0)
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: flw_fsw_global:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fadd.s a0, a0, a1
+; CHECKZFINX-NEXT:    lui a1, %hi(G)
+; CHECKZFINX-NEXT:    lw a2, %lo(G)(a1)
+; CHECKZFINX-NEXT:    sw a0, %lo(G)(a1)
+; CHECKZFINX-NEXT:    addi a1, a1, %lo(G)
+; CHECKZFINX-NEXT:    lw a2, 36(a1)
+; CHECKZFINX-NEXT:    sw a0, 36(a1)
+; CHECKZFINX-NEXT:    ret
   %1 = fadd float %a, %b
   %2 = load volatile float, float* @G
   store float %1, float* @G
   %3 = getelementptr float, float* @G, i32 9
   %4 = load volatile float, float* %3
   store float %1, float* %3
   ret float %1
 }

 ; RV64IF-LABEL: flw_fsw_constant:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    lui a0, 228023
 ; RV64IF-NEXT:    slli a0, a0, 2
 ; RV64IF-NEXT:    flw ft0, -273(a0)
 ; RV64IF-NEXT:    fadd.s fa0, fa0, ft0
 ; RV64IF-NEXT:    fsw fa0, -273(a0)
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: flw_fsw_constant:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    lui a1, 912092
+; RV32IZFINX-NEXT:    lw a2, -273(a1)
+; RV32IZFINX-NEXT:    fadd.s a0, a0, a2
+; RV32IZFINX-NEXT:    sw a0, -273(a1)
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: flw_fsw_constant:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    lui a1, 228023
+; RV64IZFINX-NEXT:    slli a1, a1, 2
+; RV64IZFINX-NEXT:    lw a2, -273(a1)
+; RV64IZFINX-NEXT:    fadd.s a0, a0, a2
+; RV64IZFINX-NEXT:    sw a0, -273(a1)
+; RV64IZFINX-NEXT:    ret
   %1 = inttoptr i32 3735928559 to float*
   %2 = load volatile float, float* %1
   %3 = fadd float %a, %2
   store float %3, float* %1
   ret float %3
 }
 
 declare void @notdead(i8*)

 ; RV64IF-NEXT:    mv a0, sp
 ; RV64IF-NEXT:    call notdead@plt
 ; RV64IF-NEXT:    flw ft0, 0(sp)
 ; RV64IF-NEXT:    fadd.s fa0, ft0, fs0
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: flw_stack:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    addi a0, sp, 4
+; RV32IZFINX-NEXT:    call notdead@plt
+; RV32IZFINX-NEXT:    lw a0, 4(sp)
+; RV32IZFINX-NEXT:    fadd.s a0, a0, s0
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: flw_stack:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -32
+; RV64IZFINX-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    mv s0, a0
+; RV64IZFINX-NEXT:    addi a0, sp, 12
+; RV64IZFINX-NEXT:    call notdead@plt
+; RV64IZFINX-NEXT:    lw a0, 12(sp)
+; RV64IZFINX-NEXT:    fadd.s a0, a0, s0
+; RV64IZFINX-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 32
+; RV64IZFINX-NEXT:    ret
   %1 = alloca float, align 4
   %2 = bitcast float* %1 to i8*
   call void @notdead(i8* %2)
   %3 = load float, float* %1
   %4 = fadd float %3, %a ; force load in to FPR32
   ret float %4
 }
 

 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
 ; RV64IF-NEXT:    fsw ft0, 4(sp)
 ; RV64IF-NEXT:    addi a0, sp, 4
 ; RV64IF-NEXT:    call notdead@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: fsw_stack:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    fadd.s a0, a0, a1
+; RV32IZFINX-NEXT:    sw a0, 8(sp)
+; RV32IZFINX-NEXT:    addi a0, sp, 8
+; RV32IZFINX-NEXT:    call notdead@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: fsw_stack:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    addi sp, sp, -16
+; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT:    fadd.s a0, a0, a1
+; RV64IZFINX-NEXT:    sw a0, 4(sp)
+; RV64IZFINX-NEXT:    addi a0, sp, 4
+; RV64IZFINX-NEXT:    call notdead@plt
+; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT:    addi sp, sp, 16
+; RV64IZFINX-NEXT:    ret
   %1 = fadd float %a, %b ; force store from FPR32
   %2 = alloca float, align 4
   store float %1, float* %2
   %3 = bitcast float* %2 to i8*
   call void @notdead(i8* %3)
   ret void
 }

llvm/test/CodeGen/RISCV/float-round-conv-sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECK,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECK,RV64IF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefixes=CHECKZFINX,RV32IZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefixes=CHECKZFINX,RV64IZFINX %s
 
 define signext i32 @test_floor_si32(float %x) {
-; RV32IF-LABEL: test_floor_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB0_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
-; RV32IF-NEXT:  .LBB0_2:
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: test_floor_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB0_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rdn
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: test_floor_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB0_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rdn
-; RV64IF-NEXT:  .LBB0_2:
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: test_floor_si32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a1, a0, a0
+; CHECKZFINX-NEXT:    bnez a1, .LBB0_2
+; CHECKZFINX-NEXT:  # %bb.1:
+; CHECKZFINX-NEXT:    li a0, 0
+; CHECKZFINX-NEXT:    ret
+; CHECKZFINX-NEXT:  .LBB0_2:
+; CHECKZFINX-NEXT:    fcvt.w.s a0, a0, rdn
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_floor_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_floor_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-LABEL: test_floor_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB1_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rdn
 ; RV64IF-NEXT:  .LBB1_2:
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_floor_si64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call floorf@plt
+; RV32IZFINX-NEXT:    lui a1, %hi(.LCPI1_0)
+; RV32IZFINX-NEXT:    lw a1, %lo(.LCPI1_0)(a1)
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    fle.s s1, a1, a0
+; RV32IZFINX-NEXT:    call __fixsfdi@plt
+; RV32IZFINX-NEXT:    mv a2, a0
+; RV32IZFINX-NEXT:    bnez s1, .LBB1_2
+; RV32IZFINX-NEXT:  # %bb.1:
+; RV32IZFINX-NEXT:    li a2, 0
+; RV32IZFINX-NEXT:  .LBB1_2:
+; RV32IZFINX-NEXT:    lui a0, %hi(.LCPI1_1)
+; RV32IZFINX-NEXT:    lw a0, %lo(.LCPI1_1)(a0)
+; RV32IZFINX-NEXT:    flt.s a3, a0, s0
+; RV32IZFINX-NEXT:    li a0, -1
+; RV32IZFINX-NEXT:    beqz a3, .LBB1_9
+; RV32IZFINX-NEXT:  # %bb.3:
+; RV32IZFINX-NEXT:    feq.s a2, s0, s0
+; RV32IZFINX-NEXT:    beqz a2, .LBB1_10
+; RV32IZFINX-NEXT:  .LBB1_4:
+; RV32IZFINX-NEXT:    lui a4, 524288
+; RV32IZFINX-NEXT:    beqz s1, .LBB1_11
+; RV32IZFINX-NEXT:  .LBB1_5:
+; RV32IZFINX-NEXT:    bnez a3, .LBB1_12
+; RV32IZFINX-NEXT:  .LBB1_6:
+; RV32IZFINX-NEXT:    bnez a2, .LBB1_8
+; RV32IZFINX-NEXT:  .LBB1_7:
+; RV32IZFINX-NEXT:    li a1, 0
+; RV32IZFINX-NEXT:  .LBB1_8:
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB1_9:
+; RV32IZFINX-NEXT:    mv a0, a2
+; RV32IZFINX-NEXT:    feq.s a2, s0, s0
+; RV32IZFINX-NEXT:    bnez a2, .LBB1_4
+; RV32IZFINX-NEXT:  .LBB1_10:
+; RV32IZFINX-NEXT:    li a0, 0
+; RV32IZFINX-NEXT:    lui a4, 524288
+; RV32IZFINX-NEXT:    bnez s1, .LBB1_5
+; RV32IZFINX-NEXT:  .LBB1_11:
+; RV32IZFINX-NEXT:    lui a1, 524288
+; RV32IZFINX-NEXT:    beqz a3, .LBB1_6
+; RV32IZFINX-NEXT:  .LBB1_12:
+; RV32IZFINX-NEXT:    addi a1, a4, -1
+; RV32IZFINX-NEXT:    beqz a2, .LBB1_7
+; RV32IZFINX-NEXT:    j .LBB1_8
+;
+; RV64IZFINX-LABEL: test_floor_si64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    feq.s a1, a0, a0
+; RV64IZFINX-NEXT:    bnez a1, .LBB1_2
+; RV64IZFINX-NEXT:  # %bb.1:
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB1_2:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rdn
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_floor_ui32(float %x) {
-; RV32IF-LABEL: test_floor_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB2_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rdn
-; RV32IF-NEXT:  .LBB2_2:
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: test_floor_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB2_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rdn
+; CHECK-NEXT:  .LBB2_2:
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: test_floor_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB2_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rdn
-; RV64IF-NEXT:  .LBB2_2:
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: test_floor_ui32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a1, a0, a0
+; CHECKZFINX-NEXT:    bnez a1, .LBB2_2
+; CHECKZFINX-NEXT:  # %bb.1:
+; CHECKZFINX-NEXT:    li a0, 0
+; CHECKZFINX-NEXT:    ret
+; CHECKZFINX-NEXT:  .LBB2_2:
+; CHECKZFINX-NEXT:    fcvt.wu.s a0, a0, rdn
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_floor_ui64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-LABEL: test_floor_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB3_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
 ; RV64IF-NEXT:  .LBB3_2:
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_floor_ui64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call floorf@plt
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    fle.s s1, zero, a0
+; RV32IZFINX-NEXT:    call __fixunssfdi@plt
+; RV32IZFINX-NEXT:    mv a3, a0
+; RV32IZFINX-NEXT:    bnez s1, .LBB3_2
+; RV32IZFINX-NEXT:  # %bb.1:
+; RV32IZFINX-NEXT:    li a3, 0
+; RV32IZFINX-NEXT:  .LBB3_2:
+; RV32IZFINX-NEXT:    lui a0, %hi(.LCPI3_0)
+; RV32IZFINX-NEXT:    lw a0, %lo(.LCPI3_0)(a0)
+; RV32IZFINX-NEXT:    flt.s a4, a0, s0
+; RV32IZFINX-NEXT:    li a2, -1
+; RV32IZFINX-NEXT:    li a0, -1
+; RV32IZFINX-NEXT:    beqz a4, .LBB3_7
+; RV32IZFINX-NEXT:  # %bb.3:
+; RV32IZFINX-NEXT:    beqz s1, .LBB3_8
+; RV32IZFINX-NEXT:  .LBB3_4:
+; RV32IZFINX-NEXT:    bnez a4, .LBB3_6
+; RV32IZFINX-NEXT:  .LBB3_5:
+; RV32IZFINX-NEXT:    mv a2, a1
+; RV32IZFINX-NEXT:  .LBB3_6:
+; RV32IZFINX-NEXT:    mv a1, a2
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB3_7:
+; RV32IZFINX-NEXT:    mv a0, a3
+; RV32IZFINX-NEXT:    bnez s1, .LBB3_4
+; RV32IZFINX-NEXT:  .LBB3_8:
+; RV32IZFINX-NEXT:    li a1, 0
+; RV32IZFINX-NEXT:    beqz a4, .LBB3_5
+; RV32IZFINX-NEXT:    j .LBB3_6
+;
+; RV64IZFINX-LABEL: test_floor_ui64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    feq.s a1, a0, a0
+; RV64IZFINX-NEXT:    bnez a1, .LBB3_2
+; RV64IZFINX-NEXT:  # %bb.1:
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB3_2:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rdn
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_si32(float %x) {
-; RV32IF-LABEL: test_ceil_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB4_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
-; RV32IF-NEXT:  .LBB4_2:
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: test_ceil_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB4_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rup
+; CHECK-NEXT:  .LBB4_2:
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: test_ceil_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB4_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rup
-; RV64IF-NEXT:  .LBB4_2:
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: test_ceil_si32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a1, a0, a0
+; CHECKZFINX-NEXT:    bnez a1, .LBB4_2
+; CHECKZFINX-NEXT:  # %bb.1:
+; CHECKZFINX-NEXT:    li a0, 0
+; CHECKZFINX-NEXT:    ret
+; CHECKZFINX-NEXT:  .LBB4_2:
+; CHECKZFINX-NEXT:    fcvt.w.s a0, a0, rup
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_ceil_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-LABEL: test_ceil_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB5_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rup
 ; RV64IF-NEXT:  .LBB5_2:
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_ceil_si64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call ceilf@plt
+; RV32IZFINX-NEXT:    lui a1, %hi(.LCPI5_0)
+; RV32IZFINX-NEXT:    lw a1, %lo(.LCPI5_0)(a1)
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    fle.s s1, a1, a0
+; RV32IZFINX-NEXT:    call __fixsfdi@plt
+; RV32IZFINX-NEXT:    mv a2, a0
+; RV32IZFINX-NEXT:    bnez s1, .LBB5_2
+; RV32IZFINX-NEXT:  # %bb.1:
+; RV32IZFINX-NEXT:    li a2, 0
+; RV32IZFINX-NEXT:  .LBB5_2:
+; RV32IZFINX-NEXT:    lui a0, %hi(.LCPI5_1)
+; RV32IZFINX-NEXT:    lw a0, %lo(.LCPI5_1)(a0)
+; RV32IZFINX-NEXT:    flt.s a3, a0, s0
+; RV32IZFINX-NEXT:    li a0, -1
+; RV32IZFINX-NEXT:    beqz a3, .LBB5_9
+; RV32IZFINX-NEXT:  # %bb.3:
+; RV32IZFINX-NEXT:    feq.s a2, s0, s0
+; RV32IZFINX-NEXT:    beqz a2, .LBB5_10
+; RV32IZFINX-NEXT:  .LBB5_4:
+; RV32IZFINX-NEXT:    lui a4, 524288
+; RV32IZFINX-NEXT:    beqz s1, .LBB5_11
+; RV32IZFINX-NEXT:  .LBB5_5:
+; RV32IZFINX-NEXT:    bnez a3, .LBB5_12
+; RV32IZFINX-NEXT:  .LBB5_6:
+; RV32IZFINX-NEXT:    bnez a2, .LBB5_8
+; RV32IZFINX-NEXT:  .LBB5_7:
+; RV32IZFINX-NEXT:    li a1, 0
+; RV32IZFINX-NEXT:  .LBB5_8:
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB5_9:
+; RV32IZFINX-NEXT:    mv a0, a2
+; RV32IZFINX-NEXT:    feq.s a2, s0, s0
+; RV32IZFINX-NEXT:    bnez a2, .LBB5_4
+; RV32IZFINX-NEXT:  .LBB5_10:
+; RV32IZFINX-NEXT:    li a0, 0
+; RV32IZFINX-NEXT:    lui a4, 524288
+; RV32IZFINX-NEXT:    bnez s1, .LBB5_5
+; RV32IZFINX-NEXT:  .LBB5_11:
+; RV32IZFINX-NEXT:    lui a1, 524288
+; RV32IZFINX-NEXT:    beqz a3, .LBB5_6
+; RV32IZFINX-NEXT:  .LBB5_12:
+; RV32IZFINX-NEXT:    addi a1, a4, -1
+; RV32IZFINX-NEXT:    beqz a2, .LBB5_7
+; RV32IZFINX-NEXT:    j .LBB5_8
+;
+; RV64IZFINX-LABEL: test_ceil_si64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    feq.s a1, a0, a0
+; RV64IZFINX-NEXT:    bnez a1, .LBB5_2
+; RV64IZFINX-NEXT:  # %bb.1:
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB5_2:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rup
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_ui32(float %x) {
-; RV32IF-LABEL: test_ceil_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB6_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rup
-; RV32IF-NEXT:  .LBB6_2:
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: test_ceil_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB6_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rup
+; CHECK-NEXT:  .LBB6_2:
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: test_ceil_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB6_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rup
-; RV64IF-NEXT:  .LBB6_2:
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: test_ceil_ui32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a1, a0, a0
+; CHECKZFINX-NEXT:    bnez a1, .LBB6_2
+; CHECKZFINX-NEXT:  # %bb.1:
+; CHECKZFINX-NEXT:    li a0, 0
+; CHECKZFINX-NEXT:    ret
+; CHECKZFINX-NEXT:  .LBB6_2:
+; CHECKZFINX-NEXT:    fcvt.wu.s a0, a0, rup
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_ceil_ui64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-LABEL: test_ceil_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB7_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
 ; RV64IF-NEXT:  .LBB7_2:
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_ceil_ui64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call ceilf@plt
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    fle.s s1, zero, a0
+; RV32IZFINX-NEXT:    call __fixunssfdi@plt
+; RV32IZFINX-NEXT:    mv a3, a0
+; RV32IZFINX-NEXT:    bnez s1, .LBB7_2
+; RV32IZFINX-NEXT:  # %bb.1:
+; RV32IZFINX-NEXT:    li a3, 0
+; RV32IZFINX-NEXT:  .LBB7_2:
+; RV32IZFINX-NEXT:    lui a0, %hi(.LCPI7_0)
+; RV32IZFINX-NEXT:    lw a0, %lo(.LCPI7_0)(a0)
+; RV32IZFINX-NEXT:    flt.s a4, a0, s0
+; RV32IZFINX-NEXT:    li a2, -1
+; RV32IZFINX-NEXT:    li a0, -1
+; RV32IZFINX-NEXT:    beqz a4, .LBB7_7
+; RV32IZFINX-NEXT:  # %bb.3:
+; RV32IZFINX-NEXT:    beqz s1, .LBB7_8
+; RV32IZFINX-NEXT:  .LBB7_4:
+; RV32IZFINX-NEXT:    bnez a4, .LBB7_6
+; RV32IZFINX-NEXT:  .LBB7_5:
+; RV32IZFINX-NEXT:    mv a2, a1
+; RV32IZFINX-NEXT:  .LBB7_6:
+; RV32IZFINX-NEXT:    mv a1, a2
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB7_7:
+; RV32IZFINX-NEXT:    mv a0, a3
+; RV32IZFINX-NEXT:    bnez s1, .LBB7_4
+; RV32IZFINX-NEXT:  .LBB7_8:
+; RV32IZFINX-NEXT:    li a1, 0
+; RV32IZFINX-NEXT:    beqz a4, .LBB7_5
+; RV32IZFINX-NEXT:    j .LBB7_6
+;
+; RV64IZFINX-LABEL: test_ceil_ui64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    feq.s a1, a0, a0
+; RV64IZFINX-NEXT:    bnez a1, .LBB7_2
+; RV64IZFINX-NEXT:  # %bb.1:
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB7_2:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rup
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_si32(float %x) {
-; RV32IF-LABEL: test_trunc_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB8_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT:  .LBB8_2:
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: test_trunc_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB8_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rtz
+; CHECK-NEXT:  .LBB8_2:
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: test_trunc_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB8_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:  .LBB8_2:
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: test_trunc_si32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a1, a0, a0
+; CHECKZFINX-NEXT:    bnez a1, .LBB8_2
+; CHECKZFINX-NEXT:  # %bb.1:
+; CHECKZFINX-NEXT:    li a0, 0
+; CHECKZFINX-NEXT:    ret
+; CHECKZFINX-NEXT:  .LBB8_2:
+; CHECKZFINX-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_trunc_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-LABEL: test_trunc_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB9_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
 ; RV64IF-NEXT:  .LBB9_2:
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_trunc_si64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call truncf@plt
+; RV32IZFINX-NEXT:    lui a1, %hi(.LCPI9_0)
+; RV32IZFINX-NEXT:    lw a1, %lo(.LCPI9_0)(a1)
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    fle.s s1, a1, a0
+; RV32IZFINX-NEXT:    call __fixsfdi@plt
+; RV32IZFINX-NEXT:    mv a2, a0
+; RV32IZFINX-NEXT:    bnez s1, .LBB9_2
+; RV32IZFINX-NEXT:  # %bb.1:
+; RV32IZFINX-NEXT:    li a2, 0
+; RV32IZFINX-NEXT:  .LBB9_2:
+; RV32IZFINX-NEXT:    lui a0, %hi(.LCPI9_1)
+; RV32IZFINX-NEXT:    lw a0, %lo(.LCPI9_1)(a0)
+; RV32IZFINX-NEXT:    flt.s a3, a0, s0
+; RV32IZFINX-NEXT:    li a0, -1
+; RV32IZFINX-NEXT:    beqz a3, .LBB9_9
+; RV32IZFINX-NEXT:  # %bb.3:
+; RV32IZFINX-NEXT:    feq.s a2, s0, s0
+; RV32IZFINX-NEXT:    beqz a2, .LBB9_10
+; RV32IZFINX-NEXT:  .LBB9_4:
+; RV32IZFINX-NEXT:    lui a4, 524288
+; RV32IZFINX-NEXT:    beqz s1, .LBB9_11
+; RV32IZFINX-NEXT:  .LBB9_5:
+; RV32IZFINX-NEXT:    bnez a3, .LBB9_12
+; RV32IZFINX-NEXT:  .LBB9_6:
+; RV32IZFINX-NEXT:    bnez a2, .LBB9_8
+; RV32IZFINX-NEXT:  .LBB9_7:
+; RV32IZFINX-NEXT:    li a1, 0
+; RV32IZFINX-NEXT:  .LBB9_8:
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB9_9:
+; RV32IZFINX-NEXT:    mv a0, a2
+; RV32IZFINX-NEXT:    feq.s a2, s0, s0
+; RV32IZFINX-NEXT:    bnez a2, .LBB9_4
+; RV32IZFINX-NEXT:  .LBB9_10:
+; RV32IZFINX-NEXT:    li a0, 0
+; RV32IZFINX-NEXT:    lui a4, 524288
+; RV32IZFINX-NEXT:    bnez s1, .LBB9_5
+; RV32IZFINX-NEXT:  .LBB9_11:
+; RV32IZFINX-NEXT:    lui a1, 524288
+; RV32IZFINX-NEXT:    beqz a3, .LBB9_6
+; RV32IZFINX-NEXT:  .LBB9_12:
+; RV32IZFINX-NEXT:    addi a1, a4, -1
+; RV32IZFINX-NEXT:    beqz a2, .LBB9_7
+; RV32IZFINX-NEXT:    j .LBB9_8
+;
+; RV64IZFINX-LABEL: test_trunc_si64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    feq.s a1, a0, a0
+; RV64IZFINX-NEXT:    bnez a1, .LBB9_2
+; RV64IZFINX-NEXT:  # %bb.1:
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB9_2:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_ui32(float %x) {
-; RV32IF-LABEL: test_trunc_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB10_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT:  .LBB10_2:
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: test_trunc_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB10_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECK-NEXT:  .LBB10_2:
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: test_trunc_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB10_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT:  .LBB10_2:
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: test_trunc_ui32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a1, a0, a0
+; CHECKZFINX-NEXT:    bnez a1, .LBB10_2
+; CHECKZFINX-NEXT:  # %bb.1:
+; CHECKZFINX-NEXT:    li a0, 0
+; CHECKZFINX-NEXT:    ret
+; CHECKZFINX-NEXT:  .LBB10_2:
+; CHECKZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_trunc_ui64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-LABEL: test_trunc_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB11_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
 ; RV64IF-NEXT:  .LBB11_2:
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_trunc_ui64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call truncf@plt
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    fle.s s1, zero, a0
+; RV32IZFINX-NEXT:    call __fixunssfdi@plt
+; RV32IZFINX-NEXT:    mv a3, a0
+; RV32IZFINX-NEXT:    bnez s1, .LBB11_2
+; RV32IZFINX-NEXT:  # %bb.1:
+; RV32IZFINX-NEXT:    li a3, 0
+; RV32IZFINX-NEXT:  .LBB11_2:
+; RV32IZFINX-NEXT:    lui a0, %hi(.LCPI11_0)
+; RV32IZFINX-NEXT:    lw a0, %lo(.LCPI11_0)(a0)
+; RV32IZFINX-NEXT:    flt.s a4, a0, s0
+; RV32IZFINX-NEXT:    li a2, -1
+; RV32IZFINX-NEXT:    li a0, -1
+; RV32IZFINX-NEXT:    beqz a4, .LBB11_7
+; RV32IZFINX-NEXT:  # %bb.3:
+; RV32IZFINX-NEXT:    beqz s1, .LBB11_8
+; RV32IZFINX-NEXT:  .LBB11_4:
+; RV32IZFINX-NEXT:    bnez a4, .LBB11_6
+; RV32IZFINX-NEXT:  .LBB11_5:
+; RV32IZFINX-NEXT:    mv a2, a1
+; RV32IZFINX-NEXT:  .LBB11_6:
+; RV32IZFINX-NEXT:    mv a1, a2
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB11_7:
+; RV32IZFINX-NEXT:    mv a0, a3
+; RV32IZFINX-NEXT:    bnez s1, .LBB11_4
+; RV32IZFINX-NEXT:  .LBB11_8:
+; RV32IZFINX-NEXT:    li a1, 0
+; RV32IZFINX-NEXT:    beqz a4, .LBB11_5
+; RV32IZFINX-NEXT:    j .LBB11_6
+;
+; RV64IZFINX-LABEL: test_trunc_ui64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    feq.s a1, a0, a0
+; RV64IZFINX-NEXT:    bnez a1, .LBB11_2
+; RV64IZFINX-NEXT:  # %bb.1:
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB11_2:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_si32(float %x) {
-; RV32IF-LABEL: test_round_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB12_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
-; RV32IF-NEXT:  .LBB12_2:
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: test_round_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB12_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rmm
+; CHECK-NEXT:  .LBB12_2:
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: test_round_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB12_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rmm
-; RV64IF-NEXT:  .LBB12_2:
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: test_round_si32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a1, a0, a0
+; CHECKZFINX-NEXT:    bnez a1, .LBB12_2
+; CHECKZFINX-NEXT:  # %bb.1:
+; CHECKZFINX-NEXT:    li a0, 0
+; CHECKZFINX-NEXT:    ret
+; CHECKZFINX-NEXT:  .LBB12_2:
+; CHECKZFINX-NEXT:    fcvt.w.s a0, a0, rmm
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_round_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_round_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-LABEL: test_round_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB13_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
 ; RV64IF-NEXT:  .LBB13_2:
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_round_si64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call roundf@plt
+; RV32IZFINX-NEXT:    lui a1, %hi(.LCPI13_0)
+; RV32IZFINX-NEXT:    lw a1, %lo(.LCPI13_0)(a1)
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    fle.s s1, a1, a0
+; RV32IZFINX-NEXT:    call __fixsfdi@plt
+; RV32IZFINX-NEXT:    mv a2, a0
+; RV32IZFINX-NEXT:    bnez s1, .LBB13_2
+; RV32IZFINX-NEXT:  # %bb.1:
+; RV32IZFINX-NEXT:    li a2, 0
+; RV32IZFINX-NEXT:  .LBB13_2:
+; RV32IZFINX-NEXT:    lui a0, %hi(.LCPI13_1)
+; RV32IZFINX-NEXT:    lw a0, %lo(.LCPI13_1)(a0)
+; RV32IZFINX-NEXT:    flt.s a3, a0, s0
+; RV32IZFINX-NEXT:    li a0, -1
+; RV32IZFINX-NEXT:    beqz a3, .LBB13_9
+; RV32IZFINX-NEXT:  # %bb.3:
+; RV32IZFINX-NEXT:    feq.s a2, s0, s0
+; RV32IZFINX-NEXT:    beqz a2, .LBB13_10
+; RV32IZFINX-NEXT:  .LBB13_4:
+; RV32IZFINX-NEXT:    lui a4, 524288
+; RV32IZFINX-NEXT:    beqz s1, .LBB13_11
+; RV32IZFINX-NEXT:  .LBB13_5:
+; RV32IZFINX-NEXT:    bnez a3, .LBB13_12
+; RV32IZFINX-NEXT:  .LBB13_6:
+; RV32IZFINX-NEXT:    bnez a2, .LBB13_8
+; RV32IZFINX-NEXT:  .LBB13_7:
+; RV32IZFINX-NEXT:    li a1, 0
+; RV32IZFINX-NEXT:  .LBB13_8:
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB13_9:
+; RV32IZFINX-NEXT:    mv a0, a2
+; RV32IZFINX-NEXT:    feq.s a2, s0, s0
+; RV32IZFINX-NEXT:    bnez a2, .LBB13_4
+; RV32IZFINX-NEXT:  .LBB13_10:
+; RV32IZFINX-NEXT:    li a0, 0
+; RV32IZFINX-NEXT:    lui a4, 524288
+; RV32IZFINX-NEXT:    bnez s1, .LBB13_5
+; RV32IZFINX-NEXT:  .LBB13_11:
+; RV32IZFINX-NEXT:    lui a1, 524288
+; RV32IZFINX-NEXT:    beqz a3, .LBB13_6
+; RV32IZFINX-NEXT:  .LBB13_12:
+; RV32IZFINX-NEXT:    addi a1, a4, -1
+; RV32IZFINX-NEXT:    beqz a2, .LBB13_7
+; RV32IZFINX-NEXT:    j .LBB13_8
+;
+; RV64IZFINX-LABEL: test_round_si64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    feq.s a1, a0, a0
+; RV64IZFINX-NEXT:    bnez a1, .LBB13_2
+; RV64IZFINX-NEXT:  # %bb.1:
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB13_2:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_ui32(float %x) {
-; RV32IF-LABEL: test_round_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB14_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rmm
-; RV32IF-NEXT:  .LBB14_2:
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: test_round_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB14_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rmm
+; CHECK-NEXT:  .LBB14_2:
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: test_round_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB14_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rmm
-; RV64IF-NEXT:  .LBB14_2:
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: test_round_ui32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a1, a0, a0
+; CHECKZFINX-NEXT:    bnez a1, .LBB14_2
+; CHECKZFINX-NEXT:  # %bb.1:
+; CHECKZFINX-NEXT:    li a0, 0
+; CHECKZFINX-NEXT:    ret
+; CHECKZFINX-NEXT:  .LBB14_2:
+; CHECKZFINX-NEXT:    fcvt.wu.s a0, a0, rmm
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_round_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_round_ui64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-LABEL: test_round_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB15_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
 ; RV64IF-NEXT:  .LBB15_2:
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_round_ui64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call roundf@plt
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    fle.s s1, zero, a0
+; RV32IZFINX-NEXT:    call __fixunssfdi@plt
+; RV32IZFINX-NEXT:    mv a3, a0
+; RV32IZFINX-NEXT:    bnez s1, .LBB15_2
+; RV32IZFINX-NEXT:  # %bb.1:
+; RV32IZFINX-NEXT:    li a3, 0
+; RV32IZFINX-NEXT:  .LBB15_2:
+; RV32IZFINX-NEXT:    lui a0, %hi(.LCPI15_0)
+; RV32IZFINX-NEXT:    lw a0, %lo(.LCPI15_0)(a0)
+; RV32IZFINX-NEXT:    flt.s a4, a0, s0
+; RV32IZFINX-NEXT:    li a2, -1
+; RV32IZFINX-NEXT:    li a0, -1
+; RV32IZFINX-NEXT:    beqz a4, .LBB15_7
+; RV32IZFINX-NEXT:  # %bb.3:
+; RV32IZFINX-NEXT:    beqz s1, .LBB15_8
+; RV32IZFINX-NEXT:  .LBB15_4:
+; RV32IZFINX-NEXT:    bnez a4, .LBB15_6
+; RV32IZFINX-NEXT:  .LBB15_5:
+; RV32IZFINX-NEXT:    mv a2, a1
+; RV32IZFINX-NEXT:  .LBB15_6:
+; RV32IZFINX-NEXT:    mv a1, a2
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB15_7:
+; RV32IZFINX-NEXT:    mv a0, a3
+; RV32IZFINX-NEXT:    bnez s1, .LBB15_4
+; RV32IZFINX-NEXT:  .LBB15_8:
+; RV32IZFINX-NEXT:    li a1, 0
+; RV32IZFINX-NEXT:    beqz a4, .LBB15_5
+; RV32IZFINX-NEXT:    j .LBB15_6
+;
+; RV64IZFINX-LABEL: test_round_ui64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    feq.s a1, a0, a0
+; RV64IZFINX-NEXT:    bnez a1, .LBB15_2
+; RV64IZFINX-NEXT:  # %bb.1:
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB15_2:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rmm
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_si32(float %x) {
-; RV32IF-LABEL: test_roundeven_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB16_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
-; RV32IF-NEXT:  .LBB16_2:
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: test_roundeven_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB16_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rne
+; CHECK-NEXT:  .LBB16_2:
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: test_roundeven_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB16_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rne
-; RV64IF-NEXT:  .LBB16_2:
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: test_roundeven_si32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a1, a0, a0
+; CHECKZFINX-NEXT:    bnez a1, .LBB16_2
+; CHECKZFINX-NEXT:  # %bb.1:
+; CHECKZFINX-NEXT:    li a0, 0
+; CHECKZFINX-NEXT:    ret
+; CHECKZFINX-NEXT:  .LBB16_2:
+; CHECKZFINX-NEXT:    fcvt.w.s a0, a0, rne
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_roundeven_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-LABEL: test_roundeven_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB17_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rne
 ; RV64IF-NEXT:  .LBB17_2:
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_roundeven_si64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call roundevenf@plt
+; RV32IZFINX-NEXT:    lui a1, %hi(.LCPI17_0)
+; RV32IZFINX-NEXT:    lw a1, %lo(.LCPI17_0)(a1)
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    fle.s s1, a1, a0
+; RV32IZFINX-NEXT:    call __fixsfdi@plt
+; RV32IZFINX-NEXT:    mv a2, a0
+; RV32IZFINX-NEXT:    bnez s1, .LBB17_2
+; RV32IZFINX-NEXT:  # %bb.1:
+; RV32IZFINX-NEXT:    li a2, 0
+; RV32IZFINX-NEXT:  .LBB17_2:
+; RV32IZFINX-NEXT:    lui a0, %hi(.LCPI17_1)
+; RV32IZFINX-NEXT:    lw a0, %lo(.LCPI17_1)(a0)
+; RV32IZFINX-NEXT:    flt.s a3, a0, s0
+; RV32IZFINX-NEXT:    li a0, -1
+; RV32IZFINX-NEXT:    beqz a3, .LBB17_9
+; RV32IZFINX-NEXT:  # %bb.3:
+; RV32IZFINX-NEXT:    feq.s a2, s0, s0
+; RV32IZFINX-NEXT:    beqz a2, .LBB17_10
+; RV32IZFINX-NEXT:  .LBB17_4:
+; RV32IZFINX-NEXT:    lui a4, 524288
+; RV32IZFINX-NEXT:    beqz s1, .LBB17_11
+; RV32IZFINX-NEXT:  .LBB17_5:
+; RV32IZFINX-NEXT:    bnez a3, .LBB17_12
+; RV32IZFINX-NEXT:  .LBB17_6:
+; RV32IZFINX-NEXT:    bnez a2, .LBB17_8
+; RV32IZFINX-NEXT:  .LBB17_7:
+; RV32IZFINX-NEXT:    li a1, 0
+; RV32IZFINX-NEXT:  .LBB17_8:
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB17_9:
+; RV32IZFINX-NEXT:    mv a0, a2
+; RV32IZFINX-NEXT:    feq.s a2, s0, s0
+; RV32IZFINX-NEXT:    bnez a2, .LBB17_4
+; RV32IZFINX-NEXT:  .LBB17_10:
+; RV32IZFINX-NEXT:    li a0, 0
+; RV32IZFINX-NEXT:    lui a4, 524288
+; RV32IZFINX-NEXT:    bnez s1, .LBB17_5
+; RV32IZFINX-NEXT:  .LBB17_11:
+; RV32IZFINX-NEXT:    lui a1, 524288
+; RV32IZFINX-NEXT:    beqz a3, .LBB17_6
+; RV32IZFINX-NEXT:  .LBB17_12:
+; RV32IZFINX-NEXT:    addi a1, a4, -1
+; RV32IZFINX-NEXT:    beqz a2, .LBB17_7
+; RV32IZFINX-NEXT:    j .LBB17_8
+;
+; RV64IZFINX-LABEL: test_roundeven_si64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    feq.s a1, a0, a0
+; RV64IZFINX-NEXT:    bnez a1, .LBB17_2
+; RV64IZFINX-NEXT:  # %bb.1:
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB17_2:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rne
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_ui32(float %x) {
-; RV32IF-LABEL: test_roundeven_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB18_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rne
-; RV32IF-NEXT:  .LBB18_2:
-; RV32IF-NEXT:    ret
+; CHECK-LABEL: test_roundeven_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB18_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rne
+; CHECK-NEXT:  .LBB18_2:
+; CHECK-NEXT:    ret
 ;
-; RV64IF-LABEL: test_roundeven_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB18_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rne
-; RV64IF-NEXT:  .LBB18_2:
-; RV64IF-NEXT:    ret
+; CHECKZFINX-LABEL: test_roundeven_ui32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    feq.s a1, a0, a0
+; CHECKZFINX-NEXT:    bnez a1, .LBB18_2
+; CHECKZFINX-NEXT:  # %bb.1:
+; CHECKZFINX-NEXT:    li a0, 0
+; CHECKZFINX-NEXT:    ret
+; CHECKZFINX-NEXT:  .LBB18_2:
+; CHECKZFINX-NEXT:    fcvt.wu.s a0, a0, rne
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_roundeven_ui64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-LABEL: test_roundeven_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB19_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
 ; RV64IF-NEXT:  .LBB19_2:
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_roundeven_ui64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    call roundevenf@plt
+; RV32IZFINX-NEXT:    mv s0, a0
+; RV32IZFINX-NEXT:    fle.s s1, zero, a0
+; RV32IZFINX-NEXT:    call __fixunssfdi@plt
+; RV32IZFINX-NEXT:    mv a3, a0
+; RV32IZFINX-NEXT:    bnez s1, .LBB19_2
+; RV32IZFINX-NEXT:  # %bb.1:
+; RV32IZFINX-NEXT:    li a3, 0
+; RV32IZFINX-NEXT:  .LBB19_2:
+; RV32IZFINX-NEXT:    lui a0, %hi(.LCPI19_0)
+; RV32IZFINX-NEXT:    lw a0, %lo(.LCPI19_0)(a0)
+; RV32IZFINX-NEXT:    flt.s a4, a0, s0
+; RV32IZFINX-NEXT:    li a2, -1
+; RV32IZFINX-NEXT:    li a0, -1
+; RV32IZFINX-NEXT:    beqz a4, .LBB19_7
+; RV32IZFINX-NEXT:  # %bb.3:
+; RV32IZFINX-NEXT:    beqz s1, .LBB19_8
+; RV32IZFINX-NEXT:  .LBB19_4:
+; RV32IZFINX-NEXT:    bnez a4, .LBB19_6
+; RV32IZFINX-NEXT:  .LBB19_5:
+; RV32IZFINX-NEXT:    mv a2, a1
+; RV32IZFINX-NEXT:  .LBB19_6:
+; RV32IZFINX-NEXT:    mv a1, a2
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+; RV32IZFINX-NEXT:  .LBB19_7:
+; RV32IZFINX-NEXT:    mv a0, a3
+; RV32IZFINX-NEXT:    bnez s1, .LBB19_4
+; RV32IZFINX-NEXT:  .LBB19_8:
+; RV32IZFINX-NEXT:    li a1, 0
+; RV32IZFINX-NEXT:    beqz a4, .LBB19_5
+; RV32IZFINX-NEXT:    j .LBB19_6
+;
+; RV64IZFINX-LABEL: test_roundeven_ui64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    feq.s a1, a0, a0
+; RV64IZFINX-NEXT:    bnez a1, .LBB19_2
+; RV64IZFINX-NEXT:  # %bb.1:
+; RV64IZFINX-NEXT:    li a0, 0
+; RV64IZFINX-NEXT:    ret
+; RV64IZFINX-NEXT:  .LBB19_2:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rne
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 declare float @llvm.floor.f32(float)
 declare float @llvm.ceil.f32(float)
 declare float @llvm.trunc.f32(float)
 declare float @llvm.round.f32(float)
 declare float @llvm.roundeven.f32(float)
 declare i32 @llvm.fptosi.sat.i32.f32(float)
 declare i64 @llvm.fptosi.sat.i64.f32(float)
 declare i32 @llvm.fptoui.sat.i32.f32(float)
 declare i64 @llvm.fptoui.sat.i64.f32(float)

llvm/test/CodeGen/RISCV/float-round-conv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECK,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECK,RV64IF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefixes=CHECKZFINX,RV32IZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefixes=CHECKZFINX,RV64IZFINX %s
 
 define signext i8 @test_floor_si8(float %x) {
 ; RV32IF-LABEL: test_floor_si8:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_floor_si8:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rdn
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_floor_si8:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rdn
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_floor_si8:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rdn
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = fptosi float %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_floor_si16(float %x) {
 ; RV32IF-LABEL: test_floor_si16:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_floor_si16:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rdn
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_floor_si16:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rdn
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_floor_si16:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rdn
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = fptosi float %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_floor_si32(float %x) {
-; RV32IF-LABEL: test_floor_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_floor_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rdn
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_floor_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rdn
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: test_floor_si32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.w.s a0, a0, rdn
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = fptosi float %a to i32
   ret i32 %b
 }
 
 define i64 @test_floor_si64(float %x) {
 ; RV32IF-LABEL: test_floor_si64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call floorf@plt
 ; RV32IF-NEXT:    call __fixsfdi@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_floor_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rdn
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_floor_si64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    .cfi_offset ra, -4
+; RV32IZFINX-NEXT:    call floorf@plt
+; RV32IZFINX-NEXT:    call __fixsfdi@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_floor_si64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rdn
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = fptosi float %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_floor_ui8(float %x) {
 ; RV32IF-LABEL: test_floor_ui8:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rdn
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_floor_ui8:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_floor_ui8:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rdn
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_floor_ui8:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rdn
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = fptoui float %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_floor_ui16(float %x) {
 ; RV32IF-LABEL: test_floor_ui16:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rdn
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_floor_ui16:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_floor_ui16:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rdn
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_floor_ui16:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rdn
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = fptoui float %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_floor_ui32(float %x) {
-; RV32IF-LABEL: test_floor_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rdn
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_floor_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rdn
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_floor_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rdn
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: test_floor_ui32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.wu.s a0, a0, rdn
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = fptoui float %a to i32
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(float %x) {
 ; RV32IF-LABEL: test_floor_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call floorf@plt
 ; RV32IF-NEXT:    call __fixunssfdi@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_floor_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_floor_ui64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    .cfi_offset ra, -4
+; RV32IZFINX-NEXT:    call floorf@plt
+; RV32IZFINX-NEXT:    call __fixunssfdi@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_floor_ui64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rdn
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = fptoui float %a to i64
   ret i64 %b
 }
 
 define signext i8 @test_ceil_si8(float %x) {
 ; RV32IF-LABEL: test_ceil_si8:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_ceil_si8:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rup
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_ceil_si8:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rup
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_ceil_si8:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rup
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = fptosi float %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_ceil_si16(float %x) {
 ; RV32IF-LABEL: test_ceil_si16:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_ceil_si16:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rup
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_ceil_si16:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rup
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_ceil_si16:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rup
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = fptosi float %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_ceil_si32(float %x) {
-; RV32IF-LABEL: test_ceil_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_ceil_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rup
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_ceil_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rup
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: test_ceil_si32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.w.s a0, a0, rup
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = fptosi float %a to i32
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(float %x) {
 ; RV32IF-LABEL: test_ceil_si64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call ceilf@plt
 ; RV32IF-NEXT:    call __fixsfdi@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_ceil_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rup
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_ceil_si64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    .cfi_offset ra, -4
+; RV32IZFINX-NEXT:    call ceilf@plt
+; RV32IZFINX-NEXT:    call __fixsfdi@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_ceil_si64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rup
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = fptosi float %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_ceil_ui8(float %x) {
 ; RV32IF-LABEL: test_ceil_ui8:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rup
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_ceil_ui8:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_ceil_ui8:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rup
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_ceil_ui8:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rup
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = fptoui float %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_ceil_ui16(float %x) {
 ; RV32IF-LABEL: test_ceil_ui16:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rup
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_ceil_ui16:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_ceil_ui16:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rup
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_ceil_ui16:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rup
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = fptoui float %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_ceil_ui32(float %x) {
-; RV32IF-LABEL: test_ceil_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rup
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_ceil_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rup
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_ceil_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rup
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: test_ceil_ui32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.wu.s a0, a0, rup
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = fptoui float %a to i32
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(float %x) {
 ; RV32IF-LABEL: test_ceil_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call ceilf@plt
 ; RV32IF-NEXT:    call __fixunssfdi@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_ceil_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_ceil_ui64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    .cfi_offset ra, -4
+; RV32IZFINX-NEXT:    call ceilf@plt
+; RV32IZFINX-NEXT:    call __fixunssfdi@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_ceil_ui64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rup
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = fptoui float %a to i64
   ret i64 %b
 }
 
 define signext i8 @test_trunc_si8(float %x) {
 ; RV32IF-LABEL: test_trunc_si8:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_trunc_si8:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_trunc_si8:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_trunc_si8:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = fptosi float %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_trunc_si16(float %x) {
 ; RV32IF-LABEL: test_trunc_si16:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_trunc_si16:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_trunc_si16:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_trunc_si16:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = fptosi float %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_trunc_si32(float %x) {
-; RV32IF-LABEL: test_trunc_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_trunc_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_trunc_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rtz
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: test_trunc_si32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = fptosi float %a to i32
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(float %x) {
 ; RV32IF-LABEL: test_trunc_si64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call truncf@plt
 ; RV32IF-NEXT:    call __fixsfdi@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_trunc_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_trunc_si64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    .cfi_offset ra, -4
+; RV32IZFINX-NEXT:    call truncf@plt
+; RV32IZFINX-NEXT:    call __fixsfdi@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_trunc_si64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = fptosi float %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_trunc_ui8(float %x) {
 ; RV32IF-LABEL: test_trunc_ui8:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_trunc_ui8:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_trunc_ui8:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_trunc_ui8:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = fptoui float %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_trunc_ui16(float %x) {
 ; RV32IF-LABEL: test_trunc_ui16:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_trunc_ui16:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_trunc_ui16:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_trunc_ui16:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = fptoui float %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_trunc_ui32(float %x) {
-; RV32IF-LABEL: test_trunc_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_trunc_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_trunc_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: test_trunc_ui32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = fptoui float %a to i32
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(float %x) {
 ; RV32IF-LABEL: test_trunc_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call truncf@plt
 ; RV32IF-NEXT:    call __fixunssfdi@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_trunc_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_trunc_ui64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    .cfi_offset ra, -4
+; RV32IZFINX-NEXT:    call truncf@plt
+; RV32IZFINX-NEXT:    call __fixunssfdi@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_trunc_ui64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = fptoui float %a to i64
   ret i64 %b
 }
 
 define signext i8 @test_round_si8(float %x) {
 ; RV32IF-LABEL: test_round_si8:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_round_si8:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_round_si8:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rmm
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_round_si8:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = fptosi float %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_round_si16(float %x) {
 ; RV32IF-LABEL: test_round_si16:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_round_si16:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_round_si16:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rmm
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_round_si16:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = fptosi float %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_round_si32(float %x) {
-; RV32IF-LABEL: test_round_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_round_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rmm
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_round_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rmm
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: test_round_si32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.w.s a0, a0, rmm
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = fptosi float %a to i32
   ret i32 %b
 }
 
 define i64 @test_round_si64(float %x) {
 ; RV32IF-LABEL: test_round_si64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call roundf@plt
 ; RV32IF-NEXT:    call __fixsfdi@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_round_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_round_si64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    .cfi_offset ra, -4
+; RV32IZFINX-NEXT:    call roundf@plt
+; RV32IZFINX-NEXT:    call __fixsfdi@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_round_si64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = fptosi float %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_round_ui8(float %x) {
 ; RV32IF-LABEL: test_round_ui8:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rmm
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_round_ui8:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_round_ui8:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rmm
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_round_ui8:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rmm
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = fptoui float %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_round_ui16(float %x) {
 ; RV32IF-LABEL: test_round_ui16:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rmm
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_round_ui16:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_round_ui16:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rmm
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_round_ui16:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rmm
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = fptoui float %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_round_ui32(float %x) {
-; RV32IF-LABEL: test_round_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rmm
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_round_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rmm
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_round_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rmm
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: test_round_ui32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.wu.s a0, a0, rmm
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = fptoui float %a to i32
   ret i32 %b
 }
 
 define i64 @test_round_ui64(float %x) {
 ; RV32IF-LABEL: test_round_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call roundf@plt
 ; RV32IF-NEXT:    call __fixunssfdi@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_round_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_round_ui64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    .cfi_offset ra, -4
+; RV32IZFINX-NEXT:    call roundf@plt
+; RV32IZFINX-NEXT:    call __fixunssfdi@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_round_ui64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rmm
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = fptoui float %a to i64
   ret i64 %b
 }
 
 define signext i8 @test_roundeven_si8(float %x) {
 ; RV32IF-LABEL: test_roundeven_si8:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_roundeven_si8:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rne
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_roundeven_si8:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rne
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_roundeven_si8:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rne
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = fptosi float %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_roundeven_si16(float %x) {
 ; RV32IF-LABEL: test_roundeven_si16:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_roundeven_si16:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rne
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_roundeven_si16:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rne
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_roundeven_si16:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rne
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = fptosi float %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_roundeven_si32(float %x) {
-; RV32IF-LABEL: test_roundeven_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_roundeven_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rne
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_roundeven_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rne
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: test_roundeven_si32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.w.s a0, a0, rne
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = fptosi float %a to i32
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(float %x) {
 ; RV32IF-LABEL: test_roundeven_si64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call roundevenf@plt
 ; RV32IF-NEXT:    call __fixsfdi@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_roundeven_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rne
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_roundeven_si64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    .cfi_offset ra, -4
+; RV32IZFINX-NEXT:    call roundevenf@plt
+; RV32IZFINX-NEXT:    call __fixsfdi@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_roundeven_si64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rne
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = fptosi float %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_roundeven_ui8(float %x) {
 ; RV32IF-LABEL: test_roundeven_ui8:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rne
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_roundeven_ui8:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_roundeven_ui8:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rne
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_roundeven_ui8:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rne
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = fptoui float %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_roundeven_ui16(float %x) {
 ; RV32IF-LABEL: test_roundeven_ui16:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rne
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_roundeven_ui16:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_roundeven_ui16:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rne
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_roundeven_ui16:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rne
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = fptoui float %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_roundeven_ui32(float %x) {
-; RV32IF-LABEL: test_roundeven_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rne
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_roundeven_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rne
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_roundeven_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rne
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: test_roundeven_ui32:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    fcvt.wu.s a0, a0, rne
+; CHECKZFINX-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = fptoui float %a to i32
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(float %x) {
 ; RV32IF-LABEL: test_roundeven_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call roundevenf@plt
 ; RV32IF-NEXT:    call __fixunssfdi@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_roundeven_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
 ; RV64IF-NEXT:    ret
+;
+; RV32IZFINX-LABEL: test_roundeven_ui64:
+; RV32IZFINX:       # %bb.0:
+; RV32IZFINX-NEXT:    addi sp, sp, -16
+; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT:    .cfi_offset ra, -4
+; RV32IZFINX-NEXT:    call roundevenf@plt
+; RV32IZFINX-NEXT:    call __fixunssfdi@plt
+; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT:    addi sp, sp, 16
+; RV32IZFINX-NEXT:    ret
+;
+; RV64IZFINX-LABEL: test_roundeven_ui64:
+; RV64IZFINX:       # %bb.0:
+; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rne
+; RV64IZFINX-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = fptoui float %a to i64
   ret i64 %b
 }
 
 declare float @llvm.floor.f32(float)
 declare float @llvm.ceil.f32(float)
 declare float @llvm.trunc.f32(float)
 declare float @llvm.round.f32(float)
 declare float @llvm.roundeven.f32(float)

llvm/test/CodeGen/RISCV/float-select-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZFINX %s
 
 define float @select_fcmp_false(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_false:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_false:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_false:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_false:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp false float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_oeq(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_oeq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    bnez a0, .LBB1_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB1_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_oeq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    bnez a0, .LBB1_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB1_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_oeq:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa1
+; CHECKIF-NEXT:    bnez a0, .LBB1_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB1_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_oeq:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    feq.s a2, a0, a1
+; CHECKIZFINX-NEXT:    bnez a2, .LBB1_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:  .LBB1_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp oeq float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ogt(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ogt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    bnez a0, .LBB2_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB2_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_ogt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    bnez a0, .LBB2_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB2_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_ogt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa1, fa0
+; CHECKIF-NEXT:    bnez a0, .LBB2_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB2_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_ogt:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    flt.s a2, a1, a0
+; CHECKIZFINX-NEXT:    bnez a2, .LBB2_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:  .LBB2_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp ogt float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_oge(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_oge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    bnez a0, .LBB3_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB3_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_oge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    bnez a0, .LBB3_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB3_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_oge:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa1, fa0
+; CHECKIF-NEXT:    bnez a0, .LBB3_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB3_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_oge:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    fle.s a2, a1, a0
+; CHECKIZFINX-NEXT:    bnez a2, .LBB3_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:  .LBB3_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp oge float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_olt(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_olt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    bnez a0, .LBB4_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB4_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_olt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    bnez a0, .LBB4_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB4_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_olt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    bnez a0, .LBB4_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB4_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_olt:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    flt.s a2, a0, a1
+; CHECKIZFINX-NEXT:    bnez a2, .LBB4_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:  .LBB4_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp olt float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ole(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ole:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    bnez a0, .LBB5_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB5_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_ole:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    bnez a0, .LBB5_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB5_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_ole:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa0, fa1
+; CHECKIF-NEXT:    bnez a0, .LBB5_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB5_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_ole:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    fle.s a2, a0, a1
+; CHECKIZFINX-NEXT:    bnez a2, .LBB5_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:  .LBB5_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp ole float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_one(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_one:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    bnez a0, .LBB6_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB6_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_one:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    bnez a0, .LBB6_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB6_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_one:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    flt.s a1, fa1, fa0
+; CHECKIF-NEXT:    or a0, a1, a0
+; CHECKIF-NEXT:    bnez a0, .LBB6_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB6_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_one:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    flt.s a2, a0, a1
+; CHECKIZFINX-NEXT:    flt.s a3, a1, a0
+; CHECKIZFINX-NEXT:    or a2, a3, a2
+; CHECKIZFINX-NEXT:    bnez a2, .LBB6_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:  .LBB6_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp one float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ord(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ord:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    bnez a0, .LBB7_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB7_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_ord:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    bnez a0, .LBB7_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB7_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_ord:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa1, fa1
+; CHECKIF-NEXT:    feq.s a1, fa0, fa0
+; CHECKIF-NEXT:    and a0, a1, a0
+; CHECKIF-NEXT:    bnez a0, .LBB7_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB7_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_ord:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    feq.s a2, a1, a1
+; CHECKIZFINX-NEXT:    feq.s a3, a0, a0
+; CHECKIZFINX-NEXT:    and a2, a3, a2
+; CHECKIZFINX-NEXT:    bnez a2, .LBB7_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:  .LBB7_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp ord float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ueq(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ueq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    beqz a0, .LBB8_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB8_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_ueq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    beqz a0, .LBB8_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB8_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_ueq:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    flt.s a1, fa1, fa0
+; CHECKIF-NEXT:    or a0, a1, a0
+; CHECKIF-NEXT:    beqz a0, .LBB8_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB8_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_ueq:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    flt.s a2, a0, a1
+; CHECKIZFINX-NEXT:    flt.s a3, a1, a0
+; CHECKIZFINX-NEXT:    or a2, a3, a2
+; CHECKIZFINX-NEXT:    beqz a2, .LBB8_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:  .LBB8_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp ueq float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ugt(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ugt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    beqz a0, .LBB9_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB9_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_ugt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    beqz a0, .LBB9_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB9_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_ugt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa0, fa1
+; CHECKIF-NEXT:    beqz a0, .LBB9_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB9_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_ugt:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    fle.s a2, a0, a1
+; CHECKIZFINX-NEXT:    beqz a2, .LBB9_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:  .LBB9_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp ugt float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_uge(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_uge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    beqz a0, .LBB10_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB10_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_uge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    beqz a0, .LBB10_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB10_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_uge:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    beqz a0, .LBB10_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB10_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_uge:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    flt.s a2, a0, a1
+; CHECKIZFINX-NEXT:    beqz a2, .LBB10_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:  .LBB10_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp uge float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ult(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ult:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    beqz a0, .LBB11_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB11_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_ult:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    beqz a0, .LBB11_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB11_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_ult:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa1, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB11_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB11_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_ult:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    fle.s a2, a1, a0
+; CHECKIZFINX-NEXT:    beqz a2, .LBB11_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:  .LBB11_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp ult float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ule(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ule:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    beqz a0, .LBB12_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB12_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_ule:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    beqz a0, .LBB12_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB12_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_ule:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa1, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB12_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB12_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_ule:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    flt.s a2, a1, a0
+; CHECKIZFINX-NEXT:    beqz a2, .LBB12_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:  .LBB12_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp ule float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_une(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_une:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    beqz a0, .LBB13_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB13_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_une:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    beqz a0, .LBB13_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB13_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_une:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa1
+; CHECKIF-NEXT:    beqz a0, .LBB13_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB13_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_une:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    feq.s a2, a0, a1
+; CHECKIZFINX-NEXT:    beqz a2, .LBB13_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:  .LBB13_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp une float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_uno(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_uno:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    beqz a0, .LBB14_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB14_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_uno:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    beqz a0, .LBB14_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB14_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_uno:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa1, fa1
+; CHECKIF-NEXT:    feq.s a1, fa0, fa0
+; CHECKIF-NEXT:    and a0, a1, a0
+; CHECKIF-NEXT:    beqz a0, .LBB14_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB14_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_uno:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    feq.s a2, a1, a1
+; CHECKIZFINX-NEXT:    feq.s a3, a0, a0
+; CHECKIZFINX-NEXT:    and a2, a3, a2
+; CHECKIZFINX-NEXT:    beqz a2, .LBB14_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a1
+; CHECKIZFINX-NEXT:  .LBB14_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp uno float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_true(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_true:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_true:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_true:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: select_fcmp_true:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp true float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 ; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
 define i32 @i32_select_fcmp_oeq(float %a, float %b, i32 %c, i32 %d) nounwind {
-; RV32IF-LABEL: i32_select_fcmp_oeq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a2, fa0, fa1
-; RV32IF-NEXT:    bnez a2, .LBB16_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    mv a0, a1
-; RV32IF-NEXT:  .LBB16_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: i32_select_fcmp_oeq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a2, fa0, fa1
-; RV64IF-NEXT:    bnez a2, .LBB16_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    mv a0, a1
-; RV64IF-NEXT:  .LBB16_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: i32_select_fcmp_oeq:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a2, fa0, fa1
+; CHECKIF-NEXT:    bnez a2, .LBB16_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    mv a0, a1
+; CHECKIF-NEXT:  .LBB16_2:
+; CHECKIF-NEXT:    ret
+;
+; CHECKIZFINX-LABEL: i32_select_fcmp_oeq:
+; CHECKIZFINX:       # %bb.0:
+; CHECKIZFINX-NEXT:    feq.s a1, a0, a1
+; CHECKIZFINX-NEXT:    mv a0, a2
+; CHECKIZFINX-NEXT:    bnez a1, .LBB16_2
+; CHECKIZFINX-NEXT:  # %bb.1:
+; CHECKIZFINX-NEXT:    mv a0, a3
+; CHECKIZFINX-NEXT:  .LBB16_2:
+; CHECKIZFINX-NEXT:    ret
   %1 = fcmp oeq float %a, %b
   %2 = select i1 %1, i32 %c, i32 %d
   ret i32 %2
 }