[mlir][RISCVV][RFC] Initial RISCVV Dialect

[zhanghb97]

Summary

This is the inital patch for RISC-V vector extension (RVV) dialect. This patch include:

• RVV Dialect Definition
  • RVV Scalable Vector Type
  • RVV Operations
  • RVV Intrinsic Operations
• Translation from RVV Dialect to LLVM Dialect

[zhanghb97]

FYI - I wrote the RFC in the LLVM discourse.

[aartbik]

some initial comments, we are also having a discussion at discourse in the RFC thread

mlir/include/mlir/Dialect/RVV/RVV.td

27–29

This is the part that will show up on the public doc website. Perhaps you can give a bit more background here, and link to the proper places to find out more onthe RISC-V Vector ops you introduce here.

39

this is copy and past from ArmSVE. We should really try to lift this to a shared definition at the proper place

87

empty line after this separator for consistency

mlir/lib/Dialect/RVV/Transforms/LegalizeForLLVMExport.cpp

150

period at tend

mlir/test/Dialect/RVV/roundtrip.mlir

3

here and below, use

CHECK-LABEL:

[rriddle]

nit on the naming, rvv feels a bit too general. I'd rather go with a longer name that spells out riscv: riscvv or something related.

[Joejiong]

mlir/lib/Dialect/RVV/Transforms/LegalizeForLLVMExport.cpp

157

double // added

[zhanghb97]

• Add more background about RVV and introduction to operations in this dialect.
• Add CHECK-LABELs for the round trip test.
• Fix some format issues.

[zhanghb97]

In D108536#2963181, @rriddle wrote:

nit on the naming, rvv feels a bit too general. I'd rather go with a longer name that spells out riscv: riscvv or something related.

Some communities tend to use RVV as the name. For example, the rvv-intrinsic-doc and OpenCV wide universal intrinsic definition: intrin_rvv.hpp. So I also use the RVV on the MLIR side at the very beginning.

If the "rvv/RVV" is too general, and to be consistent with MLIR naming convention (arm_sve/ArmSVE, x86vector/X86Vector, etc.), how about using :

• "riscv_vector" for the namespace
• "RISCVVector" for the file name, folder name, etc.

What do you think about these names?

mlir/include/mlir/Dialect/RVV/RVV.td

39

I think we can make the vector type support both static and scalable versions, for example:

• static version for SIMD architecture vector<4xi64>
• scalable version for vector architecture vector<?x4xi64>

And different ISAs can have different semantics. What do you think about this method?
I will spend some time figuring out how to implement this idea.

mlir/lib/Dialect/RVV/Transforms/LegalizeForLLVMExport.cpp

150

Sorry, I don’t understand what "period at tend" means.

[zhanghb97]

As for the integration test, I currently encounter some problems, and I will continue to find some solutions. At the same time, I will try to move the scalable vector type into the vector dialect in the next step.

And for the names, if the "rvv" is to general, we can use the following names:

• "riscv_vector" for the namespace
• "RISCVVector" for the file name, folder name, etc.

This needs further confirmation.

[Joejiong]

mlir/include/mlir/Dialect/RVV/RVV.td

30

a small typo: pleas -> please

[zhanghb97]

• Fix typo.
• Lift the scalable vector type to vector dialect. The SVE and RVV can share the definition now.

[zhanghb97]

mlir/include/mlir/Dialect/RVV/RVV.td

39

After further thinking, I think it is better for SVE and RVV to share the current scalable vector type definition. The unified scalable vector type (vector<?x4xi64> or something else) needs more exploration in the future. And I have lifted the definition to make the scalable vector type a shared version.

[zhanghb97]

For the next step, I will try to give better semantics to the type of RVV:

• let the vector type directly map LMUL and SEW.
• add a type conversion when lower the RVV operation to RVV intrinsic operation.

[jurahul]

mlir/lib/Dialect/RVV/Transforms/LegalizeForLLVMExport.cpp

150

period at end. https://llvm.org/docs/CodingStandards.html#commenting ("using proper capitalization, punctuation, etc").

[zhanghb97]

• Naming (RVV -> RISCVV)
• Scalable Vector Type (Common Scalable Vector Type + Separate RISC-V Scalable Vector Type)
  • Lift Scalable Vector Type to Vector Dialect
  • Define RVV LMUL Type, RVV Mask Type, and RVV Vector Type
  • Implement Type Mapping Process

[zhanghb97]

mlir/lib/Dialect/RVV/Transforms/LegalizeForLLVMExport.cpp

150

Thanks for informing this!

[aartbik]

In D108536#2970377, @zhanghb97 wrote:

As for the integration test, I currently encounter some problems, and I will continue to find some solutions.

Have you made more progress on this? I realize this is a bit of a hazzle, but leaving it as a TODO has a very high risk of not being done at all... :-(

[zhanghb97]

In D108536#3025499, @aartbik wrote:

Have you made more progress on this? I realize this is a bit of a hazzle, but leaving it as a TODO has a very high risk of not being done at all... :-(

I also realize the risk of not having the integration test. If LLVM IR intrinsics are changed (e.g. add a argument like this patch), the unit tests on MLIR will not be affected, but there will be problems when translating to LLVM IR.

I am trying to figure out why the cross-compiled lli and mlir-cpu-runner fail to identify the target with the QEMU, And I will also use a RISC-V machine to have a try.

[zhanghb97]

• Rebase
• Using OpAdaptor. sync to commit b54c72
• Adding vta argument. sync to commit 7d39a8
• Removing context argument from parse function. sync to commit fb093c

WIP: integration test

[zhanghb97]

• Sync to the vector type with scalable dimensions.
• Set the vta as an attribute.
• Add setvl operation.

[zhanghb97]

• Some RISC-V + JIT progress (needed by integration test)

My teammate has sent some patches hoping to support JIT for the RISC-V side.
Here I quote some sentences of his summary to show the point of the challenge:

In RISCV, temporary symbols will be used to generate dwarf, eh_frame sections..., and will be placed in object code's symbol table. However, LLVM does not use names on these temporary symbols.

For more details, please see his patches:

https://reviews.llvm.org/D116475

https://reviews.llvm.org/D116794

[jsetoain]

mlir/include/mlir/Dialect/RISCVV/RISCVV.td

37–43 ↗

(On Diff #398835)

Since this is not specific to RISC-V Vector, it should go along the other LLVM Dialect constraints (LLVMOpBase.td).

[zhanghb97]

Use the LLVM_AnyPointer constraints in LLVMOpBase.td instead of a local one.

[zhanghb97]

mlir/include/mlir/Dialect/RISCVV/RISCVV.td

37–43 ↗

(On Diff #398835)

Thanks for the suggestion! When I checked the constraints list in LLVMOpBase.td, I found there is already LLVM_AnyPointer constraint. (I didn't notice it before 😅)

[zhanghb97]

• Add integration test (test-riscvv-arithmetic, test-riscvv-memory, test-riscvv-stripmining).
• Add ConvertPolicyOperandOpToLLVMPattern and ConvertPassthruOperandOpToLLVMPattern for mask/tail policy in the RISC-V LLVM IR intrinsics.

[zhanghb97]

I provide an environment setup document to show how to build the toolchain and perform the integration tests.

[zhanghb97]

Rebase.

mlir/include/mlir/Conversion/Passes.td

def ConvertVectorToLLVM : Pass<"convert-vector-to-llvm", "ModuleOp"> {
   let summary = "Lower the operations from the vector dialect into the LLVM "
                 "dialect";
   let description = [{
 
     Convert operations from the vector dialect into the LLVM IR dialect
     operations. The lowering pass provides several options to control
     the kinds of optimizations that are allowed. It also provides options
     that enable the use of one or more architectural-specific dialects
-    (AMX, X86Vector, ArmNeon, ArmSVE, etc.) in combination with the
+    (AMX, X86Vector, ArmNeon, ArmSVE, RVV, etc.) in combination with the
     architectural-neutral vector dialect lowering.
 
   }];
   let constructor = "mlir::createConvertVectorToLLVMPass()";
   // Override explicitly in C++ to allow conditional dialect dependence.
   // let dependentDialects;
   let options = [
     Option<"reassociateFPReductions", "reassociate-fp-reductions",
let options = [
      "dialect.">,
     Option<"enableArmSVE", "enable-arm-sve",
            "bool", /*default=*/"false",
            "Enables the use of ArmSVE dialect while lowering the vector "
        "dialect.">,
     Option<"enableX86Vector", "enable-x86vector",
            "bool", /*default=*/"false",
            "Enables the use of X86Vector dialect while lowering the vector "
-     "dialect.">
+     "dialect.">,
+    Option<"enableRVV", "enable-rvv",
+           "bool", /*default=*/"false",
+           "Enables the use of RVV dialect while lowering the vector dialect.">
   ];
 }
 
 //===----------------------------------------------------------------------===//
 // VectorToROCDL
 //===----------------------------------------------------------------------===//
 
 def ConvertVectorToROCDL : Pass<"convert-vector-to-rocdl", "ModuleOp"> {

mlir/include/mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h

 /// Options to control Vector to LLVM lowering.
 ///
 /// This should kept in sync with VectorToLLVM options defined for the
 /// ConvertVectorToLLVM pass in include/mlir/Conversion/Passes.td
 struct LowerVectorToLLVMOptions {
   LowerVectorToLLVMOptions()
       : reassociateFPReductions(false), enableIndexOptimizations(true),
         enableArmNeon(false), enableArmSVE(false), enableAMX(false),
-        enableX86Vector(false) {}
+        enableX86Vector(false), enableRVV(false) {}
 
   LowerVectorToLLVMOptions &setReassociateFPReductions(bool b) {
     reassociateFPReductions = b;
     return *this;
   }
   LowerVectorToLLVMOptions &setEnableIndexOptimizations(bool b) {
     enableIndexOptimizations = b;
     return *this;
struct LowerVectorToLLVMOptions {
   LowerVectorToLLVMOptions &setEnableAMX(bool b) {
     enableAMX = b;
     return *this;
   }
   LowerVectorToLLVMOptions &setEnableX86Vector(bool b) {
     enableX86Vector = b;
     return *this;
   }
+  LowerVectorToLLVMOptions &setEnableRVV(bool b) {
+    enableRVV = b;
+    return *this;
+  }
 
   bool reassociateFPReductions;
   bool enableIndexOptimizations;
   bool enableArmNeon;
   bool enableArmSVE;
   bool enableAMX;
   bool enableX86Vector;
+  bool enableRVV;
 };
 
 /// Collect a set of patterns to convert from Vector contractions to LLVM Matrix
 /// Intrinsics. To lower to assembly, the LLVM flag -lower-matrix-intrinsics
 /// will be needed when invoking LLVM.
 void populateVectorToLLVMMatrixConversionPatterns(LLVMTypeConverter &converter,
                                                   RewritePatternSet &patterns);
 

mlir/include/mlir/Dialect/CMakeLists.txt

 add_subdirectory(Linalg)
 add_subdirectory(LLVMIR)
 add_subdirectory(MemRef)
 add_subdirectory(OpenACC)
 add_subdirectory(OpenMP)
 add_subdirectory(PDL)
 add_subdirectory(PDLInterp)
 add_subdirectory(Quant)
+add_subdirectory(RVV)
 add_subdirectory(SCF)
 add_subdirectory(Shape)
 add_subdirectory(SparseTensor)
 add_subdirectory(SPIRV)
 add_subdirectory(StandardOps)
 add_subdirectory(Tensor)
 add_subdirectory(Tosa)
 add_subdirectory(Vector)
 add_subdirectory(X86Vector)

mlir/include/mlir/Dialect/RVV/CMakeLists.txt

+add_mlir_dialect(RVV rvv)
+add_mlir_doc(RVV RVV Dialects/ -gen-dialect-doc)
+
+set(LLVM_TARGET_DEFINITIONS RVV.td)
+mlir_tablegen(RVVConversions.inc -gen-llvmir-conversions)
+add_public_tablegen_target(MLIRRVVConversionsIncGen)

mlir/include/mlir/Dialect/RVV/RVV.td

+//===-- RVV.td - RVV dialect operation definitions ---------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the basic operations for the RVV dialect.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef RVV_OPS
+#define RVV_OPS
+
+include "mlir/Dialect/LLVMIR/LLVMOpBase.td"
+
+//===----------------------------------------------------------------------===//
+// RVV dialect definition
+//===----------------------------------------------------------------------===//
+
+def RVV_Dialect : Dialect {
+  let name = "rvv";
+  let cppNamespace = "::mlir::rvv";
+  let summary = "Basic dialect to target RISC-V Vector extension";
+  let description = [{
+    This dialect contains the definitions necessary to target RISC-V Vector
+    extension operations, including the scalable vector type, RVV operations,
+    and RVV intrinsic operations.
+  }];
+}
+
+//===----------------------------------------------------------------------===//
+// RVV type definitions
+//===----------------------------------------------------------------------===//
+
+class RVV_Type<string name> : TypeDef<RVV_Dialect, name> { }
+
+def RVVScalableVectorType : RVV_Type<"RVVScalableVector"> {
+  let mnemonic = "vector";
+
+  let summary = "RVV Scalable vector type";
+
+  let description = [{
+    RVV scalable vector type shares the same syntax with standard vector type
+    but have different semantics. It can reflect LMUL and SEW, which are used
+    to configure scalable vector length at runtime.
+  }];
+
+  let parameters = (ins
+    ArrayRefParameter<"int64_t", "Vector shape">:$shape,
+    "Type":$elementType
+  );
+
+  let printer = [{
+    $_printer << "vector<";
+    for (int64_t dim : getShape())
+      $_printer << dim << 'x';
+    $_printer << getElementType() << '>';
+  }];
+
+  let parser = [{
+    VectorType vector;
+    if ($_parser.parseType(vector))
+      return Type();
+    return get($_ctxt, vector.getShape(), vector.getElementType());
+  }];
+
+  let extraClassDeclaration = [{
+    bool hasStaticShape() const {
+      return llvm::none_of(getShape(), ShapedType::isDynamic);
+    }
+    int64_t getNumElements() const {
+      assert(hasStaticShape() &&
+             "cannot get element count of dynamic shaped type");
+      ArrayRef<int64_t> shape = getShape();
+      int64_t num = 1;
+      for (auto dim : shape)
+        num *= dim;
+      return num;
+    }
+  }];
+}
+
+//===----------------------------------------------------------------------===//
+// Additional LLVM type constraints
+//===----------------------------------------------------------------------===//
+def LLVMScalableVectorType :
+  Type<CPred<"$_self.isa<::mlir::LLVM::LLVMScalableVectorType>()">,
+       "LLVM dialect scalable vector type">;
+
+def LLVMPointerType :
+  Type<CPred<"$_self.isa<::mlir::LLVM::LLVMPointerType>()">,
+       "LLVM pointer type">;
+
+//===----------------------------------------------------------------------===//
+// RVV scalable vector type constraints
+//===----------------------------------------------------------------------===//
+
+def IsRVVScalableVectorTypePred :
+    CPred<"$_self.isa<::mlir::rvv::RVVScalableVectorType>()">;
+
+class RVVScalableVectorOf<list<Type> allowedTypes> :
+    ContainerType<AnyTypeOf<allowedTypes>, IsRVVScalableVectorTypePred,
+          "$_self.cast<::mlir::rvv::RVVScalableVectorType>().getElementType()",
+          "RVV scalable vector">;
+
+//===----------------------------------------------------------------------===//
+// RVV operation definitions
+//===----------------------------------------------------------------------===//
+
+class RVV_Op<string mnemonic, list<OpTrait> traits = []> :
+  Op<RVV_Dialect, mnemonic, traits> {}
+
+def RVVLoadOp : RVV_Op<"load">,
+    Arguments<(ins Arg<AnyMemRef, "", [MemRead]>:$base, Index:$index,
+                       AnyInteger:$length)>,
+    Results<(outs RVVScalableVectorOf<[AnyType]>:$result)> {
+  let summary = "Load scalable vector from memory";
+  let description = [{
+    Load a slice of memory into scalable vector with the given element length.
+  }];
+  let extraClassDeclaration = [{
+    MemRefType getMemRefType() {
+      return base().getType().cast<MemRefType>();
+    }
+  }];
+  let assemblyFormat = "$base `[` $index `]` `,` $length attr-dict `:` "
+    "type($base) `,` type($result) `,`  type($length)";
+}
+
+def RVVStoreOp : RVV_Op<"store">,
+    Arguments<(ins RVVScalableVectorOf<[AnyType]>:$value, Arg<AnyMemRef, "",
+                   [MemWrite]>:$base, Index:$index, AnyInteger:$length)> {
+  let summary = "Store scalable vector into memory";
+  let description = [{
+    Store the given element length of a scalable vector on a slice of memory.
+  }];
+  let extraClassDeclaration = [{
+    MemRefType getMemRefType() {
+      return base().getType().cast<MemRefType>();
+    }
+  }];
+  let assemblyFormat = "$value `,` $base `[` $index `]` `,` $length attr-dict "
+    "`:` type($value) `,` type($base) `,`  type($length)";
+}
+
+class RVV_BinaryAAXNoMask_Op<string mnemonic, string op_description,
+                             list<OpTrait> traits = []> :
+  RVV_Op<mnemonic, !listconcat(traits, [AllTypesMatch<["src1", "dst"]>])> {
+  let summary = op_description # "for RVV scalable vectors";
+  let description = [{ The `rvv.}] # mnemonic # [{` operation can be of 
+    vector-vector form or vector-scalar form. It also takes the vector length 
+    value and returns a scalable vector with the result of the }]
+    # op_description # [{.}];
+  let arguments = (ins 
+          RVVScalableVectorOf<[AnyInteger]>:$src1,
+          AnyType:$src2,
+          AnyInteger:$length
+  );
+  let results = (outs RVVScalableVectorOf<[AnyInteger]>:$dst);
+  let assemblyFormat = "$src1 `,` $src2 `,` $length attr-dict `:` type($src1) "
+    "`,` type($src2) `,` type($length)";
+}
+
+class RVV_BinaryAAXMask_Op<string mnemonic, string op_description,
+                           list<OpTrait> traits = []> :
+  RVV_Op<mnemonic, !listconcat(traits,
+                       [AllTypesMatch<["maskedoff", "src1", "dst"]>])> {
+  let summary = op_description # "for RVV scalable vectors";
+  let description = [{ The `rvv.}] # mnemonic # [{` operation can be of 
+    vector-vector form or vector-scalar form. It also takes the mask vector, 
+    maskedoff vector, vector length value and returns a scalable vector with 
+    the result of the }] # op_description # [{.}];
+  let arguments = (ins 
+          RVVScalableVectorOf<[AnyInteger]>:$maskedoff,
+          RVVScalableVectorOf<[AnyInteger]>:$src1,
+          AnyType:$src2,
+          RVVScalableVectorOf<[I1]>:$mask,
+          AnyInteger:$length
+  );
+  let results = (outs RVVScalableVectorOf<[AnyInteger]>:$dst);
+  let assemblyFormat = 
+    "$maskedoff `,` $src1 `,` $src2 `,` $mask `,` $length attr-dict `:` "
+    "type($maskedoff) `,` type($src2) `,` type($mask) `,` type($length)";
+}
+
+def RVVAddOp : RVV_BinaryAAXNoMask_Op<"add", "addition">;
+def RVVSubOp : RVV_BinaryAAXNoMask_Op<"sub", "subtraction">;
+def RVVMulOp : RVV_BinaryAAXNoMask_Op<"mul", "multiplication">;
+def RVVDivOp : RVV_BinaryAAXNoMask_Op<"div", "division">;
+
+def RVVMaskedAddOp : RVV_BinaryAAXMask_Op<"masked.add", "masked addition">;
+def RVVMaskedSubOp : RVV_BinaryAAXMask_Op<"masked.sub", "masked subtraction">;
+def RVVMaskedMulOp : RVV_BinaryAAXMask_Op<"masked.mul",
+                                          "masked multiplication">;
+def RVVMaskedDivOp : RVV_BinaryAAXMask_Op<"masked.div", "masked division">;
+
+//===----------------------------------------------------------------------===//
+// RVV intrinsic operation definitions
+//===----------------------------------------------------------------------===//
+
+class RVV_USLoad_IntrOp<string mnemonic, list<OpTrait> traits = []> :
+  LLVM_IntrOpBase</*Dialect dialect=*/RVV_Dialect, 
+                  /*string opName=*/"intr." # mnemonic,
+                  /*string enumName=*/"riscv_" # !subst(".", "_", mnemonic),
+                  /*list<int> overloadedResults=*/[0], 
+                  /*list<int> overloadedOperands=*/[1], 
+                  /*list<OpTrait> traits=*/traits, 
+                  /*int numResults=*/1>;
+
+class RVV_USStore_IntrOp<string mnemonic, list<OpTrait> traits = []> :
+  LLVM_IntrOpBase</*Dialect dialect=*/RVV_Dialect, 
+                  /*string opName=*/"intr." # mnemonic,
+                  /*string enumName=*/"riscv_" # !subst(".", "_", mnemonic),
+                  /*list<int> overloadedResults=*/[], 
+                  /*list<int> overloadedOperands=*/[0, 2], 
+                  /*list<OpTrait> traits=*/traits, 
+                  /*int numResults=*/0>;
+
+class RVV_BinaryAAXNoMask_IntrOp<string mnemonic, list<OpTrait> traits = []> :
+  LLVM_IntrOpBase</*Dialect dialect=*/RVV_Dialect, 
+                  /*string opName=*/"intr." # mnemonic,
+                  /*string enumName=*/"riscv_" # !subst(".", "_", mnemonic),
+                  /*list<int> overloadedResults=*/[0], 
+                  /*list<int> overloadedOperands=*/[1, 2], 
+                  /*list<OpTrait> traits=*/traits, 
+                  /*int numResults=*/1>;
+
+class RVV_BinaryAAXMask_IntrOp<string mnemonic, list<OpTrait> traits = []> :
+  LLVM_IntrOpBase</*Dialect dialect=*/RVV_Dialect, 
+                  /*string opName=*/"intr." # mnemonic,
+                  /*string enumName=*/"riscv_" # !subst(".", "_", mnemonic),
+                  /*list<int> overloadedResults=*/[0], 
+                  /*list<int> overloadedOperands=*/[2, 4], 
+                  /*list<OpTrait> traits=*/traits, 
+                  /*int numResults=*/1>;
+
+def RVVIntrLoadEleOp : RVV_USLoad_IntrOp<"vle">,
+  Arguments<(ins LLVMPointerType, AnyInteger)>;
+def RVVIntrStoreEleOp : RVV_USStore_IntrOp<"vse">,
+  Arguments<(ins LLVMScalableVectorType, LLVMPointerType, AnyInteger)>;
+
+def RVVIntrAddOp : RVV_BinaryAAXNoMask_IntrOp<"vadd">, 
+  Arguments<(ins LLVMScalableVectorType, AnyType, AnyInteger)>;
+def RVVIntrSubOp : RVV_BinaryAAXNoMask_IntrOp<"vsub">, 
+  Arguments<(ins LLVMScalableVectorType, AnyType, AnyInteger)>;
+def RVVIntrMulOp : RVV_BinaryAAXNoMask_IntrOp<"vmul">, 
+  Arguments<(ins LLVMScalableVectorType, AnyType, AnyInteger)>;
+def RVVIntrDivOp : RVV_BinaryAAXNoMask_IntrOp<"vdiv">, 
+  Arguments<(ins LLVMScalableVectorType, AnyType, AnyInteger)>;
+
+def RVVMaskedIntrAddOp : RVV_BinaryAAXMask_IntrOp<"vadd_mask">, 
+  Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType, AnyType,
+                 LLVMScalableVectorType, AnyInteger)>;
+def RVVMaskedIntrSubOp : RVV_BinaryAAXMask_IntrOp<"vsub_mask">, 
+  Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType, AnyType, 
+                 LLVMScalableVectorType, AnyInteger)>;
+def RVVMaskedIntrMulOp : RVV_BinaryAAXMask_IntrOp<"vmul_mask">, 
+  Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType, AnyType, 
+                 LLVMScalableVectorType, AnyInteger)>;
+def RVVMaskedIntrDivOp : RVV_BinaryAAXMask_IntrOp<"vdiv_mask">, 
+  Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType, AnyType, 
+                 LLVMScalableVectorType, AnyInteger)>;
+
+#endif // RVV_OPS

mlir/include/mlir/Dialect/RVV/RVVDialect.h

+//===- RVVDialect.h - MLIR Dialect for RISC-V vector extension --*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the Target dialect for RVV in MLIR.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_RVV_RVVDIALECT_H
+#define MLIR_DIALECT_RVV_RVVDIALECT_H
+
+#include "mlir/IR/BuiltinTypes.h"
+#include "mlir/IR/Dialect.h"
+#include "mlir/IR/OpDefinition.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+
+#include "mlir/Dialect/RVV/RVVDialect.h.inc"
+
+#define GET_TYPEDEF_CLASSES
+#include "mlir/Dialect/RVV/RVVTypes.h.inc"
+
+#define GET_OP_CLASSES
+#include "mlir/Dialect/RVV/RVV.h.inc"
+
+#endif // MLIR_DIALECT_RVV_RVVDIALECT_H

mlir/include/mlir/Dialect/RVV/Transforms.h

+//===- Transforms.h - RVV Dialect Transformation Entrypoints ----*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_RVV_TRANSFORMS_H
+#define MLIR_DIALECT_RVV_TRANSFORMS_H
+
+namespace mlir {
+
+class LLVMConversionTarget;
+class LLVMTypeConverter;
+class RewritePatternSet;
+using OwningRewritePatternList = RewritePatternSet;
+
+/// Collect a set of patterns to lower RVV ops to ops that map to LLVM
+/// intrinsics.
+void populateRVVLegalizeForLLVMExportPatterns(LLVMTypeConverter &converter,
+                                              RewritePatternSet &patterns);
+
+/// Configure the target to support lowering RVV ops to ops that map to LLVM
+/// intrinsics.
+void configureRVVLegalizeForExportTarget(LLVMConversionTarget &target);
+
+} // namespace mlir
+
+#endif // MLIR_DIALECT_RVV_TRANSFORMS_H

mlir/include/mlir/InitAllDialects.h

 #include "mlir/Dialect/Linalg/IR/LinalgOps.h"
 #include "mlir/Dialect/Math/IR/Math.h"
 #include "mlir/Dialect/MemRef/IR/MemRef.h"
 #include "mlir/Dialect/OpenACC/OpenACC.h"
 #include "mlir/Dialect/OpenMP/OpenMPDialect.h"
 #include "mlir/Dialect/PDL/IR/PDL.h"
 #include "mlir/Dialect/PDLInterp/IR/PDLInterp.h"
 #include "mlir/Dialect/Quant/QuantOps.h"
+#include "mlir/Dialect/RVV/RVVDialect.h"
 #include "mlir/Dialect/SCF/SCF.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
 #include "mlir/Dialect/Shape/IR/Shape.h"
 #include "mlir/Dialect/SparseTensor/IR/SparseTensor.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
 #include "mlir/Dialect/Tensor/IR/Tensor.h"
 #include "mlir/Dialect/Tosa/IR/TosaOps.h"
 #include "mlir/Dialect/Vector/VectorOps.h"
registry.insert<acc::OpenACCDialect,
                   linalg::LinalgDialect,
                   math::MathDialect,
                   memref::MemRefDialect,
                   scf::SCFDialect,
                   omp::OpenMPDialect,
                   pdl::PDLDialect,
                   pdl_interp::PDLInterpDialect,
                   quant::QuantizationDialect,
+                  rvv::RVVDialect,
                   spirv::SPIRVDialect,
                   StandardOpsDialect,
                   arm_sve::ArmSVEDialect,
                   vector::VectorDialect,
                   NVVM::NVVMDialect,
                   ROCDL::ROCDLDialect,
                   shape::ShapeDialect,
                   sparse_tensor::SparseTensorDialect,

mlir/include/mlir/Target/LLVMIR/Dialect/All.h

 #include "mlir/Target/LLVMIR/Dialect/AMX/AMXToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/ArmNeon/ArmNeonToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/ArmSVE/ArmSVEToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.h"
+#include "mlir/Target/LLVMIR/Dialect/RVV/RVVToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/X86Vector/X86VectorToLLVMIRTranslation.h"
 
 namespace mlir {
 class DialectRegistry;
 
 /// Registers all dialects that can be translated to LLVM IR and the
 /// corresponding translation interfaces.
 static inline void registerAllToLLVMIRTranslations(DialectRegistry &registry) {
   registerArmNeonDialectTranslation(registry);
   registerAMXDialectTranslation(registry);
   registerArmSVEDialectTranslation(registry);
   registerLLVMDialectTranslation(registry);
   registerNVVMDialectTranslation(registry);
   registerOpenACCDialectTranslation(registry);
   registerOpenMPDialectTranslation(registry);
   registerROCDLDialectTranslation(registry);
+  registerRVVDialectTranslation(registry);
   registerX86VectorDialectTranslation(registry);
 }
 } // namespace mlir
 
 #endif // MLIR_TARGET_LLVMIR_DIALECT_ALL_H

mlir/include/mlir/Target/LLVMIR/Dialect/RVV/RVVToLLVMIRTranslation.h

+//=======- RVVToLLVMIRTranslation.h - RVV to LLVM IR --------*- C++ -*-=======//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This provides registration calls for RVV dialect to LLVM IR translation.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_TARGET_LLVMIR_DIALECT_RVV_RVVTOLLVMIRTRANSLATION_H
+#define MLIR_TARGET_LLVMIR_DIALECT_RVV_RVVTOLLVMIRTRANSLATION_H
+
+namespace mlir {
+
+class DialectRegistry;
+class MLIRContext;
+
+/// Register the RVV dialect and the translation from it to the LLVM IR in
+/// the given registry;
+void registerRVVDialectTranslation(DialectRegistry &registry);
+
+/// Register the RVV dialect and the translation from it in the registry
+/// associated with the given context.
+void registerRVVDialectTranslation(MLIRContext &context);
+
+} // namespace mlir
+
+#endif // MLIR_TARGET_LLVMIR_DIALECT_RVV_RVVTOLLVMIRTRANSLATION_H

mlir/lib/Conversion/VectorToLLVM/CMakeLists.txt

add_mlir_conversion_library(MLIRVectorToLLVM
   MLIRArmNeon
   MLIRArmSVE
   MLIRArmSVETransforms
   MLIRAMX
   MLIRAMXTransforms
   MLIRLLVMCommonConversion
   MLIRLLVMIR
   MLIRMemRef
+  MLIRRVV
+  MLIRRVVTransforms
   MLIRTargetLLVMIRExport
   MLIRTransforms
   MLIRVector
   MLIRX86Vector
   MLIRX86VectorTransforms
   )

mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp

 #include "mlir/Conversion/LLVMCommon/TypeConverter.h"
 #include "mlir/Dialect/AMX/AMXDialect.h"
 #include "mlir/Dialect/AMX/Transforms.h"
 #include "mlir/Dialect/ArmNeon/ArmNeonDialect.h"
 #include "mlir/Dialect/ArmSVE/ArmSVEDialect.h"
 #include "mlir/Dialect/ArmSVE/Transforms.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
 #include "mlir/Dialect/MemRef/IR/MemRef.h"
+#include "mlir/Dialect/RVV/RVVDialect.h"
+#include "mlir/Dialect/RVV/Transforms.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
 #include "mlir/Dialect/Vector/VectorOps.h"
 #include "mlir/Dialect/X86Vector/Transforms.h"
 #include "mlir/Dialect/X86Vector/X86VectorDialect.h"
 #include "mlir/Transforms/GreedyPatternRewriteDriver.h"
 
 using namespace mlir;
 using namespace mlir::vector;
 
 namespace {
 struct LowerVectorToLLVMPass
     : public ConvertVectorToLLVMBase<LowerVectorToLLVMPass> {
   LowerVectorToLLVMPass(const LowerVectorToLLVMOptions &options) {
     this->reassociateFPReductions = options.reassociateFPReductions;
     this->enableIndexOptimizations = options.enableIndexOptimizations;
     this->enableArmNeon = options.enableArmNeon;
     this->enableArmSVE = options.enableArmSVE;
     this->enableAMX = options.enableAMX;
+    this->enableRVV = options.enableRVV;
     this->enableX86Vector = options.enableX86Vector;
   }
   // Override explicitly to allow conditional dialect dependence.
   void getDependentDialects(DialectRegistry &registry) const override {
     registry.insert<LLVM::LLVMDialect>();
     registry.insert<memref::MemRefDialect>();
     if (enableArmNeon)
       registry.insert<arm_neon::ArmNeonDialect>();
     if (enableArmSVE)
       registry.insert<arm_sve::ArmSVEDialect>();
     if (enableAMX)
       registry.insert<amx::AMXDialect>();
+    if (enableRVV)
+      registry.insert<rvv::RVVDialect>();
     if (enableX86Vector)
       registry.insert<x86vector::X86VectorDialect>();
   }
   void runOnOperation() override;
 };
 } // namespace
 
 void LowerVectorToLLVMPass::runOnOperation() {
void LowerVectorToLLVMPass::runOnOperation() {
   if (enableAMX) {
     configureAMXLegalizeForExportTarget(target);
     populateAMXLegalizeForLLVMExportPatterns(converter, patterns);
   }
   if (enableX86Vector) {
     configureX86VectorLegalizeForExportTarget(target);
     populateX86VectorLegalizeForLLVMExportPatterns(converter, patterns);
   }
+  if (enableRVV) {
+    configureRVVLegalizeForExportTarget(target);
+    populateRVVLegalizeForLLVMExportPatterns(converter, patterns);
+  }
 
   if (failed(
           applyPartialConversion(getOperation(), target, std::move(patterns))))
     signalPassFailure();
 }
 
 std::unique_ptr<OperationPass<ModuleOp>>
 mlir::createConvertVectorToLLVMPass(const LowerVectorToLLVMOptions &options) {
   return std::make_unique<LowerVectorToLLVMPass>(options);
 }

mlir/lib/Dialect/CMakeLists.txt

 add_subdirectory(LLVMIR)
 add_subdirectory(Math)
 add_subdirectory(MemRef)
 add_subdirectory(OpenACC)
 add_subdirectory(OpenMP)
 add_subdirectory(PDL)
 add_subdirectory(PDLInterp)
 add_subdirectory(Quant)
+add_subdirectory(RVV)
 add_subdirectory(SCF)
 add_subdirectory(Shape)
 add_subdirectory(SparseTensor)
 add_subdirectory(SPIRV)
 add_subdirectory(StandardOps)
 add_subdirectory(Tensor)
 add_subdirectory(Tosa)
 add_subdirectory(Utils)

mlir/lib/Dialect/RVV/CMakeLists.txt

+add_subdirectory(IR)
+add_subdirectory(Transforms)

mlir/lib/Dialect/RVV/IR/CMakeLists.txt

+add_mlir_dialect_library(MLIRRVV
+  RVVDialect.cpp
+
+  ADDITIONAL_HEADER_DIRS
+  ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/RVV
+
+  LINK_LIBS PUBLIC
+  MLIRIR
+  MLIRLLVMIR
+  )

mlir/lib/Dialect/RVV/IR/RVVDialect.cpp

+//===- RVVDialect.cpp - MLIR RVV dialect implementation -------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the RVV dialect and its operations.
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Dialect/RVV/RVVDialect.h"
+#include "mlir/Dialect/LLVMIR/LLVMTypes.h"
+#include "mlir/Dialect/Vector/VectorOps.h"
+#include "mlir/IR/Builders.h"
+#include "mlir/IR/DialectImplementation.h"
+#include "mlir/IR/OpImplementation.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "llvm/ADT/TypeSwitch.h"
+
+using namespace mlir;
+
+#include "mlir/Dialect/RVV/RVVDialect.cpp.inc"
+
+#define GET_OP_CLASSES
+#include "mlir/Dialect/RVV/RVV.cpp.inc"
+
+#define GET_TYPEDEF_CLASSES
+#include "mlir/Dialect/RVV/RVVTypes.cpp.inc"
+
+void rvv::RVVDialect::initialize() {
+  addOperations<
+#define GET_OP_LIST
+#include "mlir/Dialect/RVV/RVV.cpp.inc"
+      >();
+  addTypes<
+#define GET_TYPEDEF_LIST
+#include "mlir/Dialect/RVV/RVVTypes.cpp.inc"
+      >();
+}
+
+//===----------------------------------------------------------------------===//
+// ScalableVectorType
+//===----------------------------------------------------------------------===//
+
+Type rvv::RVVDialect::parseType(DialectAsmParser &parser) const {
+  llvm::SMLoc typeLoc = parser.getCurrentLocation();
+  {
+    Type genType;
+    auto parseResult = generatedTypeParser(parser.getBuilder().getContext(),
+                                           parser, "vector", genType);
+    if (parseResult.hasValue())
+      return genType;
+  }
+  parser.emitError(typeLoc, "unknown type in RVV dialect");
+  return Type();
+}
+
+void rvv::RVVDialect::printType(Type type, DialectAsmPrinter &os) const {
+  if (failed(generatedTypePrinter(type, os)))
+    llvm_unreachable("unexpected 'rvv' type kind");
+}

mlir/lib/Dialect/RVV/Transforms/CMakeLists.txt

+add_mlir_dialect_library(MLIRRVVTransforms
+  LegalizeForLLVMExport.cpp
+
+  DEPENDS
+  MLIRRVVConversionsIncGen
+
+  LINK_LIBS PUBLIC
+  MLIRRVV
+  MLIRIR
+  MLIRLLVMCommonConversion
+  MLIRLLVMIR
+  )

mlir/lib/Dialect/RVV/Transforms/LegalizeForLLVMExport.cpp

+//===- LegalizeForLLVMExport.cpp - Prepare RVV for LLVM translation -------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Conversion/LLVMCommon/ConversionTarget.h"
+#include "mlir/Conversion/LLVMCommon/Pattern.h"
+#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
+#include "mlir/Dialect/RVV/RVVDialect.h"
+#include "mlir/Dialect/RVV/Transforms.h"
+#include "mlir/Dialect/StandardOps/IR/Ops.h"
+#include "mlir/IR/BuiltinOps.h"
+#include "mlir/IR/PatternMatch.h"
+
+using namespace mlir;
+using namespace mlir::rvv;
+
+// Extract an LLVM IR type from the LLVM IR dialect type.
+static Type unwrap(Type type) {
+  if (!type)
+    return nullptr;
+  auto *mlirContext = type.getContext();
+  if (!LLVM::isCompatibleType(type))
+    emitError(UnknownLoc::get(mlirContext),
+              "conversion resulted in a non-LLVM type");
+  return type;
+}
+
+static Optional<Type>
+convertScalableVectorTypeToLLVM(RVVScalableVectorType rvvSVType,
+                                LLVMTypeConverter &converter) {
+  auto elementType = unwrap(converter.convertType(rvvSVType.getElementType()));
+  if (!elementType)
+    return {};
+  auto sVectorType = LLVM::LLVMScalableVectorType::get(
+      elementType, rvvSVType.getShape().back());
+  return sVectorType;
+}
+
+template <typename OpTy>
+class ForwardOperands : public OpConversionPattern<OpTy> {
+  using OpConversionPattern<OpTy>::OpConversionPattern;
+
+  LogicalResult
+  matchAndRewrite(OpTy op, ArrayRef<Value> operands,
+                  ConversionPatternRewriter &rewriter) const final {
+    if (ValueRange(operands).getTypes() == op->getOperands().getTypes())
+      return rewriter.notifyMatchFailure(op, "operand types already match");
+
+    rewriter.updateRootInPlace(op, [&]() { op->setOperands(operands); });
+    return success();
+  }
+};
+
+struct RVVLoadOpLowering : public ConvertOpToLLVMPattern<RVVLoadOp> {
+  using ConvertOpToLLVMPattern<RVVLoadOp>::ConvertOpToLLVMPattern;
+
+  LogicalResult
+  matchAndRewrite(RVVLoadOp loadOp, ArrayRef<Value> operands,
+                  ConversionPatternRewriter &rewriter) const override {
+    auto type = loadOp.getMemRefType();
+    if (!isConvertibleAndHasIdentityMaps(type))
+      return failure();
+
+    RVVLoadOp::Adaptor transformed(operands);
+    LLVMTypeConverter converter(loadOp.getContext());
+
+    auto resultType = loadOp.result().getType();
+    LLVM::LLVMPointerType llvmDataTypePtr;
+    if (resultType.isa<VectorType>()) {
+      llvmDataTypePtr =
+          LLVM::LLVMPointerType::get(resultType.cast<VectorType>());
+    } else if (resultType.isa<RVVScalableVectorType>()) {
+      llvmDataTypePtr = LLVM::LLVMPointerType::get(
+          convertScalableVectorTypeToLLVM(
+              resultType.cast<RVVScalableVectorType>(), converter)
+              .getValue());
+    }
+    Value dataPtr =
+        getStridedElementPtr(loadOp.getLoc(), type, transformed.base(),
+                             transformed.index(), rewriter);
+    Value bitCastedPtr = rewriter.create<LLVM::BitcastOp>(
+        loadOp.getLoc(), llvmDataTypePtr, dataPtr);
+    Value vl = loadOp.getOperand(2);
+    rewriter.replaceOpWithNewOp<RVVIntrLoadEleOp>(
+        loadOp,
+        convertScalableVectorTypeToLLVM(
+            resultType.cast<RVVScalableVectorType>(), converter)
+            .getValue(),
+        bitCastedPtr, vl);
+    return success();
+  }
+};
+
+struct RVVStoreOpLowering : public ConvertOpToLLVMPattern<RVVStoreOp> {
+  using ConvertOpToLLVMPattern<RVVStoreOp>::ConvertOpToLLVMPattern;
+
+  LogicalResult
+  matchAndRewrite(RVVStoreOp storeOp, ArrayRef<Value> operands,
+                  ConversionPatternRewriter &rewriter) const override {
+    auto type = storeOp.getMemRefType();
+    if (!isConvertibleAndHasIdentityMaps(type))
+      return failure();
+
+    RVVStoreOp::Adaptor transformed(operands);
+    LLVMTypeConverter converter(storeOp.getContext());
+
+    auto resultType = storeOp.value().getType();
+    LLVM::LLVMPointerType llvmDataTypePtr;
+    if (resultType.isa<VectorType>()) {
+      llvmDataTypePtr =
+          LLVM::LLVMPointerType::get(resultType.cast<VectorType>());
+    } else if (resultType.isa<RVVScalableVectorType>()) {
+      llvmDataTypePtr = LLVM::LLVMPointerType::get(
+          convertScalableVectorTypeToLLVM(
+              resultType.cast<RVVScalableVectorType>(), converter)
+              .getValue());
+    }
+    Value dataPtr =
+        getStridedElementPtr(storeOp.getLoc(), type, transformed.base(),
+                             transformed.index(), rewriter);
+    Value bitCastedPtr = rewriter.create<LLVM::BitcastOp>(
+        storeOp.getLoc(), llvmDataTypePtr, dataPtr);
+    Value vl = storeOp.getOperand(3);
+    rewriter.replaceOpWithNewOp<RVVIntrStoreEleOp>(storeOp, transformed.value(),
+                                                   bitCastedPtr, vl);
+    return success();
+  }
+};
+
+using RVVAddOpLowering = OneToOneConvertToLLVMPattern<RVVAddOp, RVVIntrAddOp>;
+using RVVSubOpLowering = OneToOneConvertToLLVMPattern<RVVSubOp, RVVIntrSubOp>;
+using RVVMulOpLowering = OneToOneConvertToLLVMPattern<RVVMulOp, RVVIntrMulOp>;
+using RVVDivOpLowering = OneToOneConvertToLLVMPattern<RVVDivOp, RVVIntrDivOp>;
+using RVVMaskedAddOpLowering =
+    OneToOneConvertToLLVMPattern<RVVMaskedAddOp, RVVMaskedIntrAddOp>;
+using RVVMaskedSubOpLowering =
+    OneToOneConvertToLLVMPattern<RVVMaskedSubOp, RVVMaskedIntrSubOp>;
+using RVVMaskedMulOpLowering =
+    OneToOneConvertToLLVMPattern<RVVMaskedMulOp, RVVMaskedIntrMulOp>;
+using RVVMaskedDivOpLowering =
+    OneToOneConvertToLLVMPattern<RVVMaskedDivOp, RVVMaskedIntrDivOp>;
+
+/// Populate the given list with patterns that convert from RVV to LLVM.
+void mlir::populateRVVLegalizeForLLVMExportPatterns(
+    LLVMTypeConverter &converter, OwningRewritePatternList &patterns) {
+  // Populate conversion patterns
+  // Remove any RVV-specific types from function signatures and results.
+  populateFuncOpTypeConversionPattern(patterns, converter);
+  converter.addConversion([&converter](RVVScalableVectorType rvvSVType) {
+    return convertScalableVectorTypeToLLVM(rvvSVType, converter);
+  });
+
+  // // clang-format off
+  patterns.add<ForwardOperands<CallOp>, ForwardOperands<CallIndirectOp>,
+               ForwardOperands<ReturnOp>>(converter, &converter.getContext());
+  patterns.add<RVVLoadOpLowering, RVVStoreOpLowering>(converter);
+  patterns.add<RVVAddOpLowering, RVVSubOpLowering, RVVMulOpLowering,
+               RVVDivOpLowering, RVVSubOpLowering, RVVMaskedAddOpLowering,
+               RVVMaskedSubOpLowering, RVVMaskedMulOpLowering,
+               RVVMaskedDivOpLowering>(converter);
+}
+
+void mlir::configureRVVLegalizeForExportTarget(LLVMConversionTarget &target) {
+  // clang-format off
+  target.addLegalOp<RVVIntrLoadEleOp,
+                    RVVIntrStoreEleOp,
+                    RVVIntrAddOp,
+                    RVVIntrSubOp,
+                    RVVIntrMulOp,
+                    RVVIntrDivOp,
+                    RVVMaskedIntrAddOp,
+                    RVVMaskedIntrSubOp,
+                    RVVMaskedIntrMulOp,
+                    RVVMaskedIntrDivOp>();
+  target.addIllegalOp<RVVLoadOp,
+                      RVVStoreOp,
+                      RVVAddOp,
+                      RVVSubOp,
+                      RVVMulOp,
+                      RVVDivOp,
+                      RVVMaskedAddOp,
+                      RVVMaskedSubOp,
+                      RVVMaskedMulOp,
+                      RVVMaskedDivOp>();
+  // clang-format on
+
+  auto hasScalableVectorType = [](TypeRange types) {
+    for (Type type : types)
+      if (type.isa<rvv::RVVScalableVectorType>())
+        return true;
+    return false;
+  };
+  target.addDynamicallyLegalOp<FuncOp>([hasScalableVectorType](FuncOp op) {
+    return !hasScalableVectorType(op.getType().getInputs()) &&
+           !hasScalableVectorType(op.getType().getResults());
+  });
+  target.addDynamicallyLegalOp<CallOp, CallIndirectOp, ReturnOp>(
+      [hasScalableVectorType](Operation *op) {
+        return !hasScalableVectorType(op->getOperandTypes()) &&
+               !hasScalableVectorType(op->getResultTypes());
+      });
+}

mlir/lib/Target/LLVMIR/CMakeLists.txt

 
 add_mlir_translation_library(MLIRToLLVMIRTranslationRegistration
   ConvertToLLVMIR.cpp
 
   LINK_LIBS PUBLIC
   MLIRArmNeonToLLVMIRTranslation
   MLIRArmSVEToLLVMIRTranslation
   MLIRAMXToLLVMIRTranslation
+  MLIRRVVToLLVMIRTranslation
   MLIRX86VectorToLLVMIRTranslation
   MLIRLLVMToLLVMIRTranslation
   MLIRNVVMToLLVMIRTranslation
   MLIROpenACCToLLVMIRTranslation
   MLIROpenMPToLLVMIRTranslation
   MLIRROCDLToLLVMIRTranslation
   )
 

mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt

 add_subdirectory(ArmNeon)
 add_subdirectory(ArmSVE)
 add_subdirectory(AMX)
 add_subdirectory(LLVMIR)
 add_subdirectory(NVVM)
 add_subdirectory(OpenACC)
 add_subdirectory(OpenMP)
 add_subdirectory(ROCDL)
+add_subdirectory(RVV)
 add_subdirectory(X86Vector)

mlir/lib/Target/LLVMIR/Dialect/RVV/CMakeLists.txt

+add_mlir_translation_library(MLIRRVVToLLVMIRTranslation
+  RVVToLLVMIRTranslation.cpp
+
+  DEPENDS
+  MLIRRVVConversionsIncGen
+
+  LINK_COMPONENTS
+  Core
+
+  LINK_LIBS PUBLIC
+  MLIRIR
+  MLIRRVV
+  MLIRLLVMIR
+  MLIRSupport
+  MLIRTargetLLVMIRExport
+  )

mlir/lib/Target/LLVMIR/Dialect/RVV/RVVToLLVMIRTranslation.cpp

+//======- RVVToLLVMIRTranslation.cpp - Translate RVV to LLVM IR -------=======//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a translation between the RVV dialect and LLVM IR.
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Target/LLVMIR/Dialect/RVV/RVVToLLVMIRTranslation.h"
+#include "mlir/Dialect/RVV/RVVDialect.h"
+#include "mlir/IR/Operation.h"
+#include "mlir/Target/LLVMIR/ModuleTranslation.h"
+
+#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/IntrinsicsRISCV.h"
+
+using namespace mlir;
+using namespace mlir::LLVM;
+
+namespace {
+/// Implementation of the dialect interface that converts operations belonging
+/// to the RVV dialect to LLVM IR.
+class RVVDialectLLVMIRTranslationInterface
+    : public LLVMTranslationDialectInterface {
+public:
+  using LLVMTranslationDialectInterface::LLVMTranslationDialectInterface;
+
+  /// Translates the given operation to LLVM IR using the provided IR builder
+  /// and saving the state in `moduleTranslation`.
+  LogicalResult
+  convertOperation(Operation *op, llvm::IRBuilderBase &builder,
+                   LLVM::ModuleTranslation &moduleTranslation) const final {
+    Operation &opInst = *op;
+#include "mlir/Dialect/RVV/RVVConversions.inc"
+
+    return failure();
+  }
+};
+} // end namespace
+
+void mlir::registerRVVDialectTranslation(DialectRegistry &registry) {
+  registry.insert<rvv::RVVDialect>();
+  registry.addDialectInterface<rvv::RVVDialect,
+                               RVVDialectLLVMIRTranslationInterface>();
+}
+
+void mlir::registerRVVDialectTranslation(MLIRContext &context) {
+  DialectRegistry registry;
+  registerRVVDialectTranslation(registry);
+  context.appendDialectRegistry(registry);
+}

mlir/test/Dialect/RVV/legalize-for-llvm.mlir

+// RUN: mlir-opt %s -convert-vector-to-llvm="enable-rvv" -convert-std-to-llvm | mlir-opt | FileCheck %s
+
+func @rvv_memory(%v: !rvv.vector<4xi64>,
+                 %m: memref<?xi64>,
+                 %vl: i64) -> !rvv.vector<4xi64> {
+  %c0 = constant 0 : index
+  // CHECK: llvm.extractvalue {{.*}} : !llvm.struct<(ptr<i64>, ptr<i64>, i64, array<1 x i64>, array<1 x i64>)>
+  // CHECK-NEXT: llvm.getelementptr {{.*}} : (!llvm.ptr<i64>, i64) -> !llvm.ptr<i64>
+  // CHECK-NEXT: llvm.bitcast {{.*}} : !llvm.ptr<i64> to !llvm.ptr<vec<? x 4 x i64>>
+  // CHECK-NEXT: rvv.intr.vle{{.*}} : (!llvm.ptr<vec<? x 4 x i64>>, i64) -> !llvm.vec<? x 4 x i64>
+  %0 = rvv.load %m[%c0], %vl : memref<?xi64>, !rvv.vector<4xi64>, i64
+  // CHECK: llvm.extractvalue {{.*}} : !llvm.struct<(ptr<i64>, ptr<i64>, i64, array<1 x i64>, array<1 x i64>)>
+  // CHECK-NEXT: llvm.getelementptr {{.*}} : (!llvm.ptr<i64>, i64) -> !llvm.ptr<i64>
+  // CHECK-NEXT: llvm.bitcast {{.*}} : !llvm.ptr<i64> to !llvm.ptr<vec<? x 4 x i64>>
+  // CHECK-NEXT: rvv.intr.vse{{.*}} : (!llvm.vec<? x 4 x i64>, !llvm.ptr<vec<? x 4 x i64>>, i64) -> ()
+  rvv.store %v, %m[%c0], %vl : !rvv.vector<4xi64>, memref<?xi64>, i64
+  return %0 : !rvv.vector<4xi64>
+}
+
+func @rvv_arith(%a: !rvv.vector<4xi64>,
+                %b: !rvv.vector<4xi64>,
+                %c: i64,
+                %vl: i64) -> !rvv.vector<4xi64> {
+  // CHECK: rvv.intr.vadd{{.*}} : (!llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, i64) -> !llvm.vec<? x 4 x i64>
+  %0 = rvv.add %a, %b, %vl : !rvv.vector<4xi64>, !rvv.vector<4xi64>, i64
+  // CHECK: rvv.intr.vadd{{.*}} : (!llvm.vec<? x 4 x i64>, i64, i64) -> !llvm.vec<? x 4 x i64>
+  %1 = rvv.add %a, %c, %vl : !rvv.vector<4xi64>, i64, i64
+  // CHECK: rvv.intr.vsub{{.*}} : (!llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, i64) -> !llvm.vec<? x 4 x i64>
+  %2 = rvv.sub %a, %b, %vl : !rvv.vector<4xi64>, !rvv.vector<4xi64>, i64
+  // CHECK: rvv.intr.vsub{{.*}} : (!llvm.vec<? x 4 x i64>, i64, i64) -> !llvm.vec<? x 4 x i64>
+  %3 = rvv.sub %a, %c, %vl : !rvv.vector<4xi64>, i64, i64
+  // CHECK: rvv.intr.vmul{{.*}} : (!llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, i64) -> !llvm.vec<? x 4 x i64>
+  %4 = rvv.mul %a, %b, %vl : !rvv.vector<4xi64>, !rvv.vector<4xi64>, i64
+  // CHECK: rvv.intr.vmul{{.*}} : (!llvm.vec<? x 4 x i64>, i64, i64) -> !llvm.vec<? x 4 x i64>
+  %5 = rvv.mul %a, %c, %vl : !rvv.vector<4xi64>, i64, i64
+  // CHECK: rvv.intr.vdiv{{.*}} : (!llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, i64) -> !llvm.vec<? x 4 x i64>
+  %6 = rvv.div %a, %b, %vl : !rvv.vector<4xi64>, !rvv.vector<4xi64>, i64
+  // CHECK: rvv.intr.vdiv{{.*}} : (!llvm.vec<? x 4 x i64>, i64, i64) -> !llvm.vec<? x 4 x i64>
+  %7 = rvv.div %a, %c, %vl : !rvv.vector<4xi64>, i64, i64
+  return %7 : !rvv.vector<4xi64>
+}
+
+func @rvv_masked_arith(%maskedoff: !rvv.vector<4xi64>,
+                       %a: !rvv.vector<4xi64>,
+                       %b: !rvv.vector<4xi64>,
+                       %c: i64,
+                       %mask: !rvv.vector<4xi1>,
+                       %vl: i64) -> !rvv.vector<4xi64> {
+  // CHECK: rvv.intr.vadd_mask{{.*}} : (!llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i1>, i64) -> !llvm.vec<? x 4 x i64>
+  %0 = rvv.masked.add %maskedoff, %a, %b, %mask, %vl: !rvv.vector<4xi64>, !rvv.vector<4xi64>, !rvv.vector<4xi1>, i64
+  // CHECK: rvv.intr.vadd_mask{{.*}} : (!llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, i64, !llvm.vec<? x 4 x i1>, i64) -> !llvm.vec<? x 4 x i64>
+  %1 = rvv.masked.add %maskedoff, %a, %c, %mask, %vl: !rvv.vector<4xi64>, i64, !rvv.vector<4xi1>, i64
+  // CHECK: rvv.intr.vsub_mask{{.*}} : (!llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i1>, i64) -> !llvm.vec<? x 4 x i64>
+  %2 = rvv.masked.sub %maskedoff, %a, %b, %mask, %vl: !rvv.vector<4xi64>, !rvv.vector<4xi64>, !rvv.vector<4xi1>, i64
+  // CHECK: rvv.intr.vsub_mask{{.*}} : (!llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, i64, !llvm.vec<? x 4 x i1>, i64) -> !llvm.vec<? x 4 x i64>
+  %3 = rvv.masked.sub %maskedoff, %a, %c, %mask, %vl: !rvv.vector<4xi64>, i64, !rvv.vector<4xi1>, i64
+  // CHECK: rvv.intr.vmul_mask{{.*}} : (!llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i1>, i64) -> !llvm.vec<? x 4 x i64>
+  %4 = rvv.masked.mul %maskedoff, %a, %b, %mask, %vl: !rvv.vector<4xi64>, !rvv.vector<4xi64>, !rvv.vector<4xi1>, i64
+  // CHECK: rvv.intr.vmul_mask{{.*}} : (!llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, i64, !llvm.vec<? x 4 x i1>, i64) -> !llvm.vec<? x 4 x i64>
+  %5 = rvv.masked.mul %maskedoff, %a, %c, %mask, %vl: !rvv.vector<4xi64>, i64, !rvv.vector<4xi1>, i64
+  // CHECK: rvv.intr.vdiv_mask{{.*}} : (!llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i1>, i64) -> !llvm.vec<? x 4 x i64>
+  %6 = rvv.masked.div %maskedoff, %a, %b, %mask, %vl: !rvv.vector<4xi64>, !rvv.vector<4xi64>, !rvv.vector<4xi1>, i64
+  // CHECK: rvv.intr.vdiv_mask{{.*}} : (!llvm.vec<? x 4 x i64>, !llvm.vec<? x 4 x i64>, i64, !llvm.vec<? x 4 x i1>, i64) -> !llvm.vec<? x 4 x i64>
+  %7 = rvv.masked.div %maskedoff, %a, %c, %mask, %vl: !rvv.vector<4xi64>, i64, !rvv.vector<4xi1>, i64
+  return %7 : !rvv.vector<4xi64>
+}

mlir/test/Dialect/RVV/roundtrip.mlir

+// RUN: mlir-opt -verify-diagnostics %s | mlir-opt | FileCheck %s
+
+func @rvv_memory(%v: !rvv.vector<4xi64>,
+                 %m: memref<?xi64>,
+                 %vl: i64) -> !rvv.vector<4xi64> {
+  %c0 = constant 0 : index
+  // CHECK: rvv.load {{.*}}: memref<?xi64>, !rvv.vector<4xi64>, i64
+  %0 = rvv.load %m[%c0], %vl : memref<?xi64>, !rvv.vector<4xi64>, i64
+  // CHECK: rvv.store {{.*}}: !rvv.vector<4xi64>, memref<?xi64>, i64
+  rvv.store %v, %m[%c0], %vl : !rvv.vector<4xi64>, memref<?xi64>, i64
+  return %0 : !rvv.vector<4xi64>
+}
+
+func @rvv_arith(%a: !rvv.vector<4xi64>,
+                %b: !rvv.vector<4xi64>,
+                %c: i64,
+                %vl: i64) -> !rvv.vector<4xi64> {
+  // CHECK: rvv.add {{.*}} : !rvv.vector<4xi64>, !rvv.vector<4xi64>, i64
+  %0 = rvv.add %a, %b, %vl : !rvv.vector<4xi64>, !rvv.vector<4xi64>, i64
+  // CHECK: rvv.add {{.*}} : !rvv.vector<4xi64>, i64, i64
+  %1 = rvv.add %a, %c, %vl : !rvv.vector<4xi64>, i64, i64
+  // CHECK: rvv.sub {{.*}} : !rvv.vector<4xi64>, !rvv.vector<4xi64>, i64
+  %2 = rvv.sub %a, %b, %vl : !rvv.vector<4xi64>, !rvv.vector<4xi64>, i64
+  // CHECK: rvv.sub {{.*}} : !rvv.vector<4xi64>, i64, i64
+  %3 = rvv.sub %a, %c, %vl : !rvv.vector<4xi64>, i64, i64
+  // CHECK: rvv.mul {{.*}} : !rvv.vector<4xi64>, !rvv.vector<4xi64>, i64
+  %4 = rvv.mul %a, %b, %vl : !rvv.vector<4xi64>, !rvv.vector<4xi64>, i64
+  // CHECK: rvv.mul {{.*}} : !rvv.vector<4xi64>, i64, i64
+  %5 = rvv.mul %a, %c, %vl : !rvv.vector<4xi64>, i64, i64
+  // CHECK: rvv.div {{.*}} : !rvv.vector<4xi64>, !rvv.vector<4xi64>, i64
+  %6 = rvv.div %a, %b, %vl : !rvv.vector<4xi64>, !rvv.vector<4xi64>, i64
+  // CHECK: rvv.div {{.*}} : !rvv.vector<4xi64>, i64, i64
+  %7 = rvv.div %a, %c, %vl : !rvv.vector<4xi64>, i64, i64
+  return %7 : !rvv.vector<4xi64>
+}
+
+func @rvv_masked_arith(%maskedoff: !rvv.vector<4xi64>,
+                       %a: !rvv.vector<4xi64>,
+                       %b: !rvv.vector<4xi64>,
+                       %c: i64,
+                       %mask: !rvv.vector<4xi1>,
+                       %vl: i64) -> !rvv.vector<4xi64> {
+  // CHECK: rvv.masked.add {{.*}} : !rvv.vector<4xi64>, !rvv.vector<4xi64>, !rvv.vector<4xi1>, i64
+  %0 = rvv.masked.add %maskedoff, %a, %b, %mask, %vl : !rvv.vector<4xi64>, !rvv.vector<4xi64>, !rvv.vector<4xi1>, i64
+  // CHECK: rvv.masked.add {{.*}} : !rvv.vector<4xi64>, i64, !rvv.vector<4xi1>, i64
+  %1 = rvv.masked.add %maskedoff, %a, %c, %mask, %vl : !rvv.vector<4xi64>, i64, !rvv.vector<4xi1>, i64
+  // CHECK: rvv.masked.sub {{.*}} : !rvv.vector<4xi64>, !rvv.vector<4xi64>, !rvv.vector<4xi1>, i64
+  %2 = rvv.masked.sub %maskedoff, %a, %b, %mask, %vl : !rvv.vector<4xi64>, !rvv.vector<4xi64>, !rvv.vector<4xi1>, i64
+  // CHECK: rvv.masked.sub {{.*}} : !rvv.vector<4xi64>, i64, !rvv.vector<4xi1>, i64
+  %3 = rvv.masked.sub %maskedoff, %a, %c, %mask, %vl : !rvv.vector<4xi64>, i64, !rvv.vector<4xi1>, i64
+  // CHECK: rvv.masked.mul {{.*}} : !rvv.vector<4xi64>, !rvv.vector<4xi64>, !rvv.vector<4xi1>, i64
+  %4 = rvv.masked.mul %maskedoff, %a, %b, %mask, %vl : !rvv.vector<4xi64>, !rvv.vector<4xi64>, !rvv.vector<4xi1>, i64
+  // CHECK: rvv.masked.mul {{.*}} : !rvv.vector<4xi64>, i64, !rvv.vector<4xi1>, i64
+  %5 = rvv.masked.mul %maskedoff, %a, %c, %mask, %vl : !rvv.vector<4xi64>, i64, !rvv.vector<4xi1>, i64
+  // CHECK: rvv.masked.div {{.*}} : !rvv.vector<4xi64>, !rvv.vector<4xi64>, !rvv.vector<4xi1>, i64
+  %6 = rvv.masked.div %maskedoff, %a, %b, %mask, %vl : !rvv.vector<4xi64>, !rvv.vector<4xi64>, !rvv.vector<4xi1>, i64
+  // CHECK: rvv.masked.div {{.*}} : !rvv.vector<4xi64>, i64, !rvv.vector<4xi1>, i64
+  %7 = rvv.masked.div %maskedoff, %a, %c, %mask, %vl : !rvv.vector<4xi64>, i64, !rvv.vector<4xi1>, i64
+  return %7 : !rvv.vector<4xi64>
+}

mlir/test/mlir-opt/commandline.mlir

 // CHECK-NEXT: math
 // CHECK-NEXT: memref
 // CHECK-NEXT: nvvm
 // CHECK-NEXT: omp
 // CHECK-NEXT: pdl
 // CHECK-NEXT: pdl_interp
 // CHECK-NEXT: quant
 // CHECK-NEXT: rocdl
+// CHECK-NEXT: rvv
 // CHECK-NEXT: scf
 // CHECK-NEXT: shape
 // CHECK-NEXT: sparse_tensor
 // CHECK-NEXT: spv
 // CHECK-NEXT: std
 // CHECK-NEXT: tensor
 // CHECK-NEXT: test
 // CHECK-NEXT: tosa
 // CHECK-NEXT: vector
 // CHECK-NEXT: x86vector