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dcaballe (Diego Caballero)
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User Since
Sep 16 2016, 11:47 AM (174 w, 3 d)

Recent Activity

Fri, Jan 17

dcaballe added inline comments to D72802: [mlir] Introduce bare ptr calling convention for MemRefs in LLVM dialect.
Fri, Jan 17, 11:02 AM · Restricted Project
dcaballe updated the diff for D72802: [mlir] Introduce bare ptr calling convention for MemRefs in LLVM dialect.

Address refactor comments.

Fri, Jan 17, 10:51 AM · Restricted Project

Wed, Jan 15

dcaballe added a comment to D72802: [mlir] Introduce bare ptr calling convention for MemRefs in LLVM dialect.

Thanks, River! Some comments inline.
I think I can refactor some of the code in the patterns but I'd like to know if there is any major concern with this approach before moving forward.

Wed, Jan 15, 4:13 PM · Restricted Project
dcaballe created D72802: [mlir] Introduce bare ptr calling convention for MemRefs in LLVM dialect.
Wed, Jan 15, 1:00 PM · Restricted Project

Mon, Jan 13

dcaballe added a comment to D72545: [mlir] Remove 'valuesToRemoveIfDead' from PatternRewriter API.

Thanks River! I'll commit this in a while if no more comments.

Mon, Jan 13, 1:43 PM · Restricted Project

Fri, Jan 10

dcaballe added reviewers for D72545: [mlir] Remove 'valuesToRemoveIfDead' from PatternRewriter API: rriddle, bondhugula.
Fri, Jan 10, 3:48 PM · Restricted Project
dcaballe created D72545: [mlir] Remove 'valuesToRemoveIfDead' from PatternRewriter API.
Fri, Jan 10, 3:48 PM · Restricted Project

Mon, Dec 23

A. Unique TensorFlower <gardener@tensorflow.org> committed rG330d1ff00ea8: AffineLoopFusion: Prevent fusion of multi-out-edge producer loops (authored by dcaballe).
AffineLoopFusion: Prevent fusion of multi-out-edge producer loops
Mon, Dec 23, 9:18 PM
A. Unique TensorFlower <gardener@tensorflow.org> committed rGdd5a7cb48833: Add getRemappedValue to ConversionPatternRewriter (authored by dcaballe).
Add getRemappedValue to ConversionPatternRewriter
Mon, Dec 23, 9:15 PM
A. Unique TensorFlower <gardener@tensorflow.org> committed rGc87c7f573242: Bugfix: Keep worklistMap in sync with worklist in GreedyPatternRewriter (authored by dcaballe).
Bugfix: Keep worklistMap in sync with worklist in GreedyPatternRewriter
Mon, Dec 23, 9:11 PM
A. Unique TensorFlower <gardener@tensorflow.org> committed rG3451055614a2: Add support for some multi-store cases in affine fusion (authored by dcaballe).
Add support for some multi-store cases in affine fusion
Mon, Dec 23, 9:07 PM
A. Unique TensorFlower <gardener@tensorflow.org> committed rG9e6cf0d0258a: Fix build of affine load/store with empty map (authored by dcaballe).
Fix build of affine load/store with empty map
Mon, Dec 23, 8:48 PM
A. Unique TensorFlower <gardener@tensorflow.org> committed rG96371d25c388: Enable TTI for host TargetMachine in JitRunner (authored by dcaballe).
Enable TTI for host TargetMachine in JitRunner
Mon, Dec 23, 8:45 PM
A. Unique TensorFlower <gardener@tensorflow.org> committed rGc6a006d4c798: Fix verification of zero-dim memref in affine.load/affine.store/std.load/std. (authored by dcaballe).
Fix verification of zero-dim memref in affine.load/affine.store/std.load/std.
Mon, Dec 23, 8:44 PM
A. Unique TensorFlower <gardener@tensorflow.org> committed rG68587dfc15f2: Add TTI pass initialization to pass managers. (authored by dcaballe).
Add TTI pass initialization to pass managers.
Mon, Dec 23, 8:44 PM
A. Unique TensorFlower <gardener@tensorflow.org> committed rGc19b72d3f39a: Add StdIndexedValue to EDSC helpers (authored by dcaballe).
Add StdIndexedValue to EDSC helpers
Mon, Dec 23, 8:44 PM

Sep 14 2019

dcaballe added inline comments to D67259: [X86] Enable -mprefer-vector-width=256 by default for Skylake-avx512 and later Intel CPUs..
Sep 14 2019, 3:09 PM · Restricted Project
dcaballe added inline comments to D67259: [X86] Enable -mprefer-vector-width=256 by default for Skylake-avx512 and later Intel CPUs..
Sep 14 2019, 2:55 PM · Restricted Project

Aug 26 2019

dcaballe added a comment to D66720: [LV] Fold tail by masking - handle reductions.

Thanks, Ayal! LGTM

Aug 26 2019, 11:14 AM · Restricted Project

Aug 21 2019

dcaballe abandoned D48818: [VPlan] Introduce simplifyPlainCFG step in H-CFG builder..

Not needed for now

Aug 21 2019, 1:07 PM
dcaballe abandoned D50823: [VPlan] Introduce VPCmpInst sub-class in the instruction-level representation.

Not needed for now.

Aug 21 2019, 12:49 PM · Restricted Project

Aug 6 2019

dcaballe committed rG8bac17709e16: Re-land D65760/r367944 (authored by dcaballe).
Re-land D65760/r367944
Aug 6 2019, 9:25 AM
dcaballe committed rL368055: Re-land D65760/r367944 .
Re-land D65760/r367944
Aug 6 2019, 9:25 AM

Aug 5 2019

dcaballe added a comment to D65760: [ORC] Add host CPU name and sub-target features to JITTargetMachineBuilder::detectHost().

Thanks, @plotfi. Sorry about that. It passed with gcc in my local machine. I'll check with Clang.

Aug 5 2019, 5:08 PM · Restricted Project
dcaballe committed rG16477588824f: [ORC] Add CPU name and sub-target features to detectHost (authored by dcaballe).
[ORC] Add CPU name and sub-target features to detectHost
Aug 5 2019, 4:04 PM
dcaballe committed rL367944: [ORC] Add CPU name and sub-target features to detectHost.
[ORC] Add CPU name and sub-target features to detectHost
Aug 5 2019, 4:03 PM
dcaballe closed D65760: [ORC] Add host CPU name and sub-target features to JITTargetMachineBuilder::detectHost().
Aug 5 2019, 4:03 PM · Restricted Project
dcaballe added a comment to D65760: [ORC] Add host CPU name and sub-target features to JITTargetMachineBuilder::detectHost().

Thanks for the quick response, Lang! I'll proceed with the commit in a while, in case somebody else has any comments.

Aug 5 2019, 1:21 PM · Restricted Project
dcaballe created D65760: [ORC] Add host CPU name and sub-target features to JITTargetMachineBuilder::detectHost().
Aug 5 2019, 11:04 AM · Restricted Project

Apr 9 2019

dcaballe accepted D59952: [VPLAN] Minor improvement to testing and debug messages..

LGTM! Thanks, Francesco!

Apr 9 2019, 10:03 AM · Restricted Project

Mar 29 2019

dcaballe added a comment to D59952: [VPLAN] Minor improvement to testing and debug messages..

Or are you saying this needs to be done explicitly for stress testing?

Mar 29 2019, 2:39 PM · Restricted Project
dcaballe added a comment to D59952: [VPLAN] Minor improvement to testing and debug messages..

Should we add a small lit test that covers the new expected behavior? Probably reusing one from D57598 with the stress testing flag would suffice.

Good idea. Something that invokes stress testing and sets VF = 4 when the computed VF is 1. Did I get it right?

Mar 29 2019, 9:55 AM · Restricted Project

Mar 28 2019

dcaballe added a comment to D59952: [VPLAN] Minor improvement to testing and debug messages..

Should we add a small lit test that covers the new expected behavior? Probably reusing one from D57598 with the stress testing flag would suffice.

Mar 28 2019, 6:48 PM · Restricted Project
dcaballe added a comment to D59952: [VPLAN] Minor improvement to testing and debug messages..

I thought the point was to just have a VF to build a VPlan with and as it currently stands we build the same VPlans with VF = 4 or any other VF I think. With the programmatically determined VF, we would be a little closer to reality in the stress testing. As Hideki mentioned, having a constant factor for stress testing might have other benefits later on though

Mar 28 2019, 1:53 PM · Restricted Project
dcaballe added a comment to D59952: [VPLAN] Minor improvement to testing and debug messages..

Yep, I agree on that we should keep the stress testing mechanism. It will be very useful to make sure that the construction and predication (and maybe other transformation) are robust enough since we can run it on loop nests that are not necessarily vectorizable.
Something important, though, is that we shouldn't use this mechanism to bypass legality or pragma simd requirements to vectorize a loop, i.e., we shouldn't use it to generate actual vector code.
What are you trying to achieve, Francesco?

Mar 28 2019, 1:25 PM · Restricted Project

Mar 14 2019

dcaballe accepted D57598: [VPLAN] Determine Vector Width programmatically..

Thanks, Francesco. LGTM!

Mar 14 2019, 7:37 PM · Restricted Project

Feb 6 2019

dcaballe added a comment to D57837: [LV] Prevent interleaving if computeMaxVF returned None..

LGTM (as you could see in my previous message :))

Feb 6 2019, 4:49 PM · Restricted Project
dcaballe added a comment to D57837: [LV] Prevent interleaving if computeMaxVF returned None..
Feb 6 2019, 2:52 PM · Restricted Project

Feb 5 2019

dcaballe added inline comments to D57382: [LV] Move interleave count computation to LVP::plan()..
Feb 5 2019, 6:19 PM · Restricted Project

Feb 4 2019

dcaballe added inline comments to D57598: [VPLAN] Determine Vector Width programmatically..
Feb 4 2019, 9:33 AM · Restricted Project
dcaballe added a comment to D57598: [VPLAN] Determine Vector Width programmatically..

Thanks Francesco for helping us remove some of the constraints we have in VPlan native path!
I agree with the idea of using getSmallestAndWidestTypes() as a starting point whereas we don't have the proper cost model.

Feb 4 2019, 9:23 AM · Restricted Project

Jan 31 2019

dcaballe added inline comments to D57382: [LV] Move interleave count computation to LVP::plan()..
Jan 31 2019, 11:36 AM · Restricted Project

Jan 30 2019

dcaballe added a comment to D57382: [LV] Move interleave count computation to LVP::plan()..

Hey Florian! Thanks a lot for taking care of this! I'm leaving a comment below. Please, let me know what you think.

Jan 30 2019, 9:45 PM · Restricted Project

Jan 11 2019

dcaballe planned changes to D48818: [VPlan] Introduce simplifyPlainCFG step in H-CFG builder..

Hi Florian,

Jan 11 2019, 10:04 AM

Nov 12 2018

dcaballe added a comment to D49491: [RFC][VPlan, SLP] Add simple SLP analysis on top of VPlan..

From the VPlan point of view, LGTM. I don't have any other comments.

Nov 12 2018, 10:28 AM

Oct 10 2018

dcaballe accepted D53091: [LV] Ignore more debug info..

LGTM!

Oct 10 2018, 10:54 AM

Aug 22 2018

dcaballe added a comment to D50823: [VPlan] Introduce VPCmpInst sub-class in the instruction-level representation.

In case you missed it, there is some discussion in D50480 regarding this code. Your feedback would be appreciated.

Aug 22 2018, 3:34 PM · Restricted Project
dcaballe added reviewers for D50823: [VPlan] Introduce VPCmpInst sub-class in the instruction-level representation: mkuper, hfinkel, rkruppe.
Aug 22 2018, 3:32 PM · Restricted Project
dcaballe added a comment to D50480: [LV] Vectorizing loops of arbitrary trip count without remainder under opt for size.

Reverted to use the original ICmpULE extended opcode instead of detached ICmpInst. This can be revised quite easily once VPInstructions acquire any other form of modeling compares.

Aug 22 2018, 3:05 PM

Aug 20 2018

dcaballe added inline comments to D50480: [LV] Vectorizing loops of arbitrary trip count without remainder under opt for size.
Aug 20 2018, 3:44 PM

Aug 17 2018

dcaballe added inline comments to D50823: [VPlan] Introduce VPCmpInst sub-class in the instruction-level representation.
Aug 17 2018, 9:24 AM · Restricted Project

Aug 15 2018

dcaballe added inline comments to D50480: [LV] Vectorizing loops of arbitrary trip count without remainder under opt for size.
Aug 15 2018, 5:18 PM
dcaballe created D50823: [VPlan] Introduce VPCmpInst sub-class in the instruction-level representation.
Aug 15 2018, 5:12 PM · Restricted Project

Aug 14 2018

dcaballe added inline comments to D50480: [LV] Vectorizing loops of arbitrary trip count without remainder under opt for size.
Aug 14 2018, 6:33 PM

Aug 12 2018

dcaballe added a comment to D50480: [LV] Vectorizing loops of arbitrary trip count without remainder under opt for size.

Thanks, Ayal! Some comments below.
Do you see any potential issue that could make modeling this in the VPlan native path complicated once we have predication?

Aug 12 2018, 7:32 PM

Aug 7 2018

dcaballe added a comment to D49489: [VPlan] VPlan version of InterleavedAccessInfo..

Just a few comments.

Aug 7 2018, 11:14 AM

Aug 6 2018

dcaballe added a comment to D49491: [RFC][VPlan, SLP] Add simple SLP analysis on top of VPlan..

Thanks for working on this, Florian, and sorry for my delayed response. I added some initial comments. I'll come back soon.

Aug 6 2018, 10:18 PM

Jul 30 2018

dcaballe committed rL338346: [VPlan] Introduce VPLoopInfo analysis..
[VPlan] Introduce VPLoopInfo analysis.
Jul 30 2018, 6:58 PM
dcaballe closed D48816: [VPlan] Introduce VPLoopInfo analysis..
Jul 30 2018, 6:58 PM
dcaballe committed rL338310: [VPlan] Introduce VPlan-based dominator analysis..
[VPlan] Introduce VPlan-based dominator analysis.
Jul 30 2018, 2:34 PM
dcaballe closed D48815: [VPlan] Introduce VPlan-based dominator analysis..
Jul 30 2018, 2:33 PM

Jul 27 2018

dcaballe added a comment to D48815: [VPlan] Introduce VPlan-based dominator analysis..

Thanks, Florian! I'll go ahead with the commit!

Jul 27 2018, 12:15 PM

Jul 20 2018

dcaballe added a comment to D48816: [VPlan] Introduce VPLoopInfo analysis..

Thanks for the review, Florian!
I'll commit this once D48815 is approved and committed.

Jul 20 2018, 10:36 AM

Jul 17 2018

dcaballe updated the diff for D48816: [VPlan] Introduce VPLoopInfo analysis..

Making VPLoopInfo object a member of VPlan.

Jul 17 2018, 10:50 PM
dcaballe added inline comments to D48816: [VPlan] Introduce VPLoopInfo analysis..
Jul 17 2018, 10:21 PM
dcaballe updated the diff for D48815: [VPlan] Introduce VPlan-based dominator analysis..

Reverting GraphTraits changes and adding VPlanTestBase as friend of VPlanHCFGBuilder.

Jul 17 2018, 9:49 PM
dcaballe added inline comments to D48815: [VPlan] Introduce VPlan-based dominator analysis..
Jul 17 2018, 9:46 PM

Jul 16 2018

dcaballe added inline comments to D48815: [VPlan] Introduce VPlan-based dominator analysis..
Jul 16 2018, 5:16 PM
dcaballe updated the diff for D48815: [VPlan] Introduce VPlan-based dominator analysis..

Thanks for the comments, Florian! Addressing your comments.

Jul 16 2018, 5:13 PM

Jul 12 2018

dcaballe updated the diff for D48818: [VPlan] Introduce simplifyPlainCFG step in H-CFG builder..

Rebasing this patch on top of D49032

Jul 12 2018, 11:49 AM
dcaballe updated the diff for D48816: [VPlan] Introduce VPLoopInfo analysis..

Rebasing this patch on top of D49032.

Jul 12 2018, 11:28 AM
dcaballe updated the diff for D48815: [VPlan] Introduce VPlan-based dominator analysis..

Rebasing this patch on top of D49032.

Jul 12 2018, 11:25 AM

Jul 9 2018

dcaballe committed rL336572: [LoopInfo] Port loop exit interfaces from Loop to LoopBase.
[LoopInfo] Port loop exit interfaces from Loop to LoopBase
Jul 9 2018, 10:58 AM
dcaballe closed D48817: [LoopInfo] Port loop exit interfaces from Loop to LoopBase.
Jul 9 2018, 10:57 AM
dcaballe committed rL336554: [VPlan][LV] Introduce condition bit in VPBlockBase.
[VPlan][LV] Introduce condition bit in VPBlockBase
Jul 9 2018, 9:02 AM
dcaballe closed D48814: [VPlan] Introduce condition bit in VPBlockBase..
Jul 9 2018, 9:02 AM

Jul 6 2018

dcaballe updated the diff for D48817: [LoopInfo] Port loop exit interfaces from Loop to LoopBase.

Addressing Chandler's comments. Thanks, Chandler!
Yes, I have commit access.

Jul 6 2018, 7:11 PM
dcaballe added inline comments to D48815: [VPlan] Introduce VPlan-based dominator analysis..
Jul 6 2018, 1:08 PM
dcaballe added inline comments to D48815: [VPlan] Introduce VPlan-based dominator analysis..
Jul 6 2018, 12:15 PM
dcaballe accepted D49032: [VPlan] Add VPlanTestBase.h with helper class to build VPlan for tests..

Good idea! Thanks! LGTM. Just some minor comments.

Jul 6 2018, 12:11 PM
dcaballe added a comment to D48814: [VPlan] Introduce condition bit in VPBlockBase..

Thanks, Florian! I'll commit next week.

Jul 6 2018, 9:10 AM

Jul 1 2018

dcaballe added a parent revision for D48816: [VPlan] Introduce VPLoopInfo analysis.: D48815: [VPlan] Introduce VPlan-based dominator analysis..
Jul 1 2018, 11:00 PM
dcaballe added a child revision for D48815: [VPlan] Introduce VPlan-based dominator analysis.: D48816: [VPlan] Introduce VPLoopInfo analysis..
Jul 1 2018, 11:00 PM
dcaballe added parent revisions for D48818: [VPlan] Introduce simplifyPlainCFG step in H-CFG builder.: D48814: [VPlan] Introduce condition bit in VPBlockBase., D48815: [VPlan] Introduce VPlan-based dominator analysis., D48816: [VPlan] Introduce VPLoopInfo analysis., D48817: [LoopInfo] Port loop exit interfaces from Loop to LoopBase.
Jul 1 2018, 10:59 PM
dcaballe added a child revision for D48814: [VPlan] Introduce condition bit in VPBlockBase.: D48818: [VPlan] Introduce simplifyPlainCFG step in H-CFG builder..
Jul 1 2018, 10:59 PM
dcaballe added a child revision for D48815: [VPlan] Introduce VPlan-based dominator analysis.: D48818: [VPlan] Introduce simplifyPlainCFG step in H-CFG builder..
Jul 1 2018, 10:59 PM
dcaballe added a child revision for D48816: [VPlan] Introduce VPLoopInfo analysis.: D48818: [VPlan] Introduce simplifyPlainCFG step in H-CFG builder..
Jul 1 2018, 10:59 PM
dcaballe added a child revision for D48817: [LoopInfo] Port loop exit interfaces from Loop to LoopBase: D48818: [VPlan] Introduce simplifyPlainCFG step in H-CFG builder..
Jul 1 2018, 10:59 PM
dcaballe created D48818: [VPlan] Introduce simplifyPlainCFG step in H-CFG builder..
Jul 1 2018, 10:34 PM
dcaballe created D48817: [LoopInfo] Port loop exit interfaces from Loop to LoopBase.
Jul 1 2018, 10:29 PM
dcaballe created D48816: [VPlan] Introduce VPLoopInfo analysis..
Jul 1 2018, 10:25 PM
dcaballe created D48815: [VPlan] Introduce VPlan-based dominator analysis..
Jul 1 2018, 10:19 PM
dcaballe created D48814: [VPlan] Introduce condition bit in VPBlockBase..
Jul 1 2018, 10:14 PM

Jun 15 2018

dcaballe committed rL334854: Move redundant-vf2-cost.ll test to X86 directory.
Move redundant-vf2-cost.ll test to X86 directory
Jun 15 2018, 11:50 AM
dcaballe accepted D46827: [VPlan] Add VPInstruction to VPRecipe transformation..

Thanks a lot, Florian! LGTM!

Jun 15 2018, 11:19 AM
dcaballe committed rL334840: [LV] Prevent LV to run cost model twice for VF=2.
[LV] Prevent LV to run cost model twice for VF=2
Jun 15 2018, 9:26 AM
dcaballe closed D48048: [LV] Prevent LV to run cost model twice for VF=2.
Jun 15 2018, 9:26 AM
dcaballe added inline comments to D46827: [VPlan] Add VPInstruction to VPRecipe transformation..
Jun 15 2018, 9:11 AM

Jun 14 2018

dcaballe added inline comments to D48048: [LV] Prevent LV to run cost model twice for VF=2.
Jun 14 2018, 3:36 PM
dcaballe added a comment to D48193: [LoopVectorizer] Use an interleave count of 1 when using a vector library call.

Hi Robert,

Jun 14 2018, 1:42 PM