[RISCV] [1/2] Add intrinsic for Zbc extension

[LevyHsu]

Summary

Head files are included in the second patch in case the name needs to be changed.

RV32 / 64:
clmul
clmulh
clmulr

[craig.topper]

clang/include/clang/Basic/BuiltinsRISCV.def

22

I think we should drop the underscore in clmul_h and clmul_r. The mnemonic doesn't have a period between them. So that's different than orc.b and crc32.w.

llvm/include/llvm/IR/IntrinsicsRISCV.td

82

clmul_h -> clmulh
clmul_r -> clmulr

[LevyHsu]

1. clang/include/clang/Basic/BuiltinsRISCV.def clang/lib/CodeGen/CGBuiltin.cpp llvm/include/llvm/IR/IntrinsicsRISCV.td clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c
   • Renaming clmul_h clmul_r to clmulh clmulr

2. llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
   • Renaming clmul.h clmul.r to clmulh clmulr

[craig.topper]

LGTM. We can adjust the builtin names in the future if we need to do something different to match gcc.

clang/include/clang/Basic/BuiltinsRISCV.def

 //===----------------------------------------------------------------------===//
 
 #if defined(BUILTIN) && !defined(TARGET_BUILTIN)
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
+// Zbc extension
+TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "experimental-zbc")
+TARGET_BUILTIN(__builtin_riscv_clmul_h, "LiLiLi", "nc", "experimental-zbc")
+TARGET_BUILTIN(__builtin_riscv_clmul_r, "LiLiLi", "nc", "experimental-zbc")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/include/clang/Basic/DiagnosticSemaKinds.td

 
 // TCB warnings
 def err_tcb_conflicting_attributes : Error<
   "attributes '%0(\"%2\")' and '%1(\"%2\")' are mutually exclusive">;
 def warn_tcb_enforcement_violation : Warning<
   "calling %0 is a violation of trusted computing base '%1'">,
   InGroup<DiagGroup<"tcb-enforcement">>;
 
-// RISC-V V-extension
-def err_riscvv_builtin_requires_v : Error<
-   "builtin requires 'V' extension support to be enabled">;
+// RISC-V builtin required extension warning
+def err_riscv_builtin_requires_extension : Error<
+  "builtin requires %0 extension support to be enabled">;
 } // end of sema component.

clang/lib/CodeGen/CGBuiltin.cpp

for (unsigned i = 0, e = E->getNumArgs(); i != e; i++)
     Ops.push_back(EmitScalarExpr(E->getArg(i)));
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 
   // Required for overloaded intrinsics.
   llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
   switch (BuiltinID) {
 #include "clang/Basic/riscv_vector_builtin_cg.inc"
+
+  // Zbc
+  case RISCV::BI__builtin_riscv_clmul:
+    ID = Intrinsic::riscv_clmul;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_clmul_h:
+    ID = Intrinsic::riscv_clmul_h;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_clmul_r:
+    ID = Intrinsic::riscv_clmul_r;
+    IntrinsicTypes = {ResultType};
+    break;
+  default: {
+    llvm_unreachable("unexpected builtin ID");
+    return nullptr;
+  } // default
   }
 
   assert(ID != Intrinsic::not_intrinsic);
 
   llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
   return Builder.CreateCall(F, Ops, "");
 }

clang/lib/Sema/SemaChecking.cpp

bool Sema::CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID,
   return false;
 }
 
 bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
                                          unsigned BuiltinID,
                                          CallExpr *TheCall) {
   // CodeGenFunction can also detect this, but this gives a better error
   // message.
+  bool FeatureMissing = false;
+  SmallVector<StringRef> ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  if (Features.find("experimental-v") != StringRef::npos &&
-      !TI.hasFeature("experimental-v"))
-    return Diag(TheCall->getBeginLoc(), diag::err_riscvv_builtin_requires_v)
-           << TheCall->getSourceRange();
+  Features.split(ReqFeatures, ',');
 
-  return false;
+  // Check if each required feature is included
+  for (auto &I : ReqFeatures) {
+    if (TI.hasFeature(I))
+      continue;
+    // Make message like "experimental-zbr" to "Zbr"
+    I.consume_front("experimental-");
+    std::string FeatureStr = I.str();
+    FeatureStr[0] = std::toupper(FeatureStr[0]);
+
+    // Error message
+    FeatureMissing = true;
+    Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension)
+        << TheCall->getSourceRange() << StringRef(FeatureStr);
+  }
+
+  return FeatureMissing;
 }
 
 bool Sema::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID,
                                            CallExpr *TheCall) {
   if (BuiltinID == SystemZ::BI__builtin_tabort) {
     Expr *Arg = TheCall->getArg(0);
     if (Optional<llvm::APSInt> AbortCode = Arg->getIntegerConstantExpr(Context))
       if (AbortCode->getSExtValue() >= 0 && AbortCode->getSExtValue() < 256)

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbc -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZBC
+
+// RV32ZBC-LABEL: @clmul(
+// RV32ZBC-NEXT:  entry:
+// RV32ZBC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBC-NEXT:    store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBC-NEXT:    ret i32 [[TMP2]]
+//
+long clmul(long a, long b) {
+  return __builtin_riscv_clmul(a, b);
+}
+
+// RV32ZBC-LABEL: @clmulh(
+// RV32ZBC-NEXT:  entry:
+// RV32ZBC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBC-NEXT:    store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.h.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBC-NEXT:    ret i32 [[TMP2]]
+//
+long clmulh(long a, long b) {
+  return __builtin_riscv_clmul_h(a, b);
+}
+
+// RV32ZBC-LABEL: @clmulr(
+// RV32ZBC-NEXT:  entry:
+// RV32ZBC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBC-NEXT:    store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.r.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBC-NEXT:    ret i32 [[TMP2]]
+//
+long clmulr(long a, long b) {
+  return __builtin_riscv_clmul_r(a, b);
+}

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbc -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZBC
+
+// RV64ZBC-LABEL: @clmul(
+// RV64ZBC-NEXT:  entry:
+// RV64ZBC-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBC-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBC-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBC-NEXT:    store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBC-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBC-NEXT:    [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBC-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBC-NEXT:    ret i64 [[TMP2]]
+//
+long clmul(long a, long b) {
+  return __builtin_riscv_clmul(a, b);
+}
+
+// RV64ZBC-LABEL: @clmulh(
+// RV64ZBC-NEXT:  entry:
+// RV64ZBC-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBC-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBC-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBC-NEXT:    store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBC-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBC-NEXT:    [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBC-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.clmul.h.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBC-NEXT:    ret i64 [[TMP2]]
+//
+long clmulh(long a, long b) {
+  return __builtin_riscv_clmul_h(a, b);
+}
+
+// RV64ZBC-LABEL: @clmulr(
+// RV64ZBC-NEXT:  entry:
+// RV64ZBC-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBC-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBC-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBC-NEXT:    store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBC-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBC-NEXT:    [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBC-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.clmul.r.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBC-NEXT:    ret i64 [[TMP2]]
+//
+long clmulr(long a, long b) {
+  return __builtin_riscv_clmul_r(a, b);
+}

llvm/include/llvm/IR/IntrinsicsRISCV.td

let TargetPrefix = "riscv" in {
   defm int_riscv_masked_atomicrmw_umin : MaskedAtomicRMWFourArgIntrinsics;
 
   // @llvm.riscv.masked.cmpxchg.{i32,i64}.<p>(...)
   defm int_riscv_masked_cmpxchg : MaskedAtomicRMWFiveArgIntrinsics;
 
 } // TargetPrefix = "riscv"
 
 //===----------------------------------------------------------------------===//
+// RISC-V Bitmanip (Bit Manipulation) Extension
+// Zbc extension part
+
+let TargetPrefix = "riscv" in {
+  
+    class BitMan_GPRGPR_Intrinsics
+        : Intrinsic<[llvm_any_ty],
+                    [LLVMMatchType<0>, LLVMMatchType<0>],
+                    [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+  
+    def int_riscv_clmul : BitMan_GPRGPR_Intrinsics;
+    def int_riscv_clmul_h : BitMan_GPRGPR_Intrinsics;
+    def int_riscv_clmul_r : BitMan_GPRGPR_Intrinsics;
+
+} // TargetPrefix = "riscv"
+
+//===----------------------------------------------------------------------===//
 // Vectors
 
 class RISCVVIntrinsic {
   // These intrinsics may accept illegal integer values in their llvm_any_ty
   // operand, so they have to be extended. If set to zero then the intrinsic
   // does not have any operand that must be extended.
   Intrinsic IntrinsicID = !cast<Intrinsic>(NAME);
   bits<4> SplatOperand = 0;

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 def : Pat<(i64 (sext_inreg (or (shl GPR:$rs2, (i64 16)),
                                (and GPR:$rs1, 0x000000000000FFFF)),
                            i32)),
           (PACKW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
                    (srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))),
           (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbc] in {
+def : PatGprGpr<int_riscv_clmul, CLMUL>;
+def : PatGprGpr<int_riscv_clmul_h, CLMULH>;
+def : PatGprGpr<int_riscv_clmul_r, CLMULR>;
+} // Predicates = [HasStdExtZbc]

llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IBC
+
+declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+
+define i32 @clmul32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: clmul32:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    clmul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBC-LABEL: clmul32:
+; RV32IBC:       # %bb.0:
+; RV32IBC-NEXT:    clmul a0, a0, a1
+; RV32IBC-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.clmul.h.i32(i32 %a, i32 %b)
+
+define i32 @clmul32h(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: clmul32h:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    clmulh a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBC-LABEL: clmul32h:
+; RV32IBC:       # %bb.0:
+; RV32IBC-NEXT:    clmulh a0, a0, a1
+; RV32IBC-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.clmul.h.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.clmul.r.i32(i32 %a, i32 %b)
+
+define i32 @clmul32r(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: clmul32r:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    clmulr a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBC-LABEL: clmul32r:
+; RV32IBC:       # %bb.0:
+; RV32IBC-NEXT:    clmulr a0, a0, a1
+; RV32IBC-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.clmul.r.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}

llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBC
+
+declare i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
+
+define i64 @clmul64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: clmul64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    clmul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBC-LABEL: clmul64:
+; RV64IBC:       # %bb.0:
+; RV64IBC-NEXT:    clmul a0, a0, a1
+; RV64IBC-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.clmul.h.i64(i64 %a, i64 %b)
+
+define i64 @clmul64h(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: clmul64h:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    clmulh a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBC-LABEL: clmul64h:
+; RV64IBC:       # %bb.0:
+; RV64IBC-NEXT:    clmulh a0, a0, a1
+; RV64IBC-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.clmul.h.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.clmul.r.i64(i64 %a, i64 %b)
+
+define i64 @clmul64r(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: clmul64r:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    clmulr a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBC-LABEL: clmul64r:
+; RV64IBC:       # %bb.0:
+; RV64IBC-NEXT:    clmulr a0, a0, a1
+; RV64IBC-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.clmul.r.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}