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[clang][aarch64] Address various fixed-length SVE vector operations
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Authored by c-rhodes on Sep 24 2020, 8:34 AM.

Details

Summary

This patch adds tests and support for operations on SVE vectors created
by the 'arm_sve_vector_bits' attribute, described by the Arm C Language
Extensions (ACLE, version 00bet5, section 3.7.3.3) for SVE [1].

This covers the following:

  • VLSTs support the same forms of element-wise initialization as GNU vectors.
  • VLSTs support the same built-in C and C++ operators as GNU vectors.
  • Conditional and binary expressions containing GNU and SVE vectors (fixed or sizeless) are invalid since the ambiguity around the result type affects the ABI.

No functional changes were required to support vector initialization and
operators. The functional changes are to address unsupported conditional and
binary expressions.

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Event Timeline

c-rhodes created this revision.Sep 24 2020, 8:34 AM
Herald added a project: Restricted Project. · View Herald Transcript
c-rhodes requested review of this revision.Sep 24 2020, 8:34 AM