Page MenuHomePhabricator

[VP][RISCV] Add vp.fshl/fshr and RISC-V support.
ClosedPublic

Authored by fakepaper56 on Nov 20 2022, 8:02 AM.

Details

Summary

The patch made VectorLegalizer expand ISD::VP_FSHL and ISD::VP_FSHR to
achieve the codegen.

Diff Detail

Event Timeline

fakepaper56 created this revision.Nov 20 2022, 8:02 AM
fakepaper56 requested review of this revision.Nov 20 2022, 8:02 AM
craig.topper added inline comments.Nov 30 2022, 7:06 PM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
741

Why 9? I only counted 7 instructions.

743

VP_FRINT?

fakepaper56 added inline comments.Dec 1 2022, 3:53 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
741

I am sorry it is my counting error.

Fix wrong cost model implement and add missing test cases for cost model.

fakepaper56 marked 2 inline comments as done.Dec 1 2022, 4:39 AM
craig.topper added inline comments.Dec 6 2022, 4:10 PM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
533

i8 vector types are missing

Add missing cost model.

This revision is now accepted and ready to land.Dec 6 2022, 7:09 PM
This revision was landed with ongoing or failed builds.Dec 6 2022, 8:16 PM
This revision was automatically updated to reflect the committed changes.