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fakepaper56 (Yeting Kuo)
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Jan 13 2022, 1:26 AM (23 w, 4 d)

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Today

fakepaper56 added a comment to D128624: [RISCV] Zero extend immediate for vget/vset builtins to match vector.insert/extract intrinsics..

LGTM

Mon, Jun 27, 5:07 AM · Restricted Project, Restricted Project

Tue, Jun 14

fakepaper56 abandoned D123581: [RISCV] Teach vsetvli insertion to handle PseudoReadVL..

The function is done by D127576.

Tue, Jun 14, 11:02 PM · Restricted Project, Restricted Project
fakepaper56 committed rG9096a52566cb: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after… (authored by fakepaper56).
[RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after…
Tue, Jun 14, 10:59 PM · Restricted Project, Restricted Project
fakepaper56 closed D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF..
Tue, Jun 14, 10:58 PM · Restricted Project, Restricted Project
fakepaper56 updated the diff for D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF..

Rebase to origin/main and move the new test case into vsetvli-insert.ll.

Tue, Jun 14, 6:50 PM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF..
Tue, Jun 14, 1:56 AM · Restricted Project, Restricted Project
fakepaper56 updated the summary of D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF..
Tue, Jun 14, 12:59 AM · Restricted Project, Restricted Project
fakepaper56 updated the diff for D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF..

Refine commit summary.

Tue, Jun 14, 12:59 AM · Restricted Project, Restricted Project
fakepaper56 updated the summary of D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF..
Tue, Jun 14, 12:54 AM · Restricted Project, Restricted Project
fakepaper56 retitled D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF. from [RISCV] Teach vsetvli insertion to handle VLEFF/VLSEGFF. to [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF..
Tue, Jun 14, 12:53 AM · Restricted Project, Restricted Project
fakepaper56 updated the diff for D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF..

Address reames's comments.

Tue, Jun 14, 12:51 AM · Restricted Project, Restricted Project

Mon, Jun 13

fakepaper56 updated the diff for D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF..

Refine the comments.

Mon, Jun 13, 1:42 AM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF..
Mon, Jun 13, 1:03 AM · Restricted Project, Restricted Project
fakepaper56 updated the diff for D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF..

Address Craig's comments.

Mon, Jun 13, 1:01 AM · Restricted Project, Restricted Project

Sun, Jun 12

fakepaper56 added a comment to D127583: [RISCV] Move some methods out of RISCVInstrInfo and into RISCV namespace..

LGTM.

Sun, Jun 12, 2:43 AM · Restricted Project, Restricted Project

Sat, Jun 11

fakepaper56 added reviewers for D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF.: craig.topper, reames, rogfer01, frasercrmck.
Sat, Jun 11, 12:55 PM · Restricted Project, Restricted Project
fakepaper56 updated the summary of D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF..
Sat, Jun 11, 12:53 PM · Restricted Project, Restricted Project
fakepaper56 updated the diff for D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF..

Refine the commit message.

Sat, Jun 11, 12:52 PM · Restricted Project, Restricted Project
fakepaper56 requested review of D127576: [RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF..
Sat, Jun 11, 12:48 PM · Restricted Project, Restricted Project
fakepaper56 added a comment to D127477: [RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`.

I am sorry that giving wrong comments made @sunshaoce rewrite and commit the code repeatedly. I promise I will review code more carefully and be more familiar with llvm.

Sat, Jun 11, 10:24 AM · Restricted Project, Restricted Project

Fri, Jun 10

fakepaper56 added a comment to D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..

I am sorry for creating the trouble. Should I revert the patch first?

Fri, Jun 10, 3:45 AM · Restricted Project, Restricted Project
fakepaper56 added a comment to D127477: [RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`.

LGTM. It's fine to me that not declare isFaultFirstLoad as a static function of class RISCVInstrInfo, although I prefer this method.

Fri, Jun 10, 2:45 AM · Restricted Project, Restricted Project
fakepaper56 accepted D127477: [RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`.
Fri, Jun 10, 2:26 AM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D127477: [RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`.
Fri, Jun 10, 2:13 AM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D127477: [RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`.
Fri, Jun 10, 2:10 AM · Restricted Project, Restricted Project
fakepaper56 added a comment to D127477: [RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`.

Thank you for providing your cmake command.

Fri, Jun 10, 1:47 AM · Restricted Project, Restricted Project
fakepaper56 added a comment to D127477: [RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`.
Fri, Jun 10, 1:43 AM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D127477: [RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`.
Fri, Jun 10, 1:42 AM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D127477: [RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`.
Fri, Jun 10, 1:24 AM · Restricted Project, Restricted Project
fakepaper56 added a comment to D127477: [RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`.

I am sorry to create the trouble, but I didn't encounter this problem in my local. Could you provide me your cmake command?
My cmake command:

cmake -G "Ninja" -DLLVM_ENABLE_PROJECTS="clang" -DLLVM_BUILD_EXAMPLES=False -DLLVM_PARALLEL_LINK_JOBS=2 -DCMAKE_BUILD_TYPE=Debug ../llvm
Fri, Jun 10, 1:22 AM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D127477: [RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`.
Fri, Jun 10, 1:17 AM · Restricted Project, Restricted Project

Thu, Jun 9

fakepaper56 added a reverting change for rG4537aae0d57e: [RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF.: rGf68cad908705: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..
Thu, Jun 9, 10:57 PM · Restricted Project, Restricted Project
fakepaper56 committed rGf68cad908705: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs. (authored by fakepaper56).
[RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.
Thu, Jun 9, 10:57 PM · Restricted Project, Restricted Project
fakepaper56 added a reverting change for D125199: [RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF.: rGf68cad908705: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..
Thu, Jun 9, 10:57 PM · Restricted Project, Restricted Project
fakepaper56 closed D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..
Thu, Jun 9, 10:57 PM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..
Thu, Jun 9, 7:14 PM · Restricted Project, Restricted Project
fakepaper56 updated the diff for D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..

Remove useless definition of TSFlags.

Thu, Jun 9, 7:13 PM · Restricted Project, Restricted Project
fakepaper56 updated the diff for D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..

Add comments for RISCVInsertVSETVLI and uses MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) && !MI.isInlineAsm() to identify VLEFF/VLSEGFF instead of adding new TSFlag.

Thu, Jun 9, 12:46 AM · Restricted Project, Restricted Project

Tue, Jun 7

fakepaper56 added inline comments to D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..
Tue, Jun 7, 5:56 PM · Restricted Project, Restricted Project

Mon, Jun 6

fakepaper56 added inline comments to D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..
Mon, Jun 6, 9:40 PM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..
Mon, Jun 6, 7:55 PM · Restricted Project, Restricted Project

Sun, Jun 5

fakepaper56 added inline comments to D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..
Sun, Jun 5, 2:31 AM · Restricted Project, Restricted Project

Sat, Jun 4

fakepaper56 updated the diff for D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..

Address reames's comment to use exactly one set pseudo of VLEFF/VLSEGFF. Thank that reames's comments make the patch cleaner.

Sat, Jun 4, 5:18 AM · Restricted Project, Restricted Project

Fri, Jun 3

fakepaper56 added inline comments to D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..
Fri, Jun 3, 8:47 AM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..
Fri, Jun 3, 8:15 AM · Restricted Project, Restricted Project
fakepaper56 updated the diff for D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..

Simplify code about expanding VLEFF/VLSEGFF.

Fri, Jun 3, 8:09 AM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..
Fri, Jun 3, 3:32 AM · Restricted Project, Restricted Project

Thu, Jun 2

fakepaper56 added inline comments to D126742: [RISCV][Clang] Support RVV policy functions..
Thu, Jun 2, 2:06 AM · Restricted Project, Restricted Project

Wed, Jun 1

fakepaper56 updated the diff for D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..

Remove test cases of "[RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF."

Wed, Jun 1, 10:22 AM · Restricted Project, Restricted Project
fakepaper56 added a reverting change for rG4537aae0d57e: [RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF.: D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..
Wed, Jun 1, 10:13 AM · Restricted Project, Restricted Project
fakepaper56 requested review of D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..
Wed, Jun 1, 10:13 AM · Restricted Project, Restricted Project
fakepaper56 added a reverting change for D125199: [RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF.: D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs..
Wed, Jun 1, 10:13 AM · Restricted Project, Restricted Project

Mon, May 30

fakepaper56 accepted D126634: [RISCV][NFC] Rename variables in rvv intrinsics related files..
Mon, May 30, 9:00 PM · Restricted Project, Restricted Project
fakepaper56 added a comment to D126634: [RISCV][NFC] Rename variables in rvv intrinsics related files..

LGTM.

Mon, May 30, 2:10 AM · Restricted Project, Restricted Project

May 24 2022

fakepaper56 added a comment to D123581: [RISCV] Teach vsetvli insertion to handle PseudoReadVL..

I am generally not a fan of this patch. The entire PsuedoReadVL mechanism feels like a hack, and the unchecked assumption that the SEW and policy bits on the ReadVL match the prior VLE is worrying. Beyond that, this adds a decent amount of complexity.

I find myself agreeing with @craig.topper's comment above. It really feels like we need a pseudo instruction for VLEnFF itself here. Such a psuedo would produce two outputs, the second being the GPR version of VL. After this pass, we could lower the pseudo into two instructions (e.g. the actual VLEnFF and the CSR read). This would make the state update on this patch very minimal. This really feels to me like the "right" approach here.

May 24 2022, 9:04 PM · Restricted Project, Restricted Project
fakepaper56 added a comment to D126273: [DAGCombiner][VP] Add DAGCombine for merging VP_FADD and VP_FMUL to VP_FMA..

When I test tsvc.

The IR is:

@llvm.fmuladd.nxv2f32(<vscale x 2 x float>.....

Not

@llvm.riscv.vfmul.nxv2f32.nxv2f32(<vscale x 2 x float> ......
@llvm.riscv.vfadd.nxv2f32.nxv2f32(<vscale x 2 x float> ......

So I am not sure, we need merge vp.fmul and vp.fadd to vp.fma. maybe vp.fma is enough?

May 24 2022, 5:02 AM · Restricted Project, Restricted Project
fakepaper56 updated the diff for D126273: [DAGCombiner][VP] Add DAGCombine for merging VP_FADD and VP_FMUL to VP_FMA..

Rename fold-fadd-and-fmul.ll to fold-vp-fadd-and-vp-fmul.ll.

May 24 2022, 4:50 AM · Restricted Project, Restricted Project

May 23 2022

fakepaper56 updated the diff for D126273: [DAGCombiner][VP] Add DAGCombine for merging VP_FADD and VP_FMUL to VP_FMA..

Using clang-format.

May 23 2022, 9:30 PM · Restricted Project, Restricted Project
fakepaper56 requested review of D126273: [DAGCombiner][VP] Add DAGCombine for merging VP_FADD and VP_FMUL to VP_FMA..
May 23 2022, 9:24 PM · Restricted Project, Restricted Project

May 18 2022

fakepaper56 committed rG00999fb6e142: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes. (authored by fakepaper56).
[SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes.
May 18 2022, 1:16 AM · Restricted Project, Restricted Project
fakepaper56 closed D125600: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes..
May 18 2022, 1:15 AM · Restricted Project, Restricted Project

May 17 2022

fakepaper56 added inline comments to D125600: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes..
May 17 2022, 10:55 PM · Restricted Project, Restricted Project

May 16 2022

fakepaper56 updated the diff for D125600: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes..

After fixing getNode, pass SDNodeFlags to getNode of SDVTList version.

May 16 2022, 7:27 AM · Restricted Project, Restricted Project
fakepaper56 committed rG26a61ab6789f: [SelectionDAG] Make getNode which uses single element SDVTList pass SDNodeFlags. (authored by fakepaper56).
[SelectionDAG] Make getNode which uses single element SDVTList pass SDNodeFlags.
May 16 2022, 3:20 AM · Restricted Project, Restricted Project
fakepaper56 closed D125659: [SelectionDAG] Make getNode which uses single element SDVTList pass SDNodeFlags..
May 16 2022, 3:19 AM · Restricted Project, Restricted Project

May 15 2022

fakepaper56 requested review of D125659: [SelectionDAG] Make getNode which uses single element SDVTList pass SDNodeFlags..
May 15 2022, 9:41 PM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D125600: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes..
May 15 2022, 8:10 PM · Restricted Project, Restricted Project
fakepaper56 updated the diff for D125600: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes..

Add REQUIRES: asserts in pass-fast-math-flags-sdnode.ll.

May 15 2022, 8:09 PM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D125600: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes..
May 15 2022, 7:24 PM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D125600: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes..
May 15 2022, 5:51 AM · Restricted Project, Restricted Project
fakepaper56 retitled D125600: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes. from [VP] Pass fast math flags to VP SDNodes. to [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes..
May 15 2022, 5:49 AM · Restricted Project, Restricted Project
fakepaper56 updated the diff for D125600: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes..

The update removes the part of vp.fcmp support and using argument of DAG.getNode to pass flags.

May 15 2022, 5:44 AM · Restricted Project, Restricted Project

May 14 2022

fakepaper56 updated the summary of D123581: [RISCV] Teach vsetvli insertion to handle PseudoReadVL..
May 14 2022, 1:08 AM · Restricted Project, Restricted Project
fakepaper56 retitled D123581: [RISCV] Teach vsetvli insertion to handle PseudoReadVL. from [RISCV] Teach vsetvli insertion to handle VSETVLIInfo of vl-modified instruction. to [RISCV] Teach vsetvli insertion to handle PseudoReadVL..
May 14 2022, 1:06 AM · Restricted Project, Restricted Project
fakepaper56 added reviewers for D125600: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes.: craig.topper, frasercrmck, hussainjk.
May 14 2022, 1:04 AM · Restricted Project, Restricted Project
fakepaper56 retitled D125600: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes. from [SelectionDAGBuilder] Pass fast math flags to VP SDNodes. to [VP] Pass fast math flags to VP SDNodes..
May 14 2022, 1:03 AM · Restricted Project, Restricted Project
fakepaper56 updated the diff for D125600: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes..

Rename class form [SelectionDAGBuilder] to [VP].

May 14 2022, 1:02 AM · Restricted Project, Restricted Project
fakepaper56 requested review of D125600: [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes..
May 14 2022, 12:59 AM · Restricted Project, Restricted Project

May 12 2022

fakepaper56 updated the diff for D123581: [RISCV] Teach vsetvli insertion to handle PseudoReadVL..

Directly use PseudoReadVL to get VSETVLIInfo also change the commit name and summary.
Additionally, the update removes useless PseudoReadVL in the pass.

May 12 2022, 9:05 AM · Restricted Project, Restricted Project

May 10 2022

fakepaper56 committed rG4537aae0d57e: [RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF. (authored by fakepaper56).
[RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF.
May 10 2022, 11:08 PM · Restricted Project, Restricted Project
fakepaper56 closed D125199: [RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF..
May 10 2022, 11:08 PM · Restricted Project, Restricted Project

May 9 2022

fakepaper56 added inline comments to D125199: [RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF..
May 9 2022, 8:16 PM · Restricted Project, Restricted Project
fakepaper56 updated the diff for D125199: [RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF..

Refine the comments of createMIROperandComment.

May 9 2022, 8:05 PM · Restricted Project, Restricted Project
fakepaper56 updated the diff for D125199: [RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF..

Add human readable comment for vtypes of PseudoReadVL MIs.

May 9 2022, 7:54 PM · Restricted Project, Restricted Project

May 8 2022

fakepaper56 added reviewers for D125199: [RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF.: craig.topper, frasercrmck, rogfer01.
May 8 2022, 7:58 PM · Restricted Project, Restricted Project
fakepaper56 requested review of D125199: [RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF..
May 8 2022, 7:55 PM · Restricted Project, Restricted Project

May 1 2022

fakepaper56 added a comment to D123581: [RISCV] Teach vsetvli insertion to handle PseudoReadVL..

Should I create a new revision for changing PseudoReadVL? Or I just do the change in the revision and also update the commit name and summary?

May 1 2022, 6:38 AM · Restricted Project, Restricted Project
fakepaper56 added a comment to D123581: [RISCV] Teach vsetvli insertion to handle PseudoReadVL..

Would adding SEW and LMUL from the VLEFF to the PseudoReadVL that gets emitted for VLEFF help without requiring us to give the VLEFF the GPR output?

I think it is a better solution, we could just check vtype of PseudoReadVL for PseudoReadVL's user and we even don't need the new status VLModified.

May 1 2022, 12:36 AM · Restricted Project, Restricted Project

Apr 29 2022

fakepaper56 committed rGc069e37019f0: [RISCV] Add DAGCombine to fold base operation and reduction. (authored by fakepaper56).
[RISCV] Add DAGCombine to fold base operation and reduction.
Apr 29 2022, 11:07 PM · Restricted Project, Restricted Project
fakepaper56 closed D122563: [RISCV] Add DAGCombine to fold base operation and reduction..
Apr 29 2022, 11:07 PM · Restricted Project, Restricted Project
fakepaper56 added a comment to D123581: [RISCV] Teach vsetvli insertion to handle PseudoReadVL..

Would it simplify things if the VLEFF pseudo instruction had the GPR output and the vector register output. And we expanded it PseudoReadVL after register allocation?

Apr 29 2022, 6:30 AM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D122563: [RISCV] Add DAGCombine to fold base operation and reduction..
Apr 29 2022, 1:02 AM · Restricted Project, Restricted Project

Apr 24 2022

fakepaper56 updated the diff for D122563: [RISCV] Add DAGCombine to fold base operation and reduction..

The update replaces specefic function only calling combineBinOpToReduce with combineBinOpToReduce and uses array input version setTargetDAGCombine.

Apr 24 2022, 3:54 AM · Restricted Project, Restricted Project

Apr 23 2022

fakepaper56 added a comment to D122563: [RISCV] Add DAGCombine to fold base operation and reduction..

Since we need to transform VECREDUCE to VP_REDUCE before legalization for Fraser's method, we need to deal with illegal type of VECREDUCE. If we don't have idea to deal with illegal type nodes of VECREDUCE, how about we just use my original combine?

Apr 23 2022, 2:41 AM · Restricted Project, Restricted Project

Apr 14 2022

fakepaper56 added a comment to D122563: [RISCV] Add DAGCombine to fold base operation and reduction..

-Do we currently mark VP_REDUCE nodes as Expand on targets that don't support it? I don't see anything in TargetLoweringBase::initActions, but maybe I missed it. I think we would need that fixed to know if we could do the combine so that we only do it on targets that support it.

VP_REDUCE nodes are marked as Custom. VP_REDUCE opcodes are elements of IntegerVPOps and FloatingPointVPOps whose elements would be marked as Custom.

Apr 14 2022, 2:57 AM · Restricted Project, Restricted Project

Apr 12 2022

fakepaper56 added a comment to D123581: [RISCV] Teach vsetvli insertion to handle PseudoReadVL..

Would it simplify things if the VLEFF pseudo instruction had the GPR output and the vector register output. And we expanded it PseudoReadVL after register allocation?

Apr 12 2022, 8:32 PM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D123581: [RISCV] Teach vsetvli insertion to handle PseudoReadVL..
Apr 12 2022, 6:50 PM · Restricted Project, Restricted Project
fakepaper56 requested review of D123581: [RISCV] Teach vsetvli insertion to handle PseudoReadVL..
Apr 12 2022, 2:55 AM · Restricted Project, Restricted Project

Mar 30 2022

fakepaper56 updated the diff for D122563: [RISCV] Add DAGCombine to fold base operation and reduction..

Fix the issue raised by reviewers.

Mar 30 2022, 10:28 PM · Restricted Project, Restricted Project
fakepaper56 added inline comments to D122563: [RISCV] Add DAGCombine to fold base operation and reduction..
Mar 30 2022, 7:27 PM · Restricted Project, Restricted Project