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Differential D126689

[IR] Enable opaque pointers by default
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Authored by nikic on May 31 2022, 4:01 AM.

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bollu
jdoerfert
aartbik
ftynse
clementval
aeubanks
dcaballe
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rG41d5033eb162: [IR] Enable opaque pointers by default
Summary

This enabled opaque pointers by default in LLVM. The effect of this is twofold:

  • If IR that contains neither explicit ptr nor %T* types is passed to tools, we will now use opaque pointer mode, unless -opaque-pointers=0 has been explicitly passed.
  • Users of LLVM as a library will now default to opaque pointers. It is possible to opt-out by calling setOpaquePointers(false) on LLVMContext.

A cmake option to toggle this default will not be provided. Frontends or other tools that want to keep using typed pointers temporarily should disabled opaque pointers via LLVMContext.

Diff Detail

Event Timeline

nikic created this revision.May 31 2022, 4:01 AM
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nikic requested review of this revision.May 31 2022, 4:01 AM
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lkail added a subscriber: lkail.May 31 2022, 4:21 AM
Harbormaster completed remote builds in B167016: Diff 433048.May 31 2022, 4:28 AM
uabelho added a subscriber: uabelho.May 31 2022, 5:36 AM
bmahjour added a subscriber: bmahjour.May 31 2022, 6:57 AM
nikic updated this revision to Diff 433334.Jun 1 2022, 2:53 AM

Update more tests.

Harbormaster completed remote builds in B167214: Diff 433334.Jun 1 2022, 3:20 AM
nikic updated this revision to Diff 433408.Jun 1 2022, 8:18 AM
nikic edited the summary of this revision. (Show Details)
nikic added a reviewer: Restricted Project.

Finish updating LLVM, Clang, Polly and MLIR tests.

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Harbormaster completed remote builds in B167272: Diff 433408.Jun 1 2022, 9:12 AM
aeubanks accepted this revision.Jun 1 2022, 11:18 AM
aeubanks added a subscriber: aeubanks.

\o/

We could split out the test changes with -opaque-pointers but I'm not sure how worth it that is given that we'll probably just fix forward any regressions, and rollbacks would probably require updating a couple tests added in the meantime.

This revision is now accepted and ready to land.Jun 1 2022, 11:18 AM
asbirlea added a subscriber: asbirlea.Jun 1 2022, 11:42 AM
This revision was landed with ongoing or failed builds.Jun 2 2022, 12:41 AM
Closed by commit rG41d5033eb162: [IR] Enable opaque pointers by default (authored by nikic). · Explain Why
This revision was automatically updated to reflect the committed changes.
nikic added a commit: rG41d5033eb162: [IR] Enable opaque pointers by default.
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goncharov added a subscriber: goncharov.Jun 2 2022, 5:38 AM
anna added a subscriber: anna.Jun 2 2022, 6:26 AM
uabelho added a comment.Jun 2 2022, 6:53 AM

Is anyone here ever using llvm-stress?
I noticed that with this patch, llvm-stress seems to start producing code that llc crashes on, and it crashes even if I run on older llc versions.
One example:

llc -o /dev/null stress.ll

crashes with

llc: ../lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5974: llvm::SDValue llvm::SelectionDAG::getNode(unsigned int, const llvm::SDLoc &, llvm::EVT, llvm::SDValue, llvm::SDValue, const llvm::SDNodeFlags): Assertion `VT.isInteger() && N2.getValueType().isInteger() && "Shifts only work on integers"' failed.

Or is the X86 backend just not up to date with opaque pointers yet?

stress.ll997 BDownload

nikic added a comment.Jun 2 2022, 7:32 AM

@uabelho Here's a slightly cleaned up test case that does not use opaque pointers:

target triple = "x86_64-unknown-linux-gnu"

define void @test(i1 %cond, <1 x i16>* %p) {
  br label %loop

loop:
  %v = load <1 x i16>, <1 x i16>* %p, align 2
  %ins = insertelement <4 x double> zeroinitializer, double 0.000000e+00, i32 0
  %cmp = fcmp uge <4 x double> %ins, zeroinitializer
  %ashr = ashr <1 x i16> %v, %v
  %shuf = shufflevector <4 x i1> %cmp, <4 x i1> zeroinitializer, <4 x i32> zeroinitializer
  br i1 %cond, label %loop, label %exit

exit:
  %use1 = add <4 x i1> %shuf, zeroinitializer
  %use2 = add <1 x i16> %ashr, zeroinitializer
  ret void
}

llvm-stress can probably generate certain code patterns when opaque pointers are enabled, which it does not produce when typed pointers are used. In this case at least, the used pointer type doesn't matter in the end.

nikic mentioned this in D126886: [DAGCombine] Handle promotion of shift with both operands the same.Jun 2 2022, 8:18 AM

I believe https://reviews.llvm.org/D126886 should fix the DAGCombiner issue.

aprantl added a subscriber: aprantl.Jun 2 2022, 9:29 AM

It looks like this patch has broken 168 tests in LLDB: https://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/44239/changes#41d5033eb162cb92b684855166cabfa3983b74c6
I'm going to dig a little deeper, but I might ask you to revert this until we can figure out a solution.

aprantl mentioned this in rG8eed95c83ecd: Adapt IRForTarget::RewriteObjCSelector() for D126689..Jun 2 2022, 11:43 AM
aprantl mentioned this in rGe7b929d75650: Adapt IRForTarget::RewriteObjCConstStrings() for D126689..Jun 2 2022, 1:07 PM
aprantl added a comment.Jun 2 2022, 2:37 PM

I was able to update LLDB https://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/44252/. We can leave this in.

uabelho added a comment.EditedJun 2 2022, 10:51 PM
In D126689#3553292, @nikic wrote:

@uabelho Here's a slightly cleaned up test case that does not use opaque pointers:

target triple = "x86_64-unknown-linux-gnu"

define void @test(i1 %cond, <1 x i16>* %p) {
  br label %loop

loop:
  %v = load <1 x i16>, <1 x i16>* %p, align 2
  %ins = insertelement <4 x double> zeroinitializer, double 0.000000e+00, i32 0
  %cmp = fcmp uge <4 x double> %ins, zeroinitializer
  %ashr = ashr <1 x i16> %v, %v
  %shuf = shufflevector <4 x i1> %cmp, <4 x i1> zeroinitializer, <4 x i32> zeroinitializer
  br i1 %cond, label %loop, label %exit

exit:
  %use1 = add <4 x i1> %shuf, zeroinitializer
  %use2 = add <1 x i16> %ashr, zeroinitializer
  ret void
}

llvm-stress can probably generate certain code patterns when opaque pointers are enabled, which it does not produce when typed pointers are used. In this case at least, the used pointer type doesn't matter in the end.

Yes llvm-stress must generate something unusual with opaque pointers because normally I very rarely see that it finds something, and after the switch done here I quickly got different crashes. The one I posted above was one example.
Next crash here: https://github.com/llvm/llvm-project/issues/55846
and another (very similar) here: https://github.com/llvm/llvm-project/issues/55848

nikic mentioned this in rGad742cf85da1: [DAGCombine] Handle promotion of shift with both operands the same.Jun 3 2022, 1:01 AM
uabelho added a comment.Oct 17 2023, 1:51 AM

Hi @nikic,

I know I'm very late to the party with this, but I just noticed that since opaque pointers got turned on by default, the following program does not yield an error anymore when read by opt or llc:

declare void @bar(i16)

define void @foo() {
entry:
  call void @bar(float 1.000000e+0)
  ret void
}

With typed pointers opt and llc would fail directly with

opt: test.ll:5:13: error: '@bar' defined with type 'void (i16)*' but expected 'void (float)*'
  call void @bar(float 1.000000e+00)
            ^

but now, since all pointers are just pointers, noone seems to bother about the mismatching parameter type.

The verifier doesn't complain either. Maybe it should be improved to explicitly check parameter types now that we won't get that for free via the function pointer type?

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nikic added a comment.Oct 17 2023, 2:00 AM

@uabelho The call is well-defined from an LLVM IR perspective, so the verifier cannot reject it, just as it can't reject calling convention or ABI attribute mismatch. In this specific case, the call is likely undefined behavior, but that is not generally the case just because there is a signature mismatch. When exactly this is UB is still something of an open question (and I believe currently effectively boils down to "does the signature match after lowering or not").

uabelho added a comment.Oct 17 2023, 2:35 AM

@nikic: Thanks, nothing to do there then even if I'm surprised.

I'm not sure but I *think* that llvm-reduce may have some problems with this. For my out of tree target I recently saw a case where llvm-reduced crashed with

llvm-reduce: ../tools/llvm-reduce/deltas/ReduceOperandsToArgs.cpp:64: void replaceFunctionCalls(llvm::Function *, llvm::Function *): Assertion `CI->getCalledFunction() == OldF' failed.

and when I looked at the reduced result so far, I saw a call where parameters didn't match the declaration. So I guess it may now reduce in ways that it unexpected for it and then crash.

nikic added a comment.Oct 17 2023, 2:40 AM
In D126689#4654124, @uabelho wrote:

@nikic: Thanks, nothing to do there then even if I'm surprised.

I'm not sure but I *think* that llvm-reduce may have some problems with this. For my out of tree target I recently saw a case where llvm-reduced crashed with

llvm-reduce: ../tools/llvm-reduce/deltas/ReduceOperandsToArgs.cpp:64: void replaceFunctionCalls(llvm::Function *, llvm::Function *): Assertion `CI->getCalledFunction() == OldF' failed.

and when I looked at the reduced result so far, I saw a call where parameters didn't match the declaration. So I guess it may now reduce in ways that it unexpected for it and then crash.

Can you please file an issue for the llvm-reduce bug? I just took a quick look at the code, and it indeed has a mismatch in checks between canReplaceFunction() and replaceFunctionCalls() -- the conditions in both need to be the same, but aren't.

uabelho added a comment.Oct 17 2023, 2:49 AM
In D126689#4654126, @nikic wrote:
In D126689#4654124, @uabelho wrote:

@nikic: Thanks, nothing to do there then even if I'm surprised.

I'm not sure but I *think* that llvm-reduce may have some problems with this. For my out of tree target I recently saw a case where llvm-reduced crashed with

llvm-reduce: ../tools/llvm-reduce/deltas/ReduceOperandsToArgs.cpp:64: void replaceFunctionCalls(llvm::Function *, llvm::Function *): Assertion `CI->getCalledFunction() == OldF' failed.

and when I looked at the reduced result so far, I saw a call where parameters didn't match the declaration. So I guess it may now reduce in ways that it unexpected for it and then crash.

Can you please file an issue for the llvm-reduce bug? I just took a quick look at the code, and it indeed has a mismatch in checks between canReplaceFunction() and replaceFunctionCalls() -- the conditions in both need to be the same, but aren't.

Yeah I can do that. Unfortunately I don't have any reproducer I can share though but if you think you know at least one problem in the vicinity maybe it's good enough.

In D126689#4654126, @nikic wrote:
In D126689#4654124, @uabelho wrote:

@nikic: Thanks, nothing to do there then even if I'm surprised.

I'm not sure but I *think* that llvm-reduce may have some problems with this. For my out of tree target I recently saw a case where llvm-reduced crashed with

llvm-reduce: ../tools/llvm-reduce/deltas/ReduceOperandsToArgs.cpp:64: void replaceFunctionCalls(llvm::Function *, llvm::Function *): Assertion `CI->getCalledFunction() == OldF' failed.

and when I looked at the reduced result so far, I saw a call where parameters didn't match the declaration. So I guess it may now reduce in ways that it unexpected for it and then crash.

Can you please file an issue for the llvm-reduce bug? I just took a quick look at the code, and it indeed has a mismatch in checks between canReplaceFunction() and replaceFunctionCalls() -- the conditions in both need to be the same, but aren't.

Sure, I wrote
https://github.com/llvm/llvm-project/issues/69312
which is pretty useless since I can't share any reproducer but anyway there it is.
Good if you saw something in the vicinity that indeed looks related.

Revision Contents

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clang/
test/
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llvm/
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CodeGen/
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AMDGPU/
GlobalISel/
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ARM/
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MIR/
Generic/
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cstmaterialization/
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Diff 433675

clang/test/CodeGen/thinlto_backend.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; RUN: opt -o %t2.o %s ; RUN: opt -o %t2.o %s
; RUN: %clang -target x86_64-unknown-linux-gnu -O2 -o %t3.o -x ir %t1.o -c -fthinlto-index=%t.thinlto.bc 2>&1 | FileCheck %s -check-prefix=CHECK-ERROR2 ; RUN: %clang -target x86_64-unknown-linux-gnu -O2 -o %t3.o -x ir %t1.o -c -fthinlto-index=%t.thinlto.bc 2>&1 | FileCheck %s -check-prefix=CHECK-ERROR2
; CHECK-ERROR2: Error loading imported file {{.*}}: Could not find module summary ; CHECK-ERROR2: Error loading imported file {{.*}}: Could not find module summary
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
declare void @f2() declare void @f2()
declare i8* @f3() declare ptr @f3()
define void @f1() { define void @f1() {
call void @f2() call void @f2()
; Make sure that the backend can handle undefined references. ; Make sure that the backend can handle undefined references.
; Do an indirect call so that the undefined ref shows up in the combined index. ; Do an indirect call so that the undefined ref shows up in the combined index.
call void bitcast (i8*()* @f3 to void()*)() call void @f3()
ret void ret void
} }

clang/test/CodeGenCUDA/amdgpu-asan.cu

// Create a sample address sanitizer bitcode library. // Create a sample address sanitizer bitcode library.
// RUN: %clang_cc1 -no-opaque-pointers -x ir -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm-bc \ // RUN: %clang_cc1 -x ir -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm-bc \
// RUN: -disable-llvm-passes -o %t.asanrtl.bc %S/Inputs/amdgpu-asanrtl.ll // RUN: -disable-llvm-passes -o %t.asanrtl.bc %S/Inputs/amdgpu-asanrtl.ll
// Check sanitizer runtime library functions survive // Check sanitizer runtime library functions survive
// optimizations without being removed or parameters altered. // optimizations without being removed or parameters altered.
// RUN: %clang_cc1 -no-opaque-pointers %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \ // RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -fsanitize=address \ // RUN: -fcuda-is-device -target-cpu gfx906 -fsanitize=address \
// RUN: -mlink-bitcode-file %t.asanrtl.bc -x hip \ // RUN: -mlink-bitcode-file %t.asanrtl.bc -x hip \
// RUN: | FileCheck -check-prefixes=ASAN %s // RUN: | FileCheck -check-prefixes=ASAN %s
// RUN: %clang_cc1 -no-opaque-pointers %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \ // RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -fsanitize=address \ // RUN: -fcuda-is-device -target-cpu gfx906 -fsanitize=address \
// RUN: -O3 -mlink-bitcode-file %t.asanrtl.bc -x hip \ // RUN: -O3 -mlink-bitcode-file %t.asanrtl.bc -x hip \
// RUN: | FileCheck -check-prefixes=ASAN %s // RUN: | FileCheck -check-prefixes=ASAN %s
// RUN: %clang_cc1 -no-opaque-pointers %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \ // RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -x hip \ // RUN: -fcuda-is-device -target-cpu gfx906 -x hip \
// RUN: | FileCheck %s // RUN: | FileCheck %s
// REQUIRES: amdgpu-registered-target // REQUIRES: amdgpu-registered-target
// ASAN-DAG: define weak void @__amdgpu_device_library_preserve_asan_functions() // ASAN-DAG: define weak void @__amdgpu_device_library_preserve_asan_functions()
// ASAN-DAG: @__amdgpu_device_library_preserve_asan_functions_ptr = weak addrspace(1) constant void ()* @__amdgpu_device_library_preserve_asan_functions // ASAN-DAG: @__amdgpu_device_library_preserve_asan_functions_ptr = weak addrspace(1) constant ptr @__amdgpu_device_library_preserve_asan_functions
// ASAN-DAG: @llvm.compiler.used = {{.*}}@__amdgpu_device_library_preserve_asan_functions_ptr // ASAN-DAG: @llvm.compiler.used = {{.*}}@__amdgpu_device_library_preserve_asan_functions_ptr
// ASAN-DAG: define weak void @__asan_report_load1(i64 %{{.*}}) // ASAN-DAG: define weak void @__asan_report_load1(i64 %{{.*}})
// CHECK-NOT: @__amdgpu_device_library_preserve_asan_functions // CHECK-NOT: @__amdgpu_device_library_preserve_asan_functions
// CHECK-NOT: @__asan_report_load1 // CHECK-NOT: @__asan_report_load1

clang/test/Driver/clang-offload-wrapper.c

Show All 19 Lines
// Check bitcode produced by the wrapper tool. // Check bitcode produced by the wrapper tool.
// //
// RUN: clang-offload-wrapper -add-omp-offload-notes -target=x86_64-pc-linux-gnu -o %t.wrapper.bc %t.tgt 2>&1 | FileCheck %s --check-prefix ELF-WARNING // RUN: clang-offload-wrapper -add-omp-offload-notes -target=x86_64-pc-linux-gnu -o %t.wrapper.bc %t.tgt 2>&1 | FileCheck %s --check-prefix ELF-WARNING
// RUN: llvm-dis %t.wrapper.bc -o - | FileCheck %s --check-prefix CHECK-IR // RUN: llvm-dis %t.wrapper.bc -o - | FileCheck %s --check-prefix CHECK-IR
// ELF-WARNING: is not an ELF image, so notes cannot be added to it. // ELF-WARNING: is not an ELF image, so notes cannot be added to it.
// CHECK-IR: target triple = "x86_64-pc-linux-gnu" // CHECK-IR: target triple = "x86_64-pc-linux-gnu"
// CHECK-IR-DAG: [[ENTTY:%.+]] = type { i8*, i8*, i{{32|64}}, i32, i32 } // CHECK-IR-DAG: [[ENTTY:%.+]] = type { ptr, ptr, i{{32|64}}, i32, i32 }
// CHECK-IR-DAG: [[IMAGETY:%.+]] = type { i8*, i8*, [[ENTTY]]*, [[ENTTY]]* } // CHECK-IR-DAG: [[IMAGETY:%.+]] = type { ptr, ptr, ptr, ptr }
// CHECK-IR-DAG: [[DESCTY:%.+]] = type { i32, [[IMAGETY]]*, [[ENTTY]]*, [[ENTTY]]* } // CHECK-IR-DAG: [[DESCTY:%.+]] = type { i32, ptr, ptr, ptr }
// CHECK-IR: [[ENTBEGIN:@.+]] = external hidden constant [[ENTTY]] // CHECK-IR: [[ENTBEGIN:@.+]] = external hidden constant [[ENTTY]]
// CHECK-IR: [[ENTEND:@.+]] = external hidden constant [[ENTTY]] // CHECK-IR: [[ENTEND:@.+]] = external hidden constant [[ENTTY]]
// CHECK-IR: [[DUMMY:@.+]] = hidden constant [0 x [[ENTTY]]] zeroinitializer, section "omp_offloading_entries" // CHECK-IR: [[DUMMY:@.+]] = hidden constant [0 x [[ENTTY]]] zeroinitializer, section "omp_offloading_entries"
// CHECK-IR: [[BIN:@.+]] = internal unnamed_addr constant [[BINTY:\[[0-9]+ x i8\]]] c"Content of device file{{.+}}" // CHECK-IR: [[BIN:@.+]] = internal unnamed_addr constant [[BINTY:\[[0-9]+ x i8\]]] c"Content of device file{{.+}}"
// CHECK-IR: [[IMAGES:@.+]] = internal unnamed_addr constant [1 x [[IMAGETY]]] [{{.+}} { i8* getelementptr inbounds ([[BINTY]], [[BINTY]]* [[BIN]], i64 0, i64 0), i8* getelementptr inbounds ([[BINTY]], [[BINTY]]* [[BIN]], i64 1, i64 0), [[ENTTY]]* [[ENTBEGIN]], [[ENTTY]]* [[ENTEND]] }] // CHECK-IR: [[IMAGES:@.+]] = internal unnamed_addr constant [1 x [[IMAGETY]]] [{{.+}} { ptr [[BIN]], ptr getelementptr inbounds ([[BINTY]], ptr [[BIN]], i64 1, i64 0), ptr [[ENTBEGIN]], ptr [[ENTEND]] }]
// CHECK-IR: [[DESC:@.+]] = internal constant [[DESCTY]] { i32 1, [[IMAGETY]]* getelementptr inbounds ([1 x [[IMAGETY]]], [1 x [[IMAGETY]]]* [[IMAGES]], i64 0, i64 0), [[ENTTY]]* [[ENTBEGIN]], [[ENTTY]]* [[ENTEND]] } // CHECK-IR: [[DESC:@.+]] = internal constant [[DESCTY]] { i32 1, ptr [[IMAGES]], ptr [[ENTBEGIN]], ptr [[ENTEND]] }
// CHECK-IR: @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 1, void ()* [[REGFN:@.+]], i8* null }] // CHECK-IR: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr [[REGFN:@.+]], ptr null }]
// CHECK-IR: @llvm.global_dtors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 1, void ()* [[UNREGFN:@.+]], i8* null }] // CHECK-IR: @llvm.global_dtors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr [[UNREGFN:@.+]], ptr null }]
// CHECK-IR: define internal void [[REGFN]]() // CHECK-IR: define internal void [[REGFN]]()
// CHECK-IR: call void @__tgt_register_lib([[DESCTY]]* [[DESC]]) // CHECK-IR: call void @__tgt_register_lib(ptr [[DESC]])
// CHECK-IR: ret void // CHECK-IR: ret void
// CHECK-IR: declare void @__tgt_register_lib([[DESCTY]]*) // CHECK-IR: declare void @__tgt_register_lib(ptr)
// CHECK-IR: define internal void [[UNREGFN]]() // CHECK-IR: define internal void [[UNREGFN]]()
// CHECK-IR: call void @__tgt_unregister_lib([[DESCTY]]* [[DESC]]) // CHECK-IR: call void @__tgt_unregister_lib(ptr [[DESC]])
// CHECK-IR: ret void // CHECK-IR: ret void
// CHECK-IR: declare void @__tgt_unregister_lib([[DESCTY]]*) // CHECK-IR: declare void @__tgt_unregister_lib(ptr)
// Check that clang-offload-wrapper adds LLVMOMPOFFLOAD notes // Check that clang-offload-wrapper adds LLVMOMPOFFLOAD notes
// into the ELF offload images: // into the ELF offload images:
// RUN: yaml2obj %S/Inputs/empty-elf-template.yaml -o %t.64le -DBITS=64 -DENCODING=LSB // RUN: yaml2obj %S/Inputs/empty-elf-template.yaml -o %t.64le -DBITS=64 -DENCODING=LSB
// RUN: clang-offload-wrapper -add-omp-offload-notes -target=x86_64-pc-linux-gnu -o %t.wrapper.elf64le.bc %t.64le // RUN: clang-offload-wrapper -add-omp-offload-notes -target=x86_64-pc-linux-gnu -o %t.wrapper.elf64le.bc %t.64le
// RUN: llvm-dis %t.wrapper.elf64le.bc -o - | FileCheck %s --check-prefix OMPNOTES // RUN: llvm-dis %t.wrapper.elf64le.bc -o - | FileCheck %s --check-prefix OMPNOTES
// RUN: yaml2obj %S/Inputs/empty-elf-template.yaml -o %t.64be -DBITS=64 -DENCODING=MSB // RUN: yaml2obj %S/Inputs/empty-elf-template.yaml -o %t.64be -DBITS=64 -DENCODING=MSB
// RUN: clang-offload-wrapper -add-omp-offload-notes -target=x86_64-pc-linux-gnu -o %t.wrapper.elf64be.bc %t.64be // RUN: clang-offload-wrapper -add-omp-offload-notes -target=x86_64-pc-linux-gnu -o %t.wrapper.elf64be.bc %t.64be
Show All 13 Lines

clang/test/Driver/linker-wrapper-image.c

// REQUIRES: x86-registered-target // REQUIRES: x86-registered-target
// REQUIRES: nvptx-registered-target // REQUIRES: nvptx-registered-target
// REQUIRES: amdgpu-registered-target // REQUIRES: amdgpu-registered-target
// RUN: clang-offload-packager -o %t.out --image=file=%S/Inputs/dummy-elf.o,kind=openmp,triple=nvptx64-nvidia-cuda,arch=sm_70 // RUN: clang-offload-packager -o %t.out --image=file=%S/Inputs/dummy-elf.o,kind=openmp,triple=nvptx64-nvidia-cuda,arch=sm_70
// RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -o %t.o \ // RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -o %t.o \
// RUN: -fembed-offload-object=%t.out // RUN: -fembed-offload-object=%t.out
// RUN: clang-linker-wrapper --print-wrapped-module --dry-run --host-triple x86_64-unknown-linux-gnu \ // RUN: clang-linker-wrapper --print-wrapped-module --dry-run --host-triple x86_64-unknown-linux-gnu \
// RUN: -linker-path /usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefix=OPENMP // RUN: -linker-path /usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefix=OPENMP
// OPENMP: @__start_omp_offloading_entries = external hidden constant %__tgt_offload_entry // OPENMP: @__start_omp_offloading_entries = external hidden constant %__tgt_offload_entry
// OPENMP-NEXT: @__stop_omp_offloading_entries = external hidden constant %__tgt_offload_entry // OPENMP-NEXT: @__stop_omp_offloading_entries = external hidden constant %__tgt_offload_entry
// OPENMP-NEXT: @__dummy.omp_offloading.entry = hidden constant [0 x %__tgt_offload_entry] zeroinitializer, section "omp_offloading_entries" // OPENMP-NEXT: @__dummy.omp_offloading.entry = hidden constant [0 x %__tgt_offload_entry] zeroinitializer, section "omp_offloading_entries"
// OPENMP-NEXT: @.omp_offloading.device_image = internal unnamed_addr constant [0 x i8] zeroinitializer // OPENMP-NEXT: @.omp_offloading.device_image = internal unnamed_addr constant [0 x i8] zeroinitializer
// OPENMP-NEXT: @.omp_offloading.device_images = internal unnamed_addr constant [1 x %__tgt_device_image] [%__tgt_device_image { i8* getelementptr inbounds ([0 x i8], [0 x i8]* @.omp_offloading.device_image, i64 0, i64 0), i8* getelementptr inbounds ([0 x i8], [0 x i8]* @.omp_offloading.device_image, i64 0, i64 0), %__tgt_offload_entry* @__start_omp_offloading_entries, %__tgt_offload_entry* @__stop_omp_offloading_entries }] // OPENMP-NEXT: @.omp_offloading.device_images = internal unnamed_addr constant [1 x %__tgt_device_image] [%__tgt_device_image { ptr @.omp_offloading.device_image, ptr @.omp_offloading.device_image, ptr @__start_omp_offloading_entries, ptr @__stop_omp_offloading_entries }]
// OPENMP-NEXT: @.omp_offloading.descriptor = internal constant %__tgt_bin_desc { i32 1, %__tgt_device_image* getelementptr inbounds ([1 x %__tgt_device_image], [1 x %__tgt_device_image]* @.omp_offloading.device_images, i64 0, i64 0), %__tgt_offload_entry* @__start_omp_offloading_entries, %__tgt_offload_entry* @__stop_omp_offloading_entries } // OPENMP-NEXT: @.omp_offloading.descriptor = internal constant %__tgt_bin_desc { i32 1, ptr @.omp_offloading.device_images, ptr @__start_omp_offloading_entries, ptr @__stop_omp_offloading_entries }
// OPENMP-NEXT: @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 1, void ()* @.omp_offloading.descriptor_reg, i8* null }] // OPENMP-NEXT: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @.omp_offloading.descriptor_reg, ptr null }]
// OPENMP-NEXT: @llvm.global_dtors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 1, void ()* @.omp_offloading.descriptor_unreg, i8* null }] // OPENMP-NEXT: @llvm.global_dtors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @.omp_offloading.descriptor_unreg, ptr null }]
// OPENMP: define internal void @.omp_offloading.descriptor_reg() section ".text.startup" { // OPENMP: define internal void @.omp_offloading.descriptor_reg() section ".text.startup" {
// OPENMP-NEXT: entry: // OPENMP-NEXT: entry:
// OPENMP-NEXT: call void @__tgt_register_lib(%__tgt_bin_desc* @.omp_offloading.descriptor) // OPENMP-NEXT: call void @__tgt_register_lib(ptr @.omp_offloading.descriptor)
// OPENMP-NEXT: ret void // OPENMP-NEXT: ret void
// OPENMP-NEXT: } // OPENMP-NEXT: }
// OPENMP: define internal void @.omp_offloading.descriptor_unreg() section ".text.startup" { // OPENMP: define internal void @.omp_offloading.descriptor_unreg() section ".text.startup" {
// OPENMP-NEXT: entry: // OPENMP-NEXT: entry:
// OPENMP-NEXT: call void @__tgt_unregister_lib(%__tgt_bin_desc* @.omp_offloading.descriptor) // OPENMP-NEXT: call void @__tgt_unregister_lib(ptr @.omp_offloading.descriptor)
// OPENMP-NEXT: ret void // OPENMP-NEXT: ret void
// OPENMP-NEXT: } // OPENMP-NEXT: }
// RUN: clang-offload-packager -o %t.out --image=file=%S/Inputs/dummy-elf.o,kind=cuda,triple=nvptx64-nvidia-cuda,arch=sm_70 // RUN: clang-offload-packager -o %t.out --image=file=%S/Inputs/dummy-elf.o,kind=cuda,triple=nvptx64-nvidia-cuda,arch=sm_70
// RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -o %t.o \ // RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -o %t.o \
// RUN: -fembed-offload-object=%t.out // RUN: -fembed-offload-object=%t.out
// RUN: clang-linker-wrapper --print-wrapped-module --dry-run --host-triple x86_64-unknown-linux-gnu \ // RUN: clang-linker-wrapper --print-wrapped-module --dry-run --host-triple x86_64-unknown-linux-gnu \
// RUN: -linker-path /usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefix=CUDA // RUN: -linker-path /usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefix=CUDA
// CUDA: @.fatbin_image = internal constant [0 x i8] zeroinitializer, section ".nv_fatbin" // CUDA: @.fatbin_image = internal constant [0 x i8] zeroinitializer, section ".nv_fatbin"
// CUDA-NEXT: @.fatbin_wrapper = internal constant %fatbin_wrapper { i32 1180844977, i32 1, i8* getelementptr inbounds ([0 x i8], [0 x i8]* @.fatbin_image, i32 0, i32 0), i8* null }, section ".nvFatBinSegment", align 8 // CUDA-NEXT: @.fatbin_wrapper = internal constant %fatbin_wrapper { i32 1180844977, i32 1, ptr @.fatbin_image, ptr null }, section ".nvFatBinSegment", align 8
// CUDA-NEXT: @__dummy.cuda_offloading.entry = hidden constant [0 x %__tgt_offload_entry] zeroinitializer, section "cuda_offloading_entries" // CUDA-NEXT: @__dummy.cuda_offloading.entry = hidden constant [0 x %__tgt_offload_entry] zeroinitializer, section "cuda_offloading_entries"
// CUDA-NEXT: @.cuda.binary_handle = internal global i8** null // CUDA-NEXT: @.cuda.binary_handle = internal global ptr null
// CUDA-NEXT: @__start_cuda_offloading_entries = external hidden constant [0 x %__tgt_offload_entry] // CUDA-NEXT: @__start_cuda_offloading_entries = external hidden constant [0 x %__tgt_offload_entry]
// CUDA-NEXT: @__stop_cuda_offloading_entries = external hidden constant [0 x %__tgt_offload_entry] // CUDA-NEXT: @__stop_cuda_offloading_entries = external hidden constant [0 x %__tgt_offload_entry]
// CUDA-NEXT: @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 1, void ()* @.cuda.fatbin_reg, i8* null }] // CUDA-NEXT: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @.cuda.fatbin_reg, ptr null }]
// CUDA: define internal void @.cuda.fatbin_reg() section ".text.startup" { // CUDA: define internal void @.cuda.fatbin_reg() section ".text.startup" {
// CUDA-NEXT: entry: // CUDA-NEXT: entry:
// CUDA-NEXT: %0 = call i8** @__cudaRegisterFatBinary(i8* bitcast (%fatbin_wrapper* @.fatbin_wrapper to i8*)) // CUDA-NEXT: %0 = call ptr @__cudaRegisterFatBinary(ptr @.fatbin_wrapper)
// CUDA-NEXT: store i8** %0, i8*** @.cuda.binary_handle, align 8 // CUDA-NEXT: store ptr %0, ptr @.cuda.binary_handle, align 8
// CUDA-NEXT: call void @.cuda.globals_reg(i8** %0) // CUDA-NEXT: call void @.cuda.globals_reg(ptr %0)
// CUDA-NEXT: call void @__cudaRegisterFatBinaryEnd(i8** %0) // CUDA-NEXT: call void @__cudaRegisterFatBinaryEnd(ptr %0)
// CUDA-NEXT: %1 = call i32 @atexit(void ()* @.cuda.fatbin_unreg) // CUDA-NEXT: %1 = call i32 @atexit(ptr @.cuda.fatbin_unreg)
// CUDA-NEXT: ret void // CUDA-NEXT: ret void
// CUDA-NEXT: } // CUDA-NEXT: }
// CUDA: define internal void @.cuda.fatbin_unreg() section ".text.startup" { // CUDA: define internal void @.cuda.fatbin_unreg() section ".text.startup" {
// CUDA-NEXT: entry: // CUDA-NEXT: entry:
// CUDA-NEXT: %0 = load i8**, i8*** @.cuda.binary_handle, align 8 // CUDA-NEXT: %0 = load ptr, ptr @.cuda.binary_handle, align 8
// CUDA-NEXT: call void @__cudaUnregisterFatBinary(i8** %0) // CUDA-NEXT: call void @__cudaUnregisterFatBinary(ptr %0)
// CUDA-NEXT: ret void // CUDA-NEXT: ret void
// CUDA-NEXT: } // CUDA-NEXT: }
// CUDA: define internal void @.cuda.globals_reg(i8** %0) section ".text.startup" { // CUDA: define internal void @.cuda.globals_reg(ptr %0) section ".text.startup" {
// CUDA-NEXT: entry: // CUDA-NEXT: entry:
// CUDA-NEXT: br i1 icmp ne ([0 x %__tgt_offload_entry]* @__start_cuda_offloading_entries, [0 x %__tgt_offload_entry]* @__stop_cuda_offloading_entries), label %while.entry, label %while.end // CUDA-NEXT: br i1 icmp ne (ptr @__start_cuda_offloading_entries, ptr @__stop_cuda_offloading_entries), label %while.entry, label %while.end
// CUDA: while.entry: // CUDA: while.entry:
// CUDA-NEXT: %entry1 = phi %__tgt_offload_entry* [ getelementptr inbounds ([0 x %__tgt_offload_entry], [0 x %__tgt_offload_entry]* @__start_cuda_offloading_entries, i64 0, i64 0), %entry ], [ %7, %if.end ] // CUDA-NEXT: %entry1 = phi ptr [ @__start_cuda_offloading_entries, %entry ], [ %7, %if.end ]
// CUDA-NEXT: %1 = getelementptr inbounds %__tgt_offload_entry, %__tgt_offload_entry* %entry1, i64 0, i32 0 // CUDA-NEXT: %1 = getelementptr inbounds %__tgt_offload_entry, ptr %entry1, i64 0, i32 0
// CUDA-NEXT: %addr = load i8*, i8** %1, align 8 // CUDA-NEXT: %addr = load ptr, ptr %1, align 8
// CUDA-NEXT: %2 = getelementptr inbounds %__tgt_offload_entry, %__tgt_offload_entry* %entry1, i64 0, i32 1 // CUDA-NEXT: %2 = getelementptr inbounds %__tgt_offload_entry, ptr %entry1, i64 0, i32 1
// CUDA-NEXT: %name = load i8*, i8** %2, align 8 // CUDA-NEXT: %name = load ptr, ptr %2, align 8
// CUDA-NEXT: %3 = getelementptr inbounds %__tgt_offload_entry, %__tgt_offload_entry* %entry1, i64 0, i32 2 // CUDA-NEXT: %3 = getelementptr inbounds %__tgt_offload_entry, ptr %entry1, i64 0, i32 2
// CUDA-NEXT: %size = load i64, i64* %3, align 4 // CUDA-NEXT: %size = load i64, ptr %3, align 4
// CUDA-NEXT: %4 = icmp eq i64 %size, 0 // CUDA-NEXT: %4 = icmp eq i64 %size, 0
// CUDA-NEXT: br i1 %4, label %if.then, label %if.else // CUDA-NEXT: br i1 %4, label %if.then, label %if.else
// CUDA: if.then: // CUDA: if.then:
// CUDA-NEXT: %5 = call i32 @__cudaRegisterFunction(i8** %0, i8* %addr, i8* %name, i8* %name, i32 -1, i8* null, i8* null, i8* null, i8* null, i32* null) // CUDA-NEXT: %5 = call i32 @__cudaRegisterFunction(ptr %0, ptr %addr, ptr %name, ptr %name, i32 -1, ptr null, ptr null, ptr null, ptr null, ptr null)
// CUDA-NEXT: br label %if.end // CUDA-NEXT: br label %if.end
// CUDA: if.else: // CUDA: if.else:
// CUDA-NEXT: %6 = call i32 @__cudaRegisterVar(i8** %0, i8* %addr, i8* %name, i8* %name, i32 0, i64 %size, i32 0, i32 0) // CUDA-NEXT: %6 = call i32 @__cudaRegisterVar(ptr %0, ptr %addr, ptr %name, ptr %name, i32 0, i64 %size, i32 0, i32 0)
// CUDA-NEXT: br label %if.end // CUDA-NEXT: br label %if.end
// CUDA: if.end: // CUDA: if.end:
// CUDA-NEXT: %7 = getelementptr inbounds %__tgt_offload_entry, %__tgt_offload_entry* %entry1, i64 1 // CUDA-NEXT: %7 = getelementptr inbounds %__tgt_offload_entry, ptr %entry1, i64 1
// CUDA-NEXT: %8 = icmp eq %__tgt_offload_entry* %7, getelementptr inbounds ([0 x %__tgt_offload_entry], [0 x %__tgt_offload_entry]* @__stop_cuda_offloading_entries, i64 0, i64 0) // CUDA-NEXT: %8 = icmp eq ptr %7, @__stop_cuda_offloading_entries
// CUDA-NEXT: br i1 %8, label %while.end, label %while.entry // CUDA-NEXT: br i1 %8, label %while.end, label %while.entry
// CUDA: while.end: // CUDA: while.end:
// CUDA-NEXT: ret void // CUDA-NEXT: ret void
// CUDA-NEXT: } // CUDA-NEXT: }

llvm/docs/OpaquePointers.rst

Show First 20 Lines • Show All 189 Lines • ▼ Show 20 Lines
Additionally, it will no longer be possible to call ``LLVMGetElementType()`` Additionally, it will no longer be possible to call ``LLVMGetElementType()``
on a pointer type. on a pointer type.
Transition State Transition State
================ ================
As of April 2022 both LLVM and Clang have complete support for opaque pointers, As of April 2022 both LLVM and Clang have complete support for opaque pointers,
and opaque pointers are enabled by default in Clang. and opaque pointers are enabled by default in LLVM and Clang.
For users of the clang driver interface, it is possible to temporarily restore For users of the clang driver interface, it is possible to temporarily restore
the old default using the ``-DCLANG_ENABLE_OPAQUE_POINTERS=OFF`` cmake option, the old default using the ``-DCLANG_ENABLE_OPAQUE_POINTERS=OFF`` cmake option,
or by passing ``-Xclang -no-opaque-pointers`` to a single clang invocation. or by passing ``-Xclang -no-opaque-pointers`` to a single clang invocation.
For users of the clang cc1 interface, ``-no-opaque-pointers`` can be passed. For users of the clang cc1 interface, ``-no-opaque-pointers`` can be passed.
Note that the ``CLANG_ENABLE_OPAQUE_POINTERS`` cmake option has no effect on Note that the ``CLANG_ENABLE_OPAQUE_POINTERS`` cmake option has no effect on
the cc1 interface. the cc1 interface.
Usage for LTO can be disabled by passing ``-Wl,-plugin-opt=no-opaque-pointers`` Usage for LTO can be disabled by passing ``-Wl,-plugin-opt=no-opaque-pointers``
to the clang driver. to the clang driver.
For users of LLVM as a library, opaque pointers can be disabled by calling
``setOpaquePointers(false)`` on the ``LLVMContext``.
For users of LLVM tools like opt, opaque pointers can be disabled by passing
``-opaque-pointers=0``.
The next steps for the opaque pointer migration are: The next steps for the opaque pointer migration are:
* Migrate Clang/LLVM tests to use opaque pointers. * Migrate Clang/LLVM tests to use opaque pointers.
* Enable opaque pointers by default in LLVM.
* Remove support for typed pointers after the LLVM 15 branch has been created. * Remove support for typed pointers after the LLVM 15 branch has been created.

llvm/lib/IR/LLVMContextImpl.cpp

Show All 30 Lines
#include "llvm/Support/TypeSize.h" #include "llvm/Support/TypeSize.h"
#include <cassert> #include <cassert>
#include <utility> #include <utility>
using namespace llvm; using namespace llvm;
static cl::opt<bool> static cl::opt<bool>
OpaquePointersCL("opaque-pointers", cl::desc("Use opaque pointers"), OpaquePointersCL("opaque-pointers", cl::desc("Use opaque pointers"),
cl::init(false)); cl::init(true));
LLVMContextImpl::LLVMContextImpl(LLVMContext &C) LLVMContextImpl::LLVMContextImpl(LLVMContext &C)
: DiagHandler(std::make_unique<DiagnosticHandler>()), : DiagHandler(std::make_unique<DiagnosticHandler>()),
VoidTy(C, Type::VoidTyID), LabelTy(C, Type::LabelTyID), VoidTy(C, Type::VoidTyID), LabelTy(C, Type::LabelTyID),
HalfTy(C, Type::HalfTyID), BFloatTy(C, Type::BFloatTyID), HalfTy(C, Type::HalfTyID), BFloatTy(C, Type::BFloatTyID),
FloatTy(C, Type::FloatTyID), DoubleTy(C, Type::DoubleTyID), FloatTy(C, Type::FloatTyID), DoubleTy(C, Type::DoubleTyID),
MetadataTy(C, Type::MetadataTyID), TokenTy(C, Type::TokenTyID), MetadataTy(C, Type::MetadataTyID), TokenTy(C, Type::TokenTyID),
X86_FP80Ty(C, Type::X86_FP80TyID), FP128Ty(C, Type::FP128TyID), X86_FP80Ty(C, Type::X86_FP80TyID), FP128Ty(C, Type::FP128TyID),
▲ Show 20 Lines • Show All 219 Lines • Show Last 20 Lines

llvm/test/Assembler/comment.ll

; RUN: llvm-as < %s | llvm-dis -show-annotations | FileCheck -check-prefix=ANNOT %s ; RUN: llvm-as < %s | llvm-dis -show-annotations | FileCheck -check-prefix=ANNOT %s
; RUN: llvm-as < %s | llvm-dis | FileCheck -check-prefix=BARE %s ; RUN: llvm-as < %s | llvm-dis | FileCheck -check-prefix=BARE %s
; RUN: verify-uselistorder %s ; RUN: verify-uselistorder %s
; The bare version of this file should not have any #uses lines. ; The bare version of this file should not have any #uses lines.
; BARE: @B = ; BARE: @B =
; BARE-NOT: #uses ; BARE-NOT: #uses
; BARE: } ; BARE: }
@B = external global i32 @B = external global i32
; ANNOT: @B = external global i32 ; [#uses=0 type=i32*] ; ANNOT: @B = external global i32 ; [#uses=0 type=ptr]
define <4 x i1> @foo(<4 x float> %a, <4 x float> %b) nounwind { define <4 x i1> @foo(<4 x float> %a, <4 x float> %b) nounwind {
entry: entry:
%cmp = fcmp olt <4 x float> %a, %b ; [#uses=1] %cmp = fcmp olt <4 x float> %a, %b ; [#uses=1]
ret <4 x i1> %cmp ret <4 x i1> %cmp
} }
; ANNOT: %cmp = fcmp olt <4 x float> %a, %b ; [#uses=1 type=<4 x i1>] ; ANNOT: %cmp = fcmp olt <4 x float> %a, %b ; [#uses=1 type=<4 x i1>]

llvm/test/Assembler/invalid-vecreduce.ll

; RUN: not opt -S < %s 2>&1 | FileCheck %s ; RUN: not opt -S < %s 2>&1 | FileCheck %s
; CHECK: Intrinsic has incorrect return type! ; CHECK: Intrinsic has incorrect return type!
; CHECK-NEXT: float (double, <2 x double>)* @llvm.vector.reduce.fadd.f32.f64.v2f64 ; CHECK-NEXT: ptr @llvm.vector.reduce.fadd.f32.f64.v2f64
define float @fadd_invalid_scalar_res(double %acc, <2 x double> %in) { define float @fadd_invalid_scalar_res(double %acc, <2 x double> %in) {
%res = call float @llvm.vector.reduce.fadd.f32.f64.v2f64(double %acc, <2 x double> %in) %res = call float @llvm.vector.reduce.fadd.f32.f64.v2f64(double %acc, <2 x double> %in)
ret float %res ret float %res
} }
; CHECK: Intrinsic has incorrect argument type! ; CHECK: Intrinsic has incorrect argument type!
; CHECK-NEXT: double (float, <2 x double>)* @llvm.vector.reduce.fadd.f64.f32.v2f64 ; CHECK-NEXT: ptr @llvm.vector.reduce.fadd.f64.f32.v2f64
define double @fadd_invalid_scalar_start(float %acc, <2 x double> %in) { define double @fadd_invalid_scalar_start(float %acc, <2 x double> %in) {
%res = call double @llvm.vector.reduce.fadd.f64.f32.v2f64(float %acc, <2 x double> %in) %res = call double @llvm.vector.reduce.fadd.f64.f32.v2f64(float %acc, <2 x double> %in)
ret double %res ret double %res
} }
; CHECK: Intrinsic has incorrect return type! ; CHECK: Intrinsic has incorrect return type!
; CHECK-NEXT: <2 x double> (double, <2 x double>)* @llvm.vector.reduce.fadd.v2f64.f64.v2f64 ; CHECK-NEXT: ptr @llvm.vector.reduce.fadd.v2f64.f64.v2f64
define <2 x double> @fadd_invalid_vector_res(double %acc, <2 x double> %in) { define <2 x double> @fadd_invalid_vector_res(double %acc, <2 x double> %in) {
%res = call <2 x double> @llvm.vector.reduce.fadd.v2f64.f64.v2f64(double %acc, <2 x double> %in) %res = call <2 x double> @llvm.vector.reduce.fadd.v2f64.f64.v2f64(double %acc, <2 x double> %in)
ret <2 x double> %res ret <2 x double> %res
} }
; CHECK: Intrinsic has incorrect argument type! ; CHECK: Intrinsic has incorrect argument type!
; CHECK-NEXT: double (<2 x double>, <2 x double>)* @llvm.vector.reduce.fadd.f64.v2f64.v2f64 ; CHECK-NEXT: ptr @llvm.vector.reduce.fadd.f64.v2f64.v2f64
define double @fadd_invalid_vector_start(<2 x double> %in, <2 x double> %acc) { define double @fadd_invalid_vector_start(<2 x double> %in, <2 x double> %acc) {
%res = call double @llvm.vector.reduce.fadd.f64.v2f64.v2f64(<2 x double> %acc, <2 x double> %in) %res = call double @llvm.vector.reduce.fadd.f64.v2f64.v2f64(<2 x double> %acc, <2 x double> %in)
ret double %res ret double %res
} }
declare float @llvm.vector.reduce.fadd.f32.f64.v2f64(double %acc, <2 x double> %in) declare float @llvm.vector.reduce.fadd.f32.f64.v2f64(double %acc, <2 x double> %in)
declare double @llvm.vector.reduce.fadd.f64.f32.v2f64(float %acc, <2 x double> %in) declare double @llvm.vector.reduce.fadd.f64.f32.v2f64(float %acc, <2 x double> %in)
declare double @llvm.vector.reduce.fadd.f64.v2f64.v2f64(<2 x double> %acc, <2 x double> %in) declare double @llvm.vector.reduce.fadd.f64.v2f64.v2f64(<2 x double> %acc, <2 x double> %in)
declare <2 x double> @llvm.vector.reduce.fadd.v2f64.f64.v2f64(double %acc, <2 x double> %in) declare <2 x double> @llvm.vector.reduce.fadd.v2f64.f64.v2f64(double %acc, <2 x double> %in)

llvm/test/Bindings/llvm-c/globals.ll

; RUN: llvm-as < %s | llvm-c-test --module-list-globals | FileCheck %s ; RUN: llvm-as < %s | llvm-c-test --module-list-globals | FileCheck %s
@foo = constant [7 x i8] c"foobar\00", align 1 @foo = constant [7 x i8] c"foobar\00", align 1
;CHECK: GlobalDefinition: foo [7 x i8]* ;CHECK: GlobalDefinition: foo ptr
@bar = common global i32 0, align 4 @bar = common global i32 0, align 4
;CHECK: GlobalDefinition: bar i32* ;CHECK: GlobalDefinition: bar ptr

llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir

Show All 14 Linesbody: |
; CHECK: [[DEF1:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 9 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
; CHECK: G_BRCOND [[DEF]](s1), %bb.2 ; CHECK: G_BRCOND [[DEF]](s1), %bb.2
; CHECK: G_BR %bb.1 ; CHECK: G_BR %bb.1
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: ; CHECK: successors:
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF1]](p0) :: (load (s32) from `i32* undef`, align 8) ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF1]](p0) :: (load (s32) from `ptr undef`, align 8)
; CHECK: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[C]], [[LOAD]] ; CHECK: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[C]], [[LOAD]]
; CHECK: [[MUL1:%[0-9]+]]:_(s32) = nsw G_MUL [[MUL]], [[C1]] ; CHECK: [[MUL1:%[0-9]+]]:_(s32) = nsw G_MUL [[MUL]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL1]], [[C2]](s64) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL1]], [[C2]](s64)
; CHECK: $w0 = COPY [[SHL]](s32) ; CHECK: $w0 = COPY [[SHL]](s32)
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
bb.1: bb.1:
liveins: $x0 liveins: $x0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s1) = G_IMPLICIT_DEF %1:_(s1) = G_IMPLICIT_DEF
%3:_(p0) = G_IMPLICIT_DEF %3:_(p0) = G_IMPLICIT_DEF
%4:_(s32) = G_CONSTANT i32 16 %4:_(s32) = G_CONSTANT i32 16
%6:_(s32) = G_CONSTANT i32 9 %6:_(s32) = G_CONSTANT i32 9
%8:_(s32) = G_CONSTANT i32 2 %8:_(s32) = G_CONSTANT i32 2
%11:_(s64) = G_CONSTANT i64 2 %11:_(s64) = G_CONSTANT i64 2
G_BRCOND %1(s1), %bb.2 G_BRCOND %1(s1), %bb.2
G_BR %bb.3 G_BR %bb.3
bb.2: bb.2:
successors: successors:
bb.3: bb.3:
%2:_(s32) = G_LOAD %3(p0) :: (load (s32) from `i32* undef`, align 8) %2:_(s32) = G_LOAD %3(p0) :: (load (s32) from `ptr undef`, align 8)
%5:_(s32) = nsw G_MUL %4, %2 %5:_(s32) = nsw G_MUL %4, %2
%7:_(s32) = nsw G_MUL %5, %6 %7:_(s32) = nsw G_MUL %5, %6
%9:_(s32) = nsw G_MUL %7, %8 %9:_(s32) = nsw G_MUL %7, %8
%10:_(s64) = G_SEXT %9(s32) %10:_(s64) = G_SEXT %9(s32)
%12:_(s64) = G_MUL %10, %11 %12:_(s64) = G_MUL %10, %11
%13:_(s32) = G_TRUNC %12(s64) %13:_(s32) = G_TRUNC %12(s64)
$w0 = COPY %13(s32) $w0 = COPY %13(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...

llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir

Show All 28 Linesbody: |
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2
; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]] ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]]
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: STRHHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `half* undef`) ; CHECK-NEXT: STRHHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `ptr undef`)
; CHECK-NEXT: B %bb.2 ; CHECK-NEXT: B %bb.2
bb.0: bb.0:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
%0:gpr(s1) = G_IMPLICIT_DEF %0:gpr(s1) = G_IMPLICIT_DEF
%4:gpr(p0) = G_IMPLICIT_DEF %4:gpr(p0) = G_IMPLICIT_DEF
%8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000 %8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
bb.1: bb.1:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
%6:gpr(s32) = G_IMPLICIT_DEF %6:gpr(s32) = G_IMPLICIT_DEF
%7:gpr(s32) = G_SELECT %0(s1), %6, %6 %7:gpr(s32) = G_SELECT %0(s1), %6, %6
%1:gpr(s16) = G_TRUNC %7(s32) %1:gpr(s16) = G_TRUNC %7(s32)
bb.2: bb.2:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
%3:gpr(s16) = G_PHI %1(s16), %bb.1, %5(s16), %bb.2 %3:gpr(s16) = G_PHI %1(s16), %bb.1, %5(s16), %bb.2
%5:fpr(s16) = G_FPTRUNC %8(s32) %5:fpr(s16) = G_FPTRUNC %8(s32)
G_STORE %3(s16), %4(p0) :: (store (s16) into `half* undef`) G_STORE %3(s16), %4(p0) :: (store (s16) into `ptr undef`)
G_BR %bb.2 G_BR %bb.2
... ...
--- ---
name: test_loop_phi_gpr_to_fpr name: test_loop_phi_gpr_to_fpr
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
Show All 21 Linesbody: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[CSELWr]] ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[CSELWr]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.1 ; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.1
; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]] ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]]
; CHECK-NEXT: STRHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `half* undef`) ; CHECK-NEXT: STRHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `ptr undef`)
; CHECK-NEXT: B %bb.2 ; CHECK-NEXT: B %bb.2
bb.0: bb.0:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
%0:gpr(s1) = G_IMPLICIT_DEF %0:gpr(s1) = G_IMPLICIT_DEF
%4:gpr(p0) = G_IMPLICIT_DEF %4:gpr(p0) = G_IMPLICIT_DEF
%8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000 %8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
bb.1: bb.1:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
%6:gpr(s32) = G_IMPLICIT_DEF %6:gpr(s32) = G_IMPLICIT_DEF
%7:gpr(s32) = G_SELECT %0(s1), %6, %6 %7:gpr(s32) = G_SELECT %0(s1), %6, %6
%1:gpr(s16) = G_TRUNC %7(s32) %1:gpr(s16) = G_TRUNC %7(s32)
bb.2: bb.2:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
%3:fpr(s16) = G_PHI %5(s16), %bb.2, %1(s16), %bb.1 %3:fpr(s16) = G_PHI %5(s16), %bb.2, %1(s16), %bb.1
%5:fpr(s16) = G_FPTRUNC %8(s32) %5:fpr(s16) = G_FPTRUNC %8(s32)
G_STORE %3(s16), %4(p0) :: (store (s16) into `half* undef`) G_STORE %3(s16), %4(p0) :: (store (s16) into `ptr undef`)
G_BR %bb.2 G_BR %bb.2
... ...
--- ---
name: multiple_phis name: multiple_phis
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
▲ Show 20 Lines • Show All 90 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir

Show All 9 Lines
# aarch64 load store optimizer should not throw an assertion if a renamable # aarch64 load store optimizer should not throw an assertion if a renamable
# register picked overlap with a renamable undef register. # register picked overlap with a renamable undef register.
# This test also checks that pairwise store STP is generated. # This test also checks that pairwise store STP is generated.
# CHECK-LABLE: test # CHECK-LABLE: test
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: liveins: $x0, $x17, $x18 # CHECK-NEXT: liveins: $x0, $x17, $x18
# CHECK: renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `<16 x i8>* undef`, align 64) # CHECK: renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `ptr undef`, align 64)
# CHECK-NEXT: renamable $q23_q24_q25 = LD3Threev16b undef renamable $x18 :: (load (s384) from `<16 x i8>* undef`, align 64) # CHECK-NEXT: renamable $q23_q24_q25 = LD3Threev16b undef renamable $x18 :: (load (s384) from `ptr undef`, align 64)
# CHECK-NEXT: $q16 = EXTv16i8 renamable $q23, renamable $q23, 8 # CHECK-NEXT: $q16 = EXTv16i8 renamable $q23, renamable $q23, 8
# CHECK-NEXT: renamable $q20 = EXTv16i8 renamable $q14, renamable $q14, 8 # CHECK-NEXT: renamable $q20 = EXTv16i8 renamable $q14, renamable $q14, 8
# CHECK-NEXT: STRQui killed renamable $q20, $sp, 4 :: (store (s128)) # CHECK-NEXT: STRQui killed renamable $q20, $sp, 4 :: (store (s128))
# CHECK-NEXT: renamable $d6 = ZIP2v8i8 renamable $d23, undef renamable $d16 # CHECK-NEXT: renamable $d6 = ZIP2v8i8 renamable $d23, undef renamable $d16
# CHECK-NEXT: STRDui killed renamable $d6, $sp, 11 :: (store (s64)) # CHECK-NEXT: STRDui killed renamable $d6, $sp, 11 :: (store (s64))
# CHECK-NEXT: renamable $q6 = EXTv16i8 renamable $q13, renamable $q13, 8 # CHECK-NEXT: renamable $q6 = EXTv16i8 renamable $q13, renamable $q13, 8
# CHECK-NEXT: STPQi killed renamable $q6, killed $q16, $sp, 6 :: (store (s128)) # CHECK-NEXT: STPQi killed renamable $q6, killed $q16, $sp, 6 :: (store (s128))
# CHECK-NEXT: RET undef $lr # CHECK-NEXT: RET undef $lr
Show All 27 Lines

llvm/test/CodeGen/AArch64/taildup-inst-dup-loc.mir

Show All 14 Linesbody: |
; CHECK: [[DEF2:%[0-9]+]]:gpr64 = IMPLICIT_DEF ; CHECK: [[DEF2:%[0-9]+]]:gpr64 = IMPLICIT_DEF
; CHECK: [[DEF3:%[0-9]+]]:gpr64common = IMPLICIT_DEF ; CHECK: [[DEF3:%[0-9]+]]:gpr64common = IMPLICIT_DEF
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0 ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
; CHECK: TBNZW [[DEF]], 0, %bb.1 ; CHECK: TBNZW [[DEF]], 0, %bb.1
; CHECK: B %bb.2 ; CHECK: B %bb.2
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.9(0x80000000) ; CHECK: successors: %bb.9(0x80000000)
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[DEF3]], 0 :: (load (s64) from `i64* undef`) ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[DEF3]], 0 :: (load (s64) from `ptr undef`)
; CHECK: B %bb.9 ; CHECK: B %bb.9
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: successors: %bb.3(0x40000000), %bb.4(0x40000000) ; CHECK: successors: %bb.3(0x40000000), %bb.4(0x40000000)
; CHECK: $wzr = SUBSWri [[DEF1]], 19, 0, implicit-def $nzcv ; CHECK: $wzr = SUBSWri [[DEF1]], 19, 0, implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK: TBNZW [[CSINCWr]], 0, %bb.3 ; CHECK: TBNZW [[CSINCWr]], 0, %bb.3
; CHECK: B %bb.4 ; CHECK: B %bb.4
; CHECK: bb.3: ; CHECK: bb.3:
Show All 34 Lines bb.1:
%13:gpr32 = MOVi32imm 1 %13:gpr32 = MOVi32imm 1
%14:fpr64 = FMOVD0 %14:fpr64 = FMOVD0
TBNZW %1, 0, %bb.2 TBNZW %1, 0, %bb.2
B %bb.3 B %bb.3
bb.2: bb.2:
successors: %bb.8(0x80000000) successors: %bb.8(0x80000000)
%8:gpr64 = LDRXui %9, 0 :: (load (s64) from `i64* undef`) %8:gpr64 = LDRXui %9, 0 :: (load (s64) from `ptr undef`)
B %bb.8 B %bb.8
bb.3: bb.3:
successors: %bb.4(0x40000000), %bb.5(0x40000000) successors: %bb.4(0x40000000), %bb.5(0x40000000)
$wzr = SUBSWri %2, 19, 0, implicit-def $nzcv $wzr = SUBSWri %2, 19, 0, implicit-def $nzcv
%15:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv %15:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
TBNZW %15, 0, %bb.4 TBNZW %15, 0, %bb.4
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir

Show First 20 Lines • Show All 297 Lines • ▼ Show 20 Lines bb.0:
; CHECK-LABEL: name: test_sdiv_srem_extra_use ; CHECK-LABEL: name: test_sdiv_srem_extra_use
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK: %src1:_(s32) = COPY $vgpr0 ; CHECK: %src1:_(s32) = COPY $vgpr0
; CHECK: %src2:_(s32) = COPY $vgpr1 ; CHECK: %src2:_(s32) = COPY $vgpr1
; CHECK: %ptr1:_(p1) = G_IMPLICIT_DEF ; CHECK: %ptr1:_(p1) = G_IMPLICIT_DEF
; CHECK: %ptr2:_(p1) = G_IMPLICIT_DEF ; CHECK: %ptr2:_(p1) = G_IMPLICIT_DEF
; CHECK: %ptr3:_(p1) = COPY $vgpr2_vgpr3 ; CHECK: %ptr3:_(p1) = COPY $vgpr2_vgpr3
; CHECK: %ptr4:_(p1) = COPY $vgpr4_vgpr5 ; CHECK: %ptr4:_(p1) = COPY $vgpr4_vgpr5
; CHECK: G_STORE %src1(s32), %ptr1(p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE %src1(s32), %ptr1(p1) :: (volatile store (s32) into `ptr addrspace(1) undef`, addrspace 1)
; CHECK: G_STORE %src2(s32), %ptr2(p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE %src2(s32), %ptr2(p1) :: (volatile store (s32) into `ptr addrspace(1) undef`, addrspace 1)
; CHECK: %div:_(s32), %rem:_ = G_SDIVREM %src1, %src2 ; CHECK: %div:_(s32), %rem:_ = G_SDIVREM %src1, %src2
; CHECK: G_STORE %div(s32), %ptr3(p1) :: (store (s32), addrspace 1) ; CHECK: G_STORE %div(s32), %ptr3(p1) :: (store (s32), addrspace 1)
; CHECK: G_STORE %rem(s32), %ptr4(p1) :: (store (s32), addrspace 1) ; CHECK: G_STORE %rem(s32), %ptr4(p1) :: (store (s32), addrspace 1)
%src1:_(s32) = COPY $vgpr0 %src1:_(s32) = COPY $vgpr0
%src2:_(s32) = COPY $vgpr1 %src2:_(s32) = COPY $vgpr1
%ptr1:_(p1) = G_IMPLICIT_DEF %ptr1:_(p1) = G_IMPLICIT_DEF
%ptr2:_(p1) = G_IMPLICIT_DEF %ptr2:_(p1) = G_IMPLICIT_DEF
%ptr3:_(p1) = COPY $vgpr2_vgpr3 %ptr3:_(p1) = COPY $vgpr2_vgpr3
▲ Show 20 Lines • Show All 208 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
--- ---
name: merge_flat_load_dword_2 name: merge_flat_load_dword_2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_load_dword_2 ; GCN-LABEL: name: merge_flat_load_dword_2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `i32* undef`, align 4) ; GCN-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `ptr undef`, align 4)
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX2_]].sub0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX2_]].sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX2_]].sub1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX2_]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%2:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %2:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_flat_load_dword_3 name: merge_flat_load_dword_3
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_load_dword_3 ; GCN-LABEL: name: merge_flat_load_dword_3
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX3_:%[0-9]+]]:vreg_96_align2 = FLAT_LOAD_DWORDX3 [[DEF]], 0, 1, implicit $exec, implicit $flat_scr :: (load (s96) from `i32* undef`, align 4) ; GCN-NEXT: [[FLAT_LOAD_DWORDX3_:%[0-9]+]]:vreg_96_align2 = FLAT_LOAD_DWORDX3 [[DEF]], 0, 1, implicit $exec, implicit $flat_scr :: (load (s96) from `ptr undef`, align 4)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[FLAT_LOAD_DWORDX3_]].sub0_sub1 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[FLAT_LOAD_DWORDX3_]].sub0_sub1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX3_]].sub2 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX3_]].sub2
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub1 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 1, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 1, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%2:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 1, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %2:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 1, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%3:vgpr_32 = FLAT_LOAD_DWORD %0, 8, 1, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %3:vgpr_32 = FLAT_LOAD_DWORD %0, 8, 1, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
S_NOP 0, implicit %1, implicit %2, implicit %3 S_NOP 0, implicit %1, implicit %2, implicit %3
... ...
--- ---
name: merge_flat_load_dword_4 name: merge_flat_load_dword_4
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_load_dword_4 ; GCN-LABEL: name: merge_flat_load_dword_4
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 0, 2, implicit $exec, implicit $flat_scr :: (load (s128) from `i32* undef`, align 4) ; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 0, 2, implicit $exec, implicit $flat_scr :: (load (s128) from `ptr undef`, align 4)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[FLAT_LOAD_DWORDX4_]].sub0_sub1_sub2 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[FLAT_LOAD_DWORDX4_]].sub0_sub1_sub2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub3
; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2
; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0 ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1 ; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 2, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 2, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%2:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 2, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %2:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 2, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%3:vgpr_32 = FLAT_LOAD_DWORD %0, 8, 2, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %3:vgpr_32 = FLAT_LOAD_DWORD %0, 8, 2, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%4:vgpr_32 = FLAT_LOAD_DWORD %0, 12, 2, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %4:vgpr_32 = FLAT_LOAD_DWORD %0, 12, 2, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
S_NOP 0, implicit %1, implicit %2, implicit %3, implicit %4 S_NOP 0, implicit %1, implicit %2, implicit %3, implicit %4
... ...
--- ---
name: merge_flat_load_dword_5 name: merge_flat_load_dword_5
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_load_dword_5 ; GCN-LABEL: name: merge_flat_load_dword_5
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 0, 3, implicit $exec, implicit $flat_scr :: (load (s128) from `i32* undef`, align 4) ; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 0, 3, implicit $exec, implicit $flat_scr :: (load (s128) from `ptr undef`, align 4)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[FLAT_LOAD_DWORDX4_]].sub0_sub1_sub2 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[FLAT_LOAD_DWORDX4_]].sub0_sub1_sub2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub3
; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2
; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0 ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1 ; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1
; GCN-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 16, 3, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`) ; GCN-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 16, 3, implicit $exec, implicit $flat_scr :: (load (s32) from `ptr undef`)
; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]], implicit [[FLAT_LOAD_DWORD]] ; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]], implicit [[FLAT_LOAD_DWORD]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 3, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 3, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%2:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 3, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %2:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 3, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%3:vgpr_32 = FLAT_LOAD_DWORD %0, 8, 3, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %3:vgpr_32 = FLAT_LOAD_DWORD %0, 8, 3, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%4:vgpr_32 = FLAT_LOAD_DWORD %0, 12, 3, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %4:vgpr_32 = FLAT_LOAD_DWORD %0, 12, 3, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%5:vgpr_32 = FLAT_LOAD_DWORD %0, 16, 3, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %5:vgpr_32 = FLAT_LOAD_DWORD %0, 16, 3, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
S_NOP 0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5 S_NOP 0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5
... ...
--- ---
name: merge_flat_load_dword_6 name: merge_flat_load_dword_6
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_load_dword_6 ; GCN-LABEL: name: merge_flat_load_dword_6
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from `i32* undef`, align 4) ; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from `ptr undef`, align 4)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[FLAT_LOAD_DWORDX4_]].sub0_sub1_sub2 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[FLAT_LOAD_DWORDX4_]].sub0_sub1_sub2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub3
; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2
; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0 ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1 ; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1
; GCN-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[DEF]], 16, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `i32* undef`, align 4) ; GCN-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[DEF]], 16, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `ptr undef`, align 4)
; GCN-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX2_]].sub0 ; GCN-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX2_]].sub0
; GCN-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX2_]].sub1 ; GCN-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX2_]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]], implicit [[COPY6]], implicit [[COPY7]] ; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]], implicit [[COPY6]], implicit [[COPY7]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%2:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %2:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%3:vgpr_32 = FLAT_LOAD_DWORD %0, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %3:vgpr_32 = FLAT_LOAD_DWORD %0, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%4:vgpr_32 = FLAT_LOAD_DWORD %0, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %4:vgpr_32 = FLAT_LOAD_DWORD %0, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%5:vgpr_32 = FLAT_LOAD_DWORD %0, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %5:vgpr_32 = FLAT_LOAD_DWORD %0, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%6:vgpr_32 = FLAT_LOAD_DWORD %0, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %6:vgpr_32 = FLAT_LOAD_DWORD %0, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
S_NOP 0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6 S_NOP 0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6
... ...
--- ---
name: merge_flat_load_dwordx2 name: merge_flat_load_dwordx2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_load_dwordx2 ; GCN-LABEL: name: merge_flat_load_dwordx2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from `i64* undef`, align 4) ; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from `ptr undef`, align 4)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[FLAT_LOAD_DWORDX4_]].sub0_sub1 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[FLAT_LOAD_DWORDX4_]].sub0_sub1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub2_sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub2_sub3
; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vreg_64_align2 = FLAT_LOAD_DWORDX2 %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `i64* undef`, align 4) %1:vreg_64_align2 = FLAT_LOAD_DWORDX2 %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `i64* undef`, align 4)
%2:vreg_64_align2 = FLAT_LOAD_DWORDX2 %0, 8, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `i64* undef`, align 4) %2:vreg_64_align2 = FLAT_LOAD_DWORDX2 %0, 8, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `i64* undef`, align 4)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_flat_load_dwordx3_with_dwordx1 name: merge_flat_load_dwordx3_with_dwordx1
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_load_dwordx3_with_dwordx1 ; GCN-LABEL: name: merge_flat_load_dwordx3_with_dwordx1
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 12, 0, implicit $exec, implicit $flat_scr :: (load (s128) from `i128* undef`, align 8) ; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 12, 0, implicit $exec, implicit $flat_scr :: (load (s128) from `ptr undef`, align 8)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[FLAT_LOAD_DWORDX4_]].sub0_sub1_sub2 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[FLAT_LOAD_DWORDX4_]].sub0_sub1_sub2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub3
; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vreg_96_align2 = FLAT_LOAD_DWORDX3 %0, 12, 0, implicit $exec, implicit $flat_scr :: (load (s96) from `i128* undef`, align 8) %1:vreg_96_align2 = FLAT_LOAD_DWORDX3 %0, 12, 0, implicit $exec, implicit $flat_scr :: (load (s96) from `i128* undef`, align 8)
%2:vgpr_32 = FLAT_LOAD_DWORD %0, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %2:vgpr_32 = FLAT_LOAD_DWORD %0, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_flat_load_dwordx1_with_dwordx2 name: merge_flat_load_dwordx1_with_dwordx2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_load_dwordx1_with_dwordx2 ; GCN-LABEL: name: merge_flat_load_dwordx1_with_dwordx2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX3_:%[0-9]+]]:vreg_96_align2 = FLAT_LOAD_DWORDX3 [[DEF]], 12, 0, implicit $exec, implicit $flat_scr :: (load (s96) from `i32* undef`, align 4) ; GCN-NEXT: [[FLAT_LOAD_DWORDX3_:%[0-9]+]]:vreg_96_align2 = FLAT_LOAD_DWORDX3 [[DEF]], 12, 0, implicit $exec, implicit $flat_scr :: (load (s96) from `ptr undef`, align 4)
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX3_]].sub0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX3_]].sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY killed [[FLAT_LOAD_DWORDX3_]].sub1_sub2 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY killed [[FLAT_LOAD_DWORDX3_]].sub1_sub2
; GCN-NEXT: S_NOP 0, implicit [[COPY1]], implicit [[COPY]] ; GCN-NEXT: S_NOP 0, implicit [[COPY1]], implicit [[COPY]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%2:vgpr_32 = FLAT_LOAD_DWORD %0, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %2:vgpr_32 = FLAT_LOAD_DWORD %0, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%1:vreg_64_align2 = FLAT_LOAD_DWORDX2 %0, 16, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `i64* undef`, align 8) %1:vreg_64_align2 = FLAT_LOAD_DWORDX2 %0, 16, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `i64* undef`, align 8)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: no_merge_flat_load_dword_agpr_with_vgpr name: no_merge_flat_load_dword_agpr_with_vgpr
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_flat_load_dword_agpr_with_vgpr ; GCN-LABEL: name: no_merge_flat_load_dword_agpr_with_vgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`) ; GCN-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `ptr undef`)
; GCN-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:agpr_32 = FLAT_LOAD_DWORD [[DEF]], 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`) ; GCN-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:agpr_32 = FLAT_LOAD_DWORD [[DEF]], 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `ptr undef`)
; GCN-NEXT: S_NOP 0, implicit [[FLAT_LOAD_DWORD]], implicit [[FLAT_LOAD_DWORD1]] ; GCN-NEXT: S_NOP 0, implicit [[FLAT_LOAD_DWORD]], implicit [[FLAT_LOAD_DWORD1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%2:agpr_32 = FLAT_LOAD_DWORD %0, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %2:agpr_32 = FLAT_LOAD_DWORD %0, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: no_merge_flat_load_dword_disjoint name: no_merge_flat_load_dword_disjoint
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_flat_load_dword_disjoint ; GCN-LABEL: name: no_merge_flat_load_dword_disjoint
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`) ; GCN-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `ptr undef`)
; GCN-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`) ; GCN-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `ptr undef`)
; GCN-NEXT: S_NOP 0, implicit [[FLAT_LOAD_DWORD]], implicit [[FLAT_LOAD_DWORD1]] ; GCN-NEXT: S_NOP 0, implicit [[FLAT_LOAD_DWORD]], implicit [[FLAT_LOAD_DWORD1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%2:vgpr_32 = FLAT_LOAD_DWORD %0, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %2:vgpr_32 = FLAT_LOAD_DWORD %0, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: no_merge_flat_load_dword_overlap name: no_merge_flat_load_dword_overlap
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_flat_load_dword_overlap ; GCN-LABEL: name: no_merge_flat_load_dword_overlap
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`) ; GCN-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `ptr undef`)
; GCN-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 3, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`) ; GCN-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 3, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `ptr undef`)
; GCN-NEXT: S_NOP 0, implicit [[FLAT_LOAD_DWORD]], implicit [[FLAT_LOAD_DWORD1]] ; GCN-NEXT: S_NOP 0, implicit [[FLAT_LOAD_DWORD]], implicit [[FLAT_LOAD_DWORD1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%2:vgpr_32 = FLAT_LOAD_DWORD %0, 3, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`) %2:vgpr_32 = FLAT_LOAD_DWORD %0, 3, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: no_merge_flat_load_dword_different_cpol name: no_merge_flat_load_dword_different_cpol
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_flat_load_dword_different_cpol ; GCN-LABEL: name: no_merge_flat_load_dword_different_cpol
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 0, 1, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`) ; GCN-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 0, 1, implicit $exec, implicit $flat_scr :: (load (s32) from `ptr undef`)
; GCN-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`) ; GCN-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `ptr undef`)
; GCN-NEXT: S_NOP 0, implicit [[FLAT_LOAD_DWORD]], implicit [[FLAT_LOAD_DWORD1]] ; GCN-NEXT: S_NOP 0, implicit [[FLAT_LOAD_DWORD]], implicit [[FLAT_LOAD_DWORD1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 1, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 1, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
%2:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4) %2:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef`, align 4)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_flat_store_dword_2 name: merge_flat_store_dword_2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_store_dword_2 ; GCN-LABEL: name: merge_flat_store_dword_2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0, killed [[DEF2]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0, killed [[DEF2]], %subreg.sub1
; GCN-NEXT: FLAT_STORE_DWORDX2 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into `i32* undef`, align 4) ; GCN-NEXT: FLAT_STORE_DWORDX2 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into `ptr undef`, align 4)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
FLAT_STORE_DWORD %0, killed %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD %0, killed %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
FLAT_STORE_DWORD killed %0, killed %2, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD killed %0, killed %2, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
... ...
--- ---
name: merge_flat_store_dword_3 name: merge_flat_store_dword_3
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_store_dword_3 ; GCN-LABEL: name: merge_flat_store_dword_3
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0, killed [[DEF2]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0, killed [[DEF2]], %subreg.sub1
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, killed [[DEF3]], %subreg.sub2 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, killed [[DEF3]], %subreg.sub2
; GCN-NEXT: FLAT_STORE_DWORDX3 [[DEF]], killed [[REG_SEQUENCE1]], 4, 1, implicit $exec, implicit $flat_scr :: (store (s96) into `i32* undef`, align 4) ; GCN-NEXT: FLAT_STORE_DWORDX3 [[DEF]], killed [[REG_SEQUENCE1]], 4, 1, implicit $exec, implicit $flat_scr :: (store (s96) into `ptr undef`, align 4)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
%3:vgpr_32 = IMPLICIT_DEF %3:vgpr_32 = IMPLICIT_DEF
FLAT_STORE_DWORD %0, killed %1, 4, 1, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD %0, killed %1, 4, 1, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
FLAT_STORE_DWORD %0, killed %2, 8, 1, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD %0, killed %2, 8, 1, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
FLAT_STORE_DWORD killed %0, killed %3, 12, 1, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD killed %0, killed %3, 12, 1, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
... ...
--- ---
name: merge_flat_store_dword_4 name: merge_flat_store_dword_4
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_store_dword_4 ; GCN-LABEL: name: merge_flat_store_dword_4
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF1]].sub1, %subreg.sub1, [[DEF1]].sub0, %subreg.sub0 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF1]].sub1, %subreg.sub1, [[DEF1]].sub0, %subreg.sub0
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[DEF1]].sub2, %subreg.sub2, killed [[REG_SEQUENCE]], %subreg.sub0_sub1 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[DEF1]].sub2, %subreg.sub2, killed [[REG_SEQUENCE]], %subreg.sub0_sub1
; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[DEF1]].sub3, %subreg.sub3, killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2 ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[DEF1]].sub3, %subreg.sub3, killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2
; GCN-NEXT: FLAT_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE2]], 4, 2, implicit $exec, implicit $flat_scr :: (store (s128) into `i32* undef`, align 4) ; GCN-NEXT: FLAT_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE2]], 4, 2, implicit $exec, implicit $flat_scr :: (store (s128) into `ptr undef`, align 4)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vreg_128 = IMPLICIT_DEF %1:vreg_128 = IMPLICIT_DEF
FLAT_STORE_DWORD %0, %1.sub1, 8, 2, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD %0, %1.sub1, 8, 2, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
FLAT_STORE_DWORD %0, %1.sub2, 12, 2, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD %0, %1.sub2, 12, 2, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
FLAT_STORE_DWORD %0, %1.sub3, 16, 2, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD %0, %1.sub3, 16, 2, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
FLAT_STORE_DWORD killed %0, %1.sub0, 4, 2, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD killed %0, %1.sub0, 4, 2, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
... ...
--- ---
name: merge_flat_store_dword_5 name: merge_flat_store_dword_5
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_store_dword_5 ; GCN-LABEL: name: merge_flat_store_dword_5
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:agpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:agpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:agpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF4:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF4:%[0-9]+]]:agpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF5:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF5:%[0-9]+]]:agpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_64_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub0, [[DEF2]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_64_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub0, [[DEF2]], %subreg.sub1
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:areg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, [[DEF3]], %subreg.sub2 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:areg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, [[DEF3]], %subreg.sub2
; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2, [[DEF4]], %subreg.sub3 ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2, [[DEF4]], %subreg.sub3
; GCN-NEXT: FLAT_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE2]], 4, 3, implicit $exec, implicit $flat_scr :: (store (s128) into `i32* undef`, align 4) ; GCN-NEXT: FLAT_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE2]], 4, 3, implicit $exec, implicit $flat_scr :: (store (s128) into `ptr undef`, align 4)
; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], [[DEF5]], 20, 3, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) ; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], [[DEF5]], 20, 3, implicit $exec, implicit $flat_scr :: (store (s32) into `ptr undef`)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:agpr_32 = IMPLICIT_DEF %1:agpr_32 = IMPLICIT_DEF
%2:agpr_32 = IMPLICIT_DEF %2:agpr_32 = IMPLICIT_DEF
%3:agpr_32 = IMPLICIT_DEF %3:agpr_32 = IMPLICIT_DEF
%4:agpr_32 = IMPLICIT_DEF %4:agpr_32 = IMPLICIT_DEF
%5:agpr_32 = IMPLICIT_DEF %5:agpr_32 = IMPLICIT_DEF
FLAT_STORE_DWORD %0, %1, 4, 3, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD %0, %1, 4, 3, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
FLAT_STORE_DWORD %0, %2, 8, 3, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 8) FLAT_STORE_DWORD %0, %2, 8, 3, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 8)
Show All 13 Lines bb.0.entry:
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub0, [[DEF2]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub0, [[DEF2]], %subreg.sub1
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, [[DEF3]], %subreg.sub2 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, [[DEF3]], %subreg.sub2
; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2, [[DEF4]], %subreg.sub3 ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2, [[DEF4]], %subreg.sub3
; GCN-NEXT: FLAT_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE2]], 4, 0, implicit $exec, implicit $flat_scr :: (store (s128) into `i32* undef`, align 8) ; GCN-NEXT: FLAT_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE2]], 4, 0, implicit $exec, implicit $flat_scr :: (store (s128) into `ptr undef`, align 8)
; GCN-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF5]], %subreg.sub0, [[DEF6]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF5]], %subreg.sub0, [[DEF6]], %subreg.sub1
; GCN-NEXT: FLAT_STORE_DWORDX2 [[DEF]], killed [[REG_SEQUENCE3]], 20, 0, implicit $exec, implicit $flat_scr :: (store (s64) into `i32* undef`, align 4) ; GCN-NEXT: FLAT_STORE_DWORDX2 [[DEF]], killed [[REG_SEQUENCE3]], 20, 0, implicit $exec, implicit $flat_scr :: (store (s64) into `ptr undef`, align 4)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
%3:vgpr_32 = IMPLICIT_DEF %3:vgpr_32 = IMPLICIT_DEF
%4:vgpr_32 = IMPLICIT_DEF %4:vgpr_32 = IMPLICIT_DEF
%5:vgpr_32 = IMPLICIT_DEF %5:vgpr_32 = IMPLICIT_DEF
%6:vgpr_32 = IMPLICIT_DEF %6:vgpr_32 = IMPLICIT_DEF
FLAT_STORE_DWORD %0, %1, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 8) FLAT_STORE_DWORD %0, %1, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 8)
Show All 9 Lines
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_store_dwordx2 ; GCN-LABEL: name: merge_flat_store_dwordx2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0_sub1, killed [[DEF2]], %subreg.sub2_sub3 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0_sub1, killed [[DEF2]], %subreg.sub2_sub3
; GCN-NEXT: FLAT_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE]], 4, 0, implicit $exec, implicit $flat_scr :: (store (s128) into `i64* undef`, align 4) ; GCN-NEXT: FLAT_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE]], 4, 0, implicit $exec, implicit $flat_scr :: (store (s128) into `ptr undef`, align 4)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vreg_64_align2 = IMPLICIT_DEF %1:vreg_64_align2 = IMPLICIT_DEF
%2:vreg_64_align2 = IMPLICIT_DEF %2:vreg_64_align2 = IMPLICIT_DEF
FLAT_STORE_DWORDX2 %0, killed %1, 4, 0, implicit $exec, implicit $flat_scr :: (store (s64) into `i64* undef`, align 4) FLAT_STORE_DWORDX2 %0, killed %1, 4, 0, implicit $exec, implicit $flat_scr :: (store (s64) into `i64* undef`, align 4)
FLAT_STORE_DWORDX2 %0, killed %2, 12, 0, implicit $exec, implicit $flat_scr :: (store (s64) into `i64* undef`, align 4) FLAT_STORE_DWORDX2 %0, killed %2, 12, 0, implicit $exec, implicit $flat_scr :: (store (s64) into `i64* undef`, align 4)
... ...
--- ---
name: merge_flat_store_dwordx3_with_dwordx1 name: merge_flat_store_dwordx3_with_dwordx1
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_store_dwordx3_with_dwordx1 ; GCN-LABEL: name: merge_flat_store_dwordx3_with_dwordx1
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_96_align2 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_96_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0_sub1_sub2, killed [[DEF2]], %subreg.sub3 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0_sub1_sub2, killed [[DEF2]], %subreg.sub3
; GCN-NEXT: FLAT_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE]], 4, 0, implicit $exec, implicit $flat_scr :: (store (s128) into `i64* undef`) ; GCN-NEXT: FLAT_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE]], 4, 0, implicit $exec, implicit $flat_scr :: (store (s128) into `ptr undef`)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vreg_96_align2 = IMPLICIT_DEF %1:vreg_96_align2 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
FLAT_STORE_DWORDX3 %0, killed %1, 4, 0, implicit $exec, implicit $flat_scr :: (store (s96) into `i64* undef`, align 16) FLAT_STORE_DWORDX3 %0, killed %1, 4, 0, implicit $exec, implicit $flat_scr :: (store (s96) into `i64* undef`, align 16)
FLAT_STORE_DWORD %0, killed %2, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD %0, killed %2, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
... ...
--- ---
name: no_merge_flat_store_dword_agpr_with_vgpr name: no_merge_flat_store_dword_agpr_with_vgpr
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_flat_store_dword_agpr_with_vgpr ; GCN-LABEL: name: no_merge_flat_store_dword_agpr_with_vgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:agpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) ; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `ptr undef`)
; GCN-NEXT: FLAT_STORE_DWORD killed [[DEF]], killed [[DEF2]], 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) ; GCN-NEXT: FLAT_STORE_DWORD killed [[DEF]], killed [[DEF2]], 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `ptr undef`)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:agpr_32 = IMPLICIT_DEF %1:agpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
FLAT_STORE_DWORD %0, killed %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD %0, killed %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
FLAT_STORE_DWORD killed %0, killed %2, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD killed %0, killed %2, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
... ...
--- ---
name: no_merge_flat_store_dword_disjoint name: no_merge_flat_store_dword_disjoint
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_flat_store_dword_disjoint ; GCN-LABEL: name: no_merge_flat_store_dword_disjoint
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) ; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `ptr undef`)
; GCN-NEXT: FLAT_STORE_DWORD killed [[DEF]], killed [[DEF2]], 6, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) ; GCN-NEXT: FLAT_STORE_DWORD killed [[DEF]], killed [[DEF2]], 6, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `ptr undef`)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
FLAT_STORE_DWORD %0, killed %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD %0, killed %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
FLAT_STORE_DWORD killed %0, killed %2, 6, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD killed %0, killed %2, 6, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
... ...
--- ---
name: no_merge_flat_store_dword_overlap name: no_merge_flat_store_dword_overlap
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_flat_store_dword_overlap ; GCN-LABEL: name: no_merge_flat_store_dword_overlap
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) ; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `ptr undef`)
; GCN-NEXT: FLAT_STORE_DWORD killed [[DEF]], killed [[DEF2]], 2, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 2) ; GCN-NEXT: FLAT_STORE_DWORD killed [[DEF]], killed [[DEF2]], 2, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `ptr undef`, align 2)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
FLAT_STORE_DWORD %0, killed %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD %0, killed %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
FLAT_STORE_DWORD killed %0, killed %2, 2, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 2) FLAT_STORE_DWORD killed %0, killed %2, 2, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 2)
... ...
--- ---
name: no_merge_flat_store_dword_different_cpol name: no_merge_flat_store_dword_different_cpol
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_flat_store_dword_different_cpol ; GCN-LABEL: name: no_merge_flat_store_dword_different_cpol
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 1, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) ; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 1, implicit $exec, implicit $flat_scr :: (store (s32) into `ptr undef`)
; GCN-NEXT: FLAT_STORE_DWORD killed [[DEF]], killed [[DEF2]], 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) ; GCN-NEXT: FLAT_STORE_DWORD killed [[DEF]], killed [[DEF2]], 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `ptr undef`)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
FLAT_STORE_DWORD %0, killed %1, 0, 1, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD %0, killed %1, 0, 1, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
FLAT_STORE_DWORD killed %0, killed %2, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD killed %0, killed %2, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
... ...
--- ---
name: no_merge_flat_store_dword_different_vaddr name: no_merge_flat_store_dword_different_vaddr
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_flat_store_dword_different_vaddr ; GCN-LABEL: name: no_merge_flat_store_dword_different_vaddr
; GCN: [[DEF:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: FLAT_STORE_DWORD [[DEF]].sub0_sub1, killed [[DEF1]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) ; GCN-NEXT: FLAT_STORE_DWORD [[DEF]].sub0_sub1, killed [[DEF1]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `ptr undef`)
; GCN-NEXT: FLAT_STORE_DWORD [[DEF]].sub2_sub3, killed [[DEF2]], 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) ; GCN-NEXT: FLAT_STORE_DWORD [[DEF]].sub2_sub3, killed [[DEF2]], 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `ptr undef`)
%0:vreg_128_align2 = IMPLICIT_DEF %0:vreg_128_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
FLAT_STORE_DWORD %0.sub0_sub1, killed %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD %0.sub0_sub1, killed %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
FLAT_STORE_DWORD %0.sub2_sub3, killed %2, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4) FLAT_STORE_DWORD %0.sub2_sub3, killed %2, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`, align 4)
... ...

llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
--- ---
name: merge_flat_global_load_dword_2 name: merge_flat_global_load_dword_2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_global_load_dword_2 ; GCN-LABEL: name: merge_flat_global_load_dword_2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `float* undef` + 4, align 4) ; GCN-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `ptr undef` + 4, align 4)
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX2_]].sub0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX2_]].sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX2_]].sub1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX2_]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `float* undef` + 4, basealign 4) %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `float* undef` + 4, basealign 4)
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, basealign 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, basealign 4, addrspace 1)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_global_flat_load_dword_2 name: merge_global_flat_load_dword_2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_flat_load_dword_2 ; GCN-LABEL: name: merge_global_flat_load_dword_2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `float addrspace(1)* undef`) ; GCN-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `ptr addrspace(1) undef`)
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX2_]].sub0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX2_]].sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX2_]].sub1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX2_]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `float addrspace(1)* undef`, basealign 8, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `float addrspace(1)* undef`, basealign 8, addrspace 1)
%2:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef` + 4, basealign 8) %2:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef` + 4, basealign 8)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_global_flat_load_dword_3 name: merge_global_flat_load_dword_3
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_flat_load_dword_3 ; GCN-LABEL: name: merge_global_flat_load_dword_3
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX3_:%[0-9]+]]:vreg_96_align2 = FLAT_LOAD_DWORDX3 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from `float* undef`, align 16) ; GCN-NEXT: [[FLAT_LOAD_DWORDX3_:%[0-9]+]]:vreg_96_align2 = FLAT_LOAD_DWORDX3 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from `ptr undef`, align 16)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[FLAT_LOAD_DWORDX3_]].sub0_sub1 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[FLAT_LOAD_DWORDX3_]].sub0_sub1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX3_]].sub2 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX3_]].sub2
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub0 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub0
; GCN-NEXT: S_NOP 0, implicit [[COPY2]], implicit [[COPY3]] ; GCN-NEXT: S_NOP 0, implicit [[COPY2]], implicit [[COPY3]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 4, basealign 8, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 4, basealign 8, addrspace 1)
%2:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `float* undef`, basealign 16) %2:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `float* undef`, basealign 16)
%3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, basealign 8, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, basealign 8, addrspace 1)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_global_flat_load_dword_4 name: merge_global_flat_load_dword_4
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_flat_load_dword_4 ; GCN-LABEL: name: merge_global_flat_load_dword_4
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 4, 0, implicit $exec, implicit $flat_scr :: (load (s128) from `i32 addrspace(1)* undef` + 4, align 4, basealign 8) ; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 4, 0, implicit $exec, implicit $flat_scr :: (load (s128) from `ptr addrspace(1) undef` + 4, align 4, basealign 8)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[FLAT_LOAD_DWORDX4_]].sub0_sub1_sub2 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[FLAT_LOAD_DWORDX4_]].sub0_sub1_sub2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub3
; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2
; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0 ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1 ; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 4, basealign 8, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 4, basealign 8, addrspace 1)
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, basealign 8, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, basealign 8, addrspace 1)
%3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 12, basealign 8, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 12, basealign 8, addrspace 1)
%4:vgpr_32 = FLAT_LOAD_DWORD %0, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `float* undef` + 16) %4:vgpr_32 = FLAT_LOAD_DWORD %0, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `float* undef` + 16)
S_NOP 0, implicit %1, implicit %2, implicit %3, implicit %4 S_NOP 0, implicit %1, implicit %2, implicit %3, implicit %4
... ...
--- ---
name: merge_flat_global_load_dwordx2 name: merge_flat_global_load_dwordx2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_global_load_dwordx2 ; GCN-LABEL: name: merge_flat_global_load_dwordx2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from `double* undef`, align 8) ; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from `ptr undef`, align 8)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[FLAT_LOAD_DWORDX4_]].sub0_sub1 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[FLAT_LOAD_DWORDX4_]].sub0_sub1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub2_sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub2_sub3
; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vreg_64_align2 = FLAT_LOAD_DWORDX2 %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `double* undef`) %1:vreg_64_align2 = FLAT_LOAD_DWORDX2 %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `double* undef`)
%2:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 %0, 8, 0, implicit $exec :: (load (s64) from `i64 addrspace(1)* undef`, addrspace 1) %2:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 %0, 8, 0, implicit $exec :: (load (s64) from `i64 addrspace(1)* undef`, addrspace 1)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_flat_global_load_dwordx3 name: merge_flat_global_load_dwordx3
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_global_load_dwordx3 ; GCN-LABEL: name: merge_flat_global_load_dwordx3
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from `float* undef`, align 4) ; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from `ptr undef`, align 4)
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX4_]].sub0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX4_]].sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_96_align2 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub1_sub2_sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_96_align2 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub1_sub2_sub3
; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `float* undef`) %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `float* undef`)
%2:vreg_96_align2 = GLOBAL_LOAD_DWORDX3 %0, 4, 0, implicit $exec :: (load (s96) from `<3 x i32> addrspace(1)* undef`, addrspace 1) %2:vreg_96_align2 = GLOBAL_LOAD_DWORDX3 %0, 4, 0, implicit $exec :: (load (s96) from `<3 x i32> addrspace(1)* undef`, addrspace 1)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_global_flat_load_dwordx3 name: merge_global_flat_load_dwordx3
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_flat_load_dwordx3 ; GCN-LABEL: name: merge_global_flat_load_dwordx3
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from `i32 addrspace(1)* undef`, align 4) ; GCN-NEXT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = FLAT_LOAD_DWORDX4 [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from `ptr addrspace(1) undef`, align 4)
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX4_]].sub0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX4_]].sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_96_align2 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub1_sub2_sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_96_align2 = COPY killed [[FLAT_LOAD_DWORDX4_]].sub1_sub2_sub3
; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1)
%2:vreg_96_align2 = FLAT_LOAD_DWORDX3 %0, 4, 0, implicit $exec, implicit $flat_scr :: (load (s96) from `<3 x i32>* undef`) %2:vreg_96_align2 = FLAT_LOAD_DWORDX3 %0, 4, 0, implicit $exec, implicit $flat_scr :: (load (s96) from `<3 x i32>* undef`)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: no_merge_flat_global_load_dword_saddr name: no_merge_flat_global_load_dword_saddr
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_flat_global_load_dword_saddr ; GCN-LABEL: name: no_merge_flat_global_load_dword_saddr
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `float* undef`) ; GCN-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `ptr undef`)
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[DEF1]], [[DEF]].sub0, 4, 0, implicit $exec :: (load (s64) from `i32 addrspace(1)* undef` + 4, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[DEF1]], [[DEF]].sub0, 4, 0, implicit $exec :: (load (s64) from `ptr addrspace(1) undef` + 4, align 4, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1
; GCN-NEXT: S_NOP 0, implicit [[FLAT_LOAD_DWORD]], implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[FLAT_LOAD_DWORD]], implicit [[COPY]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:sreg_64_xexec = IMPLICIT_DEF %1:sreg_64_xexec = IMPLICIT_DEF
%2:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `float* undef`, basealign 4) %2:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `float* undef`, basealign 4)
%3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, %0.sub0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 4, basealign 4, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, %0.sub0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 4, basealign 4, addrspace 1)
%4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, %0.sub0, 8, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, basealign 4, addrspace 1) %4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, %0.sub0, 8, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, basealign 4, addrspace 1)
S_NOP 0, implicit %2, implicit %3, implicit %4 S_NOP 0, implicit %2, implicit %3, implicit %4
... ...
--- ---
name: no_merge_global_saddr_flat_load_dword name: no_merge_global_saddr_flat_load_dword
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_saddr_flat_load_dword ; GCN-LABEL: name: no_merge_global_saddr_flat_load_dword
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF1]], [[DEF]].sub0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF1]], [[DEF]].sub0, 0, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[DEF]], 4, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `i32* undef` + 4, align 4) ; GCN-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[DEF]], 4, 0, implicit $exec, implicit $flat_scr :: (load (s64) from `ptr undef` + 4, align 4)
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX2_]].sub0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[FLAT_LOAD_DWORDX2_]].sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX2_]].sub1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[FLAT_LOAD_DWORDX2_]].sub1
; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD_SADDR]], implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD_SADDR]], implicit [[COPY]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:sreg_64_xexec = IMPLICIT_DEF %1:sreg_64_xexec = IMPLICIT_DEF
%2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, %0.sub0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, %0.sub0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1)
%3:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef` + 4) %3:vgpr_32 = FLAT_LOAD_DWORD %0, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef` + 4)
%4:vgpr_32 = FLAT_LOAD_DWORD %0, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef` + 8) %4:vgpr_32 = FLAT_LOAD_DWORD %0, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `i32* undef` + 8)
S_NOP 0, implicit %2, implicit %3, implicit %4 S_NOP 0, implicit %2, implicit %3, implicit %4
... ...
--- ---
name: merge_flat_global_store_dword_2 name: merge_flat_global_store_dword_2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_global_store_dword_2 ; GCN-LABEL: name: merge_flat_global_store_dword_2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0, killed [[DEF2]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0, killed [[DEF2]], %subreg.sub1
; GCN-NEXT: FLAT_STORE_DWORDX2 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into `i32* undef`, align 4) ; GCN-NEXT: FLAT_STORE_DWORDX2 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into `ptr undef`, align 4)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
FLAT_STORE_DWORD %0, killed %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) FLAT_STORE_DWORD %0, killed %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`)
GLOBAL_STORE_DWORD killed %0, killed %2, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD killed %0, killed %2, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
... ...
--- ---
name: merge_global_flat_store_dword_2 name: merge_global_flat_store_dword_2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_flat_store_dword_2 ; GCN-LABEL: name: merge_global_flat_store_dword_2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0, killed [[DEF2]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0, killed [[DEF2]], %subreg.sub1
; GCN-NEXT: FLAT_STORE_DWORDX2 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into `i32 addrspace(1)* undef`, align 4) ; GCN-NEXT: FLAT_STORE_DWORDX2 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into `ptr addrspace(1) undef`, align 4)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD %0, killed %1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %0, killed %1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
FLAT_STORE_DWORD %0, killed %2, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) FLAT_STORE_DWORD %0, killed %2, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`)
... ...
--- ---
name: merge_flat_global_store_dwordx2 name: merge_flat_global_store_dwordx2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_global_store_dwordx2 ; GCN-LABEL: name: merge_flat_global_store_dwordx2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub0, [[DEF2]], %subreg.sub1_sub2 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub0, [[DEF2]], %subreg.sub1_sub2
; GCN-NEXT: FLAT_STORE_DWORDX3 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into `i32* undef`, align 4) ; GCN-NEXT: FLAT_STORE_DWORDX3 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into `ptr undef`, align 4)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vreg_64_align2 = IMPLICIT_DEF %2:vreg_64_align2 = IMPLICIT_DEF
FLAT_STORE_DWORD %0, %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) FLAT_STORE_DWORD %0, %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`)
GLOBAL_STORE_DWORDX2 %0, %2, 4, 0, implicit $exec :: (store (s64) into `i64 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %0, %2, 4, 0, implicit $exec :: (store (s64) into `i64 addrspace(1)* undef`, addrspace 1)
... ...
--- ---
name: merge_flat_global_store_dwordx3 name: merge_flat_global_store_dwordx3
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_flat_global_store_dwordx3 ; GCN-LABEL: name: merge_flat_global_store_dwordx3
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vreg_96_align2 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vreg_96_align2 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub0, [[DEF2]], %subreg.sub1_sub2_sub3 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub0, [[DEF2]], %subreg.sub1_sub2_sub3
; GCN-NEXT: FLAT_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into `i32* undef`, align 4) ; GCN-NEXT: FLAT_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into `ptr undef`, align 4)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vreg_96_align2 = IMPLICIT_DEF %2:vreg_96_align2 = IMPLICIT_DEF
FLAT_STORE_DWORD %0, %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) FLAT_STORE_DWORD %0, %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`)
GLOBAL_STORE_DWORDX3 %0, %2, 4, 0, implicit $exec :: (store (s96) into `<3 x i32> addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX3 %0, %2, 4, 0, implicit $exec :: (store (s96) into `<3 x i32> addrspace(1)* undef`, addrspace 1)
... ...
--- ---
name: merge_global_flat_store_dwordx2 name: merge_global_flat_store_dwordx2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_flat_store_dwordx2 ; GCN-LABEL: name: merge_global_flat_store_dwordx2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub2, [[DEF2]], %subreg.sub0_sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub2, [[DEF2]], %subreg.sub0_sub1
; GCN-NEXT: FLAT_STORE_DWORDX3 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into `i64* undef`, align 8) ; GCN-NEXT: FLAT_STORE_DWORDX3 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into `ptr undef`, align 8)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vreg_64_align2 = IMPLICIT_DEF %2:vreg_64_align2 = IMPLICIT_DEF
GLOBAL_STORE_DWORD %0, %1, 8, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %0, %1, 8, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
FLAT_STORE_DWORDX2 %0, %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into `i64* undef`) FLAT_STORE_DWORDX2 %0, %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into `i64* undef`)
... ...
--- ---
name: merge_global_flat_store_dwordx3 name: merge_global_flat_store_dwordx3
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_flat_store_dwordx3 ; GCN-LABEL: name: merge_global_flat_store_dwordx3
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vreg_96_align2 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vreg_96_align2 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub3, [[DEF2]], %subreg.sub0_sub1_sub2 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub3, [[DEF2]], %subreg.sub0_sub1_sub2
; GCN-NEXT: FLAT_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into `<3 x i32>* undef`) ; GCN-NEXT: FLAT_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into `ptr undef`)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vreg_96_align2 = IMPLICIT_DEF %2:vreg_96_align2 = IMPLICIT_DEF
GLOBAL_STORE_DWORD %0, %1, 12, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %0, %1, 12, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
FLAT_STORE_DWORDX3 %0, %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into `<3 x i32>* undef`) FLAT_STORE_DWORDX3 %0, %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into `<3 x i32>* undef`)
... ...
--- ---
name: no_merge_flat_global_store_dword_saddr name: no_merge_flat_global_store_dword_saddr
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_flat_global_store_dword_saddr ; GCN-LABEL: name: no_merge_flat_global_store_dword_saddr
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], [[DEF2]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) ; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], [[DEF2]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `ptr undef`)
; GCN-NEXT: GLOBAL_STORE_DWORD_SADDR [[DEF]].sub0, [[DEF3]], [[DEF1]], 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD_SADDR [[DEF]].sub0, [[DEF3]], [[DEF1]], 4, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:sreg_64_xexec = IMPLICIT_DEF %1:sreg_64_xexec = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
%3:vgpr_32 = IMPLICIT_DEF %3:vgpr_32 = IMPLICIT_DEF
FLAT_STORE_DWORD %0, %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) FLAT_STORE_DWORD %0, %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`)
GLOBAL_STORE_DWORD_SADDR %0.sub0, %3, %1, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD_SADDR %0.sub0, %3, %1, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
... ...
--- ---
name: no_merge_global_saddr_flat_store_dword name: no_merge_global_saddr_flat_store_dword
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_saddr_flat_store_dword ; GCN-LABEL: name: no_merge_global_saddr_flat_store_dword
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: GLOBAL_STORE_DWORD_SADDR [[DEF]].sub0, [[DEF2]], [[DEF1]], 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD_SADDR [[DEF]].sub0, [[DEF2]], [[DEF1]], 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], [[DEF3]], 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) ; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], [[DEF3]], 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `ptr undef`)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:sreg_64_xexec = IMPLICIT_DEF %1:sreg_64_xexec = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
%3:vgpr_32 = IMPLICIT_DEF %3:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD_SADDR %0.sub0, %2, %1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD_SADDR %0.sub0, %2, %1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
FLAT_STORE_DWORD %0, %3, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`) FLAT_STORE_DWORD %0, %3, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into `i32* undef`)
... ...

llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
--- ---
name: merge_global_load_dword_2 name: merge_global_load_dword_2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dword_2 ; GCN-LABEL: name: merge_global_load_dword_2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 [[DEF]], 0, 0, implicit $exec :: (load (s64) from `float addrspace(1)* undef` + 4, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 [[DEF]], 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(1) undef` + 4, align 4, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX2_]].sub1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX2_]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `float addrspace(1)* undef` + 4, basealign 4, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `float addrspace(1)* undef` + 4, basealign 4, addrspace 1)
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, basealign 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, basealign 4, addrspace 1)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_global_load_dword_3 name: merge_global_load_dword_3
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dword_3 ; GCN-LABEL: name: merge_global_load_dword_3
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX3_:%[0-9]+]]:vreg_96_align2 = GLOBAL_LOAD_DWORDX3 [[DEF]], 0, 1, implicit $exec :: (load (s96) from `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX3_:%[0-9]+]]:vreg_96_align2 = GLOBAL_LOAD_DWORDX3 [[DEF]], 0, 1, implicit $exec :: (load (s96) from `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[GLOBAL_LOAD_DWORDX3_]].sub0_sub1 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[GLOBAL_LOAD_DWORDX3_]].sub0_sub1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX3_]].sub2 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX3_]].sub2
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub1 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %1, implicit %2, implicit %3 S_NOP 0, implicit %1, implicit %2, implicit %3
... ...
--- ---
name: merge_global_load_dword_4 name: merge_global_load_dword_4
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dword_4 ; GCN-LABEL: name: merge_global_load_dword_4
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[DEF]], 0, 2, implicit $exec :: (load (s128) from `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[DEF]], 0, 2, implicit $exec :: (load (s128) from `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0_sub1_sub2 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0_sub1_sub2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX4_]].sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX4_]].sub3
; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2
; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0 ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1 ; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%4:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %4:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %1, implicit %2, implicit %3, implicit %4 S_NOP 0, implicit %1, implicit %2, implicit %3, implicit %4
... ...
--- ---
name: merge_global_load_dword_5 name: merge_global_load_dword_5
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dword_5 ; GCN-LABEL: name: merge_global_load_dword_5
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[DEF]], 0, 3, implicit $exec :: (load (s128) from `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[DEF]], 0, 3, implicit $exec :: (load (s128) from `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0_sub1_sub2 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0_sub1_sub2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX4_]].sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX4_]].sub3
; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2
; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0 ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1 ; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1
; GCN-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 16, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 16, 3, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]], implicit [[GLOBAL_LOAD_DWORD]] ; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]], implicit [[GLOBAL_LOAD_DWORD]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%4:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %4:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%5:vgpr_32 = GLOBAL_LOAD_DWORD %0, 16, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %5:vgpr_32 = GLOBAL_LOAD_DWORD %0, 16, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5 S_NOP 0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5
... ...
--- ---
name: merge_global_load_dword_6 name: merge_global_load_dword_6
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dword_6 ; GCN-LABEL: name: merge_global_load_dword_6
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[DEF]], 0, 0, implicit $exec :: (load (s128) from `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[DEF]], 0, 0, implicit $exec :: (load (s128) from `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0_sub1_sub2 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0_sub1_sub2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX4_]].sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX4_]].sub3
; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2
; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0 ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1 ; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 [[DEF]], 16, 0, implicit $exec :: (load (s64) from `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 [[DEF]], 16, 0, implicit $exec :: (load (s64) from `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub0 ; GCN-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub0
; GCN-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX2_]].sub1 ; GCN-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX2_]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]], implicit [[COPY6]], implicit [[COPY7]] ; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]], implicit [[COPY6]], implicit [[COPY7]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%4:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %4:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%5:vgpr_32 = GLOBAL_LOAD_DWORD %0, 16, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %5:vgpr_32 = GLOBAL_LOAD_DWORD %0, 16, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%6:vgpr_32 = GLOBAL_LOAD_DWORD %0, 20, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %6:vgpr_32 = GLOBAL_LOAD_DWORD %0, 20, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6 S_NOP 0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6
... ...
--- ---
name: merge_global_load_dwordx2 name: merge_global_load_dwordx2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dwordx2 ; GCN-LABEL: name: merge_global_load_dwordx2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[DEF]], 0, 0, implicit $exec :: (load (s128) from `i64 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[DEF]], 0, 0, implicit $exec :: (load (s128) from `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0_sub1 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0_sub1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY killed [[GLOBAL_LOAD_DWORDX4_]].sub2_sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY killed [[GLOBAL_LOAD_DWORDX4_]].sub2_sub3
; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 %0, 0, 0, implicit $exec :: (load (s64) from `i64 addrspace(1)* undef`, align 4, addrspace 1) %1:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 %0, 0, 0, implicit $exec :: (load (s64) from `i64 addrspace(1)* undef`, align 4, addrspace 1)
%2:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 %0, 8, 0, implicit $exec :: (load (s64) from `i64 addrspace(1)* undef`, align 4, addrspace 1) %2:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 %0, 8, 0, implicit $exec :: (load (s64) from `i64 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_global_load_dwordx3_with_dwordx1 name: merge_global_load_dwordx3_with_dwordx1
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dwordx3_with_dwordx1 ; GCN-LABEL: name: merge_global_load_dwordx3_with_dwordx1
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[DEF]], 12, 0, implicit $exec :: (load (s128) from `i128 addrspace(1)* undef`, align 8, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[DEF]], 12, 0, implicit $exec :: (load (s128) from `ptr addrspace(1) undef`, align 8, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0_sub1_sub2 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0_sub1_sub2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX4_]].sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX4_]].sub3
; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vreg_96_align2 = GLOBAL_LOAD_DWORDX3 %0, 12, 0, implicit $exec :: (load (s96) from `i128 addrspace(1)* undef`, align 8, addrspace 1) %1:vreg_96_align2 = GLOBAL_LOAD_DWORDX3 %0, 12, 0, implicit $exec :: (load (s96) from `i128 addrspace(1)* undef`, align 8, addrspace 1)
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 24, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 24, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_global_load_dwordx1_with_dwordx2 name: merge_global_load_dwordx1_with_dwordx2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dwordx1_with_dwordx2 ; GCN-LABEL: name: merge_global_load_dwordx1_with_dwordx2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX3_:%[0-9]+]]:vreg_96_align2 = GLOBAL_LOAD_DWORDX3 [[DEF]], 12, 0, implicit $exec :: (load (s96) from `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX3_:%[0-9]+]]:vreg_96_align2 = GLOBAL_LOAD_DWORDX3 [[DEF]], 12, 0, implicit $exec :: (load (s96) from `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX3_]].sub0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX3_]].sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY killed [[GLOBAL_LOAD_DWORDX3_]].sub1_sub2 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY killed [[GLOBAL_LOAD_DWORDX3_]].sub1_sub2
; GCN-NEXT: S_NOP 0, implicit [[COPY1]], implicit [[COPY]] ; GCN-NEXT: S_NOP 0, implicit [[COPY1]], implicit [[COPY]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%1:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 %0, 16, 0, implicit $exec :: (load (s64) from `i64 addrspace(1)* undef`, align 8, addrspace 1) %1:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 %0, 16, 0, implicit $exec :: (load (s64) from `i64 addrspace(1)* undef`, align 8, addrspace 1)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: no_merge_global_load_dword_agpr_with_vgpr name: no_merge_global_load_dword_agpr_with_vgpr
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_load_dword_agpr_with_vgpr ; GCN-LABEL: name: no_merge_global_load_dword_agpr_with_vgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 0, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:agpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:agpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 4, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD]], implicit [[GLOBAL_LOAD_DWORD1]] ; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD]], implicit [[GLOBAL_LOAD_DWORD1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%2:agpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:agpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: no_merge_global_load_dword_disjoint name: no_merge_global_load_dword_disjoint
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_load_dword_disjoint ; GCN-LABEL: name: no_merge_global_load_dword_disjoint
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 0, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 8, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 8, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD]], implicit [[GLOBAL_LOAD_DWORD1]] ; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD]], implicit [[GLOBAL_LOAD_DWORD1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: no_merge_global_load_dword_overlap name: no_merge_global_load_dword_overlap
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_load_dword_overlap ; GCN-LABEL: name: no_merge_global_load_dword_overlap
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 0, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 3, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 3, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD]], implicit [[GLOBAL_LOAD_DWORD1]] ; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD]], implicit [[GLOBAL_LOAD_DWORD1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 3, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 3, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: no_merge_global_load_dword_different_cpol name: no_merge_global_load_dword_different_cpol
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_load_dword_different_cpol ; GCN-LABEL: name: no_merge_global_load_dword_different_cpol
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 0, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 0, 1, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 4, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD]], implicit [[GLOBAL_LOAD_DWORD1]] ; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD]], implicit [[GLOBAL_LOAD_DWORD1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_global_load_dword_saddr_2 name: merge_global_load_dword_saddr_2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dword_saddr_2 ; GCN-LABEL: name: merge_global_load_dword_saddr_2
; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[DEF]], [[DEF1]], 0, 0, implicit $exec :: (load (s64) from `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[DEF]], [[DEF1]], 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]]
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %2, implicit %3 S_NOP 0, implicit %2, implicit %3
... ...
--- ---
name: merge_global_load_dword_saddr_3 name: merge_global_load_dword_saddr_3
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dword_saddr_3 ; GCN-LABEL: name: merge_global_load_dword_saddr_3
; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX3_SADDR:%[0-9]+]]:vreg_96_align2 = GLOBAL_LOAD_DWORDX3_SADDR [[DEF]], [[DEF1]], 0, 1, implicit $exec :: (load (s96) from `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX3_SADDR:%[0-9]+]]:vreg_96_align2 = GLOBAL_LOAD_DWORDX3_SADDR [[DEF]], [[DEF1]], 0, 1, implicit $exec :: (load (s96) from `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[GLOBAL_LOAD_DWORDX3_SADDR]].sub0_sub1 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[GLOBAL_LOAD_DWORDX3_SADDR]].sub0_sub1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX3_SADDR]].sub2 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX3_SADDR]].sub2
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub1 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY1]]
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 0, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 0, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 4, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 4, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 8, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 8, 1, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %2, implicit %3, implicit %4 S_NOP 0, implicit %2, implicit %3, implicit %4
... ...
--- ---
name: merge_global_load_dword_saddr_4 name: merge_global_load_dword_saddr_4
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dword_saddr_4 ; GCN-LABEL: name: merge_global_load_dword_saddr_4
; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_SADDR:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4_SADDR [[DEF]], [[DEF1]], 0, 2, implicit $exec :: (load (s128) from `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_SADDR:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4_SADDR [[DEF]], [[DEF1]], 0, 2, implicit $exec :: (load (s128) from `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[GLOBAL_LOAD_DWORDX4_SADDR]].sub0_sub1_sub2 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[GLOBAL_LOAD_DWORDX4_SADDR]].sub0_sub1_sub2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX4_SADDR]].sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX4_SADDR]].sub3
; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2
; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0 ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1 ; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]]
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 0, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 0, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 4, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 4, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 8, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 8, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%5:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 12, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %5:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 12, 2, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %2, implicit %3, implicit %4, implicit %5 S_NOP 0, implicit %2, implicit %3, implicit %4, implicit %5
... ...
--- ---
name: merge_global_load_dword_saddr_6 name: merge_global_load_dword_saddr_6
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dword_saddr_6 ; GCN-LABEL: name: merge_global_load_dword_saddr_6
; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_SADDR:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4_SADDR [[DEF]], [[DEF1]], 4, 3, implicit $exec :: (load (s128) from `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_SADDR:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4_SADDR [[DEF]], [[DEF1]], 4, 3, implicit $exec :: (load (s128) from `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[GLOBAL_LOAD_DWORDX4_SADDR]].sub0_sub1_sub2 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY [[GLOBAL_LOAD_DWORDX4_SADDR]].sub0_sub1_sub2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX4_SADDR]].sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX4_SADDR]].sub3
; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]].sub0_sub1
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub2
; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0 ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1 ; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]].sub1
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[DEF]], [[DEF1]], 20, 3, implicit $exec :: (load (s64) from `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[DEF]], [[DEF1]], 20, 3, implicit $exec :: (load (s64) from `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0 ; GCN-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0
; GCN-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1 ; GCN-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1
; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]], implicit [[COPY6]], implicit [[COPY7]] ; GCN-NEXT: S_NOP 0, implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY3]], implicit [[COPY1]], implicit [[COPY6]], implicit [[COPY7]]
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 4, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 4, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 8, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 8, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 12, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 12, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%5:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 16, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %5:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 16, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%6:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 20, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %6:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 20, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%7:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 24, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %7:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1, 24, 3, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7 S_NOP 0, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7
... ...
--- ---
name: merge_global_load_dwordx2_saddr name: merge_global_load_dwordx2_saddr
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dwordx2_saddr ; GCN-LABEL: name: merge_global_load_dwordx2_saddr
; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_SADDR:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4_SADDR [[DEF]], [[DEF1]], 0, 0, implicit $exec :: (load (s128) from `i64 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_SADDR:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4_SADDR [[DEF]], [[DEF1]], 0, 0, implicit $exec :: (load (s128) from `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[GLOBAL_LOAD_DWORDX4_SADDR]].sub0_sub1 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[GLOBAL_LOAD_DWORDX4_SADDR]].sub0_sub1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY killed [[GLOBAL_LOAD_DWORDX4_SADDR]].sub2_sub3 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY killed [[GLOBAL_LOAD_DWORDX4_SADDR]].sub2_sub3
; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]]
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR %0, %1, 0, 0, implicit $exec :: (load (s64) from `i64 addrspace(1)* undef`, align 4, addrspace 1) %2:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR %0, %1, 0, 0, implicit $exec :: (load (s64) from `i64 addrspace(1)* undef`, align 4, addrspace 1)
%3:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR %0, %1, 8, 0, implicit $exec :: (load (s64) from `i64 addrspace(1)* undef`, align 4, addrspace 1) %3:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR %0, %1, 8, 0, implicit $exec :: (load (s64) from `i64 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %2, implicit %3 S_NOP 0, implicit %2, implicit %3
... ...
--- ---
name: no_merge_global_load_dword_and_global_load_dword_saddr name: no_merge_global_load_dword_and_global_load_dword_saddr
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_load_dword_and_global_load_dword_saddr ; GCN-LABEL: name: no_merge_global_load_dword_and_global_load_dword_saddr
; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF1]], 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF1]], 0, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF]], [[DEF1]].sub0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF]], [[DEF1]].sub0, 4, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD]], implicit [[GLOBAL_LOAD_DWORD_SADDR]] ; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD]], implicit [[GLOBAL_LOAD_DWORD_SADDR]]
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vreg_64_align2 = IMPLICIT_DEF %1:vreg_64_align2 = IMPLICIT_DEF
%2:vgpr_32 = GLOBAL_LOAD_DWORD %1, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %1, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1.sub0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1.sub0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %2, implicit %3 S_NOP 0, implicit %2, implicit %3
... ...
--- ---
name: no_merge_global_load_dword_saddr_different_saddr name: no_merge_global_load_dword_saddr_different_saddr
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_load_dword_saddr_different_saddr ; GCN-LABEL: name: no_merge_global_load_dword_saddr_different_saddr
; GCN: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF]].sub0_sub1, [[DEF1]], 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF]].sub0_sub1, [[DEF1]], 0, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF]].sub2_sub3, [[DEF1]], 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF]].sub2_sub3, [[DEF1]], 4, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD_SADDR]], implicit [[GLOBAL_LOAD_DWORD_SADDR1]] ; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD_SADDR]], implicit [[GLOBAL_LOAD_DWORD_SADDR1]]
%0:sgpr_128 = IMPLICIT_DEF %0:sgpr_128 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0.sub0_sub1, %1, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0.sub0_sub1, %1, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0.sub2_sub3, %1, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0.sub2_sub3, %1, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %2, implicit %3 S_NOP 0, implicit %2, implicit %3
... ...
--- ---
name: no_merge_global_load_dword_saddr_different_vaddr name: no_merge_global_load_dword_saddr_different_vaddr
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_load_dword_saddr_different_vaddr ; GCN-LABEL: name: no_merge_global_load_dword_saddr_different_vaddr
; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF]], [[DEF1]].sub0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF]], [[DEF1]].sub0, 0, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF]], [[DEF1]].sub1, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORD_SADDR1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[DEF]], [[DEF1]].sub1, 4, 0, implicit $exec :: (load (s32) from `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD_SADDR]], implicit [[GLOBAL_LOAD_DWORD_SADDR1]] ; GCN-NEXT: S_NOP 0, implicit [[GLOBAL_LOAD_DWORD_SADDR]], implicit [[GLOBAL_LOAD_DWORD_SADDR1]]
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vreg_64_align2 = IMPLICIT_DEF %1:vreg_64_align2 = IMPLICIT_DEF
%2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1.sub0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1.sub0, 0, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
%3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1.sub1, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %0, %1.sub1, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %2, implicit %3 S_NOP 0, implicit %2, implicit %3
... ...
name: merge_global_load_dword_2_out_of_order name: merge_global_load_dword_2_out_of_order
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dword_2_out_of_order ; GCN-LABEL: name: merge_global_load_dword_2_out_of_order
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 [[DEF]], 0, 0, implicit $exec :: (load (s64) from `float addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 [[DEF]], 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub1 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX2_]].sub0 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX2_]].sub0
; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]] ; GCN-NEXT: S_NOP 0, implicit [[COPY]], implicit [[COPY1]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 4, basealign 8, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 4, basealign 8, addrspace 1)
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `float addrspace(1)* undef`, align 4, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `float addrspace(1)* undef`, align 4, addrspace 1)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_global_load_dword_3_out_of_order name: merge_global_load_dword_3_out_of_order
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_load_dword_3_out_of_order ; GCN-LABEL: name: merge_global_load_dword_3_out_of_order
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[GLOBAL_LOAD_DWORDX3_:%[0-9]+]]:vreg_96_align2 = GLOBAL_LOAD_DWORDX3 [[DEF]], 0, 0, implicit $exec :: (load (s96) from `float addrspace(1)* undef`, align 16, addrspace 1) ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX3_:%[0-9]+]]:vreg_96_align2 = GLOBAL_LOAD_DWORDX3 [[DEF]], 0, 0, implicit $exec :: (load (s96) from `ptr addrspace(1) undef`, align 16, addrspace 1)
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[GLOBAL_LOAD_DWORDX3_]].sub0_sub1 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[GLOBAL_LOAD_DWORDX3_]].sub0_sub1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX3_]].sub2 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[GLOBAL_LOAD_DWORDX3_]].sub2
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub0 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY]].sub0
; GCN-NEXT: S_NOP 0, implicit [[COPY2]], implicit [[COPY3]] ; GCN-NEXT: S_NOP 0, implicit [[COPY2]], implicit [[COPY3]]
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 4, align 4, addrspace 1) %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 4, align 4, addrspace 1)
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `float addrspace(1)* undef`, align 16, addrspace 1) %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (load (s32) from `float addrspace(1)* undef`, align 16, addrspace 1)
%3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, align 8, addrspace 1) %3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, implicit $exec :: (load (s32) from `i32 addrspace(1)* undef` + 8, align 8, addrspace 1)
S_NOP 0, implicit %1, implicit %2 S_NOP 0, implicit %1, implicit %2
... ...
--- ---
name: merge_global_store_dword_2 name: merge_global_store_dword_2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_store_dword_2 ; GCN-LABEL: name: merge_global_store_dword_2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0, killed [[DEF2]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0, killed [[DEF2]], %subreg.sub1
; GCN-NEXT: GLOBAL_STORE_DWORDX2 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (s64) into `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORDX2 [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(1) undef`, align 4, addrspace 1)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD %0, killed %1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %0, killed %1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD killed %0, killed %2, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD killed %0, killed %2, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
... ...
--- ---
name: merge_global_store_dword_3 name: merge_global_store_dword_3
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_store_dword_3 ; GCN-LABEL: name: merge_global_store_dword_3
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0, killed [[DEF2]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0, killed [[DEF2]], %subreg.sub1
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, killed [[DEF3]], %subreg.sub2 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, killed [[DEF3]], %subreg.sub2
; GCN-NEXT: GLOBAL_STORE_DWORDX3 [[DEF]], killed [[REG_SEQUENCE1]], 4, 1, implicit $exec :: (store (s96) into `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORDX3 [[DEF]], killed [[REG_SEQUENCE1]], 4, 1, implicit $exec :: (store (s96) into `ptr addrspace(1) undef`, align 4, addrspace 1)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
%3:vgpr_32 = IMPLICIT_DEF %3:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD %0, killed %1, 4, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %0, killed %1, 4, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD %0, killed %2, 8, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %0, killed %2, 8, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD killed %0, killed %3, 12, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD killed %0, killed %3, 12, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
... ...
--- ---
name: merge_global_store_dword_4 name: merge_global_store_dword_4
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_store_dword_4 ; GCN-LABEL: name: merge_global_store_dword_4
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF1]].sub1, %subreg.sub1, [[DEF1]].sub0, %subreg.sub0 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF1]].sub1, %subreg.sub1, [[DEF1]].sub0, %subreg.sub0
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[DEF1]].sub2, %subreg.sub2, killed [[REG_SEQUENCE]], %subreg.sub0_sub1 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[DEF1]].sub2, %subreg.sub2, killed [[REG_SEQUENCE]], %subreg.sub0_sub1
; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[DEF1]].sub3, %subreg.sub3, killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2 ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[DEF1]].sub3, %subreg.sub3, killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2
; GCN-NEXT: GLOBAL_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE2]], 4, 2, implicit $exec :: (store (s128) into `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE2]], 4, 2, implicit $exec :: (store (s128) into `ptr addrspace(1) undef`, align 4, addrspace 1)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vreg_128 = IMPLICIT_DEF %1:vreg_128 = IMPLICIT_DEF
GLOBAL_STORE_DWORD %0, %1.sub1, 8, 2, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %0, %1.sub1, 8, 2, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD %0, %1.sub2, 12, 2, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %0, %1.sub2, 12, 2, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD %0, %1.sub3, 16, 2, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %0, %1.sub3, 16, 2, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD killed %0, %1.sub0, 4, 2, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD killed %0, %1.sub0, 4, 2, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
... ...
--- ---
name: merge_global_store_dword_5 name: merge_global_store_dword_5
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_store_dword_5 ; GCN-LABEL: name: merge_global_store_dword_5
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:agpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:agpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:agpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF4:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF4:%[0-9]+]]:agpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF5:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF5:%[0-9]+]]:agpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_64_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub0, [[DEF2]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_64_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub0, [[DEF2]], %subreg.sub1
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:areg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, [[DEF3]], %subreg.sub2 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:areg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, [[DEF3]], %subreg.sub2
; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2, [[DEF4]], %subreg.sub3 ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2, [[DEF4]], %subreg.sub3
; GCN-NEXT: GLOBAL_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE2]], 4, 3, implicit $exec :: (store (s128) into `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE2]], 4, 3, implicit $exec :: (store (s128) into `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF]], [[DEF5]], 20, 3, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF]], [[DEF5]], 20, 3, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:agpr_32 = IMPLICIT_DEF %1:agpr_32 = IMPLICIT_DEF
%2:agpr_32 = IMPLICIT_DEF %2:agpr_32 = IMPLICIT_DEF
%3:agpr_32 = IMPLICIT_DEF %3:agpr_32 = IMPLICIT_DEF
%4:agpr_32 = IMPLICIT_DEF %4:agpr_32 = IMPLICIT_DEF
%5:agpr_32 = IMPLICIT_DEF %5:agpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD %0, %1, 4, 3, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %0, %1, 4, 3, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD %0, %2, 8, 3, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 8, addrspace 1) GLOBAL_STORE_DWORD %0, %2, 8, 3, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 8, addrspace 1)
Show All 13 Lines bb.0.entry:
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub0, [[DEF2]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF1]], %subreg.sub0, [[DEF2]], %subreg.sub1
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, [[DEF3]], %subreg.sub2 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, [[DEF3]], %subreg.sub2
; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2, [[DEF4]], %subreg.sub3 ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2, [[DEF4]], %subreg.sub3
; GCN-NEXT: GLOBAL_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE2]], 4, 0, implicit $exec :: (store (s128) into `i32 addrspace(1)* undef`, align 8, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE2]], 4, 0, implicit $exec :: (store (s128) into `ptr addrspace(1) undef`, align 8, addrspace 1)
; GCN-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF5]], %subreg.sub0, [[DEF6]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF5]], %subreg.sub0, [[DEF6]], %subreg.sub1
; GCN-NEXT: GLOBAL_STORE_DWORDX2 [[DEF]], killed [[REG_SEQUENCE3]], 20, 0, implicit $exec :: (store (s64) into `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORDX2 [[DEF]], killed [[REG_SEQUENCE3]], 20, 0, implicit $exec :: (store (s64) into `ptr addrspace(1) undef`, align 4, addrspace 1)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
%3:vgpr_32 = IMPLICIT_DEF %3:vgpr_32 = IMPLICIT_DEF
%4:vgpr_32 = IMPLICIT_DEF %4:vgpr_32 = IMPLICIT_DEF
%5:vgpr_32 = IMPLICIT_DEF %5:vgpr_32 = IMPLICIT_DEF
%6:vgpr_32 = IMPLICIT_DEF %6:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD %0, %1, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 8, addrspace 1) GLOBAL_STORE_DWORD %0, %1, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 8, addrspace 1)
Show All 9 Lines
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_store_dwordx2 ; GCN-LABEL: name: merge_global_store_dwordx2
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0_sub1, killed [[DEF2]], %subreg.sub2_sub3 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0_sub1, killed [[DEF2]], %subreg.sub2_sub3
; GCN-NEXT: GLOBAL_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE]], 4, 0, implicit $exec :: (store (s128) into `i64 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE]], 4, 0, implicit $exec :: (store (s128) into `ptr addrspace(1) undef`, align 4, addrspace 1)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vreg_64_align2 = IMPLICIT_DEF %1:vreg_64_align2 = IMPLICIT_DEF
%2:vreg_64_align2 = IMPLICIT_DEF %2:vreg_64_align2 = IMPLICIT_DEF
GLOBAL_STORE_DWORDX2 %0, killed %1, 4, 0, implicit $exec :: (store (s64) into `i64 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORDX2 %0, killed %1, 4, 0, implicit $exec :: (store (s64) into `i64 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORDX2 %0, killed %2, 12, 0, implicit $exec :: (store (s64) into `i64 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORDX2 %0, killed %2, 12, 0, implicit $exec :: (store (s64) into `i64 addrspace(1)* undef`, align 4, addrspace 1)
... ...
--- ---
name: merge_global_store_dwordx3_with_dwordx1 name: merge_global_store_dwordx3_with_dwordx1
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_store_dwordx3_with_dwordx1 ; GCN-LABEL: name: merge_global_store_dwordx3_with_dwordx1
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_96_align2 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_96_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0_sub1_sub2, killed [[DEF2]], %subreg.sub3 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[DEF1]], %subreg.sub0_sub1_sub2, killed [[DEF2]], %subreg.sub3
; GCN-NEXT: GLOBAL_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE]], 4, 0, implicit $exec :: (store (s128) into `i64 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORDX4 [[DEF]], killed [[REG_SEQUENCE]], 4, 0, implicit $exec :: (store (s128) into `ptr addrspace(1) undef`, addrspace 1)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vreg_96_align2 = IMPLICIT_DEF %1:vreg_96_align2 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORDX3 %0, killed %1, 4, 0, implicit $exec :: (store (s96) into `i64 addrspace(1)* undef`, align 16, addrspace 1) GLOBAL_STORE_DWORDX3 %0, killed %1, 4, 0, implicit $exec :: (store (s96) into `i64 addrspace(1)* undef`, align 16, addrspace 1)
GLOBAL_STORE_DWORD %0, killed %2, 16, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %0, killed %2, 16, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
... ...
--- ---
name: no_merge_global_store_dword_agpr_with_vgpr name: no_merge_global_store_dword_agpr_with_vgpr
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_store_dword_agpr_with_vgpr ; GCN-LABEL: name: no_merge_global_store_dword_agpr_with_vgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:agpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: GLOBAL_STORE_DWORD killed [[DEF]], killed [[DEF2]], 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD killed [[DEF]], killed [[DEF2]], 4, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:agpr_32 = IMPLICIT_DEF %1:agpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD %0, killed %1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %0, killed %1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD killed %0, killed %2, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD killed %0, killed %2, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
... ...
--- ---
name: no_merge_global_store_dword_disjoint name: no_merge_global_store_dword_disjoint
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_store_dword_disjoint ; GCN-LABEL: name: no_merge_global_store_dword_disjoint
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: GLOBAL_STORE_DWORD killed [[DEF]], killed [[DEF2]], 6, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD killed [[DEF]], killed [[DEF2]], 6, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD %0, killed %1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %0, killed %1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD killed %0, killed %2, 6, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD killed %0, killed %2, 6, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
... ...
--- ---
name: no_merge_global_store_dword_overlap name: no_merge_global_store_dword_overlap
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_store_dword_overlap ; GCN-LABEL: name: no_merge_global_store_dword_overlap
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: GLOBAL_STORE_DWORD killed [[DEF]], killed [[DEF2]], 2, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 2, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD killed [[DEF]], killed [[DEF2]], 2, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, align 2, addrspace 1)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD %0, killed %1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %0, killed %1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD killed %0, killed %2, 2, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 2, addrspace 1) GLOBAL_STORE_DWORD killed %0, killed %2, 2, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 2, addrspace 1)
... ...
--- ---
name: no_merge_global_store_dword_different_cpol name: no_merge_global_store_dword_different_cpol
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_store_dword_different_cpol ; GCN-LABEL: name: no_merge_global_store_dword_different_cpol
; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF]], killed [[DEF1]], 0, 1, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: GLOBAL_STORE_DWORD killed [[DEF]], killed [[DEF2]], 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD killed [[DEF]], killed [[DEF2]], 4, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
%0:vreg_64_align2 = IMPLICIT_DEF %0:vreg_64_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD %0, killed %1, 0, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %0, killed %1, 0, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD killed %0, killed %2, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD killed %0, killed %2, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
... ...
--- ---
name: no_merge_global_store_dword_different_vaddr name: no_merge_global_store_dword_different_vaddr
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_store_dword_different_vaddr ; GCN-LABEL: name: no_merge_global_store_dword_different_vaddr
; GCN: [[DEF:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF]].sub0_sub1, killed [[DEF1]], 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF]].sub0_sub1, killed [[DEF1]], 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF]].sub2_sub3, killed [[DEF2]], 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF]].sub2_sub3, killed [[DEF2]], 4, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
%0:vreg_128_align2 = IMPLICIT_DEF %0:vreg_128_align2 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD %0.sub0_sub1, killed %1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %0.sub0_sub1, killed %1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD %0.sub2_sub3, killed %2, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %0.sub2_sub3, killed %2, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
... ...
--- ---
name: merge_global_store_dword_saddr_2 name: merge_global_store_dword_saddr_2
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_store_dword_saddr_2 ; GCN-LABEL: name: merge_global_store_dword_saddr_2
; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF2]], %subreg.sub0, [[DEF3]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF2]], %subreg.sub0, [[DEF3]], %subreg.sub1
; GCN-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[DEF1]], killed [[REG_SEQUENCE]], [[DEF]], 0, 0, implicit $exec :: (store (s64) into `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[DEF1]], killed [[REG_SEQUENCE]], [[DEF]], 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(1) undef`, align 4, addrspace 1)
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
%3:vgpr_32 = IMPLICIT_DEF %3:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD_SADDR %1, %2, %0, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD_SADDR %1, %2, %0, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD_SADDR %1, %3, %0, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD_SADDR %1, %3, %0, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
... ...
--- ---
name: merge_global_store_dword_saddr_3 name: merge_global_store_dword_saddr_3
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: merge_global_store_dword_saddr_3 ; GCN-LABEL: name: merge_global_store_dword_saddr_3
; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF2]], %subreg.sub0, [[DEF3]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF2]], %subreg.sub0, [[DEF3]], %subreg.sub1
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, [[DEF4]], %subreg.sub2 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, [[DEF4]], %subreg.sub2
; GCN-NEXT: GLOBAL_STORE_DWORDX3_SADDR [[DEF1]], killed [[REG_SEQUENCE1]], [[DEF]], 4, 1, implicit $exec :: (store (s96) into `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORDX3_SADDR [[DEF1]], killed [[REG_SEQUENCE1]], [[DEF]], 4, 1, implicit $exec :: (store (s96) into `ptr addrspace(1) undef`, align 4, addrspace 1)
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
%3:vgpr_32 = IMPLICIT_DEF %3:vgpr_32 = IMPLICIT_DEF
%4:vgpr_32 = IMPLICIT_DEF %4:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD_SADDR %1, %2, %0, 4, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD_SADDR %1, %2, %0, 4, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD_SADDR %1, %3, %0, 8, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD_SADDR %1, %3, %0, 8, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD_SADDR %1, %4, %0, 12, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD_SADDR %1, %4, %0, 12, 1, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
Show All 9 Lines bb.0.entry:
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF2]], %subreg.sub0, [[DEF3]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF2]], %subreg.sub0, [[DEF3]], %subreg.sub1
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, [[DEF4]], %subreg.sub2 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, [[DEF4]], %subreg.sub2
; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2, [[DEF5]], %subreg.sub3 ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2, [[DEF5]], %subreg.sub3
; GCN-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[DEF1]], killed [[REG_SEQUENCE2]], [[DEF]], 4, 2, implicit $exec :: (store (s128) into `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[DEF1]], killed [[REG_SEQUENCE2]], [[DEF]], 4, 2, implicit $exec :: (store (s128) into `ptr addrspace(1) undef`, align 4, addrspace 1)
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
%3:vgpr_32 = IMPLICIT_DEF %3:vgpr_32 = IMPLICIT_DEF
%4:vgpr_32 = IMPLICIT_DEF %4:vgpr_32 = IMPLICIT_DEF
%5:vgpr_32 = IMPLICIT_DEF %5:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD_SADDR %1, %2, %0, 4, 2, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD_SADDR %1, %2, %0, 4, 2, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD_SADDR %1, %3, %0, 8, 2, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD_SADDR %1, %3, %0, 8, 2, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
Show All 13 Lines bb.0.entry:
; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF2]], %subreg.sub0, [[DEF3]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF2]], %subreg.sub0, [[DEF3]], %subreg.sub1
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, [[DEF4]], %subreg.sub2 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, [[DEF4]], %subreg.sub2
; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2, [[DEF5]], %subreg.sub3 ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE killed [[REG_SEQUENCE1]], %subreg.sub0_sub1_sub2, [[DEF5]], %subreg.sub3
; GCN-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[DEF1]], killed [[REG_SEQUENCE2]], [[DEF]], 4, 3, implicit $exec :: (store (s128) into `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[DEF1]], killed [[REG_SEQUENCE2]], [[DEF]], 4, 3, implicit $exec :: (store (s128) into `ptr addrspace(1) undef`, align 4, addrspace 1)
; GCN-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF6]], %subreg.sub0, [[DEF7]], %subreg.sub1 ; GCN-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[DEF6]], %subreg.sub0, [[DEF7]], %subreg.sub1
; GCN-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[DEF1]], killed [[REG_SEQUENCE3]], [[DEF]], 20, 3, implicit $exec :: (store (s64) into `i32 addrspace(1)* undef`, align 4, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[DEF1]], killed [[REG_SEQUENCE3]], [[DEF]], 20, 3, implicit $exec :: (store (s64) into `ptr addrspace(1) undef`, align 4, addrspace 1)
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
%3:vgpr_32 = IMPLICIT_DEF %3:vgpr_32 = IMPLICIT_DEF
%4:vgpr_32 = IMPLICIT_DEF %4:vgpr_32 = IMPLICIT_DEF
%5:vgpr_32 = IMPLICIT_DEF %5:vgpr_32 = IMPLICIT_DEF
%6:vgpr_32 = IMPLICIT_DEF %6:vgpr_32 = IMPLICIT_DEF
%7:vgpr_32 = IMPLICIT_DEF %7:vgpr_32 = IMPLICIT_DEF
Show All 10 Lines
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_store_dword_saddr_with_global_store_dword ; GCN-LABEL: name: no_merge_global_store_dword_saddr_with_global_store_dword
; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: GLOBAL_STORE_DWORD_SADDR [[DEF1]].sub0, [[DEF2]], [[DEF]], 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD_SADDR [[DEF1]].sub0, [[DEF2]], [[DEF]], 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF1]], [[DEF3]], 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD [[DEF1]], [[DEF3]], 4, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vreg_64_align2 = IMPLICIT_DEF %1:vreg_64_align2 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
%3:vgpr_32 = IMPLICIT_DEF %3:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD_SADDR %1.sub0, %2, %0, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD_SADDR %1.sub0, %2, %0, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD %1, %3, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD %1, %3, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
... ...
--- ---
name: no_merge_global_store_dword_saddr_different_vaddr name: no_merge_global_store_dword_saddr_different_vaddr
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_store_dword_saddr_different_vaddr ; GCN-LABEL: name: no_merge_global_store_dword_saddr_different_vaddr
; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: GLOBAL_STORE_DWORD_SADDR [[DEF1]].sub0, [[DEF2]], [[DEF]], 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD_SADDR [[DEF1]].sub0, [[DEF2]], [[DEF]], 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: GLOBAL_STORE_DWORD_SADDR [[DEF1]].sub1, [[DEF3]], [[DEF]], 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD_SADDR [[DEF1]].sub1, [[DEF3]], [[DEF]], 4, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vreg_64_align2 = IMPLICIT_DEF %1:vreg_64_align2 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
%3:vgpr_32 = IMPLICIT_DEF %3:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD_SADDR %1.sub0, %2, %0, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD_SADDR %1.sub0, %2, %0, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD_SADDR %1.sub1, %3, %0, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD_SADDR %1.sub1, %3, %0, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
... ...
--- ---
name: no_merge_global_store_dword_saddr_different_saddr name: no_merge_global_store_dword_saddr_different_saddr
body: | body: |
bb.0.entry: bb.0.entry:
; GCN-LABEL: name: no_merge_global_store_dword_saddr_different_saddr ; GCN-LABEL: name: no_merge_global_store_dword_saddr_different_saddr
; GCN: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: GLOBAL_STORE_DWORD_SADDR [[DEF1]], [[DEF2]], [[DEF]].sub0_sub1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD_SADDR [[DEF1]], [[DEF2]], [[DEF]].sub0_sub1, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
; GCN-NEXT: GLOBAL_STORE_DWORD_SADDR [[DEF1]], [[DEF3]], [[DEF]].sub2_sub3, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; GCN-NEXT: GLOBAL_STORE_DWORD_SADDR [[DEF1]], [[DEF3]], [[DEF]].sub2_sub3, 4, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)
%0:sgpr_128 = IMPLICIT_DEF %0:sgpr_128 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
%3:vgpr_32 = IMPLICIT_DEF %3:vgpr_32 = IMPLICIT_DEF
GLOBAL_STORE_DWORD_SADDR %1, %2, %0.sub0_sub1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD_SADDR %1, %2, %0.sub0_sub1, 0, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
GLOBAL_STORE_DWORD_SADDR %1, %3, %0.sub2_sub3, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1) GLOBAL_STORE_DWORD_SADDR %1, %3, %0.sub2_sub3, 4, 0, implicit $exec :: (store (s32) into `i32 addrspace(1)* undef`, align 4, addrspace 1)
... ...

llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir

Show All 23 Lines
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RW-DEFAULT-NOMOVT: constants: # RW-DEFAULT-NOMOVT: constants:
# RW-DEFAULT-NOMOVT: id: 0 # RW-DEFAULT-NOMOVT: id: 0
# RW-DEFAULT-NOMOVT: value: 'i32* @internal_global' # RW-DEFAULT-NOMOVT: value: 'ptr @internal_global'
# RWPI-NOMOVT: constants: # RWPI-NOMOVT: constants:
# RWPI-NOMOVT: id: 0 # RWPI-NOMOVT: id: 0
# RWPI-NOMOVT: value: 'internal_global(SBREL)' # RWPI-NOMOVT: value: 'internal_global(SBREL)'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global %0(p0) = G_GLOBAL_VALUE @internal_global
; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool) ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool)
Show All 17 Lines
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RW-DEFAULT-NOMOVT: constants: # RW-DEFAULT-NOMOVT: constants:
# RW-DEFAULT-NOMOVT: id: 0 # RW-DEFAULT-NOMOVT: id: 0
# RW-DEFAULT-NOMOVT: value: 'i32* @external_global' # RW-DEFAULT-NOMOVT: value: 'ptr @external_global'
# RWPI-NOMOVT: constants: # RWPI-NOMOVT: constants:
# RWPI-NOMOVT: id: 0 # RWPI-NOMOVT: id: 0
# RWPI-NOMOVT: value: 'external_global(SBREL)' # RWPI-NOMOVT: value: 'external_global(SBREL)'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global %0(p0) = G_GLOBAL_VALUE @external_global
; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool) ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool)
Show All 17 Lines
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RO-DEFAULT-NOMOVT: constants: # RO-DEFAULT-NOMOVT: constants:
# RO-DEFAULT-NOMOVT: id: 0 # RO-DEFAULT-NOMOVT: id: 0
# RO-DEFAULT-NOMOVT: value: 'i32* @internal_constant' # RO-DEFAULT-NOMOVT: value: 'ptr @internal_constant'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_constant %0(p0) = G_GLOBAL_VALUE @internal_constant
; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @internal_constant ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @internal_constant
; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant
; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant
; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool) ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool)
Show All 13 Lines
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RO-DEFAULT-NOMOVT: constants: # RO-DEFAULT-NOMOVT: constants:
# RO-DEFAULT-NOMOVT: id: 0 # RO-DEFAULT-NOMOVT: id: 0
# RO-DEFAULT-NOMOVT: value: 'i32* @external_constant' # RO-DEFAULT-NOMOVT: value: 'ptr @external_constant'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_constant %0(p0) = G_GLOBAL_VALUE @external_constant
; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @external_constant ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @external_constant
; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @external_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @external_constant
; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_constant
; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool) ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool)
Show All 9 Lines

llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir

Show All 15 Lines
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# ELF-NOMOVT: constants: # ELF-NOMOVT: constants:
# ELF-NOMOVT: id: 0 # ELF-NOMOVT: id: 0
# ELF-NOMOVT: value: 'i32* @internal_global' # ELF-NOMOVT: value: 'ptr @internal_global'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global %0(p0) = G_GLOBAL_VALUE @internal_global
; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool) ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool)
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @internal_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @internal_global
Show All 13 Lines
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# ELF-NOMOVT: constants: # ELF-NOMOVT: constants:
# ELF-NOMOVT: id: 0 # ELF-NOMOVT: id: 0
# ELF-NOMOVT: value: 'i32* @external_global' # ELF-NOMOVT: value: 'ptr @external_global'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global %0(p0) = G_GLOBAL_VALUE @external_global
; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool) ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool)
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @external_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @external_global
Show All 9 Lines

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-ropi-rwpi.mir

Show All 23 Lines
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RW-DEFAULT-NOMOVT: constants: # RW-DEFAULT-NOMOVT: constants:
# RW-DEFAULT-NOMOVT: id: 0 # RW-DEFAULT-NOMOVT: id: 0
# RW-DEFAULT-NOMOVT: value: 'i32* @internal_global' # RW-DEFAULT-NOMOVT: value: 'ptr @internal_global'
# RWPI-NOMOVT: constants: # RWPI-NOMOVT: constants:
# RWPI-NOMOVT: id: 0 # RWPI-NOMOVT: id: 0
# RWPI-NOMOVT: value: 'internal_global(SBREL)' # RWPI-NOMOVT: value: 'internal_global(SBREL)'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global %0(p0) = G_GLOBAL_VALUE @internal_global
; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global
; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool) ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool)
Show All 17 Lines
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RW-DEFAULT-NOMOVT: constants: # RW-DEFAULT-NOMOVT: constants:
# RW-DEFAULT-NOMOVT: id: 0 # RW-DEFAULT-NOMOVT: id: 0
# RW-DEFAULT-NOMOVT: value: 'i32* @external_global' # RW-DEFAULT-NOMOVT: value: 'ptr @external_global'
# RWPI-NOMOVT: constants: # RWPI-NOMOVT: constants:
# RWPI-NOMOVT: id: 0 # RWPI-NOMOVT: id: 0
# RWPI-NOMOVT: value: 'external_global(SBREL)' # RWPI-NOMOVT: value: 'external_global(SBREL)'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global %0(p0) = G_GLOBAL_VALUE @external_global
; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global
; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool) ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool)
Show All 17 Lines
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RO-DEFAULT-NOMOVT: constants: # RO-DEFAULT-NOMOVT: constants:
# RO-DEFAULT-NOMOVT: id: 0 # RO-DEFAULT-NOMOVT: id: 0
# RO-DEFAULT-NOMOVT: value: 'i32* @internal_constant' # RO-DEFAULT-NOMOVT: value: 'ptr @internal_constant'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_constant %0(p0) = G_GLOBAL_VALUE @internal_constant
; ROPI-MOVT: [[G:%[0-9]+]]:rgpr = t2MOV_ga_pcrel @internal_constant ; ROPI-MOVT: [[G:%[0-9]+]]:rgpr = t2MOV_ga_pcrel @internal_constant
; ROPI-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @internal_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @internal_constant
; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_constant
; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool) ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool)
Show All 13 Lines
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RO-DEFAULT-NOMOVT: constants: # RO-DEFAULT-NOMOVT: constants:
# RO-DEFAULT-NOMOVT: id: 0 # RO-DEFAULT-NOMOVT: id: 0
# RO-DEFAULT-NOMOVT: value: 'i32* @external_constant' # RO-DEFAULT-NOMOVT: value: 'ptr @external_constant'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_constant %0(p0) = G_GLOBAL_VALUE @external_constant
; ROPI-MOVT: [[G:%[0-9]+]]:rgpr = t2MOV_ga_pcrel @external_constant ; ROPI-MOVT: [[G:%[0-9]+]]:rgpr = t2MOV_ga_pcrel @external_constant
; ROPI-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @external_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @external_constant
; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_constant
; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool) ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool)
Show All 9 Lines

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-static.mir

Show All 15 Lines
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# ELF-NOMOVT: constants: # ELF-NOMOVT: constants:
# ELF-NOMOVT: id: 0 # ELF-NOMOVT: id: 0
# ELF-NOMOVT: value: 'i32* @internal_global' # ELF-NOMOVT: value: 'ptr @internal_global'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global %0(p0) = G_GLOBAL_VALUE @internal_global
; ELF-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global ; ELF-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global
; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool) ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool)
; DARWIN-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global ; DARWIN-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_abs @internal_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_abs @internal_global
Show All 13 Lines
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# ELF-NOMOVT: constants: # ELF-NOMOVT: constants:
# ELF-NOMOVT: id: 0 # ELF-NOMOVT: id: 0
# ELF-NOMOVT: value: 'i32* @external_global' # ELF-NOMOVT: value: 'ptr @external_global'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global %0(p0) = G_GLOBAL_VALUE @external_global
; ELF-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global ; ELF-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global
; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool) ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load (p0) from constant-pool)
; DARWIN-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global ; DARWIN-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_abs @external_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_abs @external_global
Show All 9 Lines

llvm/test/CodeGen/MIR/Generic/aligned-memoperands.mir

# RUN: llc -run-pass none -o - %s | FileCheck %s # RUN: llc -run-pass none -o - %s | FileCheck %s
--- ---
name: aligned_memoperands name: aligned_memoperands
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: aligned_memoperands ; CHECK-LABEL: name: aligned_memoperands
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `i32* undef`) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `ptr undef`)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `i32* undef`, align 2) ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `ptr undef`, align 2)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `i32* undef`) ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `ptr undef`)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `i32* undef`, align 8) ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `ptr undef`, align 8)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `i32* undef` + 12, align 2) ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `ptr undef` + 12, align 2)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `i32* undef` + 12) ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `ptr undef` + 12)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `i32* undef` + 12, align 2) ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `ptr undef` + 12, align 2)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `i32* undef` + 12) ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `ptr undef` + 12)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `i32* undef` + 12, basealign 8) ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `ptr undef` + 12, basealign 8)
%0:_(p0) = IMPLICIT_DEF %0:_(p0) = IMPLICIT_DEF
%1:_(s32) = G_LOAD %0 :: (load (s32) from `i32* undef`) %1:_(s32) = G_LOAD %0 :: (load (s32) from `ptr undef`)
%1:_(s32) = G_LOAD %0 :: (load (s32) from `i32* undef`, align 2) %1:_(s32) = G_LOAD %0 :: (load (s32) from `ptr undef`, align 2)
%1:_(s32) = G_LOAD %0 :: (load (s32) from `i32* undef`, align 4) ; redundant %1:_(s32) = G_LOAD %0 :: (load (s32) from `ptr undef`, align 4) ; redundant
%1:_(s32) = G_LOAD %0 :: (load (s32) from `i32* undef`, align 8) %1:_(s32) = G_LOAD %0 :: (load (s32) from `ptr undef`, align 8)
%1:_(s32) = G_LOAD %0 :: (load (s32) from `i32* undef` + 12, align 2) %1:_(s32) = G_LOAD %0 :: (load (s32) from `ptr undef` + 12, align 2)
%1:_(s32) = G_LOAD %0 :: (load (s32) from `i32* undef` + 12, align 4) ; redundant %1:_(s32) = G_LOAD %0 :: (load (s32) from `ptr undef` + 12, align 4) ; redundant
%1:_(s32) = G_LOAD %0 :: (load (s32) from `i32* undef` + 12, basealign 2) ; printed as "align" %1:_(s32) = G_LOAD %0 :: (load (s32) from `ptr undef` + 12, basealign 2) ; printed as "align"
%1:_(s32) = G_LOAD %0 :: (load (s32) from `i32* undef` + 12, basealign 4) ; redundant %1:_(s32) = G_LOAD %0 :: (load (s32) from `ptr undef` + 12, basealign 4) ; redundant
%1:_(s32) = G_LOAD %0 :: (load (s32) from `i32* undef` + 12, basealign 8) %1:_(s32) = G_LOAD %0 :: (load (s32) from `ptr undef` + 12, basealign 8)
... ...

llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll

Show All 15 Linesentry:
call void @e (i32 150994946) call void @e (i32 150994946)
ret void ret void
} }
; MIPS-LABEL: ===== Instruction selection ends: ; MIPS-LABEL: ===== Instruction selection ends:
; MIPS-DAG: t{{[0-9]+}}: i32 = ADDiu Register:i32 $zero, TargetConstant:i32<1> ; MIPS-DAG: t{{[0-9]+}}: i32 = ADDiu Register:i32 $zero, TargetConstant:i32<1>
; MIPS-DAG: t{{[0-9]+}}: i32 = ADDiu Register:i32 $zero, TargetConstant:i32<2048> ; MIPS-DAG: t{{[0-9]+}}: i32 = ADDiu Register:i32 $zero, TargetConstant:i32<2048>
; MIPS-DAG: t{{[0-9]+}}: i32 = LUi TargetConstant:i32<128> ; MIPS-DAG: t{{[0-9]+}}: i32 = LUi TargetConstant:i32<128>
; MIPS: t{{[0-9]+}}: ch,glue = JAL TargetGlobalAddress:i32<void (i32, i32, i32)* @f> ; MIPS: t{{[0-9]+}}: ch,glue = JAL TargetGlobalAddress:i32<ptr @f>
; MIPS: t[[A:[0-9]+]]: i32 = LUi TargetConstant:i32<2304> ; MIPS: t[[A:[0-9]+]]: i32 = LUi TargetConstant:i32<2304>
; MIPS: t{{[0-9]+}}: i32 = ORi t[[A]], TargetConstant:i32<2> ; MIPS: t{{[0-9]+}}: i32 = ORi t[[A]], TargetConstant:i32<2>
; MM-LABEL: ===== Instruction selection ends: ; MM-LABEL: ===== Instruction selection ends:
; MM-DAG: t{{[0-9]+}}: i32 = LI16_MM TargetConstant:i32<1> ; MM-DAG: t{{[0-9]+}}: i32 = LI16_MM TargetConstant:i32<1>
; MM-DAG: t{{[0-9]+}}: i32 = ADDiu_MM Register:i32 $zero, TargetConstant:i32<2048> ; MM-DAG: t{{[0-9]+}}: i32 = ADDiu_MM Register:i32 $zero, TargetConstant:i32<2048>
; MM-DAG: t{{[0-9]+}}: i32 = LUi_MM TargetConstant:i32<128> ; MM-DAG: t{{[0-9]+}}: i32 = LUi_MM TargetConstant:i32<128>
; MM: t{{[0-9]+}}: ch,glue = JAL_MM TargetGlobalAddress:i32<void (i32, i32, i32)* @f> ; MM: t{{[0-9]+}}: ch,glue = JAL_MM TargetGlobalAddress:i32<ptr @f>
; MM: t[[A:[0-9]+]]: i32 = LUi_MM TargetConstant:i32<2304> ; MM: t[[A:[0-9]+]]: i32 = LUi_MM TargetConstant:i32<2304>
; MM: t{{[0-9]+}}: i32 = ORi_MM t[[A]], TargetConstant:i32<2> ; MM: t{{[0-9]+}}: i32 = ORi_MM t[[A]], TargetConstant:i32<2>

llvm/test/CodeGen/PowerPC/fmf-propagation.ll

Show First 20 Lines • Show All 571 Lines • ▼ Show 20 Lines; GLOBAL-NEXT: blr
%cmp = fcmp nnan ult double %a, 0.0 %cmp = fcmp nnan ult double %a, 0.0
%z.y = select i1 %cmp, double %z, double %y %z.y = select i1 %cmp, double %z, double %y
ret double %z.y ret double %z.y
} }
; FP library calls can have fast-math-flags. ; FP library calls can have fast-math-flags.
; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'log2_approx:' ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'log2_approx:'
; FMFDEBUG: ch,glue = PPCISD::CALL_NOP t11, TargetGlobalAddress:i64<double (double)* @log2> ; FMFDEBUG: ch,glue = PPCISD::CALL_NOP t11, TargetGlobalAddress:i64<ptr @log2>
; FMFDEBUG: ch,glue = callseq_end t15, TargetConstant:i64<32>, TargetConstant:i64<0>, t15:1 ; FMFDEBUG: ch,glue = callseq_end t15, TargetConstant:i64<32>, TargetConstant:i64<0>, t15:1
; FMFDEBUG: f64,ch,glue = CopyFromReg t16, Register:f64 $f1, t16:1 ; FMFDEBUG: f64,ch,glue = CopyFromReg t16, Register:f64 $f1, t16:1
; FMFDEBUG: Type-legalized selection DAG: %bb.0 'log2_approx:' ; FMFDEBUG: Type-legalized selection DAG: %bb.0 'log2_approx:'
; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'log2_approx:' ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'log2_approx:'
; GLOBALDEBUG: ch,glue = PPCISD::CALL_NOP t11, TargetGlobalAddress:i64<double (double)* @log2> ; GLOBALDEBUG: ch,glue = PPCISD::CALL_NOP t11, TargetGlobalAddress:i64<ptr @log2>
; GLOBALDEBUG: ch,glue = callseq_end t15, TargetConstant:i64<32>, TargetConstant:i64<0>, t15:1 ; GLOBALDEBUG: ch,glue = callseq_end t15, TargetConstant:i64<32>, TargetConstant:i64<0>, t15:1
; GLOBALDEBUG: f64,ch,glue = CopyFromReg t16, Register:f64 $f1, t16:1 ; GLOBALDEBUG: f64,ch,glue = CopyFromReg t16, Register:f64 $f1, t16:1
; GLOBALDEBUG: Type-legalized selection DAG: %bb.0 'log2_approx:' ; GLOBALDEBUG: Type-legalized selection DAG: %bb.0 'log2_approx:'
declare double @log2(double) declare double @log2(double)
define double @log2_approx(double %x) nounwind { define double @log2_approx(double %x) nounwind {
; FMF-LABEL: log2_approx: ; FMF-LABEL: log2_approx:
; FMF: # %bb.0: ; FMF: # %bb.0:
▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines

llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir

Show All 29 Linesbody: |
; CHECK: undef %20.subreg_l32:gr64bit = IMPLICIT_DEF ; CHECK: undef %20.subreg_l32:gr64bit = IMPLICIT_DEF
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.3(0x00000001), %bb.4(0x7fffffff) ; CHECK: successors: %bb.3(0x00000001), %bb.4(0x7fffffff)
; CHECK: CHIMux [[LHIMux]], 0, implicit-def $cc ; CHECK: CHIMux [[LHIMux]], 0, implicit-def $cc
; CHECK: BRC 14, 6, %bb.3, implicit killed $cc ; CHECK: BRC 14, 6, %bb.3, implicit killed $cc
; CHECK: J %bb.4 ; CHECK: J %bb.4
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: successors: ; CHECK: successors:
; CHECK: STMux %20.subreg_l32, undef %8:addr64bit, 0, $noreg :: (store (s32) into `i32* undef`) ; CHECK: STMux %20.subreg_l32, undef %8:addr64bit, 0, $noreg :: (store (s32) into `ptr undef`)
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: successors: ; CHECK: successors:
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: successors: %bb.5(0x30000000), %bb.6(0x50000000) ; CHECK: successors: %bb.5(0x30000000), %bb.6(0x50000000)
; CHECK: [[LAY:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19838, $noreg ; CHECK: [[LAY:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19838, $noreg
; CHECK: [[LAY1:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19840, $noreg ; CHECK: [[LAY1:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19840, $noreg
; CHECK: [[LAY2:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19844, $noreg ; CHECK: [[LAY2:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19844, $noreg
; CHECK: [[OGR:%[0-9]+]]:gr64bit = OGR [[OGR]], [[LAY]], implicit-def dead $cc ; CHECK: [[OGR:%[0-9]+]]:gr64bit = OGR [[OGR]], [[LAY]], implicit-def dead $cc
Show All 32 Lines bb.1:
%0:addr64bit = COPY killed %23 %0:addr64bit = COPY killed %23
CHIMux %8, 0, implicit-def $cc CHIMux %8, 0, implicit-def $cc
BRC 14, 6, %bb.3, implicit killed $cc BRC 14, 6, %bb.3, implicit killed $cc
J %bb.4 J %bb.4
bb.2: bb.2:
successors: successors:
STMux killed %4, undef %22:addr64bit, 0, $noreg :: (store (s32) into `i32* undef`) STMux killed %4, undef %22:addr64bit, 0, $noreg :: (store (s32) into `ptr undef`)
bb.3: bb.3:
successors: successors:
bb.4: bb.4:
successors: %bb.5(0x30000000), %bb.6(0x50000000) successors: %bb.5(0x30000000), %bb.6(0x50000000)
Show All 36 Lines

llvm/test/CodeGen/X86/bug47278.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=i386-unknown-linux-musl -verify-machineinstrs -run-pass=regallocfast -o - %s | FileCheck %s # RUN: llc -mtriple=i386-unknown-linux-musl -verify-machineinstrs -run-pass=regallocfast -o - %s | FileCheck %s
# Make sure this case doesn't assert or try to assign $ecx to %1 on # Make sure this case doesn't assert or try to assign $ecx to %1 on
# SHRD32rrCL # SHRD32rrCL
--- ---
name: foo name: foo
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: foo ; CHECK-LABEL: name: foo
; CHECK: renamable $eax = IMPLICIT_DEF ; CHECK: renamable $eax = IMPLICIT_DEF
; CHECK: renamable $edx = MOVZX32rm8 renamable $eax, 1, $noreg, 0, $noreg :: (load (s8) from `i168* undef` + 20, align 4, basealign 16) ; CHECK: renamable $edx = MOVZX32rm8 renamable $eax, 1, $noreg, 0, $noreg :: (load (s8) from `ptr undef` + 20, align 4, basealign 16)
; CHECK: dead renamable $ecx = MOV32rm renamable $eax, 1, $noreg, 0, $noreg :: (load (s32) from `i168* undef` + 12, basealign 16) ; CHECK: dead renamable $ecx = MOV32rm renamable $eax, 1, $noreg, 0, $noreg :: (load (s32) from `ptr undef` + 12, basealign 16)
; CHECK: renamable $al = MOV8rm killed renamable $eax, 1, $noreg, 0, $noreg :: (load (s8) from `i32* undef`, align 4) ; CHECK: renamable $al = MOV8rm killed renamable $eax, 1, $noreg, 0, $noreg :: (load (s8) from `ptr undef`, align 4)
; CHECK: dead renamable $ecx = COPY renamable $edx ; CHECK: dead renamable $ecx = COPY renamable $edx
; CHECK: dead renamable $ecx = COPY renamable $edx ; CHECK: dead renamable $ecx = COPY renamable $edx
; CHECK: dead renamable $ecx = COPY renamable $edx ; CHECK: dead renamable $ecx = COPY renamable $edx
; CHECK: renamable $esi = IMPLICIT_DEF ; CHECK: renamable $esi = IMPLICIT_DEF
; CHECK: renamable $ecx = IMPLICIT_DEF ; CHECK: renamable $ecx = IMPLICIT_DEF
; CHECK: renamable $ecx = CMOV32rr renamable $ecx, killed renamable $esi, 2, implicit undef $eflags ; CHECK: renamable $ecx = CMOV32rr renamable $ecx, killed renamable $esi, 2, implicit undef $eflags
; CHECK: renamable $cl = MOV8ri -128 ; CHECK: renamable $cl = MOV8ri -128
; CHECK: $cl = IMPLICIT_DEF ; CHECK: $cl = IMPLICIT_DEF
; CHECK: renamable $eax = COPY renamable $edx ; CHECK: renamable $eax = COPY renamable $edx
; CHECK: dead renamable $eax = SHRD32rrCL renamable $eax, killed renamable $edx, implicit-def dead $eflags, implicit killed $cl ; CHECK: dead renamable $eax = SHRD32rrCL renamable $eax, killed renamable $edx, implicit-def dead $eflags, implicit killed $cl
; CHECK: RET32 ; CHECK: RET32
%0:gr32 = IMPLICIT_DEF %0:gr32 = IMPLICIT_DEF
%1:gr32 = MOVZX32rm8 %0, 1, $noreg, 0, $noreg :: (load (s8) from `i168* undef` + 20, align 4, basealign 16) %1:gr32 = MOVZX32rm8 %0, 1, $noreg, 0, $noreg :: (load (s8) from `ptr undef` + 20, align 4, basealign 16)
%2:gr32 = MOV32rm %0, 1, $noreg, 0, $noreg :: (load (s32) from `i168* undef` + 12, basealign 16) %2:gr32 = MOV32rm %0, 1, $noreg, 0, $noreg :: (load (s32) from `ptr undef` + 12, basealign 16)
%3:gr8 = MOV8rm %0, 1, $noreg, 0, $noreg :: (load (s8) from `i32* undef`, align 4) %3:gr8 = MOV8rm %0, 1, $noreg, 0, $noreg :: (load (s8) from `ptr undef`, align 4)
%4:gr32 = COPY %1 %4:gr32 = COPY %1
%5:gr32 = COPY %1 %5:gr32 = COPY %1
%6:gr32 = COPY %1 %6:gr32 = COPY %1
%7:gr32 = IMPLICIT_DEF %7:gr32 = IMPLICIT_DEF
%8:gr32 = IMPLICIT_DEF %8:gr32 = IMPLICIT_DEF
%8:gr32 = CMOV32rr %8, killed %7, 2, implicit undef $eflags %8:gr32 = CMOV32rr %8, killed %7, 2, implicit undef $eflags
%9:gr8 = MOV8ri -128 %9:gr8 = MOV8ri -128
%9:gr8 = COPY %3 %9:gr8 = COPY %3
$cl = IMPLICIT_DEF $cl = IMPLICIT_DEF
%8:gr32 = COPY %1 %8:gr32 = COPY %1
%8:gr32 = SHRD32rrCL %8, %1, implicit-def dead $eflags, implicit $cl %8:gr32 = SHRD32rrCL %8, %1, implicit-def dead $eflags, implicit $cl
RET32 RET32
... ...

llvm/test/Instrumentation/AddressSanitizer/no-globals.ll

; A module with no asan-instrumented globals has no asan destructor, and has an asan constructor in a comdat. ; A module with no asan-instrumented globals has no asan destructor, and has an asan constructor in a comdat.
; RUN: opt -mtriple=x86_64-unknown-linux-gnu < %s -passes='asan-pipeline' -asan-with-comdat=1 -asan-globals-live-support=1 -S | FileCheck %s ; RUN: opt -mtriple=x86_64-unknown-linux-gnu < %s -passes='asan-pipeline' -asan-with-comdat=1 -asan-globals-live-support=1 -S | FileCheck %s
define void @f() { define void @f() {
ret void ret void
} }
; CHECK-NOT: @llvm.global_dtors ; CHECK-NOT: @llvm.global_dtors
; CHECK: @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 1, void ()* @asan.module_ctor, i8* bitcast (void ()* @asan.module_ctor to i8*) }] ; CHECK: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @asan.module_ctor, ptr @asan.module_ctor }]
; CHECK-NOT: @llvm.global_dtors ; CHECK-NOT: @llvm.global_dtors
; CHECK: define internal void @asan.module_ctor() #[[#]] comdat ; CHECK: define internal void @asan.module_ctor() #[[#]] comdat
; CHECK-NOT: @llvm.global_dtors ; CHECK-NOT: @llvm.global_dtors

llvm/test/Instrumentation/AddressSanitizer/odr-check-ignore.ll

; RUN: opt < %s -passes='asan-pipeline' -asan-use-private-alias=0 -S | FileCheck %s --check-prefix=NOALIAS ; RUN: opt < %s -passes='asan-pipeline' -asan-use-private-alias=0 -S | FileCheck %s --check-prefix=NOALIAS
; RUN: opt < %s -passes='asan-pipeline' -asan-use-private-alias=1 -S | FileCheck %s --check-prefix=ALIAS ; RUN: opt < %s -passes='asan-pipeline' -asan-use-private-alias=1 -S | FileCheck %s --check-prefix=ALIAS
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@a = global [2 x i32] zeroinitializer, align 4 @a = global [2 x i32] zeroinitializer, align 4
@b = private global [2 x i32] zeroinitializer, align 4 @b = private global [2 x i32] zeroinitializer, align 4
@c = internal global [2 x i32] zeroinitializer, align 4 @c = internal global [2 x i32] zeroinitializer, align 4
@d = unnamed_addr global [2 x i32] zeroinitializer, align 4 @d = unnamed_addr global [2 x i32] zeroinitializer, align 4
; NOALIAS: @__asan_global_a = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [24 x i8] }* @a to i64), i64 8, i64 32, i64 ptrtoint ([2 x i8]* @___asan_gen_.1 to i64), i64 ptrtoint ([8 x i8]* @___asan_gen_ to i64), i64 0, i64 0, i64 0 } ; NOALIAS: @__asan_global_a = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint (ptr @a to i64), i64 8, i64 32, i64 ptrtoint (ptr @___asan_gen_.1 to i64), i64 ptrtoint (ptr @___asan_gen_ to i64), i64 0, i64 0, i64 0 }
; NOALIAS-NEXT: @__asan_global_b = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [24 x i8] }* @b to i64), i64 8, i64 32, i64 ptrtoint ([2 x i8]* @___asan_gen_.2 to i64), i64 ptrtoint ([8 x i8]* @___asan_gen_ to i64), i64 0, i64 0, i64 -1 } ; NOALIAS-NEXT: @__asan_global_b = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint (ptr @b to i64), i64 8, i64 32, i64 ptrtoint (ptr @___asan_gen_.2 to i64), i64 ptrtoint (ptr @___asan_gen_ to i64), i64 0, i64 0, i64 -1 }
; NOALIAS-NEXT: @__asan_global_c = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [24 x i8] }* @c to i64), i64 8, i64 32, i64 ptrtoint ([2 x i8]* @___asan_gen_.3 to i64), i64 ptrtoint ([8 x i8]* @___asan_gen_ to i64), i64 0, i64 0, i64 -1 } ; NOALIAS-NEXT: @__asan_global_c = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint (ptr @c to i64), i64 8, i64 32, i64 ptrtoint (ptr @___asan_gen_.3 to i64), i64 ptrtoint (ptr @___asan_gen_ to i64), i64 0, i64 0, i64 -1 }
; NOALIAS-NEXT: @__asan_global_d = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [24 x i8] }* @d to i64), i64 8, i64 32, i64 ptrtoint ([2 x i8]* @___asan_gen_.4 to i64), i64 ptrtoint ([8 x i8]* @___asan_gen_ to i64), i64 0, i64 0, i64 0 } ; NOALIAS-NEXT: @__asan_global_d = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint (ptr @d to i64), i64 8, i64 32, i64 ptrtoint (ptr @___asan_gen_.4 to i64), i64 ptrtoint (ptr @___asan_gen_ to i64), i64 0, i64 0, i64 0 }
; ALIAS: @__asan_global_a = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [24 x i8] }* @0 to i64), i64 8, i64 32, i64 ptrtoint ([2 x i8]* @___asan_gen_.1 to i64), i64 ptrtoint ([8 x i8]* @___asan_gen_ to i64), i64 0, i64 0, i64 0 } ; ALIAS: @__asan_global_a = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint (ptr @0 to i64), i64 8, i64 32, i64 ptrtoint (ptr @___asan_gen_.1 to i64), i64 ptrtoint (ptr @___asan_gen_ to i64), i64 0, i64 0, i64 0 }
; ALIAS-NEXT: @__asan_global_b = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [24 x i8] }* @1 to i64), i64 8, i64 32, i64 ptrtoint ([2 x i8]* @___asan_gen_.2 to i64), i64 ptrtoint ([8 x i8]* @___asan_gen_ to i64), i64 0, i64 0, i64 -1 } ; ALIAS-NEXT: @__asan_global_b = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint (ptr @1 to i64), i64 8, i64 32, i64 ptrtoint (ptr @___asan_gen_.2 to i64), i64 ptrtoint (ptr @___asan_gen_ to i64), i64 0, i64 0, i64 -1 }
; ALIAS-NEXT: @__asan_global_c = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [24 x i8] }* @2 to i64), i64 8, i64 32, i64 ptrtoint ([2 x i8]* @___asan_gen_.3 to i64), i64 ptrtoint ([8 x i8]* @___asan_gen_ to i64), i64 0, i64 0, i64 -1 } ; ALIAS-NEXT: @__asan_global_c = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint (ptr @2 to i64), i64 8, i64 32, i64 ptrtoint (ptr @___asan_gen_.3 to i64), i64 ptrtoint (ptr @___asan_gen_ to i64), i64 0, i64 0, i64 -1 }
; ALIAS-NEXT: @__asan_global_d = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [24 x i8] }* @3 to i64), i64 8, i64 32, i64 ptrtoint ([2 x i8]* @___asan_gen_.4 to i64), i64 ptrtoint ([8 x i8]* @___asan_gen_ to i64), i64 0, i64 0, i64 0 } ; ALIAS-NEXT: @__asan_global_d = private global { i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint (ptr @3 to i64), i64 8, i64 32, i64 ptrtoint (ptr @___asan_gen_.4 to i64), i64 ptrtoint (ptr @___asan_gen_ to i64), i64 0, i64 0, i64 0 }
; ALIAS: @0 = private alias {{.*}} @a ; ALIAS: @0 = private alias {{.*}} @a
; ALIAS-NEXT: @1 = private alias {{.*}} @b ; ALIAS-NEXT: @1 = private alias {{.*}} @b
; ALIAS-NEXT: @2 = private alias {{.*}} @c ; ALIAS-NEXT: @2 = private alias {{.*}} @c
; ALIAS-NEXT: @3 = private alias {{.*}} @d ; ALIAS-NEXT: @3 = private alias {{.*}} @d

llvm/test/Instrumentation/DataFlowSanitizer/arith.ll

; RUN: opt < %s -dfsan -S | FileCheck %s ; RUN: opt < %s -dfsan -S | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]]
; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]]
define i8 @add(i8 %a, i8 %b) { define i8 @add(i8 %a, i8 %b) {
; CHECK: @add.dfsan ; CHECK: @add.dfsan
; CHECK-DAG: %[[#ALABEL:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[ARGTLSTYPE:\[100 x i64\]]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN:2]] ; CHECK-DAG: %[[#ALABEL:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN:2]]
; CHECK-DAG: %[[#BLABEL:]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[ARGTLSTYPE]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN]] ; CHECK-DAG: %[[#BLABEL:]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]]
; CHECK: %[[#UNION:]] = or i[[#SBITS]] %[[#ALABEL]], %[[#BLABEL]] ; CHECK: %[[#UNION:]] = or i[[#SBITS]] %[[#ALABEL]], %[[#BLABEL]]
; CHECK: %c = add i8 %a, %b ; CHECK: %c = add i8 %a, %b
; CHECK: store i[[#SBITS]] %[[#UNION]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] ; CHECK: store i[[#SBITS]] %[[#UNION]], ptr @__dfsan_retval_tls, align [[ALIGN]]
; CHECK: ret i8 %c ; CHECK: ret i8 %c
%c = add i8 %a, %b %c = add i8 %a, %b
ret i8 %c ret i8 %c
} }
define i8 @sub(i8 %a, i8 %b) { define i8 @sub(i8 %a, i8 %b) {
; CHECK: @sub.dfsan ; CHECK: @sub.dfsan
; CHECK: load{{.*}}__dfsan_arg_tls ; CHECK: load{{.*}}__dfsan_arg_tls
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/Instrumentation/DataFlowSanitizer/origin_call.ll

Show All 24 Lines
i1 %a150, i1 %a151, i1 %a152, i1 %a153, i1 %a154, i1 %a155, i1 %a156, i1 %a157, i1 %a158, i1 %a159, i1 %a150, i1 %a151, i1 %a152, i1 %a153, i1 %a154, i1 %a155, i1 %a156, i1 %a157, i1 %a158, i1 %a159,
i1 %a160, i1 %a161, i1 %a162, i1 %a163, i1 %a164, i1 %a165, i1 %a166, i1 %a167, i1 %a168, i1 %a169, i1 %a160, i1 %a161, i1 %a162, i1 %a163, i1 %a164, i1 %a165, i1 %a166, i1 %a167, i1 %a168, i1 %a169,
i1 %a170, i1 %a171, i1 %a172, i1 %a173, i1 %a174, i1 %a175, i1 %a176, i1 %a177, i1 %a178, i1 %a179, i1 %a170, i1 %a171, i1 %a172, i1 %a173, i1 %a174, i1 %a175, i1 %a176, i1 %a177, i1 %a178, i1 %a179,
i1 %a180, i1 %a181, i1 %a182, i1 %a183, i1 %a184, i1 %a185, i1 %a186, i1 %a187, i1 %a188, i1 %a189, i1 %a180, i1 %a181, i1 %a182, i1 %a183, i1 %a184, i1 %a185, i1 %a186, i1 %a187, i1 %a188, i1 %a189,
i1 %a190, i1 %a191, i1 %a192, i1 %a193, i1 %a194, i1 %a195, i1 %a196, i1 %a197, i1 %a198, i1 %a199, i1 %a190, i1 %a191, i1 %a192, i1 %a193, i1 %a194, i1 %a195, i1 %a196, i1 %a197, i1 %a198, i1 %a199,
i1 %a200 i1 %a200
) { ) {
; CHECK: @arg_overflow.dfsan ; CHECK: @arg_overflow.dfsan
; CHECK: [[A199:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 199), align 4 ; CHECK: [[A199:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 199), align 4
; CHECK: store i32 [[A199]], i32* @__dfsan_retval_origin_tls, align 4 ; CHECK: store i32 [[A199]], ptr @__dfsan_retval_origin_tls, align 4
%r = add i1 %a199, %a200 %r = add i1 %a199, %a200
ret i1 %r ret i1 %r
} }
define i1 @param_overflow(i1 %a) { define i1 @param_overflow(i1 %a) {
; CHECK: @param_overflow.dfsan ; CHECK: @param_overflow.dfsan
; CHECK: store i32 %1, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 199), align 4 ; CHECK: store i32 %1, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 199), align 4
; CHECK-NEXT: store i[[#SBITS]] %2, i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 398) to i[[#SBITS]]*), align 2 ; CHECK-NEXT: store i[[#SBITS]] %2, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 398) to ptr), align 2
; CHECK-NEXT: store i[[#SBITS]] %2, i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 400) to i[[#SBITS]]*), align 2 ; CHECK-NEXT: store i[[#SBITS]] %2, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 400) to ptr), align 2
; CHECK-NEXT: %r = call i1 @arg_overflow.dfsan ; CHECK-NEXT: %r = call i1 @arg_overflow.dfsan
; CHECK: %_dfsret_o = load i32, i32* @__dfsan_retval_origin_tls, align 4 ; CHECK: %_dfsret_o = load i32, ptr @__dfsan_retval_origin_tls, align 4
; CHECK: store i32 %_dfsret_o, i32* @__dfsan_retval_origin_tls, align 4 ; CHECK: store i32 %_dfsret_o, ptr @__dfsan_retval_origin_tls, align 4
%r = call i1 @arg_overflow( %r = call i1 @arg_overflow(
i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a,
i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a,
i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a,
i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a,
i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a,
i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a, i1 %a,
Show All 15 Lines
) )
ret i1 %r ret i1 %r
} }
declare void @foo(i1 %a) declare void @foo(i1 %a)
define void @param_with_zero_shadow() { define void @param_with_zero_shadow() {
; CHECK: @param_with_zero_shadow.dfsan ; CHECK: @param_with_zero_shadow.dfsan
; CHECK-NEXT: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 ; CHECK-NEXT: store i[[#SBITS]] 0, ptr @__dfsan_arg_tls, align 2
; CHECK-NEXT: call void @foo.dfsan(i1 true) ; CHECK-NEXT: call void @foo.dfsan(i1 true)
call void @foo(i1 1) call void @foo(i1 1)
ret void ret void
} }

llvm/test/Instrumentation/DataFlowSanitizer/origin_phi.ll

; RUN: opt < %s -dfsan -dfsan-track-origins=1 -S | FileCheck %s ; RUN: opt < %s -dfsan -dfsan-track-origins=1 -S | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; CHECK: @__dfsan_arg_tls = external thread_local(initialexec) global [[TLS_ARR:\[100 x i64\]]] ; CHECK: @__dfsan_arg_tls = external thread_local(initialexec) global [[TLS_ARR:\[100 x i64\]]]
; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]]
; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]]
define i32 @phiop(i32 %a, i32 %b, i1 %c) { define i32 @phiop(i32 %a, i32 %b, i1 %c) {
; CHECK: @phiop.dfsan ; CHECK: @phiop.dfsan
; CHECK: entry: ; CHECK: entry:
; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN:2]] ; CHECK: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN:2]]
; CHECK: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] ; CHECK: [[AS:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]]
; CHECK: br i1 %c, label %next, label %done ; CHECK: br i1 %c, label %next, label %done
; CHECK: next: ; CHECK: next:
; CHECK: br i1 %c, label %T, label %F ; CHECK: br i1 %c, label %T, label %F
; CHECK: T: ; CHECK: T:
; CHECK: [[BS_NE:%.*]] = icmp ne i[[#SBITS]] [[BS]], 0 ; CHECK: [[BS_NE:%.*]] = icmp ne i[[#SBITS]] [[BS]], 0
; CHECK: [[BAO_T:%.*]] = select i1 [[BS_NE]], i32 [[BO]], i32 [[AO]] ; CHECK: [[BAO_T:%.*]] = select i1 [[BS_NE]], i32 [[BO]], i32 [[AO]]
; CHECK: br label %done ; CHECK: br label %done
; CHECK: F: ; CHECK: F:
; CHECK: [[AS_NE:%.*]] = icmp ne i[[#SBITS]] [[AS]], 0 ; CHECK: [[AS_NE:%.*]] = icmp ne i[[#SBITS]] [[AS]], 0
; CHECK: [[BAO_F:%.*]] = select i1 [[AS_NE]], i32 [[AO]], i32 [[BO]] ; CHECK: [[BAO_F:%.*]] = select i1 [[AS_NE]], i32 [[AO]], i32 [[BO]]
; CHECK: br label %done ; CHECK: br label %done
; CHECK: done: ; CHECK: done:
; CHECK: [[PO:%.*]] = phi i32 [ [[BAO_T]], %T ], [ [[BAO_F]], %F ], [ [[AO]], %entry ] ; CHECK: [[PO:%.*]] = phi i32 [ [[BAO_T]], %T ], [ [[BAO_F]], %F ], [ [[AO]], %entry ]
; CHECK: store i32 [[PO]], i32* @__dfsan_retval_origin_tls, align 4 ; CHECK: store i32 [[PO]], ptr @__dfsan_retval_origin_tls, align 4
entry: entry:
br i1 %c, label %next, label %done br i1 %c, label %next, label %done
next: next:
br i1 %c, label %T, label %F br i1 %c, label %T, label %F
T: T:
%sum = add i32 %a, %b %sum = add i32 %a, %b
br label %done br label %done
F: F:
%diff = sub i32 %b, %a %diff = sub i32 %b, %a
br label %done br label %done
done: done:
%r = phi i32 [%sum, %T], [%diff, %F], [%a, %entry] %r = phi i32 [%sum, %T], [%diff, %F], [%a, %entry]
ret i32 %r ret i32 %r
} }
No newline at end of file No newline at end of file

llvm/test/Instrumentation/DataFlowSanitizer/origin_select.ll

; RUN: opt < %s -dfsan -dfsan-track-select-control-flow=1 -dfsan-track-origins=1 -S | FileCheck %s --check-prefixes=CHECK,TRACK_CONTROL_FLOW ; RUN: opt < %s -dfsan -dfsan-track-select-control-flow=1 -dfsan-track-origins=1 -S | FileCheck %s --check-prefixes=CHECK,TRACK_CONTROL_FLOW
; RUN: opt < %s -dfsan -dfsan-track-select-control-flow=0 -dfsan-track-origins=1 -S | FileCheck %s --check-prefixes=CHECK,NO_TRACK_CONTROL_FLOW ; RUN: opt < %s -dfsan -dfsan-track-select-control-flow=0 -dfsan-track-origins=1 -S | FileCheck %s --check-prefixes=CHECK,NO_TRACK_CONTROL_FLOW
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; CHECK: @__dfsan_arg_tls = external thread_local(initialexec) global [[TLS_ARR:\[100 x i64\]]] ; CHECK: @__dfsan_arg_tls = external thread_local(initialexec) global [[TLS_ARR:\[100 x i64\]]]
; CHECK: @__dfsan_retval_tls = external thread_local(initialexec) global [[TLS_ARR]] ; CHECK: @__dfsan_retval_tls = external thread_local(initialexec) global [[TLS_ARR]]
; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]]
; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]]
define i8 @select8(i1 %c, i8 %t, i8 %f) { define i8 @select8(i1 %c, i8 %t, i8 %f) {
; TRACK_CONTROL_FLOW: @select8.dfsan ; TRACK_CONTROL_FLOW: @select8.dfsan
; TRACK_CONTROL_FLOW: [[CO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 ; TRACK_CONTROL_FLOW: [[CO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; TRACK_CONTROL_FLOW: [[FO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 2), align 4 ; TRACK_CONTROL_FLOW: [[FO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
; TRACK_CONTROL_FLOW: [[TO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 ; TRACK_CONTROL_FLOW: [[TO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
; TRACK_CONTROL_FLOW: [[CS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 ; TRACK_CONTROL_FLOW: [[CS:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2
; TRACK_CONTROL_FLOW: [[TFO:%.*]] = select i1 %c, i32 [[TO]], i32 [[FO]] ; TRACK_CONTROL_FLOW: [[TFO:%.*]] = select i1 %c, i32 [[TO]], i32 [[FO]]
; TRACK_CONTROL_FLOW: [[CS_NE:%.*]] = icmp ne i[[#SBITS]] [[CS]], 0 ; TRACK_CONTROL_FLOW: [[CS_NE:%.*]] = icmp ne i[[#SBITS]] [[CS]], 0
; TRACK_CONTROL_FLOW: [[CTFO:%.*]] = select i1 [[CS_NE]], i32 [[CO]], i32 [[TFO]] ; TRACK_CONTROL_FLOW: [[CTFO:%.*]] = select i1 [[CS_NE]], i32 [[CO]], i32 [[TFO]]
; TRACK_CONTROL_FLOW: store i32 [[CTFO]], i32* @__dfsan_retval_origin_tls, align 4 ; TRACK_CONTROL_FLOW: store i32 [[CTFO]], ptr @__dfsan_retval_origin_tls, align 4
; NO_TRACK_CONTROL_FLOW: @select8.dfsan ; NO_TRACK_CONTROL_FLOW: @select8.dfsan
; NO_TRACK_CONTROL_FLOW: [[FO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 2), align 4 ; NO_TRACK_CONTROL_FLOW: [[FO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
; NO_TRACK_CONTROL_FLOW: [[TO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 ; NO_TRACK_CONTROL_FLOW: [[TO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
; NO_TRACK_CONTROL_FLOW: [[TFO:%.*]] = select i1 %c, i32 [[TO]], i32 [[FO]] ; NO_TRACK_CONTROL_FLOW: [[TFO:%.*]] = select i1 %c, i32 [[TO]], i32 [[FO]]
; NO_TRACK_CONTROL_FLOW: store i32 [[TFO]], i32* @__dfsan_retval_origin_tls, align 4 ; NO_TRACK_CONTROL_FLOW: store i32 [[TFO]], ptr @__dfsan_retval_origin_tls, align 4
%a = select i1 %c, i8 %t, i8 %f %a = select i1 %c, i8 %t, i8 %f
ret i8 %a ret i8 %a
} }
define i8 @select8e(i1 %c, i8 %tf) { define i8 @select8e(i1 %c, i8 %tf) {
; TRACK_CONTROL_FLOW: @select8e.dfsan ; TRACK_CONTROL_FLOW: @select8e.dfsan
; TRACK_CONTROL_FLOW: [[CO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 ; TRACK_CONTROL_FLOW: [[CO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; TRACK_CONTROL_FLOW: [[TFO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 ; TRACK_CONTROL_FLOW: [[TFO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
; TRACK_CONTROL_FLOW: [[CS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 ; TRACK_CONTROL_FLOW: [[CS:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2
; TRACK_CONTROL_FLOW: [[CS_NE:%.*]] = icmp ne i[[#SBITS]] [[CS]], 0 ; TRACK_CONTROL_FLOW: [[CS_NE:%.*]] = icmp ne i[[#SBITS]] [[CS]], 0
; TRACK_CONTROL_FLOW: [[CTFO:%.*]] = select i1 [[CS_NE]], i32 [[CO]], i32 [[TFO]] ; TRACK_CONTROL_FLOW: [[CTFO:%.*]] = select i1 [[CS_NE]], i32 [[CO]], i32 [[TFO]]
; TRACK_CONTROL_FLOW: store i32 [[CTFO]], i32* @__dfsan_retval_origin_tls, align 4 ; TRACK_CONTROL_FLOW: store i32 [[CTFO]], ptr @__dfsan_retval_origin_tls, align 4
; NO_TRACK_CONTROL_FLOW: @select8e.dfsan ; NO_TRACK_CONTROL_FLOW: @select8e.dfsan
; NO_TRACK_CONTROL_FLOW: [[TFO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 ; NO_TRACK_CONTROL_FLOW: [[TFO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
; NO_TRACK_CONTROL_FLOW: store i32 [[TFO]], i32* @__dfsan_retval_origin_tls, align 4 ; NO_TRACK_CONTROL_FLOW: store i32 [[TFO]], ptr @__dfsan_retval_origin_tls, align 4
%a = select i1 %c, i8 %tf, i8 %tf %a = select i1 %c, i8 %tf, i8 %tf
ret i8 %a ret i8 %a
} }
define <4 x i8> @select8v(<4 x i1> %c, <4 x i8> %t, <4 x i8> %f) { define <4 x i8> @select8v(<4 x i1> %c, <4 x i8> %t, <4 x i8> %f) {
; TRACK_CONTROL_FLOW: @select8v.dfsan ; TRACK_CONTROL_FLOW: @select8v.dfsan
; TRACK_CONTROL_FLOW: [[CO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 ; TRACK_CONTROL_FLOW: [[CO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; TRACK_CONTROL_FLOW: [[FO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 2), align 4 ; TRACK_CONTROL_FLOW: [[FO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
; TRACK_CONTROL_FLOW: [[TO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 ; TRACK_CONTROL_FLOW: [[TO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
; TRACK_CONTROL_FLOW: [[FS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 4) to i[[#SBITS]]*), align 2 ; TRACK_CONTROL_FLOW: [[FS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 4) to ptr), align 2
; TRACK_CONTROL_FLOW: [[CS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 ; TRACK_CONTROL_FLOW: [[CS:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2
; TRACK_CONTROL_FLOW: [[FS_NE:%.*]] = icmp ne i[[#SBITS]] [[FS]], 0 ; TRACK_CONTROL_FLOW: [[FS_NE:%.*]] = icmp ne i[[#SBITS]] [[FS]], 0
; TRACK_CONTROL_FLOW: [[FTO:%.*]] = select i1 [[FS_NE]], i32 [[FO]], i32 [[TO]] ; TRACK_CONTROL_FLOW: [[FTO:%.*]] = select i1 [[FS_NE]], i32 [[FO]], i32 [[TO]]
; TRACK_CONTROL_FLOW: [[CS_NE:%.*]] = icmp ne i[[#SBITS]] [[CS]], 0 ; TRACK_CONTROL_FLOW: [[CS_NE:%.*]] = icmp ne i[[#SBITS]] [[CS]], 0
; TRACK_CONTROL_FLOW: [[CFTO:%.*]] = select i1 [[CS_NE]], i32 [[CO]], i32 [[FTO]] ; TRACK_CONTROL_FLOW: [[CFTO:%.*]] = select i1 [[CS_NE]], i32 [[CO]], i32 [[FTO]]
; TRACK_CONTROL_FLOW: store i32 [[CFTO]], i32* @__dfsan_retval_origin_tls, align 4 ; TRACK_CONTROL_FLOW: store i32 [[CFTO]], ptr @__dfsan_retval_origin_tls, align 4
; NO_TRACK_CONTROL_FLOW: @select8v.dfsan ; NO_TRACK_CONTROL_FLOW: @select8v.dfsan
; NO_TRACK_CONTROL_FLOW: [[FO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 2), align 4 ; NO_TRACK_CONTROL_FLOW: [[FO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
; NO_TRACK_CONTROL_FLOW: [[TO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 ; NO_TRACK_CONTROL_FLOW: [[TO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
; NO_TRACK_CONTROL_FLOW: [[FS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 4) to i[[#SBITS]]*), align 2 ; NO_TRACK_CONTROL_FLOW: [[FS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 4) to ptr), align 2
; NO_TRACK_CONTROL_FLOW: [[FS_NE:%.*]] = icmp ne i[[#SBITS]] [[FS]], 0 ; NO_TRACK_CONTROL_FLOW: [[FS_NE:%.*]] = icmp ne i[[#SBITS]] [[FS]], 0
; NO_TRACK_CONTROL_FLOW: [[FTO:%.*]] = select i1 [[FS_NE]], i32 [[FO]], i32 [[TO]] ; NO_TRACK_CONTROL_FLOW: [[FTO:%.*]] = select i1 [[FS_NE]], i32 [[FO]], i32 [[TO]]
; NO_TRACK_CONTROL_FLOW: store i32 [[FTO]], i32* @__dfsan_retval_origin_tls, align 4 ; NO_TRACK_CONTROL_FLOW: store i32 [[FTO]], ptr @__dfsan_retval_origin_tls, align 4
%a = select <4 x i1> %c, <4 x i8> %t, <4 x i8> %f %a = select <4 x i1> %c, <4 x i8> %t, <4 x i8> %f
ret <4 x i8> %a ret <4 x i8> %a
} }
No newline at end of file No newline at end of file

llvm/test/Instrumentation/DataFlowSanitizer/phi.ll

; RUN: opt < %s -dfsan -S | FileCheck %s ; RUN: opt < %s -dfsan -S | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]]
; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]]
define {i32, i32} @test({i32, i32} %a, i1 %c) { define {i32, i32} @test({i32, i32} %a, i1 %c) {
; CHECK: %[[#AL:]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN:2]] ; CHECK: %[[#AL:]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_arg_tls, align [[ALIGN:2]]
; CHECK: %[[#AL0:]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } %[[#AL]], i[[#SBITS]] 0, 0 ; CHECK: %[[#AL0:]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } %[[#AL]], i[[#SBITS]] 0, 0
; CHECK: %[[#AL1:]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } %[[#AL]], i[[#SBITS]] 0, 1 ; CHECK: %[[#AL1:]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } %[[#AL]], i[[#SBITS]] 0, 1
; CHECK: %[[#PL:]] = phi { i[[#SBITS]], i[[#SBITS]] } [ %[[#AL0]], %T ], [ %[[#AL1]], %F ] ; CHECK: %[[#PL:]] = phi { i[[#SBITS]], i[[#SBITS]] } [ %[[#AL0]], %T ], [ %[[#AL1]], %F ]
; CHECK: store { i[[#SBITS]], i[[#SBITS]] } %[[#PL]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } %[[#PL]], ptr @__dfsan_retval_tls, align [[ALIGN]]
entry: entry:
br i1 %c, label %T, label %F br i1 %c, label %T, label %F
T: T:
%at = insertvalue {i32, i32} %a, i32 1, 0 %at = insertvalue {i32, i32} %a, i32 1, 0
br label %done br label %done
F: F:
%af = insertvalue {i32, i32} %a, i32 1, 1 %af = insertvalue {i32, i32} %a, i32 1, 1
br label %done br label %done
done: done:
%b = phi {i32, i32} [%at, %T], [%af, %F] %b = phi {i32, i32} [%at, %T], [%af, %F]
ret {i32, i32} %b ret {i32, i32} %b
} }

llvm/test/Instrumentation/DataFlowSanitizer/select.ll

; RUN: opt < %s -dfsan -dfsan-track-select-control-flow=true -S | FileCheck %s --check-prefixes=CHECK,TRACK_CF ; RUN: opt < %s -dfsan -dfsan-track-select-control-flow=true -S | FileCheck %s --check-prefixes=CHECK,TRACK_CF
; RUN: opt < %s -dfsan -dfsan-track-select-control-flow=false -S | FileCheck %s --check-prefixes=CHECK,NO_TRACK_CF ; RUN: opt < %s -dfsan -dfsan-track-select-control-flow=false -S | FileCheck %s --check-prefixes=CHECK,NO_TRACK_CF
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; CHECK: @__dfsan_arg_tls = external thread_local(initialexec) global [[TLS_ARR:\[100 x i64\]]] ; CHECK: @__dfsan_arg_tls = external thread_local(initialexec) global [[TLS_ARR:\[100 x i64\]]]
; CHECK: @__dfsan_retval_tls = external thread_local(initialexec) global [[TLS_ARR]] ; CHECK: @__dfsan_retval_tls = external thread_local(initialexec) global [[TLS_ARR]]
; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]]
; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]]
define i8 @select8(i1 %c, i8 %t, i8 %f) { define i8 @select8(i1 %c, i8 %t, i8 %f) {
; TRACK_CF: @select8.dfsan ; TRACK_CF: @select8.dfsan
; TRACK_CF: %[[#R:]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 4) to i[[#SBITS]]*), align [[ALIGN:2]] ; TRACK_CF: %[[#R:]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 4) to ptr), align [[ALIGN:2]]
; TRACK_CF: %[[#R+1]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN]] ; TRACK_CF: %[[#R+1]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]]
; TRACK_CF: %[[#R+2]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] ; TRACK_CF: %[[#R+2]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]]
; TRACK_CF: %[[#R+3]] = select i1 %c, i[[#SBITS]] %[[#R+1]], i[[#SBITS]] %[[#R]] ; TRACK_CF: %[[#R+3]] = select i1 %c, i[[#SBITS]] %[[#R+1]], i[[#SBITS]] %[[#R]]
; TRACK_CF: %[[#RO:]] = or i[[#SBITS]] %[[#R+2]], %[[#R+3]] ; TRACK_CF: %[[#RO:]] = or i[[#SBITS]] %[[#R+2]], %[[#R+3]]
; TRACK_CF: %a = select i1 %c, i8 %t, i8 %f ; TRACK_CF: %a = select i1 %c, i8 %t, i8 %f
; TRACK_CF: store i[[#SBITS]] %[[#RO]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] ; TRACK_CF: store i[[#SBITS]] %[[#RO]], ptr @__dfsan_retval_tls, align [[ALIGN]]
; TRACK_CF: ret i8 %a ; TRACK_CF: ret i8 %a
; NO_TRACK_CF: @select8.dfsan ; NO_TRACK_CF: @select8.dfsan
; NO_TRACK_CF: %[[#R:]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 4) to i[[#SBITS]]*), align [[ALIGN:2]] ; NO_TRACK_CF: %[[#R:]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 4) to ptr), align [[ALIGN:2]]
; NO_TRACK_CF: %[[#R+1]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN]] ; NO_TRACK_CF: %[[#R+1]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]]
; NO_TRACK_CF: %[[#R+2]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] ; NO_TRACK_CF: %[[#R+2]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]]
; NO_TRACK_CF: %[[#R+3]] = select i1 %c, i[[#SBITS]] %[[#R+1]], i[[#SBITS]] %[[#R]] ; NO_TRACK_CF: %[[#R+3]] = select i1 %c, i[[#SBITS]] %[[#R+1]], i[[#SBITS]] %[[#R]]
; NO_TRACK_CF: %a = select i1 %c, i8 %t, i8 %f ; NO_TRACK_CF: %a = select i1 %c, i8 %t, i8 %f
; NO_TRACK_CF: store i[[#SBITS]] %[[#R+3]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] ; NO_TRACK_CF: store i[[#SBITS]] %[[#R+3]], ptr @__dfsan_retval_tls, align [[ALIGN]]
; NO_TRACK_CF: ret i8 %a ; NO_TRACK_CF: ret i8 %a
%a = select i1 %c, i8 %t, i8 %f %a = select i1 %c, i8 %t, i8 %f
ret i8 %a ret i8 %a
} }
define i8 @select8e(i1 %c, i8 %tf) { define i8 @select8e(i1 %c, i8 %tf) {
; TRACK_CF: @select8e.dfsan ; TRACK_CF: @select8e.dfsan
; TRACK_CF: %[[#R:]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN]] ; TRACK_CF: %[[#R:]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]]
; TRACK_CF: %[[#R+1]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] ; TRACK_CF: %[[#R+1]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]]
; TRACK_CF: %[[#RO:]] = or i[[#SBITS]] %[[#R+1]], %[[#R]] ; TRACK_CF: %[[#RO:]] = or i[[#SBITS]] %[[#R+1]], %[[#R]]
; TRACK_CF: %a = select i1 %c, i8 %tf, i8 %tf ; TRACK_CF: %a = select i1 %c, i8 %tf, i8 %tf
; TRACK_CF: store i[[#SBITS]] %[[#RO]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] ; TRACK_CF: store i[[#SBITS]] %[[#RO]], ptr @__dfsan_retval_tls, align [[ALIGN]]
; TRACK_CF: ret i8 %a ; TRACK_CF: ret i8 %a
; NO_TRACK_CF: @select8e.dfsan ; NO_TRACK_CF: @select8e.dfsan
; NO_TRACK_CF: %[[#R:]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN]] ; NO_TRACK_CF: %[[#R:]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]]
; NO_TRACK_CF: %[[#R+1]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] ; NO_TRACK_CF: %[[#R+1]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]]
; NO_TRACK_CF: %a = select i1 %c, i8 %tf, i8 %tf ; NO_TRACK_CF: %a = select i1 %c, i8 %tf, i8 %tf
; NO_TRACK_CF: store i[[#SBITS]] %[[#R]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] ; NO_TRACK_CF: store i[[#SBITS]] %[[#R]], ptr @__dfsan_retval_tls, align [[ALIGN]]
; NO_TRACK_CF: ret i8 %a ; NO_TRACK_CF: ret i8 %a
%a = select i1 %c, i8 %tf, i8 %tf %a = select i1 %c, i8 %tf, i8 %tf
ret i8 %a ret i8 %a
} }
define <4 x i8> @select8v(<4 x i1> %c, <4 x i8> %t, <4 x i8> %f) { define <4 x i8> @select8v(<4 x i1> %c, <4 x i8> %t, <4 x i8> %f) {
; TRACK_CF: @select8v.dfsan ; TRACK_CF: @select8v.dfsan
; TRACK_CF: %[[#R:]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 4) to i[[#SBITS]]*), align [[ALIGN:2]] ; TRACK_CF: %[[#R:]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 4) to ptr), align [[ALIGN:2]]
; TRACK_CF: %[[#R+1]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN]] ; TRACK_CF: %[[#R+1]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]]
; TRACK_CF: %[[#R+2]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] ; TRACK_CF: %[[#R+2]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]]
; TRACK_CF: %[[#R+3]] = or i[[#SBITS]] %[[#R+1]], %[[#R]] ; TRACK_CF: %[[#R+3]] = or i[[#SBITS]] %[[#R+1]], %[[#R]]
; TRACK_CF: %[[#RO:]] = or i[[#SBITS]] %[[#R+2]], %[[#R+3]] ; TRACK_CF: %[[#RO:]] = or i[[#SBITS]] %[[#R+2]], %[[#R+3]]
; TRACK_CF: %a = select <4 x i1> %c, <4 x i8> %t, <4 x i8> %f ; TRACK_CF: %a = select <4 x i1> %c, <4 x i8> %t, <4 x i8> %f
; TRACK_CF: store i[[#SBITS]] %[[#RO]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] ; TRACK_CF: store i[[#SBITS]] %[[#RO]], ptr @__dfsan_retval_tls, align [[ALIGN]]
; TRACK_CF: ret <4 x i8> %a ; TRACK_CF: ret <4 x i8> %a
; NO_TRACK_CF: @select8v.dfsan ; NO_TRACK_CF: @select8v.dfsan
; NO_TRACK_CF: %[[#R:]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 4) to i[[#SBITS]]*), align [[ALIGN:2]] ; NO_TRACK_CF: %[[#R:]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 4) to ptr), align [[ALIGN:2]]
; NO_TRACK_CF: %[[#R+1]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN]] ; NO_TRACK_CF: %[[#R+1]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]]
; NO_TRACK_CF: %[[#R+2]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] ; NO_TRACK_CF: %[[#R+2]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]]
; NO_TRACK_CF: %[[#RO:]] = or i[[#SBITS]] %[[#R+1]], %[[#R]] ; NO_TRACK_CF: %[[#RO:]] = or i[[#SBITS]] %[[#R+1]], %[[#R]]
; NO_TRACK_CF: %a = select <4 x i1> %c, <4 x i8> %t, <4 x i8> %f ; NO_TRACK_CF: %a = select <4 x i1> %c, <4 x i8> %t, <4 x i8> %f
; NO_TRACK_CF: store i[[#SBITS]] %[[#RO]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] ; NO_TRACK_CF: store i[[#SBITS]] %[[#RO]], ptr @__dfsan_retval_tls, align [[ALIGN]]
; NO_TRACK_CF: ret <4 x i8> %a ; NO_TRACK_CF: ret <4 x i8> %a
%a = select <4 x i1> %c, <4 x i8> %t, <4 x i8> %f %a = select <4 x i1> %c, <4 x i8> %t, <4 x i8> %f
ret <4 x i8> %a ret <4 x i8> %a
} }

llvm/test/Instrumentation/DataFlowSanitizer/shadow-args-zext.ll

; RUN: opt -mtriple=x86_64-unknown-linux-gnu < %s -dfsan -S --dfsan-abilist=%S/Inputs/shadow-args-abilist.txt | FileCheck %s ; RUN: opt -mtriple=x86_64-unknown-linux-gnu < %s -dfsan -S --dfsan-abilist=%S/Inputs/shadow-args-abilist.txt | FileCheck %s
; REQUIRES: x86-registered-target ; REQUIRES: x86-registered-target
; Test that the custom abi marks shadow parameters as zero extended. ; Test that the custom abi marks shadow parameters as zero extended.
; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]]
; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]]
define i32 @m() { define i32 @m() {
; CHECK-LABEL: @m.dfsan ; CHECK-LABEL: @m.dfsan
; CHECK: %{{.*}} = call zeroext i16 @__dfsw_dfsan_get_label(i64 signext 56, i[[#SBITS]] zeroext 0, i[[#SBITS]]* %{{.*}}) ; CHECK: %{{.*}} = call zeroext i16 @__dfsw_dfsan_get_label(i64 signext 56, i[[#SBITS]] zeroext 0, ptr %{{.*}})
entry: entry:
%call = call zeroext i16 @dfsan_get_label(i64 signext 56) %call = call zeroext i16 @dfsan_get_label(i64 signext 56)
%conv = zext i16 %call to i32 %conv = zext i16 %call to i32
ret i32 %conv ret i32 %conv
} }
define i32 @k() { define i32 @k() {
; CHECK-LABEL: @k.dfsan ; CHECK-LABEL: @k.dfsan
; CHECK: %{{.*}} = call zeroext i16 @__dfsw_k2(i64 signext 56, i64 signext 67, i[[#SBITS]] zeroext {{.*}}, i[[#SBITS]] zeroext {{.*}}, i[[#SBITS]]* %{{.*}}) ; CHECK: %{{.*}} = call zeroext i16 @__dfsw_k2(i64 signext 56, i64 signext 67, i[[#SBITS]] zeroext {{.*}}, i[[#SBITS]] zeroext {{.*}}, ptr %{{.*}})
entry: entry:
%call = call zeroext i16 @k2(i64 signext 56, i64 signext 67) %call = call zeroext i16 @k2(i64 signext 56, i64 signext 67)
%conv = zext i16 %call to i32 %conv = zext i16 %call to i32
ret i32 %conv ret i32 %conv
} }
define i32 @k3() { define i32 @k3() {
; CHECK-LABEL: @k3.dfsan ; CHECK-LABEL: @k3.dfsan
; CHECK: %{{.*}} = call zeroext i16 @__dfsw_k4(i64 signext 56, i64 signext 67, i64 signext 78, i64 signext 89, i[[#SBITS]] zeroext {{.*}}, i[[#SBITS]] zeroext {{.*}}, i[[#SBITS]] zeroext {{.*}}, i[[#SBITS]] zeroext {{.*}}, i[[#SBITS]]* %{{.*}}) ; CHECK: %{{.*}} = call zeroext i16 @__dfsw_k4(i64 signext 56, i64 signext 67, i64 signext 78, i64 signext 89, i[[#SBITS]] zeroext {{.*}}, i[[#SBITS]] zeroext {{.*}}, i[[#SBITS]] zeroext {{.*}}, i[[#SBITS]] zeroext {{.*}}, ptr %{{.*}})
entry: entry:
%call = call zeroext i16 @k4(i64 signext 56, i64 signext 67, i64 signext 78, i64 signext 89) %call = call zeroext i16 @k4(i64 signext 56, i64 signext 67, i64 signext 78, i64 signext 89)
%conv = zext i16 %call to i32 %conv = zext i16 %call to i32
ret i32 %conv ret i32 %conv
} }
declare zeroext i16 @dfsan_get_label(i64 signext) declare zeroext i16 @dfsan_get_label(i64 signext)
; CHECK-LABEL: @"dfsw$dfsan_get_label" ; CHECK-LABEL: @"dfsw$dfsan_get_label"
; CHECK: %{{.*}} = call i16 @__dfsw_dfsan_get_label(i64 %0, i[[#SBITS]] zeroext %1, i[[#SBITS]]* %{{.*}}) ; CHECK: %{{.*}} = call i16 @__dfsw_dfsan_get_label(i64 %0, i[[#SBITS]] zeroext %1, ptr %{{.*}})
declare zeroext i16 @k2(i64 signext, i64 signext) declare zeroext i16 @k2(i64 signext, i64 signext)
; CHECK-LABEL: @"dfsw$k2" ; CHECK-LABEL: @"dfsw$k2"
; CHECK: %{{.*}} = call i16 @__dfsw_k2(i64 %{{.*}}, i64 %{{.*}}, i[[#SBITS]] zeroext %{{.*}}, i[[#SBITS]] zeroext %{{.*}}, i[[#SBITS]]* %{{.*}}) ; CHECK: %{{.*}} = call i16 @__dfsw_k2(i64 %{{.*}}, i64 %{{.*}}, i[[#SBITS]] zeroext %{{.*}}, i[[#SBITS]] zeroext %{{.*}}, ptr %{{.*}})
declare zeroext i16 @k4(i64 signext, i64 signext, i64 signext, i64 signext) declare zeroext i16 @k4(i64 signext, i64 signext, i64 signext, i64 signext)
; CHECK-LABEL: @"dfsw$k4" ; CHECK-LABEL: @"dfsw$k4"
; CHECK: %{{.*}} = call i16 @__dfsw_k4(i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}, i[[#SBITS]] zeroext %{{.*}}, i[[#SBITS]] zeroext %{{.*}}, i[[#SBITS]] zeroext %{{.*}}, i[[#SBITS]] zeroext %{{.*}}, i[[#SBITS]]* %{{.*}}) ; CHECK: %{{.*}} = call i16 @__dfsw_k4(i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}, i[[#SBITS]] zeroext %{{.*}}, i[[#SBITS]] zeroext %{{.*}}, i[[#SBITS]] zeroext %{{.*}}, i[[#SBITS]] zeroext %{{.*}}, ptr %{{.*}})
; CHECK: declare zeroext i16 @__dfsw_dfsan_get_label(i64 signext, i[[#SBITS]], i[[#SBITS]]*) ; CHECK: declare zeroext i16 @__dfsw_dfsan_get_label(i64 signext, i[[#SBITS]], ptr)
; CHECK: declare zeroext i16 @__dfsw_k2(i64 signext, i64 signext, i[[#SBITS]], i[[#SBITS]], i[[#SBITS]]*) ; CHECK: declare zeroext i16 @__dfsw_k2(i64 signext, i64 signext, i[[#SBITS]], i[[#SBITS]], ptr)
; CHECK: declare zeroext i16 @__dfsw_k4(i64 signext, i64 signext, i64 signext, i64 signext, i[[#SBITS]], i[[#SBITS]], i[[#SBITS]], i[[#SBITS]], i[[#SBITS]]*) ; CHECK: declare zeroext i16 @__dfsw_k4(i64 signext, i64 signext, i64 signext, i64 signext, i[[#SBITS]], i[[#SBITS]], i[[#SBITS]], i[[#SBITS]], ptr)

llvm/test/Instrumentation/HWAddressSanitizer/X86/globals.ll

; RUN: opt < %s -S -passes=hwasan -mtriple=x86_64-unknown-linux-gnu | FileCheck %s ; RUN: opt < %s -S -passes=hwasan -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
; CHECK: @__start_hwasan_globals = external hidden constant [0 x i8] ; CHECK: @__start_hwasan_globals = external hidden constant [0 x i8]
; CHECK: @__stop_hwasan_globals = external hidden constant [0 x i8] ; CHECK: @__stop_hwasan_globals = external hidden constant [0 x i8]
; CHECK: @hwasan.note = private constant { i32, i32, i32, [8 x i8], i32, i32 } { i32 8, i32 8, i32 3, [8 x i8] c"LLVM\00\00\00\00", i32 trunc (i64 sub (i64 ptrtoint ([0 x i8]* @__start_hwasan_globals to i64), i64 ptrtoint ({ i32, i32, i32, [8 x i8], i32, i32 }* @hwasan.note to i64)) to i32), i32 trunc (i64 sub (i64 ptrtoint ([0 x i8]* @__stop_hwasan_globals to i64), i64 ptrtoint ({ i32, i32, i32, [8 x i8], i32, i32 }* @hwasan.note to i64)) to i32) }, section ".note.hwasan.globals", comdat($hwasan.module_ctor), align 4 ; CHECK: @hwasan.note = private constant { i32, i32, i32, [8 x i8], i32, i32 } { i32 8, i32 8, i32 3, [8 x i8] c"LLVM\00\00\00\00", i32 trunc (i64 sub (i64 ptrtoint (ptr @__start_hwasan_globals to i64), i64 ptrtoint (ptr @hwasan.note to i64)) to i32), i32 trunc (i64 sub (i64 ptrtoint (ptr @__stop_hwasan_globals to i64), i64 ptrtoint (ptr @hwasan.note to i64)) to i32) }, section ".note.hwasan.globals", comdat($hwasan.module_ctor), align 4
; CHECK: @hwasan.dummy.global = private constant [0 x i8] zeroinitializer, section "hwasan_globals", comdat($hwasan.module_ctor), !associated [[NOTE:![0-9]+]] ; CHECK: @hwasan.dummy.global = private constant [0 x i8] zeroinitializer, section "hwasan_globals", comdat($hwasan.module_ctor), !associated [[NOTE:![0-9]+]]
; CHECK: @four.hwasan = private global { i32, [12 x i8] } { i32 1, [12 x i8] c"\00\00\00\00\00\00\00\00\00\00\00," }, align 16 ; CHECK: @four.hwasan = private global { i32, [12 x i8] } { i32 1, [12 x i8] c"\00\00\00\00\00\00\00\00\00\00\00," }, align 16
; CHECK: @four.hwasan.descriptor = private constant { i32, i32 } { i32 trunc (i64 sub (i64 ptrtoint ({ i32, [12 x i8] }* @four.hwasan to i64), i64 ptrtoint ({ i32, i32 }* @four.hwasan.descriptor to i64)) to i32), i32 738197508 }, section "hwasan_globals", !associated [[FOUR:![0-9]+]] ; CHECK: @four.hwasan.descriptor = private constant { i32, i32 } { i32 trunc (i64 sub (i64 ptrtoint (ptr @four.hwasan to i64), i64 ptrtoint (ptr @four.hwasan.descriptor to i64)) to i32), i32 738197508 }, section "hwasan_globals", !associated [[FOUR:![0-9]+]]
; CHECK: @sixteen.hwasan = private global [16 x i8] zeroinitializer, align 16 ; CHECK: @sixteen.hwasan = private global [16 x i8] zeroinitializer, align 16
; CHECK: @sixteen.hwasan.descriptor = private constant { i32, i32 } { i32 trunc (i64 sub (i64 ptrtoint ([16 x i8]* @sixteen.hwasan to i64), i64 ptrtoint ({ i32, i32 }* @sixteen.hwasan.descriptor to i64)) to i32), i32 754974736 }, section "hwasan_globals", !associated [[SIXTEEN:![0-9]+]] ; CHECK: @sixteen.hwasan.descriptor = private constant { i32, i32 } { i32 trunc (i64 sub (i64 ptrtoint (ptr @sixteen.hwasan to i64), i64 ptrtoint (ptr @sixteen.hwasan.descriptor to i64)) to i32), i32 754974736 }, section "hwasan_globals", !associated [[SIXTEEN:![0-9]+]]
; CHECK: @huge.hwasan = private global [16777232 x i8] zeroinitializer, align 16 ; CHECK: @huge.hwasan = private global [16777232 x i8] zeroinitializer, align 16
; CHECK: @huge.hwasan.descriptor = private constant { i32, i32 } { i32 trunc (i64 sub (i64 ptrtoint ([16777232 x i8]* @huge.hwasan to i64), i64 ptrtoint ({ i32, i32 }* @huge.hwasan.descriptor to i64)) to i32), i32 788529136 }, section "hwasan_globals", !associated [[HUGE:![0-9]+]] ; CHECK: @huge.hwasan.descriptor = private constant { i32, i32 } { i32 trunc (i64 sub (i64 ptrtoint (ptr @huge.hwasan to i64), i64 ptrtoint (ptr @huge.hwasan.descriptor to i64)) to i32), i32 788529136 }, section "hwasan_globals", !associated [[HUGE:![0-9]+]]
; CHECK: @huge.hwasan.descriptor.1 = private constant { i32, i32 } { i32 trunc (i64 add (i64 sub (i64 ptrtoint ([16777232 x i8]* @huge.hwasan to i64), i64 ptrtoint ({ i32, i32 }* @huge.hwasan.descriptor.1 to i64)), i64 16777200) to i32), i32 771751968 }, section "hwasan_globals", !associated [[HUGE]] ; CHECK: @huge.hwasan.descriptor.1 = private constant { i32, i32 } { i32 trunc (i64 add (i64 sub (i64 ptrtoint (ptr @huge.hwasan to i64), i64 ptrtoint (ptr @huge.hwasan.descriptor.1 to i64)), i64 16777200) to i32), i32 771751968 }, section "hwasan_globals", !associated [[HUGE]]
; CHECK: @four = alias i32, inttoptr (i64 add (i64 ptrtoint ({ i32, [12 x i8] }* @four.hwasan to i64), i64 6341068275337658368) to i32*) ; CHECK: @four = alias i32, inttoptr (i64 add (i64 ptrtoint (ptr @four.hwasan to i64), i64 6341068275337658368) to ptr)
; CHECK: @sixteen = alias [16 x i8], inttoptr (i64 add (i64 ptrtoint ([16 x i8]* @sixteen.hwasan to i64), i64 6485183463413514240) to [16 x i8]*) ; CHECK: @sixteen = alias [16 x i8], inttoptr (i64 add (i64 ptrtoint (ptr @sixteen.hwasan to i64), i64 6485183463413514240) to ptr)
; CHECK: @huge = alias [16777232 x i8], inttoptr (i64 add (i64 ptrtoint ([16777232 x i8]* @huge.hwasan to i64), i64 6629298651489370112) to [16777232 x i8]*) ; CHECK: @huge = alias [16777232 x i8], inttoptr (i64 add (i64 ptrtoint (ptr @huge.hwasan to i64), i64 6629298651489370112) to ptr)
; CHECK: [[NOTE]] = !{{{{}} i32, i32, i32, [8 x i8], i32, i32 }* @hwasan.note} ; CHECK: [[NOTE]] = !{ptr @hwasan.note}
; CHECK: [[FOUR]] = !{{{{}} i32, [12 x i8] }* @four.hwasan} ; CHECK: [[FOUR]] = !{ptr @four.hwasan}
; CHECK: [[SIXTEEN]] = !{[16 x i8]* @sixteen.hwasan} ; CHECK: [[SIXTEEN]] = !{ptr @sixteen.hwasan}
; CHECK: [[HUGE]] = !{[16777232 x i8]* @huge.hwasan} ; CHECK: [[HUGE]] = !{ptr @huge.hwasan}
source_filename = "foo" source_filename = "foo"
@four = global i32 1 @four = global i32 1
@sixteen = global [16 x i8] zeroinitializer @sixteen = global [16 x i8] zeroinitializer
@huge = global [16777232 x i8] zeroinitializer @huge = global [16777232 x i8] zeroinitializer

llvm/test/Instrumentation/InstrOrderFile/basic.ll

; RUN: opt -instrorderfile -S < %s | FileCheck %s ; RUN: opt -instrorderfile -S < %s | FileCheck %s
; RUN: opt -passes=instrorderfile -S < %s | FileCheck %s ; RUN: opt -passes=instrorderfile -S < %s | FileCheck %s
target triple = "x86_64-apple-macosx10.10.0" target triple = "x86_64-apple-macosx10.10.0"
; CHECK: @_llvm_order_file_buffer ={{.*}}global [131072 x i64] zeroinitializer ; CHECK: @_llvm_order_file_buffer ={{.*}}global [131072 x i64] zeroinitializer
; CHECK: @_llvm_order_file_buffer_idx = linkonce_odr global i32 0 ; CHECK: @_llvm_order_file_buffer_idx = linkonce_odr global i32 0
; CHECK: @bitmap_0 ={{.*}}global [1 x i8] zeroinitializer ; CHECK: @bitmap_0 ={{.*}}global [1 x i8] zeroinitializer
define i32 @_Z1fv() { define i32 @_Z1fv() {
ret i32 0 ret i32 0
} }
; CHECK-LABEL: define i32 @_Z1fv ; CHECK-LABEL: define i32 @_Z1fv
; CHECK: order_file_entry ; CHECK: order_file_entry
; CHECK: %[[T1:.+]] = load i8, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @bitmap_0, i32 0, i32 0 ; CHECK: %[[T1:.+]] = load i8, ptr @bitmap_0
; CHECK: store i8 1, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @bitmap_0, i32 0, i32 0) ; CHECK: store i8 1, ptr @bitmap_0
; CHECK: %[[T2:.+]] = icmp eq i8 %[[T1]], 0 ; CHECK: %[[T2:.+]] = icmp eq i8 %[[T1]], 0
; CHECK: br i1 %[[T2]], label %order_file_set, label ; CHECK: br i1 %[[T2]], label %order_file_set, label
; CHECK: order_file_set ; CHECK: order_file_set
; CHECK: %[[T3:.+]] = atomicrmw add i32* @_llvm_order_file_buffer_idx, i32 1 seq_cst ; CHECK: %[[T3:.+]] = atomicrmw add ptr @_llvm_order_file_buffer_idx, i32 1 seq_cst
; CHECK: %[[T5:.+]] = and i32 %[[T3]], 131071 ; CHECK: %[[T5:.+]] = and i32 %[[T3]], 131071
; CHECK: %[[T4:.+]] = getelementptr [131072 x i64], [131072 x i64]* @_llvm_order_file_buffer, i32 0, i32 %[[T5]] ; CHECK: %[[T4:.+]] = getelementptr [131072 x i64], ptr @_llvm_order_file_buffer, i32 0, i32 %[[T5]]
; CHECK: store i64 {{.*}}, i64* %[[T4]] ; CHECK: store i64 {{.*}}, ptr %[[T4]]

llvm/test/Instrumentation/JustMyCode/jmc-instrument-elf.ll

; RUN: opt -jmc-instrument -mtriple=x86_64-unknown-linux-gnu -S < %s | FileCheck %s ; RUN: opt -jmc-instrument -mtriple=x86_64-unknown-linux-gnu -S < %s | FileCheck %s
; CHECK: @"__7DF23CF5_x@c" = internal unnamed_addr global i8 1, section ".just.my.code", align 1, !dbg !0 ; CHECK: @"__7DF23CF5_x@c" = internal unnamed_addr global i8 1, section ".just.my.code", align 1, !dbg !0
; CHECK: @"__A8764FDD_x@c" = internal unnamed_addr global i8 1, section ".just.my.code", align 1, !dbg !5 ; CHECK: @"__A8764FDD_x@c" = internal unnamed_addr global i8 1, section ".just.my.code", align 1, !dbg !5
; CHECK: define void @l1() !dbg !12 { ; CHECK: define void @l1() !dbg !12 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__7DF23CF5_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__7DF23CF5_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @l2() !dbg !16 { ; CHECK: define void @l2() !dbg !16 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__7DF23CF5_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__7DF23CF5_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @w1() !dbg !18 { ; CHECK: define void @w1() !dbg !18 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__A8764FDD_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__A8764FDD_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @w2() !dbg !19 { ; CHECK: define void @w2() !dbg !19 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__A8764FDD_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__A8764FDD_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @w3() !dbg !21 { ; CHECK: define void @w3() !dbg !21 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__A8764FDD_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__A8764FDD_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @w4() !dbg !23 { ; CHECK: define void @w4() !dbg !23 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__A8764FDD_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__A8764FDD_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define weak void @__CheckForDebuggerJustMyCode(i8* noundef %0) unnamed_addr { ; CHECK: define weak void @__CheckForDebuggerJustMyCode(ptr noundef %0) unnamed_addr {
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: !llvm.dbg.cu = !{!2} ; CHECK: !llvm.dbg.cu = !{!2}
; CHECK: !llvm.module.flags = !{!9, !10} ; CHECK: !llvm.module.flags = !{!9, !10}
; CHECK: !llvm.ident = !{!11} ; CHECK: !llvm.ident = !{!11}
; CHECK: !0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) ; CHECK: !0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression())
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llvm/test/Instrumentation/JustMyCode/jmc-instrument-x86.ll

; RUN: opt -jmc-instrument -S < %s | FileCheck %s ; RUN: opt -jmc-instrument -S < %s | FileCheck %s
; CHECK: $_JustMyCode_Default = comdat any ; CHECK: $_JustMyCode_Default = comdat any
; CHECK: @"_A8764FDD_x@c" = internal unnamed_addr global i8 1, section ".msvcjmc", align 1, !dbg !0 ; CHECK: @"_A8764FDD_x@c" = internal unnamed_addr global i8 1, section ".msvcjmc", align 1, !dbg !0
; CHECK: @llvm.used = appending global [1 x i8*] [i8* bitcast (void (i8*)* @_JustMyCode_Default to i8*)], section "llvm.metadata" ; CHECK: @llvm.used = appending global [1 x ptr] [ptr @_JustMyCode_Default], section "llvm.metadata"
; CHECK: define void @w1() #0 !dbg !10 { ; CHECK: define void @w1() #0 !dbg !10 {
; CHECK: call x86_fastcallcc void @__CheckForDebuggerJustMyCode(i8* inreg noundef @"_A8764FDD_x@c") ; CHECK: call x86_fastcallcc void @__CheckForDebuggerJustMyCode(ptr inreg noundef @"_A8764FDD_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @_JustMyCode_Default(i8* inreg noundef %0) unnamed_addr comdat { ; CHECK: define void @_JustMyCode_Default(ptr inreg noundef %0) unnamed_addr comdat {
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: declare x86_fastcallcc void @__CheckForDebuggerJustMyCode(i8* inreg noundef) unnamed_addr ; CHECK: declare x86_fastcallcc void @__CheckForDebuggerJustMyCode(ptr inreg noundef) unnamed_addr
; CHECK: !0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) ; CHECK: !0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression())
; CHECK: !1 = distinct !DIGlobalVariable(name: "_A8764FDD_x@c", scope: !2, file: !3, type: !5, isLocal: true, isDefinition: true) ; CHECK: !1 = distinct !DIGlobalVariable(name: "_A8764FDD_x@c", scope: !2, file: !3, type: !5, isLocal: true, isDefinition: true)
; CHECK: !2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: !4, splitDebugInlining: false, nameTableKind: None) ; CHECK: !2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: !4, splitDebugInlining: false, nameTableKind: None)
; CHECK: !3 = !DIFile(filename: "./b/./../b/x.c", directory: "C:\\\\a\\\\") ; CHECK: !3 = !DIFile(filename: "./b/./../b/x.c", directory: "C:\\\\a\\\\")
; CHECK: !4 = !{!0} ; CHECK: !4 = !{!0}
; CHECK: !5 = !DIBasicType(name: "unsigned char", size: 8, encoding: DW_ATE_unsigned_char, flags: DIFlagArtificial) ; CHECK: !5 = !DIBasicType(name: "unsigned char", size: 8, encoding: DW_ATE_unsigned_char, flags: DIFlagArtificial)
; CHECK: !6 = !{i32 2, !"CodeView", i32 1} ; CHECK: !6 = !{i32 2, !"CodeView", i32 1}
Show All 28 Lines

llvm/test/Instrumentation/JustMyCode/jmc-instrument.ll

; RUN: opt -jmc-instrument -mtriple=x86_64-pc-windows-msvc -S < %s | FileCheck %s ; RUN: opt -jmc-instrument -mtriple=x86_64-pc-windows-msvc -S < %s | FileCheck %s
; RUN: opt -jmc-instrument -mtriple=aarch64-pc-windows-msvc -S < %s | FileCheck %s ; RUN: opt -jmc-instrument -mtriple=aarch64-pc-windows-msvc -S < %s | FileCheck %s
; RUN: opt -jmc-instrument -mtriple=arm-pc-windows-msvc -S < %s | FileCheck %s ; RUN: opt -jmc-instrument -mtriple=arm-pc-windows-msvc -S < %s | FileCheck %s
; CHECK: $__JustMyCode_Default = comdat any ; CHECK: $__JustMyCode_Default = comdat any
; CHECK: @"__7DF23CF5_x@c" = internal unnamed_addr global i8 1, section ".msvcjmc", align 1, !dbg !0 ; CHECK: @"__7DF23CF5_x@c" = internal unnamed_addr global i8 1, section ".msvcjmc", align 1, !dbg !0
; CHECK: @llvm.used = appending global [1 x i8*] [i8* bitcast (void (i8*)* @__JustMyCode_Default to i8*)], section "llvm.metadata" ; CHECK: @llvm.used = appending global [1 x ptr] [ptr @__JustMyCode_Default], section "llvm.metadata"
; CHECK: @"__A8764FDD_x@c" = internal unnamed_addr global i8 1, section ".msvcjmc", align 1, !dbg !5 ; CHECK: @"__A8764FDD_x@c" = internal unnamed_addr global i8 1, section ".msvcjmc", align 1, !dbg !5
; CHECK: @"__0C712A50_x@c" = internal unnamed_addr global i8 1, section ".msvcjmc", align 1, !dbg !9 ; CHECK: @"__0C712A50_x@c" = internal unnamed_addr global i8 1, section ".msvcjmc", align 1, !dbg !9
; CHECK: @"__A3605329_x@c" = internal unnamed_addr global i8 1, section ".msvcjmc", align 1, !dbg !12 ; CHECK: @"__A3605329_x@c" = internal unnamed_addr global i8 1, section ".msvcjmc", align 1, !dbg !12
; CHECK: define void @l1() !dbg !19 { ; CHECK: define void @l1() !dbg !19 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__7DF23CF5_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__7DF23CF5_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @l2() !dbg !23 { ; CHECK: define void @l2() !dbg !23 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__7DF23CF5_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__7DF23CF5_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @w1() !dbg !25 { ; CHECK: define void @w1() !dbg !25 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__A8764FDD_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__A8764FDD_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @w2() !dbg !26 { ; CHECK: define void @w2() !dbg !26 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__A8764FDD_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__A8764FDD_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @w3() !dbg !28 { ; CHECK: define void @w3() !dbg !28 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__A8764FDD_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__A8764FDD_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @w4() !dbg !30 { ; CHECK: define void @w4() !dbg !30 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__A8764FDD_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__A8764FDD_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @w5() !dbg !32 { ; CHECK: define void @w5() !dbg !32 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__0C712A50_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__0C712A50_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @w6() !dbg !33 { ; CHECK: define void @w6() !dbg !33 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__A3605329_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__A3605329_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @w7() !dbg !34 { ; CHECK: define void @w7() !dbg !34 {
; CHECK: call void @__CheckForDebuggerJustMyCode(i8* noundef @"__0C712A50_x@c") ; CHECK: call void @__CheckForDebuggerJustMyCode(ptr noundef @"__0C712A50_x@c")
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: define void @__JustMyCode_Default(i8* noundef %0) unnamed_addr comdat { ; CHECK: define void @__JustMyCode_Default(ptr noundef %0) unnamed_addr comdat {
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; CHECK: declare void @__CheckForDebuggerJustMyCode(i8* noundef) unnamed_addr ; CHECK: declare void @__CheckForDebuggerJustMyCode(ptr noundef) unnamed_addr
; CHECK: !llvm.linker.options = !{!18} ; CHECK: !llvm.linker.options = !{!18}
; CHECK: !0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) ; CHECK: !0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression())
; CHECK: !1 = distinct !DIGlobalVariable(name: "__7DF23CF5_x@c", scope: !2, file: !3, type: !8, isLocal: true, isDefinition: true) ; CHECK: !1 = distinct !DIGlobalVariable(name: "__7DF23CF5_x@c", scope: !2, file: !3, type: !8, isLocal: true, isDefinition: true)
; CHECK: !2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: !4, splitDebugInlining: false, nameTableKind: None) ; CHECK: !2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: !4, splitDebugInlining: false, nameTableKind: None)
; CHECK: !3 = !DIFile(filename: "a/x.c", directory: "/tmp") ; CHECK: !3 = !DIFile(filename: "a/x.c", directory: "/tmp")
; CHECK: !4 = !{!0, !5, !9, !12} ; CHECK: !4 = !{!0, !5, !9, !12}
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

llvm/test/Instrumentation/MemorySanitizer/SystemZ/vararg-kernel.ll

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; - overflow@(200 + 4) == float %arg11 - right-justified, shadow is 32-bit ; - overflow@(200 + 4) == float %arg11 - right-justified, shadow is 32-bit
; - overflow@208 == i32 sext %arg12 - shadow is sign-extended ; - overflow@208 == i32 sext %arg12 - shadow is sign-extended
; - overflow@216 == double %arg13 - straightforward ; - overflow@216 == double %arg13 - straightforward
; - overflow@224 == i64 %arg14 - straightforward ; - overflow@224 == i64 %arg14 - straightforward
; Overflow arg area size is 72. ; Overflow arg area size is 72.
; CHECK-LABEL: @bar ; CHECK-LABEL: @bar
; CHECK: [[B:%.*]] = ptrtoint [100 x i64]* %va_arg_shadow to i64 ; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64
; CHECK: [[S:%.*]] = add i64 [[B]], 24 ; CHECK: [[S:%.*]] = add i64 [[B]], 24
; CHECK: [[V:%.*]] = zext {{.*}} ; CHECK: [[V:%.*]] = zext {{.*}}
; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to i64* ; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr
; CHECK: store {{.*}} [[V]], {{.*}} [[M]] ; CHECK: store {{.*}} [[V]], {{.*}} [[M]]
; CHECK: [[B:%.*]] = ptrtoint [100 x i64]* %va_arg_shadow to i64 ; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64
; CHECK: [[S:%.*]] = add i64 [[B]], 36 ; CHECK: [[S:%.*]] = add i64 [[B]], 36
; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to i32* ; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr
; CHECK: store {{.*}} [[M]] ; CHECK: store {{.*}} [[M]]
; CHECK: [[B:%.*]] = ptrtoint [100 x i64]* %va_arg_shadow to i64 ; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64
; CHECK: [[S:%.*]] = add i64 [[B]], 40 ; CHECK: [[S:%.*]] = add i64 [[B]], 40
; CHECK: [[V:%.*]] = sext {{.*}} ; CHECK: [[V:%.*]] = sext {{.*}}
; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to i64* ; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr
; CHECK: store {{.*}} [[V]], {{.*}} [[M]] ; CHECK: store {{.*}} [[V]], {{.*}} [[M]]
; CHECK: [[B:%.*]] = ptrtoint [100 x i64]* %va_arg_shadow to i64 ; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64
; CHECK: [[S:%.*]] = add i64 [[B]], 48 ; CHECK: [[S:%.*]] = add i64 [[B]], 48
; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to i64* ; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr
; CHECK: store {{.*}} [[M]] ; CHECK: store {{.*}} [[M]]
; CHECK: [[B:%.*]] = ptrtoint [100 x i64]* %va_arg_shadow to i64 ; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64
; CHECK: [[S:%.*]] = add i64 [[B]], 160 ; CHECK: [[S:%.*]] = add i64 [[B]], 160
; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to i64* ; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr
; CHECK: store {{.*}} [[M]] ; CHECK: store {{.*}} [[M]]
; CHECK: [[B:%.*]] = ptrtoint [100 x i64]* %va_arg_shadow to i64 ; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64
; CHECK: [[S:%.*]] = add i64 [[B]], 168 ; CHECK: [[S:%.*]] = add i64 [[B]], 168
; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to i64* ; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr
; CHECK: store {{.*}} [[M]] ; CHECK: store {{.*}} [[M]]
; CHECK: [[B:%.*]] = ptrtoint [100 x i64]* %va_arg_shadow to i64 ; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64
; CHECK: [[S:%.*]] = add i64 [[B]], 176 ; CHECK: [[S:%.*]] = add i64 [[B]], 176
; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to i64* ; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr
; CHECK: store {{.*}} [[M]] ; CHECK: store {{.*}} [[M]]
; CHECK: [[B:%.*]] = ptrtoint [100 x i64]* %va_arg_shadow to i64 ; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64
; CHECK: [[S:%.*]] = add i64 [[B]], 184 ; CHECK: [[S:%.*]] = add i64 [[B]], 184
; CHECK: [[V:%.*]] = zext {{.*}} ; CHECK: [[V:%.*]] = zext {{.*}}
; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to i64* ; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr
; CHECK: store {{.*}} [[V]], {{.*}} [[M]] ; CHECK: store {{.*}} [[V]], {{.*}} [[M]]
; CHECK: [[B:%.*]] = ptrtoint [100 x i64]* %va_arg_shadow to i64 ; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64
; CHECK: [[S:%.*]] = add i64 [[B]], 192 ; CHECK: [[S:%.*]] = add i64 [[B]], 192
; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to i64* ; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr
; CHECK: store {{.*}} [[M]] ; CHECK: store {{.*}} [[M]]
; CHECK: [[B:%.*]] = ptrtoint [100 x i64]* %va_arg_shadow to i64 ; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64
; CHECK: [[S:%.*]] = add i64 [[B]], 204 ; CHECK: [[S:%.*]] = add i64 [[B]], 204
; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to i32* ; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr
; CHECK: store {{.*}} [[M]] ; CHECK: store {{.*}} [[M]]
; CHECK: [[B:%.*]] = ptrtoint [100 x i64]* %va_arg_shadow to i64 ; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64
; CHECK: [[S:%.*]] = add i64 [[B]], 208 ; CHECK: [[S:%.*]] = add i64 [[B]], 208
; CHECK: [[V:%.*]] = sext {{.*}} ; CHECK: [[V:%.*]] = sext {{.*}}
; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to i64* ; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr
; CHECK: store {{.*}} [[V]], {{.*}} [[M]] ; CHECK: store {{.*}} [[V]], {{.*}} [[M]]
; CHECK: [[B:%.*]] = ptrtoint [100 x i64]* %va_arg_shadow to i64 ; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64
; CHECK: [[S:%.*]] = add i64 [[B]], 216 ; CHECK: [[S:%.*]] = add i64 [[B]], 216
; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to i64* ; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr
; CHECK: store {{.*}} [[M]] ; CHECK: store {{.*}} [[M]]
; CHECK: [[B:%.*]] = ptrtoint [100 x i64]* %va_arg_shadow to i64 ; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64
; CHECK: [[S:%.*]] = add i64 [[B]], 224 ; CHECK: [[S:%.*]] = add i64 [[B]], 224
; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to i64* ; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr
; CHECK: store {{.*}} [[M]] ; CHECK: store {{.*}} [[M]]
; CHECK: store {{.*}} 72, {{.*}} %va_arg_overflow_size ; CHECK: store {{.*}} 72, {{.*}} %va_arg_overflow_size

llvm/test/Instrumentation/MemorySanitizer/X86/vararg-too-large.ll

Show All 23 Lines %ret = call i64 (i64, ...) @sum(i64 120,
i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1 i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1
) )
ret i64 %ret ret i64 %ret
} }
; If the size of __msan_va_arg_tls changes the second argument of `add` must also be changed. ; If the size of __msan_va_arg_tls changes the second argument of `add` must also be changed.
; CHECK-LABEL: @many_args ; CHECK-LABEL: @many_args
; CHECK: i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 792) ; CHECK: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 792)
; CHECK-NOT: i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 800) ; CHECK-NOT: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 800)
declare i64 @sum(i64 %n, ...) declare i64 @sum(i64 %n, ...)

llvm/test/Instrumentation/MemorySanitizer/abs-vector.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt %s -S -msan-check-access-address=0 -passes=msan 2>&1 | FileCheck %s ; RUN: opt %s -S -msan-check-access-address=0 -passes=msan 2>&1 | FileCheck %s
; RUN: opt %s -S -msan-check-access-address=0 -msan-track-origins=2 -passes=msan 2>&1 | FileCheck %s --check-prefixes=CHECK,ORIGIN ; RUN: opt %s -S -msan-check-access-address=0 -msan-track-origins=2 -passes=msan 2>&1 | FileCheck %s --check-prefixes=CHECK,ORIGIN
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define <4 x i64> @test_mm256_abs_epi8(<4 x i64> %a) local_unnamed_addr #0 { define <4 x i64> @test_mm256_abs_epi8(<4 x i64> %a) local_unnamed_addr #0 {
; CHECK-LABEL: @test_mm256_abs_epi8( ; CHECK-LABEL: @test_mm256_abs_epi8(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 ; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4 ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
; CHECK: call void @llvm.donothing() ; CHECK: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <32 x i8> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <32 x i8>
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <32 x i8> ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <32 x i8>
; CHECK-NEXT: [[TMP4:%.*]] = tail call <32 x i8> @llvm.abs.v32i8(<32 x i8> [[TMP3]], i1 false) ; CHECK-NEXT: [[TMP4:%.*]] = tail call <32 x i8> @llvm.abs.v32i8(<32 x i8> [[TMP3]], i1 false)
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <32 x i8> [[TMP2]] to <4 x i64> ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <32 x i8> [[TMP2]] to <4 x i64>
; CHECK-NEXT: [[TMP6:%.*]] = bitcast <32 x i8> [[TMP4]] to <4 x i64> ; CHECK-NEXT: [[TMP6:%.*]] = bitcast <32 x i8> [[TMP4]] to <4 x i64>
; CHECK-NEXT: store <4 x i64> [[TMP5]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 ; CHECK-NEXT: store <4 x i64> [[TMP5]], ptr @__msan_retval_tls, align 8
; ORIGIN-NEXT: store i32 [[TMP1]], i32* @__msan_retval_origin_tls, align 4 ; ORIGIN-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 4
; CHECK: ret <4 x i64> [[TMP6]] ; CHECK: ret <4 x i64> [[TMP6]]
; ;
entry: entry:
%0 = bitcast <4 x i64> %a to <32 x i8> %0 = bitcast <4 x i64> %a to <32 x i8>
%1 = tail call <32 x i8> @llvm.abs.v32i8(<32 x i8> %0, i1 false) %1 = tail call <32 x i8> @llvm.abs.v32i8(<32 x i8> %0, i1 false)
%2 = bitcast <32 x i8> %1 to <4 x i64> %2 = bitcast <32 x i8> %1 to <4 x i64>
ret <4 x i64> %2 ret <4 x i64> %2
} }
define <4 x i64> @test_mm256_abs_epi16(<4 x i64> %a) local_unnamed_addr #0 { define <4 x i64> @test_mm256_abs_epi16(<4 x i64> %a) local_unnamed_addr #0 {
; CHECK-LABEL: @test_mm256_abs_epi16( ; CHECK-LABEL: @test_mm256_abs_epi16(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 ; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4 ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
; CHECK: call void @llvm.donothing() ; CHECK: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <16 x i16> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <16 x i16>
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <16 x i16> ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <16 x i16>
; CHECK-NEXT: [[TMP4:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP3]], i1 false) ; CHECK-NEXT: [[TMP4:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP3]], i1 false)
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i16> [[TMP2]] to <4 x i64> ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i16> [[TMP2]] to <4 x i64>
; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i16> [[TMP4]] to <4 x i64> ; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i16> [[TMP4]] to <4 x i64>
; CHECK-NEXT: store <4 x i64> [[TMP5]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 ; CHECK-NEXT: store <4 x i64> [[TMP5]], ptr @__msan_retval_tls, align 8
; ORIGIN-NEXT: store i32 [[TMP1]], i32* @__msan_retval_origin_tls, align 4 ; ORIGIN-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 4
; CHECK: ret <4 x i64> [[TMP6]] ; CHECK: ret <4 x i64> [[TMP6]]
; ;
entry: entry:
%0 = bitcast <4 x i64> %a to <16 x i16> %0 = bitcast <4 x i64> %a to <16 x i16>
%1 = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> %0, i1 false) %1 = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> %0, i1 false)
%2 = bitcast <16 x i16> %1 to <4 x i64> %2 = bitcast <16 x i16> %1 to <4 x i64>
ret <4 x i64> %2 ret <4 x i64> %2
} }
define <4 x i64> @test_mm256_abs_epi32(<4 x i64> %a) local_unnamed_addr #0 { define <4 x i64> @test_mm256_abs_epi32(<4 x i64> %a) local_unnamed_addr #0 {
; CHECK-LABEL: @test_mm256_abs_epi32( ; CHECK-LABEL: @test_mm256_abs_epi32(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 ; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4 ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
; CHECK: call void @llvm.donothing() ; CHECK: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <8 x i32> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <8 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <8 x i32> ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <8 x i32>
; CHECK-NEXT: [[TMP4:%.*]] = tail call <8 x i32> @llvm.abs.v8i32(<8 x i32> [[TMP3]], i1 false) ; CHECK-NEXT: [[TMP4:%.*]] = tail call <8 x i32> @llvm.abs.v8i32(<8 x i32> [[TMP3]], i1 false)
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to <4 x i64> ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to <4 x i64>
; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP4]] to <4 x i64> ; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP4]] to <4 x i64>
; CHECK-NEXT: store <4 x i64> [[TMP5]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 ; CHECK-NEXT: store <4 x i64> [[TMP5]], ptr @__msan_retval_tls, align 8
; ORIGIN-NEXT: store i32 [[TMP1]], i32* @__msan_retval_origin_tls, align 4 ; ORIGIN-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 4
; CHECK: ret <4 x i64> [[TMP6]] ; CHECK: ret <4 x i64> [[TMP6]]
; ;
entry: entry:
%0 = bitcast <4 x i64> %a to <8 x i32> %0 = bitcast <4 x i64> %a to <8 x i32>
%1 = tail call <8 x i32> @llvm.abs.v8i32(<8 x i32> %0, i1 false) %1 = tail call <8 x i32> @llvm.abs.v8i32(<8 x i32> %0, i1 false)
%2 = bitcast <8 x i32> %1 to <4 x i64> %2 = bitcast <8 x i32> %1 to <4 x i64>
ret <4 x i64> %2 ret <4 x i64> %2
} }
define <4 x double> @test_fabs(<4 x double> %a) local_unnamed_addr #0 { define <4 x double> @test_fabs(<4 x double> %a) local_unnamed_addr #0 {
; CHECK-LABEL: @test_fabs( ; CHECK-LABEL: @test_fabs(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 ; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4 ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
; CHECK: call void @llvm.donothing() ; CHECK: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x double> @llvm.fabs.v4f64(<4 x double> [[A:%.*]]) ; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x double> @llvm.fabs.v4f64(<4 x double> [[A:%.*]])
; CHECK-NEXT: store <4 x i64> [[TMP0]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 ; CHECK-NEXT: store <4 x i64> [[TMP0]], ptr @__msan_retval_tls, align 8
; ORIGIN-NEXT: store i32 [[TMP1]], i32* @__msan_retval_origin_tls, align 4 ; ORIGIN-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 4
; CHECK: ret <4 x double> [[TMP2]] ; CHECK: ret <4 x double> [[TMP2]]
; ;
entry: entry:
%0 = tail call <4 x double> @llvm.fabs.v4f64(<4 x double> %a) %0 = tail call <4 x double> @llvm.fabs.v4f64(<4 x double> %a)
ret <4 x double> %0 ret <4 x double> %0
} }
declare <32 x i8> @llvm.abs.v32i8(<32 x i8>, i1 immarg) #1 declare <32 x i8> @llvm.abs.v32i8(<32 x i8>, i1 immarg) #1
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llvm/test/Instrumentation/MemorySanitizer/array_types.ll

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define [2 x i32] @InsertValue(i32 %x, i32 %y) sanitize_memory { define [2 x i32] @InsertValue(i32 %x, i32 %y) sanitize_memory {
entry: entry:
%a = insertvalue [2 x i32] undef, i32 %x, 0 %a = insertvalue [2 x i32] undef, i32 %x, 0
%b = insertvalue [2 x i32] %a, i32 %y, 1 %b = insertvalue [2 x i32] %a, i32 %y, 1
ret [2 x i32] %b ret [2 x i32] %b
} }
; CHECK-LABEL: @InsertValue( ; CHECK-LABEL: @InsertValue(
; CHECK-DAG: [[Sx:%.*]] = load i32, i32* {{.*}}@__msan_param_tls to i32*) ; CHECK-DAG: [[Sx:%.*]] = load i32, ptr @__msan_param_tls
; CHECK-DAG: [[Sy:%.*]] = load i32, i32* {{.*}}@__msan_param_tls to i64), i64 8) to i32*) ; CHECK-DAG: [[Sy:%.*]] = load i32, ptr {{.*}}@__msan_param_tls to i64), i64 8)
; CHECK: [[A:%.*]] = insertvalue [2 x i32] [i32 -1, i32 -1], i32 [[Sx]], 0 ; CHECK: [[A:%.*]] = insertvalue [2 x i32] [i32 -1, i32 -1], i32 [[Sx]], 0
; CHECK: [[B:%.*]] = insertvalue [2 x i32] [[A]], i32 [[Sy]], 1 ; CHECK: [[B:%.*]] = insertvalue [2 x i32] [[A]], i32 [[Sy]], 1
; CHECK: store [2 x i32] [[B]], [2 x i32]* {{.*}}@__msan_retval_tls ; CHECK: store [2 x i32] [[B]], ptr {{.*}}@__msan_retval_tls
; CHECK: ret [2 x i32] ; CHECK: ret [2 x i32]
define [2 x double] @InsertValueDouble(double %x, double %y) sanitize_memory { define [2 x double] @InsertValueDouble(double %x, double %y) sanitize_memory {
entry: entry:
%a = insertvalue [2 x double] undef, double %x, 0 %a = insertvalue [2 x double] undef, double %x, 0
%b = insertvalue [2 x double] %a, double %y, 1 %b = insertvalue [2 x double] %a, double %y, 1
ret [2 x double] %b ret [2 x double] %b
} }
; CHECK-LABEL: @InsertValueDouble( ; CHECK-LABEL: @InsertValueDouble(
; CHECK-DAG: [[Sx:%.*]] = load i64, i64* getelementptr {{.*}}@__msan_param_tls, i32 0, i32 0 ; CHECK-DAG: [[Sx:%.*]] = load i64, ptr @__msan_param_tls
; CHECK-DAG: [[Sy:%.*]] = load i64, i64* {{.*}}@__msan_param_tls to i64), i64 8) to i64*) ; CHECK-DAG: [[Sy:%.*]] = load i64, ptr {{.*}}@__msan_param_tls to i64), i64 8)
; CHECK: [[A:%.*]] = insertvalue [2 x i64] [i64 -1, i64 -1], i64 [[Sx]], 0 ; CHECK: [[A:%.*]] = insertvalue [2 x i64] [i64 -1, i64 -1], i64 [[Sx]], 0
; CHECK: [[B:%.*]] = insertvalue [2 x i64] [[A]], i64 [[Sy]], 1 ; CHECK: [[B:%.*]] = insertvalue [2 x i64] [[A]], i64 [[Sy]], 1
; CHECK: store [2 x i64] [[B]], [2 x i64]* {{.*}}@__msan_retval_tls ; CHECK: store [2 x i64] [[B]], ptr {{.*}}@__msan_retval_tls
; CHECK: ret [2 x double] ; CHECK: ret [2 x double]
define i32 @ExtractValue([2 x i32] %a) sanitize_memory { define i32 @ExtractValue([2 x i32] %a) sanitize_memory {
entry: entry:
%x = extractvalue [2 x i32] %a, 1 %x = extractvalue [2 x i32] %a, 1
ret i32 %x ret i32 %x
} }
; CHECK-LABEL: @ExtractValue( ; CHECK-LABEL: @ExtractValue(
; CHECK: [[Sa:%.*]] = load [2 x i32], [2 x i32]* {{.*}}@__msan_param_tls to [2 x i32]*) ; CHECK: [[Sa:%.*]] = load [2 x i32], ptr @__msan_param_tls
; CHECK: [[Sx:%.*]] = extractvalue [2 x i32] [[Sa]], 1 ; CHECK: [[Sx:%.*]] = extractvalue [2 x i32] [[Sa]], 1
; CHECK: store i32 [[Sx]], i32* {{.*}}@__msan_retval_tls ; CHECK: store i32 [[Sx]], ptr @__msan_retval_tls
; CHECK: ret i32 ; CHECK: ret i32
; Regression test for PR20493. ; Regression test for PR20493.
%MyStruct = type { i32, i32, [3 x i32] } %MyStruct = type { i32, i32, [3 x i32] }
define i32 @ArrayInStruct(%MyStruct %s) sanitize_memory { define i32 @ArrayInStruct(%MyStruct %s) sanitize_memory {
%x = extractvalue %MyStruct %s, 2, 1 %x = extractvalue %MyStruct %s, 2, 1
ret i32 %x ret i32 %x
} }
; CHECK-LABEL: @ArrayInStruct( ; CHECK-LABEL: @ArrayInStruct(
; CHECK: [[Ss:%.*]] = load { i32, i32, [3 x i32] }, { i32, i32, [3 x i32] }* {{.*}}@__msan_param_tls to { i32, i32, [3 x i32] }*) ; CHECK: [[Ss:%.*]] = load { i32, i32, [3 x i32] }, ptr @__msan_param_tls
; CHECK: [[Sx:%.*]] = extractvalue { i32, i32, [3 x i32] } [[Ss]], 2, 1 ; CHECK: [[Sx:%.*]] = extractvalue { i32, i32, [3 x i32] } [[Ss]], 2, 1
; CHECK: store i32 [[Sx]], i32* {{.*}}@__msan_retval_tls ; CHECK: store i32 [[Sx]], ptr @__msan_retval_tls
; CHECK: ret i32 ; CHECK: ret i32
define i32 @ArrayOfStructs([3 x { i32, i32 }] %a) sanitize_memory { define i32 @ArrayOfStructs([3 x { i32, i32 }] %a) sanitize_memory {
%x = extractvalue [3 x { i32, i32 }] %a, 2, 1 %x = extractvalue [3 x { i32, i32 }] %a, 2, 1
ret i32 %x ret i32 %x
} }
; CHECK-LABEL: @ArrayOfStructs( ; CHECK-LABEL: @ArrayOfStructs(
; CHECK: [[Ss:%.*]] = load [3 x { i32, i32 }], [3 x { i32, i32 }]* {{.*}}@__msan_param_tls to [3 x { i32, i32 }]*) ; CHECK: [[Ss:%.*]] = load [3 x { i32, i32 }], ptr @__msan_param_tls
; CHECK: [[Sx:%.*]] = extractvalue [3 x { i32, i32 }] [[Ss]], 2, 1 ; CHECK: [[Sx:%.*]] = extractvalue [3 x { i32, i32 }] [[Ss]], 2, 1
; CHECK: store i32 [[Sx]], i32* {{.*}}@__msan_retval_tls ; CHECK: store i32 [[Sx]], ptr @__msan_retval_tls
; CHECK: ret i32 ; CHECK: ret i32
define <8 x i16> @ArrayOfVectors([3 x <8 x i16>] %a) sanitize_memory { define <8 x i16> @ArrayOfVectors([3 x <8 x i16>] %a) sanitize_memory {
%x = extractvalue [3 x <8 x i16>] %a, 1 %x = extractvalue [3 x <8 x i16>] %a, 1
ret <8 x i16> %x ret <8 x i16> %x
} }
; CHECK-LABEL: @ArrayOfVectors( ; CHECK-LABEL: @ArrayOfVectors(
; CHECK: [[Ss:%.*]] = load [3 x <8 x i16>], [3 x <8 x i16>]* {{.*}}@__msan_param_tls to [3 x <8 x i16>]*) ; CHECK: [[Ss:%.*]] = load [3 x <8 x i16>], ptr @__msan_param_tls
; CHECK: [[Sx:%.*]] = extractvalue [3 x <8 x i16>] [[Ss]], 1 ; CHECK: [[Sx:%.*]] = extractvalue [3 x <8 x i16>] [[Ss]], 1
; CHECK: store <8 x i16> [[Sx]], <8 x i16>* {{.*}}@__msan_retval_tls ; CHECK: store <8 x i16> [[Sx]], ptr @__msan_retval_tls
; CHECK: ret <8 x i16> ; CHECK: ret <8 x i16>

llvm/test/Instrumentation/MemorySanitizer/bmi.ll

Show All 16 Lines
define i32 @Test_bzhi_32(i32 %a, i32 %b) sanitize_memory { define i32 @Test_bzhi_32(i32 %a, i32 %b) sanitize_memory {
entry: entry:
%c = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %a, i32 %b) %c = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %a, i32 %b)
ret i32 %c ret i32 %c
} }
; CHECK-LABEL: @Test_bzhi_32( ; CHECK-LABEL: @Test_bzhi_32(
; CHECK-DAG: %[[SA:.*]] = load i32, {{.*}}@__msan_param_tls to i32*) ; CHECK-DAG: %[[SA:.*]] = load i32, ptr @__msan_param_tls
; CHECK-DAG: %[[SB:.*]] = load i32, {{.*}}@__msan_param_tls to i64), i64 8) ; CHECK-DAG: %[[SB:.*]] = load i32, {{.*}}@__msan_param_tls to i64), i64 8)
; CHECK-DAG: %[[SB0:.*]] = icmp ne i32 %[[SB]], 0 ; CHECK-DAG: %[[SB0:.*]] = icmp ne i32 %[[SB]], 0
; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i32 ; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i32
; CHECK-DAG: %[[X:.*]] = call i32 @llvm.x86.bmi.bzhi.32(i32 %[[SA]], i32 %b) ; CHECK-DAG: %[[X:.*]] = call i32 @llvm.x86.bmi.bzhi.32(i32 %[[SA]], i32 %b)
; CHECK-DAG: %[[S:.*]] = or i32 %[[SB1]], %[[X]] ; CHECK-DAG: %[[S:.*]] = or i32 %[[SB1]], %[[X]]
; CHECK-DAG: store i32 %[[S]], {{.*}}@__msan_retval_tls ; CHECK-DAG: store i32 %[[S]], {{.*}}@__msan_retval_tls
; CHECK: ret i32 ; CHECK: ret i32
define i64 @Test_bzhi_64(i64 %a, i64 %b) sanitize_memory { define i64 @Test_bzhi_64(i64 %a, i64 %b) sanitize_memory {
entry: entry:
%c = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %a, i64 %b) %c = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %a, i64 %b)
ret i64 %c ret i64 %c
} }
; CHECK-LABEL: @Test_bzhi_64( ; CHECK-LABEL: @Test_bzhi_64(
; CHECK-DAG: %[[SA:.*]] = load i64, {{.*}}@__msan_param_tls, i32 0, i32 0 ; CHECK-DAG: %[[SA:.*]] = load i64, ptr @__msan_param_tls
; CHECK-DAG: %[[SB:.*]] = load i64, {{.*}}@__msan_param_tls to i64), i64 8) ; CHECK-DAG: %[[SB:.*]] = load i64, {{.*}}@__msan_param_tls to i64), i64 8)
; CHECK-DAG: %[[SB0:.*]] = icmp ne i64 %[[SB]], 0 ; CHECK-DAG: %[[SB0:.*]] = icmp ne i64 %[[SB]], 0
; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i64 ; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i64
; CHECK-DAG: %[[X:.*]] = call i64 @llvm.x86.bmi.bzhi.64(i64 %[[SA]], i64 %b) ; CHECK-DAG: %[[X:.*]] = call i64 @llvm.x86.bmi.bzhi.64(i64 %[[SA]], i64 %b)
; CHECK-DAG: %[[S:.*]] = or i64 %[[SB1]], %[[X]] ; CHECK-DAG: %[[S:.*]] = or i64 %[[SB1]], %[[X]]
; CHECK-DAG: store i64 %[[S]], {{.*}}@__msan_retval_tls ; CHECK-DAG: store i64 %[[S]], {{.*}}@__msan_retval_tls
; CHECK: ret i64 ; CHECK: ret i64
define i32 @Test_bextr_32(i32 %a, i32 %b) sanitize_memory { define i32 @Test_bextr_32(i32 %a, i32 %b) sanitize_memory {
entry: entry:
%c = tail call i32 @llvm.x86.bmi.bextr.32(i32 %a, i32 %b) %c = tail call i32 @llvm.x86.bmi.bextr.32(i32 %a, i32 %b)
ret i32 %c ret i32 %c
} }
; CHECK-LABEL: @Test_bextr_32( ; CHECK-LABEL: @Test_bextr_32(
; CHECK-DAG: %[[SA:.*]] = load i32, {{.*}}@__msan_param_tls to i32*) ; CHECK-DAG: %[[SA:.*]] = load i32, ptr @__msan_param_tls
; CHECK-DAG: %[[SB:.*]] = load i32, {{.*}}@__msan_param_tls to i64), i64 8) ; CHECK-DAG: %[[SB:.*]] = load i32, {{.*}}@__msan_param_tls to i64), i64 8)
; CHECK-DAG: %[[SB0:.*]] = icmp ne i32 %[[SB]], 0 ; CHECK-DAG: %[[SB0:.*]] = icmp ne i32 %[[SB]], 0
; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i32 ; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i32
; CHECK-DAG: %[[X:.*]] = call i32 @llvm.x86.bmi.bextr.32(i32 %[[SA]], i32 %b) ; CHECK-DAG: %[[X:.*]] = call i32 @llvm.x86.bmi.bextr.32(i32 %[[SA]], i32 %b)
; CHECK-DAG: %[[S:.*]] = or i32 %[[SB1]], %[[X]] ; CHECK-DAG: %[[S:.*]] = or i32 %[[SB1]], %[[X]]
; CHECK-DAG: store i32 %[[S]], {{.*}}@__msan_retval_tls ; CHECK-DAG: store i32 %[[S]], {{.*}}@__msan_retval_tls
; CHECK: ret i32 ; CHECK: ret i32
define i64 @Test_bextr_64(i64 %a, i64 %b) sanitize_memory { define i64 @Test_bextr_64(i64 %a, i64 %b) sanitize_memory {
entry: entry:
%c = tail call i64 @llvm.x86.bmi.bextr.64(i64 %a, i64 %b) %c = tail call i64 @llvm.x86.bmi.bextr.64(i64 %a, i64 %b)
ret i64 %c ret i64 %c
} }
; CHECK-LABEL: @Test_bextr_64( ; CHECK-LABEL: @Test_bextr_64(
; CHECK-DAG: %[[SA:.*]] = load i64, {{.*}}@__msan_param_tls, i32 0, i32 0 ; CHECK-DAG: %[[SA:.*]] = load i64, ptr @__msan_param_tls
; CHECK-DAG: %[[SB:.*]] = load i64, {{.*}}@__msan_param_tls to i64), i64 8) ; CHECK-DAG: %[[SB:.*]] = load i64, {{.*}}@__msan_param_tls to i64), i64 8)
; CHECK-DAG: %[[SB0:.*]] = icmp ne i64 %[[SB]], 0 ; CHECK-DAG: %[[SB0:.*]] = icmp ne i64 %[[SB]], 0
; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i64 ; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i64
; CHECK-DAG: %[[X:.*]] = call i64 @llvm.x86.bmi.bextr.64(i64 %[[SA]], i64 %b) ; CHECK-DAG: %[[X:.*]] = call i64 @llvm.x86.bmi.bextr.64(i64 %[[SA]], i64 %b)
; CHECK-DAG: %[[S:.*]] = or i64 %[[SB1]], %[[X]] ; CHECK-DAG: %[[S:.*]] = or i64 %[[SB1]], %[[X]]
; CHECK-DAG: store i64 %[[S]], {{.*}}@__msan_retval_tls ; CHECK-DAG: store i64 %[[S]], {{.*}}@__msan_retval_tls
; CHECK: ret i64 ; CHECK: ret i64
define i32 @Test_pdep_32(i32 %a, i32 %b) sanitize_memory { define i32 @Test_pdep_32(i32 %a, i32 %b) sanitize_memory {
entry: entry:
%c = tail call i32 @llvm.x86.bmi.pdep.32(i32 %a, i32 %b) %c = tail call i32 @llvm.x86.bmi.pdep.32(i32 %a, i32 %b)
ret i32 %c ret i32 %c
} }
; CHECK-LABEL: @Test_pdep_32( ; CHECK-LABEL: @Test_pdep_32(
; CHECK-DAG: %[[SA:.*]] = load i32, {{.*}}@__msan_param_tls to i32*) ; CHECK-DAG: %[[SA:.*]] = load i32, ptr @__msan_param_tls
; CHECK-DAG: %[[SB:.*]] = load i32, {{.*}}@__msan_param_tls to i64), i64 8) ; CHECK-DAG: %[[SB:.*]] = load i32, {{.*}}@__msan_param_tls to i64), i64 8)
; CHECK-DAG: %[[SB0:.*]] = icmp ne i32 %[[SB]], 0 ; CHECK-DAG: %[[SB0:.*]] = icmp ne i32 %[[SB]], 0
; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i32 ; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i32
; CHECK-DAG: %[[X:.*]] = call i32 @llvm.x86.bmi.pdep.32(i32 %[[SA]], i32 %b) ; CHECK-DAG: %[[X:.*]] = call i32 @llvm.x86.bmi.pdep.32(i32 %[[SA]], i32 %b)
; CHECK-DAG: %[[S:.*]] = or i32 %[[SB1]], %[[X]] ; CHECK-DAG: %[[S:.*]] = or i32 %[[SB1]], %[[X]]
; CHECK-DAG: store i32 %[[S]], {{.*}}@__msan_retval_tls ; CHECK-DAG: store i32 %[[S]], {{.*}}@__msan_retval_tls
; CHECK: ret i32 ; CHECK: ret i32
define i64 @Test_pdep_64(i64 %a, i64 %b) sanitize_memory { define i64 @Test_pdep_64(i64 %a, i64 %b) sanitize_memory {
entry: entry:
%c = tail call i64 @llvm.x86.bmi.pdep.64(i64 %a, i64 %b) %c = tail call i64 @llvm.x86.bmi.pdep.64(i64 %a, i64 %b)
ret i64 %c ret i64 %c
} }
; CHECK-LABEL: @Test_pdep_64( ; CHECK-LABEL: @Test_pdep_64(
; CHECK-DAG: %[[SA:.*]] = load i64, {{.*}}@__msan_param_tls, i32 0, i32 0 ; CHECK-DAG: %[[SA:.*]] = load i64, ptr @__msan_param_tls
; CHECK-DAG: %[[SB:.*]] = load i64, {{.*}}@__msan_param_tls to i64), i64 8) ; CHECK-DAG: %[[SB:.*]] = load i64, {{.*}}@__msan_param_tls to i64), i64 8)
; CHECK-DAG: %[[SB0:.*]] = icmp ne i64 %[[SB]], 0 ; CHECK-DAG: %[[SB0:.*]] = icmp ne i64 %[[SB]], 0
; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i64 ; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i64
; CHECK-DAG: %[[X:.*]] = call i64 @llvm.x86.bmi.pdep.64(i64 %[[SA]], i64 %b) ; CHECK-DAG: %[[X:.*]] = call i64 @llvm.x86.bmi.pdep.64(i64 %[[SA]], i64 %b)
; CHECK-DAG: %[[S:.*]] = or i64 %[[SB1]], %[[X]] ; CHECK-DAG: %[[S:.*]] = or i64 %[[SB1]], %[[X]]
; CHECK-DAG: store i64 %[[S]], {{.*}}@__msan_retval_tls ; CHECK-DAG: store i64 %[[S]], {{.*}}@__msan_retval_tls
; CHECK: ret i64 ; CHECK: ret i64
define i32 @Test_pext_32(i32 %a, i32 %b) sanitize_memory { define i32 @Test_pext_32(i32 %a, i32 %b) sanitize_memory {
entry: entry:
%c = tail call i32 @llvm.x86.bmi.pext.32(i32 %a, i32 %b) %c = tail call i32 @llvm.x86.bmi.pext.32(i32 %a, i32 %b)
ret i32 %c ret i32 %c
} }
; CHECK-LABEL: @Test_pext_32( ; CHECK-LABEL: @Test_pext_32(
; CHECK-DAG: %[[SA:.*]] = load i32, {{.*}}@__msan_param_tls to i32*) ; CHECK-DAG: %[[SA:.*]] = load i32, ptr @__msan_param_tls
; CHECK-DAG: %[[SB:.*]] = load i32, {{.*}}@__msan_param_tls to i64), i64 8) ; CHECK-DAG: %[[SB:.*]] = load i32, {{.*}}@__msan_param_tls to i64), i64 8)
; CHECK-DAG: %[[SB0:.*]] = icmp ne i32 %[[SB]], 0 ; CHECK-DAG: %[[SB0:.*]] = icmp ne i32 %[[SB]], 0
; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i32 ; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i32
; CHECK-DAG: %[[X:.*]] = call i32 @llvm.x86.bmi.pext.32(i32 %[[SA]], i32 %b) ; CHECK-DAG: %[[X:.*]] = call i32 @llvm.x86.bmi.pext.32(i32 %[[SA]], i32 %b)
; CHECK-DAG: %[[S:.*]] = or i32 %[[SB1]], %[[X]] ; CHECK-DAG: %[[S:.*]] = or i32 %[[SB1]], %[[X]]
; CHECK-DAG: store i32 %[[S]], {{.*}}@__msan_retval_tls ; CHECK-DAG: store i32 %[[S]], {{.*}}@__msan_retval_tls
; CHECK: ret i32 ; CHECK: ret i32
define i64 @Test_pext_64(i64 %a, i64 %b) sanitize_memory { define i64 @Test_pext_64(i64 %a, i64 %b) sanitize_memory {
entry: entry:
%c = tail call i64 @llvm.x86.bmi.pext.64(i64 %a, i64 %b) %c = tail call i64 @llvm.x86.bmi.pext.64(i64 %a, i64 %b)
ret i64 %c ret i64 %c
} }
; CHECK-LABEL: @Test_pext_64( ; CHECK-LABEL: @Test_pext_64(
; CHECK-DAG: %[[SA:.*]] = load i64, {{.*}}@__msan_param_tls, i32 0, i32 0 ; CHECK-DAG: %[[SA:.*]] = load i64, ptr @__msan_param_tls
; CHECK-DAG: %[[SB:.*]] = load i64, {{.*}}@__msan_param_tls to i64), i64 8) ; CHECK-DAG: %[[SB:.*]] = load i64, {{.*}}@__msan_param_tls to i64), i64 8)
; CHECK-DAG: %[[SB0:.*]] = icmp ne i64 %[[SB]], 0 ; CHECK-DAG: %[[SB0:.*]] = icmp ne i64 %[[SB]], 0
; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i64 ; CHECK-DAG: %[[SB1:.*]] = sext i1 %[[SB0]] to i64
; CHECK-DAG: %[[X:.*]] = call i64 @llvm.x86.bmi.pext.64(i64 %[[SA]], i64 %b) ; CHECK-DAG: %[[X:.*]] = call i64 @llvm.x86.bmi.pext.64(i64 %[[SA]], i64 %b)
; CHECK-DAG: %[[S:.*]] = or i64 %[[SB1]], %[[X]] ; CHECK-DAG: %[[S:.*]] = or i64 %[[SB1]], %[[X]]
; CHECK-DAG: store i64 %[[S]], {{.*}}@__msan_retval_tls ; CHECK-DAG: store i64 %[[S]], {{.*}}@__msan_retval_tls
; CHECK: ret i64 ; CHECK: ret i64

llvm/test/Instrumentation/MemorySanitizer/clmul.ll

Show All 10 Lines
define <2 x i64> @clmul00(<2 x i64> %a, <2 x i64> %b) sanitize_memory { define <2 x i64> @clmul00(<2 x i64> %a, <2 x i64> %b) sanitize_memory {
entry: entry:
%0 = tail call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a, <2 x i64> %b, i8 0) %0 = tail call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a, <2 x i64> %b, i8 0)
ret <2 x i64> %0 ret <2 x i64> %0
} }
; CHECK-LABEL: @clmul00 ; CHECK-LABEL: @clmul00
; CHECK: %[[S0:.*]] = load <2 x i64>, <2 x i64>* {{.*}}@__msan_param_tls ; CHECK: %[[S0:.*]] = load <2 x i64>, ptr {{.*}}@__msan_param_tls
; CHECK: %[[S1:.*]] = load <2 x i64>, <2 x i64>* {{.*}}@__msan_param_tls ; CHECK: %[[S1:.*]] = load <2 x i64>, ptr {{.*}}@__msan_param_tls
; CHECK: %[[SHUF0:.*]] = shufflevector <2 x i64> %[[S0]], <2 x i64> poison, <2 x i32> zeroinitializer ; CHECK: %[[SHUF0:.*]] = shufflevector <2 x i64> %[[S0]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK: %[[SHUF1:.*]] = shufflevector <2 x i64> %[[S1]], <2 x i64> poison, <2 x i32> zeroinitializer ; CHECK: %[[SHUF1:.*]] = shufflevector <2 x i64> %[[S1]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK: %[[SRET:.*]] = or <2 x i64> %[[SHUF0]], %[[SHUF1]] ; CHECK: %[[SRET:.*]] = or <2 x i64> %[[SHUF0]], %[[SHUF1]]
; CHECK: store <2 x i64> %[[SRET]], <2 x i64>* {{.*}}@__msan_retval_tls ; CHECK: store <2 x i64> %[[SRET]], ptr {{.*}}@__msan_retval_tls
define <2 x i64> @clmul10(<2 x i64> %a, <2 x i64> %b) sanitize_memory { define <2 x i64> @clmul10(<2 x i64> %a, <2 x i64> %b) sanitize_memory {
entry: entry:
%0 = tail call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a, <2 x i64> %b, i8 16) %0 = tail call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a, <2 x i64> %b, i8 16)
ret <2 x i64> %0 ret <2 x i64> %0
} }
; CHECK-LABEL: @clmul10 ; CHECK-LABEL: @clmul10
; CHECK: %[[S0:.*]] = load <2 x i64>, <2 x i64>* {{.*}}@__msan_param_tls ; CHECK: %[[S0:.*]] = load <2 x i64>, ptr {{.*}}@__msan_param_tls
; CHECK: %[[S1:.*]] = load <2 x i64>, <2 x i64>* {{.*}}@__msan_param_tls ; CHECK: %[[S1:.*]] = load <2 x i64>, ptr {{.*}}@__msan_param_tls
; CHECK: %[[SHUF0:.*]] = shufflevector <2 x i64> %[[S0]], <2 x i64> poison, <2 x i32> zeroinitializer ; CHECK: %[[SHUF0:.*]] = shufflevector <2 x i64> %[[S0]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK: %[[SHUF1:.*]] = shufflevector <2 x i64> %[[S1]], <2 x i64> poison, <2 x i32> <i32 1, i32 1> ; CHECK: %[[SHUF1:.*]] = shufflevector <2 x i64> %[[S1]], <2 x i64> poison, <2 x i32> <i32 1, i32 1>
; CHECK: %[[SRET:.*]] = or <2 x i64> %[[SHUF0]], %[[SHUF1]] ; CHECK: %[[SRET:.*]] = or <2 x i64> %[[SHUF0]], %[[SHUF1]]
; CHECK: store <2 x i64> %[[SRET]], <2 x i64>* {{.*}}@__msan_retval_tls ; CHECK: store <2 x i64> %[[SRET]], ptr {{.*}}@__msan_retval_tls
define <4 x i64> @clmul11_256(<4 x i64> %a, <4 x i64> %b) sanitize_memory { define <4 x i64> @clmul11_256(<4 x i64> %a, <4 x i64> %b) sanitize_memory {
entry: entry:
%0 = tail call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a, <4 x i64> %b, i8 17) %0 = tail call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a, <4 x i64> %b, i8 17)
ret <4 x i64> %0 ret <4 x i64> %0
} }
; CHECK-LABEL: @clmul11_256 ; CHECK-LABEL: @clmul11_256
; CHECK: %[[S0:.*]] = load <4 x i64>, <4 x i64>* {{.*}}@__msan_param_tls ; CHECK: %[[S0:.*]] = load <4 x i64>, ptr {{.*}}@__msan_param_tls
; CHECK: %[[S1:.*]] = load <4 x i64>, <4 x i64>* {{.*}}@__msan_param_tls ; CHECK: %[[S1:.*]] = load <4 x i64>, ptr {{.*}}@__msan_param_tls
; CHECK: %[[SHUF0:.*]] = shufflevector <4 x i64> %[[S0]], <4 x i64> poison, <4 x i32> <i32 1, i32 1, i32 3, i32 3> ; CHECK: %[[SHUF0:.*]] = shufflevector <4 x i64> %[[S0]], <4 x i64> poison, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
; CHECK: %[[SHUF1:.*]] = shufflevector <4 x i64> %[[S1]], <4 x i64> poison, <4 x i32> <i32 1, i32 1, i32 3, i32 3> ; CHECK: %[[SHUF1:.*]] = shufflevector <4 x i64> %[[S1]], <4 x i64> poison, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
; CHECK: %[[SRET:.*]] = or <4 x i64> %[[SHUF0]], %[[SHUF1]] ; CHECK: %[[SRET:.*]] = or <4 x i64> %[[SHUF0]], %[[SHUF1]]
; CHECK: store <4 x i64> %[[SRET]], <4 x i64>* {{.*}}@__msan_retval_tls ; CHECK: store <4 x i64> %[[SRET]], ptr {{.*}}@__msan_retval_tls
define <8 x i64> @clmul01_512(<8 x i64> %a, <8 x i64> %b) sanitize_memory { define <8 x i64> @clmul01_512(<8 x i64> %a, <8 x i64> %b) sanitize_memory {
entry: entry:
%0 = tail call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> %a, <8 x i64> %b, i8 16) %0 = tail call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> %a, <8 x i64> %b, i8 16)
ret <8 x i64> %0 ret <8 x i64> %0
} }
; CHECK-LABEL: @clmul01_512 ; CHECK-LABEL: @clmul01_512
; CHECK: %[[S0:.*]] = load <8 x i64>, <8 x i64>* {{.*}}@__msan_param_tls ; CHECK: %[[S0:.*]] = load <8 x i64>, ptr {{.*}}@__msan_param_tls
; CHECK: %[[S1:.*]] = load <8 x i64>, <8 x i64>* {{.*}}@__msan_param_tls ; CHECK: %[[S1:.*]] = load <8 x i64>, ptr {{.*}}@__msan_param_tls
; CHECK: %[[SHUF0:.*]] = shufflevector <8 x i64> %[[S0]], <8 x i64> poison, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6> ; CHECK: %[[SHUF0:.*]] = shufflevector <8 x i64> %[[S0]], <8 x i64> poison, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
; CHECK: %[[SHUF1:.*]] = shufflevector <8 x i64> %[[S1]], <8 x i64> poison, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7> ; CHECK: %[[SHUF1:.*]] = shufflevector <8 x i64> %[[S1]], <8 x i64> poison, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
; CHECK: %[[SRET:.*]] = or <8 x i64> %[[SHUF0]], %[[SHUF1]] ; CHECK: %[[SRET:.*]] = or <8 x i64> %[[SHUF0]], %[[SHUF1]]
; ORIGIN: %[[FLAT:.*]] = bitcast <8 x i64> %[[SHUF1]] to i512 ; ORIGIN: %[[FLAT:.*]] = bitcast <8 x i64> %[[SHUF1]] to i512
; ORIGIN: %[[I:.*]] = icmp ne i512 %[[FLAT]], 0 ; ORIGIN: %[[I:.*]] = icmp ne i512 %[[FLAT]], 0
; ORIGIN: %[[O:.*]] = select i1 %[[I]], ; ORIGIN: %[[O:.*]] = select i1 %[[I]],
; CHECK: store <8 x i64> %[[SRET]], <8 x i64>* {{.*}}@__msan_retval_tls ; CHECK: store <8 x i64> %[[SRET]], ptr {{.*}}@__msan_retval_tls
; ORIGIN: store i32 %[[O]], i32* @__msan_retval_origin_tls ; ORIGIN: store i32 %[[O]], i32* @__msan_retval_origin_tls

llvm/test/Instrumentation/MemorySanitizer/funnel_shift.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s ; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define void @var_funnel_i64(i64 %a64, <2 x i64> %a128, <4 x i64> %a256, <8 x i64> %a512, i64 %b64, <2 x i64> %b128, <4 x i64> %b256, <8 x i64> %b512, i64 %c64, <2 x i64> %c128, <4 x i64> %c256, <8 x i64> %c512) sanitize_memory { define void @var_funnel_i64(i64 %a64, <2 x i64> %a128, <4 x i64> %a256, <8 x i64> %a512, i64 %b64, <2 x i64> %b128, <4 x i64> %b256, <8 x i64> %b512, i64 %c64, <2 x i64> %c128, <4 x i64> %c256, <8 x i64> %c512) sanitize_memory {
; CHECK-LABEL: @var_funnel_i64( ; CHECK-LABEL: @var_funnel_i64(
; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 120) to i64*), align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 120) to ptr), align 8
; CHECK-NEXT: [[TMP3:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 240) to i64*), align 8 ; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 240) to ptr), align 8
; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <2 x i64>*), align 8 ; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 128) to <2 x i64>*), align 8 ; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 128) to ptr), align 8
; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 248) to <2 x i64>*), align 8 ; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 248) to ptr), align 8
; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <4 x i64>*), align 8 ; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8
; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 144) to <4 x i64>*), align 8 ; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 144) to ptr), align 8
; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 264) to <4 x i64>*), align 8 ; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 264) to ptr), align 8
; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i64>, <8 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 56) to <8 x i64>*), align 8 ; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 56) to ptr), align 8
; CHECK-NEXT: [[TMP11:%.*]] = load <8 x i64>, <8 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 176) to <8 x i64>*), align 8 ; CHECK-NEXT: [[TMP11:%.*]] = load <8 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 176) to ptr), align 8
; CHECK-NEXT: [[TMP12:%.*]] = load <8 x i64>, <8 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 296) to <8 x i64>*), align 8 ; CHECK-NEXT: [[TMP12:%.*]] = load <8 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 296) to ptr), align 8
; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP3]], 0 ; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP3]], 0
; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i64 ; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i64
; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.fshl.i64(i64 [[TMP1]], i64 [[TMP2]], i64 [[C64:%.*]]) ; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.fshl.i64(i64 [[TMP1]], i64 [[TMP2]], i64 [[C64:%.*]])
; CHECK-NEXT: [[TMP16:%.*]] = or i64 [[TMP15]], [[TMP14]] ; CHECK-NEXT: [[TMP16:%.*]] = or i64 [[TMP15]], [[TMP14]]
; CHECK-NEXT: [[I64:%.*]] = call i64 @llvm.fshl.i64(i64 [[A64:%.*]], i64 [[B64:%.*]], i64 [[C64]]) ; CHECK-NEXT: [[I64:%.*]] = call i64 @llvm.fshl.i64(i64 [[A64:%.*]], i64 [[B64:%.*]], i64 [[C64]])
; CHECK-NEXT: [[TMP17:%.*]] = icmp ne <2 x i64> [[TMP6]], zeroinitializer ; CHECK-NEXT: [[TMP17:%.*]] = icmp ne <2 x i64> [[TMP6]], zeroinitializer
; CHECK-NEXT: [[TMP18:%.*]] = sext <2 x i1> [[TMP17]] to <2 x i64> ; CHECK-NEXT: [[TMP18:%.*]] = sext <2 x i1> [[TMP17]] to <2 x i64>
Show All 16 Lines;
%V2I64 = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a128, <2 x i64> %b128, <2 x i64> %c128) %V2I64 = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a128, <2 x i64> %b128, <2 x i64> %c128)
%V4I64 = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a256, <4 x i64> %b256, <4 x i64> %c256) %V4I64 = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a256, <4 x i64> %b256, <4 x i64> %c256)
%V8I64 = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a512, <8 x i64> %b512, <8 x i64> %c512) %V8I64 = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a512, <8 x i64> %b512, <8 x i64> %c512)
ret void ret void
} }
define void @var_funnel_i32(i32 %a32, <4 x i32> %a128, <8 x i32> %a256, <16 x i32> %a512, i32 %b32, <4 x i32> %b128, <8 x i32> %b256, <16 x i32> %b512, i32 %c32, <4 x i32> %c128, <8 x i32> %c256, <16 x i32> %c512) sanitize_memory { define void @var_funnel_i32(i32 %a32, <4 x i32> %a128, <8 x i32> %a256, <16 x i32> %a512, i32 %b32, <4 x i32> %b128, <8 x i32> %b256, <16 x i32> %b512, i32 %c32, <4 x i32> %c128, <8 x i32> %c256, <16 x i32> %c512) sanitize_memory {
; CHECK-LABEL: @var_funnel_i32( ; CHECK-LABEL: @var_funnel_i32(
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* bitcast ([100 x i64]* @__msan_param_tls to i32*), align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 120) to i32*), align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 120) to ptr), align 8
; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 240) to i32*), align 8 ; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 240) to ptr), align 8
; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i32>*), align 8 ; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 128) to <4 x i32>*), align 8 ; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 128) to ptr), align 8
; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 248) to <4 x i32>*), align 8 ; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 248) to ptr), align 8
; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <8 x i32>*), align 8 ; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8
; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 144) to <8 x i32>*), align 8 ; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 144) to ptr), align 8
; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 264) to <8 x i32>*), align 8 ; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 264) to ptr), align 8
; CHECK-NEXT: [[TMP10:%.*]] = load <16 x i32>, <16 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 56) to <16 x i32>*), align 8 ; CHECK-NEXT: [[TMP10:%.*]] = load <16 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 56) to ptr), align 8
; CHECK-NEXT: [[TMP11:%.*]] = load <16 x i32>, <16 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 176) to <16 x i32>*), align 8 ; CHECK-NEXT: [[TMP11:%.*]] = load <16 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 176) to ptr), align 8
; CHECK-NEXT: [[TMP12:%.*]] = load <16 x i32>, <16 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 296) to <16 x i32>*), align 8 ; CHECK-NEXT: [[TMP12:%.*]] = load <16 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 296) to ptr), align 8
; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP3]], 0 ; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP3]], 0
; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i32 ; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i32
; CHECK-NEXT: [[TMP15:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP2]], i32 [[C32:%.*]]) ; CHECK-NEXT: [[TMP15:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP2]], i32 [[C32:%.*]])
; CHECK-NEXT: [[TMP16:%.*]] = or i32 [[TMP15]], [[TMP14]] ; CHECK-NEXT: [[TMP16:%.*]] = or i32 [[TMP15]], [[TMP14]]
; CHECK-NEXT: [[I32:%.*]] = call i32 @llvm.fshl.i32(i32 [[A32:%.*]], i32 [[B32:%.*]], i32 [[C32]]) ; CHECK-NEXT: [[I32:%.*]] = call i32 @llvm.fshl.i32(i32 [[A32:%.*]], i32 [[B32:%.*]], i32 [[C32]])
; CHECK-NEXT: [[TMP17:%.*]] = icmp ne <4 x i32> [[TMP6]], zeroinitializer ; CHECK-NEXT: [[TMP17:%.*]] = icmp ne <4 x i32> [[TMP6]], zeroinitializer
; CHECK-NEXT: [[TMP18:%.*]] = sext <4 x i1> [[TMP17]] to <4 x i32> ; CHECK-NEXT: [[TMP18:%.*]] = sext <4 x i1> [[TMP17]] to <4 x i32>
Show All 16 Lines;
%V2I32 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a128, <4 x i32> %b128, <4 x i32> %c128) %V2I32 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a128, <4 x i32> %b128, <4 x i32> %c128)
%V4I32 = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a256, <8 x i32> %b256, <8 x i32> %c256) %V4I32 = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a256, <8 x i32> %b256, <8 x i32> %c256)
%V8I32 = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a512, <16 x i32> %b512, <16 x i32> %c512) %V8I32 = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a512, <16 x i32> %b512, <16 x i32> %c512)
ret void ret void
} }
define void @var_funnel_i16(i16 %a16, <8 x i16> %a128, <16 x i16> %a256, <32 x i16> %a512, i16 %b16, <8 x i16> %b128, <16 x i16> %b256, <32 x i16> %b512, i16 %c16, <8 x i16> %c128, <16 x i16> %c256, <32 x i16> %c512) sanitize_memory { define void @var_funnel_i16(i16 %a16, <8 x i16> %a128, <16 x i16> %a256, <32 x i16> %a512, i16 %b16, <8 x i16> %b128, <16 x i16> %b256, <32 x i16> %b512, i16 %c16, <8 x i16> %c128, <16 x i16> %c256, <32 x i16> %c512) sanitize_memory {
; CHECK-LABEL: @var_funnel_i16( ; CHECK-LABEL: @var_funnel_i16(
; CHECK-NEXT: [[TMP1:%.*]] = load i16, i16* bitcast ([100 x i64]* @__msan_param_tls to i16*), align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
; CHECK-NEXT: [[TMP2:%.*]] = load i16, i16* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 120) to i16*), align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 120) to ptr), align 8
; CHECK-NEXT: [[TMP3:%.*]] = load i16, i16* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 240) to i16*), align 8 ; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 240) to ptr), align 8
; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <8 x i16>*), align 8 ; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 128) to <8 x i16>*), align 8 ; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 128) to ptr), align 8
; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 248) to <8 x i16>*), align 8 ; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 248) to ptr), align 8
; CHECK-NEXT: [[TMP7:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <16 x i16>*), align 8 ; CHECK-NEXT: [[TMP7:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8
; CHECK-NEXT: [[TMP8:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 144) to <16 x i16>*), align 8 ; CHECK-NEXT: [[TMP8:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 144) to ptr), align 8
; CHECK-NEXT: [[TMP9:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 264) to <16 x i16>*), align 8 ; CHECK-NEXT: [[TMP9:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 264) to ptr), align 8
; CHECK-NEXT: [[TMP10:%.*]] = load <32 x i16>, <32 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 56) to <32 x i16>*), align 8 ; CHECK-NEXT: [[TMP10:%.*]] = load <32 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 56) to ptr), align 8
; CHECK-NEXT: [[TMP11:%.*]] = load <32 x i16>, <32 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 176) to <32 x i16>*), align 8 ; CHECK-NEXT: [[TMP11:%.*]] = load <32 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 176) to ptr), align 8
; CHECK-NEXT: [[TMP12:%.*]] = load <32 x i16>, <32 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 296) to <32 x i16>*), align 8 ; CHECK-NEXT: [[TMP12:%.*]] = load <32 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 296) to ptr), align 8
; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i16 [[TMP3]], 0 ; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i16 [[TMP3]], 0
; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i16 ; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i16
; CHECK-NEXT: [[TMP15:%.*]] = call i16 @llvm.fshl.i16(i16 [[TMP1]], i16 [[TMP2]], i16 [[C16:%.*]]) ; CHECK-NEXT: [[TMP15:%.*]] = call i16 @llvm.fshl.i16(i16 [[TMP1]], i16 [[TMP2]], i16 [[C16:%.*]])
; CHECK-NEXT: [[TMP16:%.*]] = or i16 [[TMP15]], [[TMP14]] ; CHECK-NEXT: [[TMP16:%.*]] = or i16 [[TMP15]], [[TMP14]]
; CHECK-NEXT: [[I16:%.*]] = call i16 @llvm.fshl.i16(i16 [[A16:%.*]], i16 [[B16:%.*]], i16 [[C16]]) ; CHECK-NEXT: [[I16:%.*]] = call i16 @llvm.fshl.i16(i16 [[A16:%.*]], i16 [[B16:%.*]], i16 [[C16]])
; CHECK-NEXT: [[TMP17:%.*]] = icmp ne <8 x i16> [[TMP6]], zeroinitializer ; CHECK-NEXT: [[TMP17:%.*]] = icmp ne <8 x i16> [[TMP6]], zeroinitializer
; CHECK-NEXT: [[TMP18:%.*]] = sext <8 x i1> [[TMP17]] to <8 x i16> ; CHECK-NEXT: [[TMP18:%.*]] = sext <8 x i1> [[TMP17]] to <8 x i16>
Show All 16 Lines;
%V8I16 = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a128, <8 x i16> %b128, <8 x i16> %c128) %V8I16 = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a128, <8 x i16> %b128, <8 x i16> %c128)
%V16I16 = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a256, <16 x i16> %b256, <16 x i16> %c256) %V16I16 = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a256, <16 x i16> %b256, <16 x i16> %c256)
%V32I16 = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a512, <32 x i16> %b512, <32 x i16> %c512) %V32I16 = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a512, <32 x i16> %b512, <32 x i16> %c512)
ret void ret void
} }
define void @var_funnel_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <64 x i8> %a512, i8 %b8, <16 x i8> %b128, <32 x i8> %b256, <64 x i8> %b512, i8 %c8, <16 x i8> %c128, <32 x i8> %c256, <64 x i8> %c512) sanitize_memory { define void @var_funnel_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <64 x i8> %a512, i8 %b8, <16 x i8> %b128, <32 x i8> %b256, <64 x i8> %b512, i8 %c8, <16 x i8> %c128, <32 x i8> %c256, <64 x i8> %c512) sanitize_memory {
; CHECK-LABEL: @var_funnel_i8( ; CHECK-LABEL: @var_funnel_i8(
; CHECK-NEXT: [[TMP1:%.*]] = load i8, i8* bitcast ([100 x i64]* @__msan_param_tls to i8*), align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @__msan_param_tls, align 8
; CHECK-NEXT: [[TMP2:%.*]] = load i8, i8* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 120) to i8*), align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 120) to ptr), align 8
; CHECK-NEXT: [[TMP3:%.*]] = load i8, i8* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 240) to i8*), align 8 ; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 240) to ptr), align 8
; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i8>, <16 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <16 x i8>*), align 8 ; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
; CHECK-NEXT: [[TMP5:%.*]] = load <16 x i8>, <16 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 128) to <16 x i8>*), align 8 ; CHECK-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 128) to ptr), align 8
; CHECK-NEXT: [[TMP6:%.*]] = load <16 x i8>, <16 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 248) to <16 x i8>*), align 8 ; CHECK-NEXT: [[TMP6:%.*]] = load <16 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 248) to ptr), align 8
; CHECK-NEXT: [[TMP7:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <32 x i8>*), align 8 ; CHECK-NEXT: [[TMP7:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8
; CHECK-NEXT: [[TMP8:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 144) to <32 x i8>*), align 8 ; CHECK-NEXT: [[TMP8:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 144) to ptr), align 8
; CHECK-NEXT: [[TMP9:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 264) to <32 x i8>*), align 8 ; CHECK-NEXT: [[TMP9:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 264) to ptr), align 8
; CHECK-NEXT: [[TMP10:%.*]] = load <64 x i8>, <64 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 56) to <64 x i8>*), align 8 ; CHECK-NEXT: [[TMP10:%.*]] = load <64 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 56) to ptr), align 8
; CHECK-NEXT: [[TMP11:%.*]] = load <64 x i8>, <64 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 176) to <64 x i8>*), align 8 ; CHECK-NEXT: [[TMP11:%.*]] = load <64 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 176) to ptr), align 8
; CHECK-NEXT: [[TMP12:%.*]] = load <64 x i8>, <64 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 296) to <64 x i8>*), align 8 ; CHECK-NEXT: [[TMP12:%.*]] = load <64 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 296) to ptr), align 8
; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP3]], 0 ; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP3]], 0
; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i8 ; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i8
; CHECK-NEXT: [[TMP15:%.*]] = call i8 @llvm.fshl.i8(i8 [[TMP1]], i8 [[TMP2]], i8 [[C8:%.*]]) ; CHECK-NEXT: [[TMP15:%.*]] = call i8 @llvm.fshl.i8(i8 [[TMP1]], i8 [[TMP2]], i8 [[C8:%.*]])
; CHECK-NEXT: [[TMP16:%.*]] = or i8 [[TMP15]], [[TMP14]] ; CHECK-NEXT: [[TMP16:%.*]] = or i8 [[TMP15]], [[TMP14]]
; CHECK-NEXT: [[I8:%.*]] = call i8 @llvm.fshl.i8(i8 [[A8:%.*]], i8 [[B8:%.*]], i8 [[C8]]) ; CHECK-NEXT: [[I8:%.*]] = call i8 @llvm.fshl.i8(i8 [[A8:%.*]], i8 [[B8:%.*]], i8 [[C8]])
; CHECK-NEXT: [[TMP17:%.*]] = icmp ne <16 x i8> [[TMP6]], zeroinitializer ; CHECK-NEXT: [[TMP17:%.*]] = icmp ne <16 x i8> [[TMP6]], zeroinitializer
; CHECK-NEXT: [[TMP18:%.*]] = sext <16 x i1> [[TMP17]] to <16 x i8> ; CHECK-NEXT: [[TMP18:%.*]] = sext <16 x i1> [[TMP17]] to <16 x i8>
Show All 16 Lines;
%V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %b128, <16 x i8> %c128) %V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %b128, <16 x i8> %c128)
%V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %b256, <32 x i8> %c256) %V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %b256, <32 x i8> %c256)
%V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %b512, <64 x i8> %c512) %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %b512, <64 x i8> %c512)
ret void ret void
} }
define void @var_rotate_i64(i64 %a64, <2 x i64> %a128, <4 x i64> %a256, <8 x i64> %a512, i64 %c64, <2 x i64> %c128, <4 x i64> %c256, <8 x i64> %c512) sanitize_memory { define void @var_rotate_i64(i64 %a64, <2 x i64> %a128, <4 x i64> %a256, <8 x i64> %a512, i64 %c64, <2 x i64> %c128, <4 x i64> %c256, <8 x i64> %c512) sanitize_memory {
; CHECK-LABEL: @var_rotate_i64( ; CHECK-LABEL: @var_rotate_i64(
; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 120) to i64*), align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 120) to ptr), align 8
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <2 x i64>*), align 8 ; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 128) to <2 x i64>*), align 8 ; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 128) to ptr), align 8
; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <4 x i64>*), align 8 ; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8
; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 144) to <4 x i64>*), align 8 ; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 144) to ptr), align 8
; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i64>, <8 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 56) to <8 x i64>*), align 8 ; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 56) to ptr), align 8
; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i64>, <8 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 176) to <8 x i64>*), align 8 ; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 176) to ptr), align 8
; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[TMP2]], 0
; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i64 ; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i64
; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.fshl.i64(i64 [[TMP1]], i64 [[TMP1]], i64 [[C64:%.*]]) ; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.fshl.i64(i64 [[TMP1]], i64 [[TMP1]], i64 [[C64:%.*]])
; CHECK-NEXT: [[TMP12:%.*]] = or i64 [[TMP11]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = or i64 [[TMP11]], [[TMP10]]
; CHECK-NEXT: [[I64:%.*]] = call i64 @llvm.fshl.i64(i64 [[A64:%.*]], i64 [[A64]], i64 [[C64]]) ; CHECK-NEXT: [[I64:%.*]] = call i64 @llvm.fshl.i64(i64 [[A64:%.*]], i64 [[A64]], i64 [[C64]])
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne <2 x i64> [[TMP4]], zeroinitializer ; CHECK-NEXT: [[TMP13:%.*]] = icmp ne <2 x i64> [[TMP4]], zeroinitializer
; CHECK-NEXT: [[TMP14:%.*]] = sext <2 x i1> [[TMP13]] to <2 x i64> ; CHECK-NEXT: [[TMP14:%.*]] = sext <2 x i1> [[TMP13]] to <2 x i64>
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%V2I64 = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a128, <2 x i64> %a128, <2 x i64> %c128) %V2I64 = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a128, <2 x i64> %a128, <2 x i64> %c128)
%V4I64 = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a256, <4 x i64> %a256, <4 x i64> %c256) %V4I64 = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a256, <4 x i64> %a256, <4 x i64> %c256)
%V8I64 = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a512, <8 x i64> %a512, <8 x i64> %c512) %V8I64 = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a512, <8 x i64> %a512, <8 x i64> %c512)
ret void ret void
} }
define void @var_rotate_i32(i32 %a32, <4 x i32> %a128, <8 x i32> %a256, <16 x i32> %a512, i32 %c32, <4 x i32> %c128, <8 x i32> %c256, <16 x i32> %c512) sanitize_memory { define void @var_rotate_i32(i32 %a32, <4 x i32> %a128, <8 x i32> %a256, <16 x i32> %a512, i32 %c32, <4 x i32> %c128, <8 x i32> %c256, <16 x i32> %c512) sanitize_memory {
; CHECK-LABEL: @var_rotate_i32( ; CHECK-LABEL: @var_rotate_i32(
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* bitcast ([100 x i64]* @__msan_param_tls to i32*), align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 120) to i32*), align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 120) to ptr), align 8
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i32>*), align 8 ; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 128) to <4 x i32>*), align 8 ; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 128) to ptr), align 8
; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <8 x i32>*), align 8 ; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8
; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 144) to <8 x i32>*), align 8 ; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 144) to ptr), align 8
; CHECK-NEXT: [[TMP7:%.*]] = load <16 x i32>, <16 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 56) to <16 x i32>*), align 8 ; CHECK-NEXT: [[TMP7:%.*]] = load <16 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 56) to ptr), align 8
; CHECK-NEXT: [[TMP8:%.*]] = load <16 x i32>, <16 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 176) to <16 x i32>*), align 8 ; CHECK-NEXT: [[TMP8:%.*]] = load <16 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 176) to ptr), align 8
; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP2]], 0 ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP2]], 0
; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i32 ; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i32
; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 [[C32:%.*]]) ; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 [[C32:%.*]])
; CHECK-NEXT: [[TMP12:%.*]] = or i32 [[TMP11]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = or i32 [[TMP11]], [[TMP10]]
; CHECK-NEXT: [[I32:%.*]] = call i32 @llvm.fshl.i32(i32 [[A32:%.*]], i32 [[A32]], i32 [[C32]]) ; CHECK-NEXT: [[I32:%.*]] = call i32 @llvm.fshl.i32(i32 [[A32:%.*]], i32 [[A32]], i32 [[C32]])
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne <4 x i32> [[TMP4]], zeroinitializer ; CHECK-NEXT: [[TMP13:%.*]] = icmp ne <4 x i32> [[TMP4]], zeroinitializer
; CHECK-NEXT: [[TMP14:%.*]] = sext <4 x i1> [[TMP13]] to <4 x i32> ; CHECK-NEXT: [[TMP14:%.*]] = sext <4 x i1> [[TMP13]] to <4 x i32>
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%V2I32 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a128, <4 x i32> %a128, <4 x i32> %c128) %V2I32 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a128, <4 x i32> %a128, <4 x i32> %c128)
%V4I32 = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a256, <8 x i32> %a256, <8 x i32> %c256) %V4I32 = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a256, <8 x i32> %a256, <8 x i32> %c256)
%V8I32 = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a512, <16 x i32> %a512, <16 x i32> %c512) %V8I32 = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a512, <16 x i32> %a512, <16 x i32> %c512)
ret void ret void
} }
define void @var_rotate_i16(i16 %a16, <8 x i16> %a128, <16 x i16> %a256, <32 x i16> %a512, i16 %c16, <8 x i16> %c128, <16 x i16> %c256, <32 x i16> %c512) sanitize_memory { define void @var_rotate_i16(i16 %a16, <8 x i16> %a128, <16 x i16> %a256, <32 x i16> %a512, i16 %c16, <8 x i16> %c128, <16 x i16> %c256, <32 x i16> %c512) sanitize_memory {
; CHECK-LABEL: @var_rotate_i16( ; CHECK-LABEL: @var_rotate_i16(
; CHECK-NEXT: [[TMP1:%.*]] = load i16, i16* bitcast ([100 x i64]* @__msan_param_tls to i16*), align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
; CHECK-NEXT: [[TMP2:%.*]] = load i16, i16* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 120) to i16*), align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 120) to ptr), align 8
; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <8 x i16>*), align 8 ; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 128) to <8 x i16>*), align 8 ; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 128) to ptr), align 8
; CHECK-NEXT: [[TMP5:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <16 x i16>*), align 8 ; CHECK-NEXT: [[TMP5:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8
; CHECK-NEXT: [[TMP6:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 144) to <16 x i16>*), align 8 ; CHECK-NEXT: [[TMP6:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 144) to ptr), align 8
; CHECK-NEXT: [[TMP7:%.*]] = load <32 x i16>, <32 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 56) to <32 x i16>*), align 8 ; CHECK-NEXT: [[TMP7:%.*]] = load <32 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 56) to ptr), align 8
; CHECK-NEXT: [[TMP8:%.*]] = load <32 x i16>, <32 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 176) to <32 x i16>*), align 8 ; CHECK-NEXT: [[TMP8:%.*]] = load <32 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 176) to ptr), align 8
; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i16 [[TMP2]], 0 ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i16 [[TMP2]], 0
; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i16 ; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i16
; CHECK-NEXT: [[TMP11:%.*]] = call i16 @llvm.fshl.i16(i16 [[TMP1]], i16 [[TMP1]], i16 [[C16:%.*]]) ; CHECK-NEXT: [[TMP11:%.*]] = call i16 @llvm.fshl.i16(i16 [[TMP1]], i16 [[TMP1]], i16 [[C16:%.*]])
; CHECK-NEXT: [[TMP12:%.*]] = or i16 [[TMP11]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = or i16 [[TMP11]], [[TMP10]]
; CHECK-NEXT: [[I16:%.*]] = call i16 @llvm.fshl.i16(i16 [[A16:%.*]], i16 [[A16]], i16 [[C16]]) ; CHECK-NEXT: [[I16:%.*]] = call i16 @llvm.fshl.i16(i16 [[A16:%.*]], i16 [[A16]], i16 [[C16]])
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne <8 x i16> [[TMP4]], zeroinitializer ; CHECK-NEXT: [[TMP13:%.*]] = icmp ne <8 x i16> [[TMP4]], zeroinitializer
; CHECK-NEXT: [[TMP14:%.*]] = sext <8 x i1> [[TMP13]] to <8 x i16> ; CHECK-NEXT: [[TMP14:%.*]] = sext <8 x i1> [[TMP13]] to <8 x i16>
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%V8I16 = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a128, <8 x i16> %a128, <8 x i16> %c128) %V8I16 = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a128, <8 x i16> %a128, <8 x i16> %c128)
%V16I16 = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a256, <16 x i16> %a256, <16 x i16> %c256) %V16I16 = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a256, <16 x i16> %a256, <16 x i16> %c256)
%V32I16 = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a512, <32 x i16> %a512, <32 x i16> %c512) %V32I16 = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a512, <32 x i16> %a512, <32 x i16> %c512)
ret void ret void
} }
define void @var_rotate_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <64 x i8> %a512, i8 %c8, <16 x i8> %c128, <32 x i8> %c256, <64 x i8> %c512) sanitize_memory { define void @var_rotate_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <64 x i8> %a512, i8 %c8, <16 x i8> %c128, <32 x i8> %c256, <64 x i8> %c512) sanitize_memory {
; CHECK-LABEL: @var_rotate_i8( ; CHECK-LABEL: @var_rotate_i8(
; CHECK-NEXT: [[TMP1:%.*]] = load i8, i8* bitcast ([100 x i64]* @__msan_param_tls to i8*), align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @__msan_param_tls, align 8
; CHECK-NEXT: [[TMP2:%.*]] = load i8, i8* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 120) to i8*), align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 120) to ptr), align 8
; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, <16 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <16 x i8>*), align 8 ; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i8>, <16 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 128) to <16 x i8>*), align 8 ; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 128) to ptr), align 8
; CHECK-NEXT: [[TMP5:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <32 x i8>*), align 8 ; CHECK-NEXT: [[TMP5:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8
; CHECK-NEXT: [[TMP6:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 144) to <32 x i8>*), align 8 ; CHECK-NEXT: [[TMP6:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 144) to ptr), align 8
; CHECK-NEXT: [[TMP7:%.*]] = load <64 x i8>, <64 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 56) to <64 x i8>*), align 8 ; CHECK-NEXT: [[TMP7:%.*]] = load <64 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 56) to ptr), align 8
; CHECK-NEXT: [[TMP8:%.*]] = load <64 x i8>, <64 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 176) to <64 x i8>*), align 8 ; CHECK-NEXT: [[TMP8:%.*]] = load <64 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 176) to ptr), align 8
; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP2]], 0 ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP2]], 0
; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i8 ; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i8
; CHECK-NEXT: [[TMP11:%.*]] = call i8 @llvm.fshl.i8(i8 [[TMP1]], i8 [[TMP1]], i8 [[C8:%.*]]) ; CHECK-NEXT: [[TMP11:%.*]] = call i8 @llvm.fshl.i8(i8 [[TMP1]], i8 [[TMP1]], i8 [[C8:%.*]])
; CHECK-NEXT: [[TMP12:%.*]] = or i8 [[TMP11]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = or i8 [[TMP11]], [[TMP10]]
; CHECK-NEXT: [[I8:%.*]] = call i8 @llvm.fshl.i8(i8 [[A8:%.*]], i8 [[A8]], i8 [[C8]]) ; CHECK-NEXT: [[I8:%.*]] = call i8 @llvm.fshl.i8(i8 [[A8:%.*]], i8 [[A8]], i8 [[C8]])
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne <16 x i8> [[TMP4]], zeroinitializer ; CHECK-NEXT: [[TMP13:%.*]] = icmp ne <16 x i8> [[TMP4]], zeroinitializer
; CHECK-NEXT: [[TMP14:%.*]] = sext <16 x i1> [[TMP13]] to <16 x i8> ; CHECK-NEXT: [[TMP14:%.*]] = sext <16 x i1> [[TMP13]] to <16 x i8>
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llvm/test/Instrumentation/MemorySanitizer/missing_origin.ll

Show All 9 Lines
define <4 x i32> @Shuffle(<4 x i32> %x) nounwind uwtable sanitize_memory { define <4 x i32> @Shuffle(<4 x i32> %x) nounwind uwtable sanitize_memory {
entry: entry:
%y = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %y = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
ret <4 x i32> %y ret <4 x i32> %y
} }
; CHECK-LABEL: @Shuffle( ; CHECK-LABEL: @Shuffle(
; CHECK: [[A:%.*]] = load i32, i32* {{.*}}@__msan_param_origin_tls, ; CHECK: [[A:%.*]] = load i32, ptr @__msan_param_origin_tls
; CHECK: store i32 [[A]], i32* @__msan_retval_origin_tls ; CHECK: store i32 [[A]], ptr @__msan_retval_origin_tls
; CHECK: ret <4 x i32> ; CHECK: ret <4 x i32>
; Regression test for origin propagation in "select i1, float, float". ; Regression test for origin propagation in "select i1, float, float".
; https://github.com/google/sanitizers/issues/581 ; https://github.com/google/sanitizers/issues/581
define float @SelectFloat(i1 %b, float %x, float %y) nounwind uwtable sanitize_memory { define float @SelectFloat(i1 %b, float %x, float %y) nounwind uwtable sanitize_memory {
entry: entry:
%z = select i1 %b, float %x, float %y %z = select i1 %b, float %x, float %y
ret float %z ret float %z
} }
; CHECK-LABEL: @SelectFloat( ; CHECK-LABEL: @SelectFloat(
; CHECK-NOT: select {{.*}} i32 0, i32 0 ; CHECK-NOT: select {{.*}} i32 0, i32 0
; CHECK: ret float ; CHECK: ret float

llvm/test/Instrumentation/SanitizerCoverage/cmp-tracing-api-x86_32.ll

Show All 13 Lines
; CHECK-DAG: declare void @__sanitizer_cov_trace_cmp8(i64, i64) ; CHECK-DAG: declare void @__sanitizer_cov_trace_cmp8(i64, i64)
; CHECK-DAG: declare void @__sanitizer_cov_trace_const_cmp1(i8 zeroext, i8 zeroext) ; CHECK-DAG: declare void @__sanitizer_cov_trace_const_cmp1(i8 zeroext, i8 zeroext)
; CHECK-DAG: declare void @__sanitizer_cov_trace_const_cmp2(i16 zeroext, i16 zeroext) ; CHECK-DAG: declare void @__sanitizer_cov_trace_const_cmp2(i16 zeroext, i16 zeroext)
; CHECK-DAG: declare void @__sanitizer_cov_trace_const_cmp4(i32 zeroext, i32 zeroext) ; CHECK-DAG: declare void @__sanitizer_cov_trace_const_cmp4(i32 zeroext, i32 zeroext)
; CHECK-DAG: declare void @__sanitizer_cov_trace_const_cmp8(i64, i64) ; CHECK-DAG: declare void @__sanitizer_cov_trace_const_cmp8(i64, i64)
; CHECK-DAG: declare void @__sanitizer_cov_trace_div4(i32 zeroext) ; CHECK-DAG: declare void @__sanitizer_cov_trace_div4(i32 zeroext)
; CHECK-DAG: declare void @__sanitizer_cov_trace_div8(i64) ; CHECK-DAG: declare void @__sanitizer_cov_trace_div8(i64)
; CHECK-DAG: declare void @__sanitizer_cov_trace_gep(i64) ; CHECK-DAG: declare void @__sanitizer_cov_trace_gep(i64)
; CHECK-DAG: declare void @__sanitizer_cov_trace_switch(i64, i64*) ; CHECK-DAG: declare void @__sanitizer_cov_trace_switch(i64, ptr)
; CHECK-DAG: declare void @__sanitizer_cov_trace_pc() ; CHECK-DAG: declare void @__sanitizer_cov_trace_pc()
; CHECK-DAG: declare void @__sanitizer_cov_trace_pc_guard(i32*) ; CHECK-DAG: declare void @__sanitizer_cov_trace_pc_guard(ptr)
; CHECK-DAG: declare void @__sanitizer_cov_trace_pc_guard_init(i32*, i32*) ; CHECK-DAG: declare void @__sanitizer_cov_trace_pc_guard_init(ptr, ptr)
; CHECK-NOT: declare ; CHECK-NOT: declare

llvm/test/Instrumentation/SanitizerCoverage/cmp-tracing-api-x86_64.ll

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; CHECK-DAG: declare void @__sanitizer_cov_trace_pc_indir(i64) ; CHECK-DAG: declare void @__sanitizer_cov_trace_pc_indir(i64)
; CHECK-DAG: declare void @__sanitizer_cov_trace_cmp1(i8 zeroext, i8 zeroext) ; CHECK-DAG: declare void @__sanitizer_cov_trace_cmp1(i8 zeroext, i8 zeroext)
; CHECK-DAG: declare void @__sanitizer_cov_trace_cmp2(i16 zeroext, i16 zeroext) ; CHECK-DAG: declare void @__sanitizer_cov_trace_cmp2(i16 zeroext, i16 zeroext)
; CHECK-DAG: declare void @__sanitizer_cov_trace_cmp4(i32 zeroext, i32 zeroext) ; CHECK-DAG: declare void @__sanitizer_cov_trace_cmp4(i32 zeroext, i32 zeroext)
; CHECK-DAG: declare void @__sanitizer_cov_trace_cmp8(i64, i64) ; CHECK-DAG: declare void @__sanitizer_cov_trace_cmp8(i64, i64)
; CHECK-DAG: declare void @__sanitizer_cov_trace_div4(i32 zeroext) ; CHECK-DAG: declare void @__sanitizer_cov_trace_div4(i32 zeroext)
; CHECK-DAG: declare void @__sanitizer_cov_trace_div8(i64) ; CHECK-DAG: declare void @__sanitizer_cov_trace_div8(i64)
; CHECK-DAG: declare void @__sanitizer_cov_trace_gep(i64) ; CHECK-DAG: declare void @__sanitizer_cov_trace_gep(i64)
; CHECK-DAG: declare void @__sanitizer_cov_trace_switch(i64, i64*) ; CHECK-DAG: declare void @__sanitizer_cov_trace_switch(i64, ptr)
; CHECK-DAG: declare void @__sanitizer_cov_trace_pc() ; CHECK-DAG: declare void @__sanitizer_cov_trace_pc()
; CHECK-DAG: declare void @__sanitizer_cov_trace_pc_guard(i32*) ; CHECK-DAG: declare void @__sanitizer_cov_trace_pc_guard(ptr)
; CHECK-DAG: declare void @__sanitizer_cov_trace_pc_guard_init(i32*, i32*) ; CHECK-DAG: declare void @__sanitizer_cov_trace_pc_guard_init(ptr, ptr)
; CHECK-NOT: declare ; CHECK-NOT: declare

llvm/test/Instrumentation/SanitizerCoverage/coff-comdat.ll

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; CHECK: $foo = comdat nodeduplicate ; CHECK: $foo = comdat nodeduplicate
; CHECK: $bar = comdat nodeduplicate ; CHECK: $bar = comdat nodeduplicate
; Tables for 'foo' should be in the 'foo' comdat. ; Tables for 'foo' should be in the 'foo' comdat.
; CHECK: @__sancov_gen_{{.*}} = private global [1 x i8] zeroinitializer, section ".SCOV$CM", comdat($foo), align 1 ; CHECK: @__sancov_gen_{{.*}} = private global [1 x i8] zeroinitializer, section ".SCOV$CM", comdat($foo), align 1
; CHECK: @__sancov_gen_{{.*}} = private constant [2 x i64*] ; CHECK: @__sancov_gen_{{.*}} = private constant [2 x ptr]
; CHECK-SAME: [i64* bitcast (i32 (i32)* @foo to i64*), i64* inttoptr (i64 1 to i64*)], ; CHECK-SAME: [ptr @foo, ptr inttoptr (i64 1 to ptr)],
; CHECK-SAME: section ".SCOVP$M", comdat($foo), align 8 ; CHECK-SAME: section ".SCOVP$M", comdat($foo), align 8
; Tables for 'bar' should be in the 'bar' comdat. ; Tables for 'bar' should be in the 'bar' comdat.
; CHECK: @__sancov_gen_{{.*}} = private global [1 x i8] zeroinitializer, section ".SCOV$CM", comdat($bar), align 1 ; CHECK: @__sancov_gen_{{.*}} = private global [1 x i8] zeroinitializer, section ".SCOV$CM", comdat($bar), align 1
; CHECK: @__sancov_gen_{{.*}} = private constant [2 x i64*] ; CHECK: @__sancov_gen_{{.*}} = private constant [2 x ptr]
; CHECK-SAME: [i64* bitcast (i32 (i32)* @bar to i64*), i64* inttoptr (i64 1 to i64*)], ; CHECK-SAME: [ptr @bar, ptr inttoptr (i64 1 to ptr)],
; CHECK-SAME: section ".SCOVP$M", comdat($bar), align 8 ; CHECK-SAME: section ".SCOVP$M", comdat($bar), align 8
; 'foo' and 'bar' should be in their new comdat groups. ; 'foo' and 'bar' should be in their new comdat groups.
; CHECK: define dso_local i32 @foo(i32 %x){{.*}} comdat { ; CHECK: define dso_local i32 @foo(i32 %x){{.*}} comdat {
; CHECK: define internal fastcc i32 @bar(i32 %x){{.*}} comdat { ; CHECK: define internal fastcc i32 @bar(i32 %x){{.*}} comdat {
target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
Show All 39 Lines

llvm/test/Instrumentation/SanitizerCoverage/inline-8bit-counters.ll

; Test -sanitizer-coverage-inline-8bit-counters=1 ; Test -sanitizer-coverage-inline-8bit-counters=1
; RUN: opt < %s -passes='module(sancov-module)' -sanitizer-coverage-level=1 -sanitizer-coverage-inline-8bit-counters=1 -S | FileCheck %s ; RUN: opt < %s -passes='module(sancov-module)' -sanitizer-coverage-level=1 -sanitizer-coverage-inline-8bit-counters=1 -S | FileCheck %s
; CHECK: @__sancov_gen_ = private global [1 x i8] zeroinitializer, section "__sancov_cntrs", comdat($foo), align 1 ; CHECK: @__sancov_gen_ = private global [1 x i8] zeroinitializer, section "__sancov_cntrs", comdat($foo), align 1
; CHECK: @__start___sancov_cntrs = extern_weak hidden global i8 ; CHECK: @__start___sancov_cntrs = extern_weak hidden global i8
; CHECK-NEXT: @__stop___sancov_cntrs = extern_weak hidden global i8 ; CHECK-NEXT: @__stop___sancov_cntrs = extern_weak hidden global i8
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define void @foo() { define void @foo() {
entry: entry:
; CHECK: %0 = load i8, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @__sancov_gen_, i64 0, i64 0), align 1, !nosanitize ; CHECK: %0 = load i8, ptr @__sancov_gen_, align 1, !nosanitize
; CHECK: %1 = add i8 %0, 1 ; CHECK: %1 = add i8 %0, 1
; CHECK: store i8 %1, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @__sancov_gen_, i64 0, i64 0), align 1, !nosanitize ; CHECK: store i8 %1, ptr @__sancov_gen_, align 1, !nosanitize
ret void ret void
} }
; CHECK: call void @__sanitizer_cov_8bit_counters_init(i8* @__start___sancov_cntrs, i8* @__stop___sancov_cntrs) ; CHECK: call void @__sanitizer_cov_8bit_counters_init(ptr @__start___sancov_cntrs, ptr @__stop___sancov_cntrs)

llvm/test/Instrumentation/SanitizerCoverage/inline-bool-flag.ll

; Test -sanitizer-coverage-inline-bool-flag=1 ; Test -sanitizer-coverage-inline-bool-flag=1
; RUN: opt < %s -passes='module(sancov-module)' -sanitizer-coverage-level=1 -sanitizer-coverage-inline-bool-flag=1 -S | FileCheck %s ; RUN: opt < %s -passes='module(sancov-module)' -sanitizer-coverage-level=1 -sanitizer-coverage-inline-bool-flag=1 -S | FileCheck %s
; CHECK: $foo = comdat nodeduplicate ; CHECK: $foo = comdat nodeduplicate
; CHECK: @__sancov_gen_ = private global [1 x i1] zeroinitializer, section "__sancov_bools", comdat($foo), align 1{{$}} ; CHECK: @__sancov_gen_ = private global [1 x i1] zeroinitializer, section "__sancov_bools", comdat($foo), align 1{{$}}
; CHECK: @__start___sancov_bools = extern_weak hidden global i1 ; CHECK: @__start___sancov_bools = extern_weak hidden global i1
; CHECK-NEXT: @__stop___sancov_bools = extern_weak hidden global i1 ; CHECK-NEXT: @__stop___sancov_bools = extern_weak hidden global i1
; CHECK: @llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @sancov.module_ctor_bool_flag to i8*)], section "llvm.metadata" ; CHECK: @llvm.used = appending global [1 x ptr] [ptr @sancov.module_ctor_bool_flag], section "llvm.metadata"
; CHECK: @llvm.compiler.used = appending global [1 x i8*] [i8* bitcast ([1 x i1]* @__sancov_gen_ to i8*)], section "llvm.metadata" ; CHECK: @llvm.compiler.used = appending global [1 x ptr] [ptr @__sancov_gen_], section "llvm.metadata"
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define void @foo() { define void @foo() {
; CHECK-LABEL: @foo( ; CHECK-LABEL: @foo(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i1, i1* getelementptr inbounds ([1 x i1], [1 x i1]* @__sancov_gen_, i64 0, i64 0), align 1, !nosanitize ![[#EMPTY:]] ; CHECK-NEXT: [[TMP0:%.*]] = load i1, ptr @__sancov_gen_, align 1, !nosanitize ![[#EMPTY:]]
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i1 [[TMP0]], false ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i1 [[TMP0]], false
; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] ; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]]
; CHECK: 2: ; CHECK: 2:
; CHECK-NEXT: store i1 true, i1* getelementptr inbounds ([1 x i1], [1 x i1]* @__sancov_gen_, i64 0, i64 0), align 1, !nosanitize ![[#EMPTY:]] ; CHECK-NEXT: store i1 true, ptr @__sancov_gen_, align 1, !nosanitize ![[#EMPTY:]]
; CHECK-NEXT: br label [[TMP3]] ; CHECK-NEXT: br label [[TMP3]]
; CHECK: 3: ; CHECK: 3:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
ret void ret void
} }
; CHECK: call void @__sanitizer_cov_bool_flag_init(i1* @__start___sancov_bools, i1* @__stop___sancov_bools) ; CHECK: call void @__sanitizer_cov_bool_flag_init(ptr @__start___sancov_bools, ptr @__stop___sancov_bools)
; CHECK: ![[#EMPTY]] = !{} ; CHECK: ![[#EMPTY]] = !{}

llvm/test/Instrumentation/SanitizerCoverage/switch-tracing.ll

; Test -sanitizer-coverage-trace-compares=1 (instrumenting a switch) ; Test -sanitizer-coverage-trace-compares=1 (instrumenting a switch)
; RUN: opt < %s -passes='module(sancov-module)' -sanitizer-coverage-level=1 -sanitizer-coverage-trace-compares=1 -S | FileCheck %s ; RUN: opt < %s -passes='module(sancov-module)' -sanitizer-coverage-level=1 -sanitizer-coverage-trace-compares=1 -S | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
declare void @_Z3bari(i32) declare void @_Z3bari(i32)
define void @foo(i32 %x) { define void @foo(i32 %x) {
entry: entry:
; CHECK: __sancov_gen_cov_switch_values = internal global [5 x i64] [i64 3, i64 32, i64 1, i64 101, i64 1001] ; CHECK: __sancov_gen_cov_switch_values = internal global [5 x i64] [i64 3, i64 32, i64 1, i64 101, i64 1001]
; CHECK: [[TMP:%[0-9]*]] = zext i32 %x to i64 ; CHECK: [[TMP:%[0-9]*]] = zext i32 %x to i64
; CHECK-NEXT: call void @__sanitizer_cov_trace_switch(i64 [[TMP]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @__sancov_gen_cov_switch_values, i32 0, i32 0)) ; CHECK-NEXT: call void @__sanitizer_cov_trace_switch(i64 [[TMP]], ptr @__sancov_gen_cov_switch_values)
switch i32 %x, label %sw.epilog [ switch i32 %x, label %sw.epilog [
i32 1, label %sw.bb i32 1, label %sw.bb
i32 1001, label %sw.bb.1 i32 1001, label %sw.bb.1
i32 101, label %sw.bb.2 i32 101, label %sw.bb.2
] ]
sw.bb: ; preds = %entry sw.bb: ; preds = %entry
tail call void @_Z3bari(i32 4) tail call void @_Z3bari(i32 4)
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llvm/test/Linker/2003-01-30-LinkerRename.ll

; RUN: llvm-as %S/Inputs/2003-01-30-LinkerRename.ll -o %t.1.bc ; RUN: llvm-as %S/Inputs/2003-01-30-LinkerRename.ll -o %t.1.bc
; RUN: llvm-as %s -o %t.2.bc ; RUN: llvm-as %s -o %t.2.bc
; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s ; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s
; CHECK: @bar = global i32 ()* @foo.2 ; CHECK: @bar = global ptr @foo.2
; CHECK: define internal i32 @foo.2() { ; CHECK: define internal i32 @foo.2() {
; CHECK-NEXT: ret i32 7 ; CHECK-NEXT: ret i32 7
; CHECK-NEXT: } ; CHECK-NEXT: }
; CHECK: define i32 @foo() { ; CHECK: define i32 @foo() {
; CHECK-NEXT: ret i32 0 ; CHECK-NEXT: ret i32 0
; CHECK-NEXT: } ; CHECK-NEXT: }
define i32 @foo() { define i32 @foo() {
ret i32 0 ret i32 0
} }

llvm/test/Linker/2008-07-06-AliasFnDecl.ll

; PR2146 ; PR2146
; RUN: llvm-as %s -o %t1.bc ; RUN: llvm-as %s -o %t1.bc
; RUN: llvm-as %p/2008-07-06-AliasFnDecl2.ll -o %t2.bc ; RUN: llvm-as %p/2008-07-06-AliasFnDecl2.ll -o %t2.bc
; RUN: llvm-link %t1.bc %t2.bc -o %t3.bc ; RUN: llvm-link %t1.bc %t2.bc -o %t3.bc
@b = alias void (), void ()* @a @b = alias void (), ptr @a
define void @a() nounwind { define void @a() nounwind {
entry: entry:
br label %return br label %return
return: return:
ret void ret void
} }

llvm/test/Linker/2008-07-06-AliasWeakDest.ll

; PR2463 ; PR2463
; RUN: llvm-as %s -o %t1.bc ; RUN: llvm-as %s -o %t1.bc
; RUN: llvm-as %p/2008-07-06-AliasWeakDest2.ll -o %t2.bc ; RUN: llvm-as %p/2008-07-06-AliasWeakDest2.ll -o %t2.bc
; RUN: llvm-link %t1.bc %t2.bc -o %t3.bc ; RUN: llvm-link %t1.bc %t2.bc -o %t3.bc
; RUN: llvm-link %t2.bc %t1.bc -o %t4.bc ; RUN: llvm-link %t2.bc %t1.bc -o %t4.bc
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i386-pc-linux-gnu" target triple = "i386-pc-linux-gnu"
@sched_clock = alias i64 (), i64 ()* @native_sched_clock @sched_clock = alias i64 (), ptr @native_sched_clock
@foo = alias i32, i32* @realfoo @foo = alias i32, ptr @realfoo
@realfoo = global i32 0 @realfoo = global i32 0
define i64 @native_sched_clock() nounwind { define i64 @native_sched_clock() nounwind {
entry: entry:
ret i64 0 ret i64 0
} }

llvm/test/Linker/AppendingLinkage.ll

; Test that appending linkage works correctly. ; Test that appending linkage works correctly.
; RUN: echo "@X = appending global [1 x i32] [i32 8] " | \ ; RUN: echo "@X = appending global [1 x i32] [i32 8] " | \
; RUN: llvm-as > %t.2.bc ; RUN: llvm-as > %t.2.bc
; RUN: llvm-as < %s > %t.1.bc ; RUN: llvm-as < %s > %t.1.bc
; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s ; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s
; CHECK: [i32 7, i32 4, i32 8] ; CHECK: [i32 7, i32 4, i32 8]
@X = appending global [2 x i32] [ i32 7, i32 4 ] ; <[2 x i32]*> [#uses=2] @X = appending global [2 x i32] [ i32 7, i32 4 ]
@Y = global i32* getelementptr ([2 x i32], [2 x i32]* @X, i64 0, i64 0) ; <i32**> [#uses=0] @Y = global ptr @X
define void @foo(i64 %V) { define void @foo(i64 %V) {
%Y = getelementptr [2 x i32], [2 x i32]* @X, i64 0, i64 %V ; <i32*> [#uses=0] %Y = getelementptr [2 x i32], ptr @X, i64 0, i64 %V
ret void ret void
} }

llvm/test/Linker/Inputs/2003-01-30-LinkerRename.ll

@bar = global i32()* @foo @bar = global ptr @foo
define internal i32 @foo() { define internal i32 @foo() {
ret i32 7 ret i32 7
} }

llvm/test/Linker/Inputs/only-needed-debug-metadata.ll

@X = external global i32 @X = external global i32
declare i32 @foo() declare i32 @foo()
define void @bar() !dbg !4 { define void @bar() !dbg !4 {
load i32, i32* @X, !dbg !10 load i32, ptr @X, !dbg !10
call i32 @foo(), !dbg !11 call i32 @foo(), !dbg !11
ret void, !dbg !12 ret void, !dbg !12
} }
!llvm.dbg.cu = !{!0} !llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!7, !8} !llvm.module.flags = !{!7, !8}
!llvm.ident = !{!9} !llvm.ident = !{!9}
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llvm/test/Linker/Inputs/pr26037.ll

define i32 @main() #0 !dbg !4 { define i32 @main() #0 !dbg !4 {
entry: entry:
%retval = alloca i32, align 4 %retval = alloca i32, align 4
store i32 0, i32* %retval, align 4 store i32 0, ptr %retval, align 4
ret i32 0, !dbg !11 ret i32 0, !dbg !11
} }
!llvm.dbg.cu = !{!0} !llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!8, !9} !llvm.module.flags = !{!8, !9}
!llvm.ident = !{!10} !llvm.ident = !{!10}
!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 3.8.0 (trunk 256934) (llvm/trunk 256936)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 3.8.0 (trunk 256934) (llvm/trunk 256936)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
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llvm/test/Linker/alias-2.ll

; RUN: llvm-link %s %S/Inputs/alias-2.ll -S -o - | FileCheck %s ; RUN: llvm-link %s %S/Inputs/alias-2.ll -S -o - | FileCheck %s
; RUN: llvm-link %S/Inputs/alias-2.ll %s -S -o - | FileCheck %s ; RUN: llvm-link %S/Inputs/alias-2.ll %s -S -o - | FileCheck %s
; Test the fix for PR26152, where A from the second module is ; Test the fix for PR26152, where A from the second module is
; erroneously renamed to A.1 and not linked to the declaration from ; erroneously renamed to A.1 and not linked to the declaration from
; the first module ; the first module
@C = alias void (), void ()* @A @C = alias void (), ptr @A
define void @D() { define void @D() {
call void @C() call void @C()
ret void ret void
} }
define void @A() { define void @A() {
ret void ret void
} }
; CHECK-DAG: @C = alias void (), void ()* @A ; CHECK-DAG: @C = alias void (), ptr @A
; CHECK-DAG: define void @B() ; CHECK-DAG: define void @B()
; CHECK-DAG: call void @A() ; CHECK-DAG: call void @A()
; CHECK-DAG: define void @D() ; CHECK-DAG: define void @D()
; CHECK-DAG: call void @C() ; CHECK-DAG: call void @C()
; CHECK-DAG: define void @A() ; CHECK-DAG: define void @A()

llvm/test/Linker/alias-threadlocal.ll

; RUN: llvm-link %s %p/Inputs/alias-threadlocal-defs.ll -S -o - | FileCheck %s ; RUN: llvm-link %s %p/Inputs/alias-threadlocal-defs.ll -S -o - | FileCheck %s
; PR46297 ; PR46297
; Verify that linking GlobalAliases preserves the thread_local attribute ; Verify that linking GlobalAliases preserves the thread_local attribute
; CHECK: @tlsvar1 = thread_local global i32 0, align 4 ; CHECK: @tlsvar1 = thread_local global i32 0, align 4
; CHECK: @tlsvar2 = hidden thread_local alias i32, i32* @tlsvar1 ; CHECK: @tlsvar2 = hidden thread_local alias i32, ptr @tlsvar1
@tlsvar2 = external thread_local global i32, align 4 @tlsvar2 = external thread_local global i32, align 4

llvm/test/Linker/comdat-any.ll

Show All 27 Lines
define void @bar() comdat($foo) { define void @bar() comdat($foo) {
ret void ret void
} }
;--- 2.ll ;--- 2.ll
$c1 = comdat any $c1 = comdat any
@v1 = weak_odr global i32 42, comdat($c1) @v1 = weak_odr global i32 42, comdat($c1)
define weak_odr i32 @f1(i8*) comdat($c1) { define weak_odr i32 @f1(ptr) comdat($c1) {
bb10: bb10:
br label %bb11 br label %bb11
bb11: bb11:
ret i32 42 ret i32 42
} }
@r11 = global i32* @v1 @r11 = global ptr @v1
@r12 = global i32 (i8*)* @f1 @r12 = global ptr @f1
@a11 = alias i32, i32* @v1 @a11 = alias i32, ptr @v1
@a12 = alias i16, bitcast (i32* @v1 to i16*) @a12 = alias i16, ptr @v1
@a13 = alias i32 (i8*), i32 (i8*)* @f1 @a13 = alias i32 (ptr), ptr @f1
@a14 = alias i16, bitcast (i32 (i8*)* @f1 to i16*) @a14 = alias i16, ptr @f1
@a15 = alias i16, i16* @a14 @a15 = alias i16, ptr @a14
; CHECK2: $c1 = comdat any ; CHECK2: $c1 = comdat any
; CHECK2: $c2 = comdat any ; CHECK2: $c2 = comdat any
; CHECK2-DAG: @will_be_undefined = external global i32 ; CHECK2-DAG: @will_be_undefined = external global i32
; CHECK2-DAG: @v1 = weak_odr global i32 42, comdat($c1) ; CHECK2-DAG: @v1 = weak_odr global i32 42, comdat($c1)
; CHECK2-DAG: @r11 = global i32* @v1{{$}} ; CHECK2-DAG: @r11 = global ptr @v1{{$}}
; CHECK2-DAG: @r12 = global i32 (i8*)* @f1{{$}} ; CHECK2-DAG: @r12 = global ptr @f1{{$}}
; CHECK2-DAG: @r21 = global i32* @v1{{$}} ; CHECK2-DAG: @r21 = global ptr @v1{{$}}
; CHECK2-DAG: @r22 = global i32 (i8*)* @f1{{$}} ; CHECK2-DAG: @r22 = global ptr @f1{{$}}
; CHECK2-DAG: @v1.1 = internal global i32 41, comdat($c2) ; CHECK2-DAG: @v1.1 = internal global i32 41, comdat($c2)
; CHECK2-DAG: @a11 = alias i32, i32* @v1{{$}} ; CHECK2-DAG: @a11 = alias i32, ptr @v1{{$}}
; CHECK2-DAG: @a12 = alias i16, bitcast (i32* @v1 to i16*) ; CHECK2-DAG: @a12 = alias i16, ptr @v1
; CHECK2-DAG: @a13 = alias i32 (i8*), i32 (i8*)* @f1{{$}} ; CHECK2-DAG: @a13 = alias i32 (ptr), ptr @f1{{$}}
; CHECK2-DAG: @a14 = alias i16, bitcast (i32 (i8*)* @f1 to i16*) ; CHECK2-DAG: @a14 = alias i16, ptr @f1
; CHECK2-DAG: @a21 = alias i32, i32* @v1.1{{$}} ; CHECK2-DAG: @a21 = alias i32, ptr @v1.1{{$}}
; CHECK2-DAG: @a22 = alias i16, bitcast (i32* @v1.1 to i16*) ; CHECK2-DAG: @a22 = alias i16, ptr @v1.1
; CHECK2-DAG: @a23 = alias i32 (i8*), i32 (i8*)* @f1.2{{$}} ; CHECK2-DAG: @a23 = alias i32 (ptr), ptr @f1.2{{$}}
; CHECK2-DAG: @a24 = alias i16, bitcast (i32 (i8*)* @f1.2 to i16*) ; CHECK2-DAG: @a24 = alias i16, ptr @f1.2
; CHECK2: define weak_odr protected i32 @f1(i8* %0) comdat($c1) { ; CHECK2: define weak_odr protected i32 @f1(ptr %0) comdat($c1) {
; CHECK2-NEXT: bb10: ; CHECK2-NEXT: bb10:
; CHECK2-NEXT: br label %bb11{{$}} ; CHECK2-NEXT: br label %bb11{{$}}
; CHECK2: bb11: ; CHECK2: bb11:
; CHECK2-NEXT: ret i32 42 ; CHECK2-NEXT: ret i32 42
; CHECK2-NEXT: } ; CHECK2-NEXT: }
; CHECK2: define internal i32 @f1.2(i8* %this) comdat($c2) { ; CHECK2: define internal i32 @f1.2(ptr %this) comdat($c2) {
; CHECK2-NEXT: bb20: ; CHECK2-NEXT: bb20:
; CHECK2-NEXT: store i8* %this, i8** null ; CHECK2-NEXT: store ptr %this, ptr null
; CHECK2-NEXT: br label %bb21 ; CHECK2-NEXT: br label %bb21
; CHECK2: bb21: ; CHECK2: bb21:
; CHECK2-NEXT: ret i32 41 ; CHECK2-NEXT: ret i32 41
; CHECK2-NEXT: } ; CHECK2-NEXT: }
;--- 2-aux.ll ;--- 2-aux.ll
$c2 = comdat any $c2 = comdat any
$c1 = comdat any $c1 = comdat any
; This is only present in this file. The linker will keep $c1 from the first ; This is only present in this file. The linker will keep $c1 from the first
; file and this will be undefined. ; file and this will be undefined.
@will_be_undefined = global i32 1, comdat($c1) @will_be_undefined = global i32 1, comdat($c1)
@use = global i32* @will_be_undefined @use = global ptr @will_be_undefined
@v1 = weak_odr global i32 41, comdat($c2) @v1 = weak_odr global i32 41, comdat($c2)
define weak_odr protected i32 @f1(i8* %this) comdat($c2) { define weak_odr protected i32 @f1(ptr %this) comdat($c2) {
bb20: bb20:
store i8* %this, i8** null store ptr %this, ptr null
br label %bb21 br label %bb21
bb21: bb21:
ret i32 41 ret i32 41
} }
@r21 = global i32* @v1 @r21 = global ptr @v1
@r22 = global i32(i8*)* @f1 @r22 = global ptr @f1
@a21 = alias i32, i32* @v1 @a21 = alias i32, ptr @v1
@a22 = alias i16, bitcast (i32* @v1 to i16*) @a22 = alias i16, ptr @v1
@a23 = alias i32(i8*), i32(i8*)* @f1 @a23 = alias i32(ptr), ptr @f1
@a24 = alias i16, bitcast (i32(i8*)* @f1 to i16*) @a24 = alias i16, ptr @f1
@a25 = alias i16, i16* @a24 @a25 = alias i16, ptr @a24
;--- 3.ll ;--- 3.ll
; CHECK3: @bar = global i32 0, comdat($a1) ; CHECK3: @bar = global i32 0, comdat($a1)
; CHECK3: @baz = private global i32 42, comdat($a1) ; CHECK3: @baz = private global i32 42, comdat($a1)
; CHECK3: @a1 = internal alias i32, i32* @baz ; CHECK3: @a1 = internal alias i32, ptr @baz
$a1 = comdat any $a1 = comdat any
@bar = global i32 0, comdat($a1) @bar = global i32 0, comdat($a1)
;--- 3-aux.ll ;--- 3-aux.ll
$a1 = comdat any $a1 = comdat any
@baz = private global i32 42, comdat($a1) @baz = private global i32 42, comdat($a1)
@a1 = internal alias i32, i32* @baz @a1 = internal alias i32, ptr @baz
define i32* @abc() { define ptr @abc() {
ret i32* @a1 ret ptr @a1
} }

llvm/test/Linker/ctors2.ll

; RUN: llvm-link -S %s %p/Inputs/ctors2.ll -o - | FileCheck %s ; RUN: llvm-link -S %s %p/Inputs/ctors2.ll -o - | FileCheck %s
$foo = comdat any $foo = comdat any
@foo = global i8 0, comdat @foo = global i8 0, comdat
; CHECK: @llvm.global_ctors = appending global [0 x { i32, void ()*, i8* }] zeroinitializer ; CHECK: @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer
; CHECK: @foo = global i8 0, comdat ; CHECK: @foo = global i8 0, comdat

llvm/test/Linker/ctors3.ll

; RUN: llvm-link -S %s %p/Inputs/ctors3.ll -o - | FileCheck %s ; RUN: llvm-link -S %s %p/Inputs/ctors3.ll -o - | FileCheck %s
$foo = comdat any $foo = comdat any
%t = type { i8 } %t = type { i8 }
@foo = global %t zeroinitializer, comdat @foo = global %t zeroinitializer, comdat
; CHECK: @llvm.global_ctors = appending global [0 x { i32, void ()*, i8* }] zeroinitializer ; CHECK: @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer
; CHECK: @foo = global %t zeroinitializer, comdat ; CHECK: @foo = global %t zeroinitializer, comdat

llvm/test/Linker/funcimport.ll

Show All 10 Lines
; RUN: llvm-lto -thinlto -o %t3 %t.bc %t2.bc ; RUN: llvm-lto -thinlto -o %t3 %t.bc %t2.bc
; Ensure statics are promoted/renamed correctly from this file (all but ; Ensure statics are promoted/renamed correctly from this file (all but
; constant variable need promotion). ; constant variable need promotion).
; RUN: llvm-link %t.bc -summary-index=%t3.thinlto.bc -S | FileCheck %s --check-prefix=EXPORTSTATIC ; RUN: llvm-link %t.bc -summary-index=%t3.thinlto.bc -S | FileCheck %s --check-prefix=EXPORTSTATIC
; EXPORTSTATIC-DAG: @staticvar.llvm.{{.*}} = hidden global ; EXPORTSTATIC-DAG: @staticvar.llvm.{{.*}} = hidden global
; Eventually @staticconstvar can be exported as a copy and not promoted ; Eventually @staticconstvar can be exported as a copy and not promoted
; EXPORTSTATIC-DAG: @staticconstvar.llvm.0 = hidden unnamed_addr constant ; EXPORTSTATIC-DAG: @staticconstvar.llvm.0 = hidden unnamed_addr constant
; EXPORTSTATIC-DAG: @P.llvm.{{.*}} = hidden global void ()* null ; EXPORTSTATIC-DAG: @P.llvm.{{.*}} = hidden global ptr null
; EXPORTSTATIC-DAG: define hidden i32 @staticfunc.llvm. ; EXPORTSTATIC-DAG: define hidden i32 @staticfunc.llvm.
; EXPORTSTATIC-DAG: define hidden void @staticfunc2.llvm. ; EXPORTSTATIC-DAG: define hidden void @staticfunc2.llvm.
; Ensure that both weak alias to an imported function and strong alias to a ; Ensure that both weak alias to an imported function and strong alias to a
; non-imported function are correctly turned into declarations. ; non-imported function are correctly turned into declarations.
; Also ensures that alias to a linkonce function is turned into a declaration ; Also ensures that alias to a linkonce function is turned into a declaration
; and that the associated linkonce function is not in the output, as it is ; and that the associated linkonce function is not in the output, as it is
; lazily linked and never referenced/materialized. ; lazily linked and never referenced/materialized.
Show All 39 Lines
; Ensure that imported static variable and function references are correctly ; Ensure that imported static variable and function references are correctly
; promoted and renamed (including static constant variable). ; promoted and renamed (including static constant variable).
; RUN: llvm-link %t2.bc -summary-index=%t3.thinlto.bc -import=referencestatics:%t.bc -S | FileCheck %s --check-prefix=IMPORTSTATIC ; RUN: llvm-link %t2.bc -summary-index=%t3.thinlto.bc -import=referencestatics:%t.bc -S | FileCheck %s --check-prefix=IMPORTSTATIC
; IMPORTSTATIC-DAG: @staticvar.llvm.{{.*}} = external hidden global ; IMPORTSTATIC-DAG: @staticvar.llvm.{{.*}} = external hidden global
; Eventually @staticconstvar can be imported as a copy ; Eventually @staticconstvar can be imported as a copy
; IMPORTSTATIC-DAG: @staticconstvar.llvm.{{.*}} = external hidden unnamed_addr constant ; IMPORTSTATIC-DAG: @staticconstvar.llvm.{{.*}} = external hidden unnamed_addr constant
; IMPORTSTATIC-DAG: define available_externally i32 @referencestatics ; IMPORTSTATIC-DAG: define available_externally i32 @referencestatics
; IMPORTSTATIC-DAG: %call = call i32 @staticfunc.llvm. ; IMPORTSTATIC-DAG: %call = call i32 @staticfunc.llvm.
; IMPORTSTATIC-DAG: %0 = load i32, i32* @staticvar.llvm. ; IMPORTSTATIC-DAG: %0 = load i32, ptr @staticvar.llvm.
; IMPORTSTATIC-DAG: declare hidden i32 @staticfunc.llvm. ; IMPORTSTATIC-DAG: declare hidden i32 @staticfunc.llvm.
; Ensure that imported global (external) function and variable references ; Ensure that imported global (external) function and variable references
; are handled correctly (including referenced variable imported as ; are handled correctly (including referenced variable imported as
; available_externally definition) ; available_externally definition)
; RUN: llvm-link %t2.bc -summary-index=%t3.thinlto.bc -import=referenceglobals:%t.bc -S | FileCheck %s --check-prefix=IMPORTGLOBALS ; RUN: llvm-link %t2.bc -summary-index=%t3.thinlto.bc -import=referenceglobals:%t.bc -S | FileCheck %s --check-prefix=IMPORTGLOBALS
; IMPORTGLOBALS-DAG: @globalvar = external global ; IMPORTGLOBALS-DAG: @globalvar = external global
; IMPORTGLOBALS-DAG: declare void @globalfunc1() ; IMPORTGLOBALS-DAG: declare void @globalfunc1()
; IMPORTGLOBALS-DAG: define available_externally i32 @referenceglobals ; IMPORTGLOBALS-DAG: define available_externally i32 @referenceglobals
; Ensure that common variable correctly imported as common defition. ; Ensure that common variable correctly imported as common defition.
; RUN: llvm-link %t2.bc -summary-index=%t3.thinlto.bc -import=referencecommon:%t.bc -S | FileCheck %s --check-prefix=IMPORTCOMMON ; RUN: llvm-link %t2.bc -summary-index=%t3.thinlto.bc -import=referencecommon:%t.bc -S | FileCheck %s --check-prefix=IMPORTCOMMON
; IMPORTCOMMON-DAG: @commonvar = external global ; IMPORTCOMMON-DAG: @commonvar = external global
; IMPORTCOMMON-DAG: define available_externally i32 @referencecommon ; IMPORTCOMMON-DAG: define available_externally i32 @referencecommon
; Ensure that imported static function pointer correctly promoted and renamed. ; Ensure that imported static function pointer correctly promoted and renamed.
; RUN: llvm-link %t2.bc -summary-index=%t3.thinlto.bc -import=callfuncptr:%t.bc -S | FileCheck %s --check-prefix=IMPORTFUNCPTR ; RUN: llvm-link %t2.bc -summary-index=%t3.thinlto.bc -import=callfuncptr:%t.bc -S | FileCheck %s --check-prefix=IMPORTFUNCPTR
; IMPORTFUNCPTR-DAG: @P.llvm.{{.*}} = external hidden global void ()* ; IMPORTFUNCPTR-DAG: @P.llvm.{{.*}} = external hidden global ptr
; IMPORTFUNCPTR-DAG: define available_externally void @callfuncptr ; IMPORTFUNCPTR-DAG: define available_externally void @callfuncptr
; IMPORTFUNCPTR-DAG: %0 = load void ()*, void ()** @P.llvm. ; IMPORTFUNCPTR-DAG: %0 = load ptr, ptr @P.llvm.
; Ensure that imported weak function reference/definition handled properly. ; Ensure that imported weak function reference/definition handled properly.
; Imported weak_any definition should be skipped with warning, and imported ; Imported weak_any definition should be skipped with warning, and imported
; reference should turned into an external_weak declaration. ; reference should turned into an external_weak declaration.
; RUN: llvm-link %t2.bc -summary-index=%t3.thinlto.bc -import=callweakfunc:%t.bc -import=weakfunc:%t.bc -S 2>&1 | FileCheck %s --check-prefix=IMPORTWEAKFUNC ; RUN: llvm-link %t2.bc -summary-index=%t3.thinlto.bc -import=callweakfunc:%t.bc -import=weakfunc:%t.bc -S 2>&1 | FileCheck %s --check-prefix=IMPORTWEAKFUNC
; IMPORTWEAKFUNC-DAG: Ignoring import request for weak-any function weakfunc ; IMPORTWEAKFUNC-DAG: Ignoring import request for weak-any function weakfunc
; IMPORTWEAKFUNC-DAG: declare void @weakfunc ; IMPORTWEAKFUNC-DAG: declare void @weakfunc
; IMPORTWEAKFUNC-DAG: define available_externally void @callweakfunc ; IMPORTWEAKFUNC-DAG: define available_externally void @callweakfunc
; IMPORTWEAKFUNC-NOT: @weakvar = extern_weak global i32, align 4 ; IMPORTWEAKFUNC-NOT: @weakvar = extern_weak global i32, align 4
@globalvar = global i32 1, align 4 @globalvar = global i32 1, align 4
@staticvar = internal global i32 1, align 4 @staticvar = internal global i32 1, align 4
@staticconstvar = internal unnamed_addr constant [2 x i32] [i32 10, i32 20], align 4 @staticconstvar = internal unnamed_addr constant [2 x i32] [i32 10, i32 20], align 4
@commonvar = common global i32 0, align 4 @commonvar = common global i32 0, align 4
@P = internal global void ()* null, align 8 @P = internal global ptr null, align 8
@weakalias = weak alias void (...), bitcast (void ()* @globalfunc1 to void (...)*) @weakalias = weak alias void (...), ptr @globalfunc1
@analias = alias void (...), bitcast (void ()* @globalfunc2 to void (...)*) @analias = alias void (...), ptr @globalfunc2
@linkoncealias = alias void (...), bitcast (void ()* @linkoncefunc to void (...)*) @linkoncealias = alias void (...), ptr @linkoncefunc
define void @globalfunc1() #0 { define void @globalfunc1() #0 {
entry: entry:
ret void ret void
} }
define void @globalfunc2() #0 { define void @globalfunc2() #0 {
entry: entry:
ret void ret void
} }
define linkonce_odr void @linkoncefunc() #0 { define linkonce_odr void @linkoncefunc() #0 {
entry: entry:
ret void ret void
} }
define i32 @referencestatics(i32 %i) #0 { define i32 @referencestatics(i32 %i) #0 {
entry: entry:
%i.addr = alloca i32, align 4 %i.addr = alloca i32, align 4
store i32 %i, i32* %i.addr, align 4 store i32 %i, ptr %i.addr, align 4
%call = call i32 @staticfunc() %call = call i32 @staticfunc()
%0 = load i32, i32* @staticvar, align 4 %0 = load i32, ptr @staticvar, align 4
%add = add nsw i32 %call, %0 %add = add nsw i32 %call, %0
%1 = load i32, i32* %i.addr, align 4 %1 = load i32, ptr %i.addr, align 4
%idxprom = sext i32 %1 to i64 %idxprom = sext i32 %1 to i64
%arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* @staticconstvar, i64 0, i64 %idxprom %arrayidx = getelementptr inbounds [2 x i32], ptr @staticconstvar, i64 0, i64 %idxprom
%2 = load i32, i32* %arrayidx, align 4 %2 = load i32, ptr %arrayidx, align 4
%add1 = add nsw i32 %add, %2 %add1 = add nsw i32 %add, %2
ret i32 %add1 ret i32 %add1
} }
define i32 @referenceglobals(i32 %i) #0 { define i32 @referenceglobals(i32 %i) #0 {
entry: entry:
%i.addr = alloca i32, align 4 %i.addr = alloca i32, align 4
store i32 %i, i32* %i.addr, align 4 store i32 %i, ptr %i.addr, align 4
call void @globalfunc1() call void @globalfunc1()
%0 = load i32, i32* @globalvar, align 4 %0 = load i32, ptr @globalvar, align 4
ret i32 %0 ret i32 %0
} }
define i32 @referencecommon(i32 %i) #0 { define i32 @referencecommon(i32 %i) #0 {
entry: entry:
%i.addr = alloca i32, align 4 %i.addr = alloca i32, align 4
store i32 %i, i32* %i.addr, align 4 store i32 %i, ptr %i.addr, align 4
%0 = load i32, i32* @commonvar, align 4 %0 = load i32, ptr @commonvar, align 4
ret i32 %0 ret i32 %0
} }
define void @setfuncptr() #0 { define void @setfuncptr() #0 {
entry: entry:
store void ()* @staticfunc2, void ()** @P, align 8 store ptr @staticfunc2, ptr @P, align 8
ret void ret void
} }
define void @callfuncptr() #0 { define void @callfuncptr() #0 {
entry: entry:
%0 = load void ()*, void ()** @P, align 8 %0 = load ptr, ptr @P, align 8
call void %0() call void %0()
ret void ret void
} }
@weakvar = weak global i32 1, align 4 @weakvar = weak global i32 1, align 4
define weak void @weakfunc() #0 { define weak void @weakfunc() #0 {
entry: entry:
ret void ret void
Show All 17 Lines

llvm/test/Linker/ifunc.ll

; RUN: split-file %s %t ; RUN: split-file %s %t
; RUN: llvm-link %t/a.ll %t/b.ll -S -o - | FileCheck %s ; RUN: llvm-link %t/a.ll %t/b.ll -S -o - | FileCheck %s
;; Check that ifuncs are linked in properly. ;; Check that ifuncs are linked in properly.
; CHECK-DAG: @foo = ifunc void (), void ()* ()* @foo_resolve ; CHECK-DAG: @foo = ifunc void (), ptr @foo_resolve
; CHECK-DAG: define internal void ()* @foo_resolve() { ; CHECK-DAG: define internal ptr @foo_resolve() {
; CHECK-DAG: @bar = ifunc void (), void ()* ()* @bar_resolve ; CHECK-DAG: @bar = ifunc void (), ptr @bar_resolve
; CHECK-DAG: define internal void ()* @bar_resolve() { ; CHECK-DAG: define internal ptr @bar_resolve() {
;--- a.ll ;--- a.ll
declare void @bar() declare void @bar()
;--- b.ll ;--- b.ll
@foo = ifunc void (), void ()* ()* @foo_resolve @foo = ifunc void (), ptr @foo_resolve
@bar = ifunc void (), void ()* ()* @bar_resolve @bar = ifunc void (), ptr @bar_resolve
define internal void ()* @foo_resolve() { define internal ptr @foo_resolve() {
ret void ()* null ret ptr null
} }
define internal void ()* @bar_resolve() { define internal ptr @bar_resolve() {
ret void ()* null ret ptr null
} }

llvm/test/Linker/wrong-addrspace-gv-declaration.ll

; RUN: llvm-link %s %p/Inputs/wrong-addrspace-gv-declaration.ll -S | FileCheck %s ; RUN: llvm-link %s %p/Inputs/wrong-addrspace-gv-declaration.ll -S | FileCheck %s
; RUN: llvm-link %p/Inputs/wrong-addrspace-gv-declaration.ll %s -S | FileCheck %s ; RUN: llvm-link %p/Inputs/wrong-addrspace-gv-declaration.ll %s -S | FileCheck %s
; The address space is declared incorrectly here, so an addrspacecast ; The address space is declared incorrectly here, so an addrspacecast
; is needed to link. ; is needed to link.
@is_really_as1_gv = external global i32 @is_really_as1_gv = external global i32
@is_really_as1_gv_other_type = external global i32 @is_really_as1_gv_other_type = external global i32
; CHECK-LABEL: @foo( ; CHECK-LABEL: @foo(
; CHECK: %load0 = load volatile i32, i32* addrspacecast (i32 addrspace(1)* @is_really_as1_gv to i32*), align 4 ; CHECK: %load0 = load volatile i32, ptr addrspacecast (ptr addrspace(1) @is_really_as1_gv to ptr), align 4
; CHECK: %load1 = load volatile i32, i32* addrspacecast (i32 addrspace(1)* bitcast (float addrspace(1)* @is_really_as1_gv_other_type to i32 addrspace(1)*) to i32*), align 4 ; CHECK: %load1 = load volatile i32, ptr addrspacecast (ptr addrspace(1) @is_really_as1_gv_other_type to ptr), align 4
define void @foo() { define void @foo() {
%load0 = load volatile i32, i32* @is_really_as1_gv, align 4 %load0 = load volatile i32, ptr @is_really_as1_gv, align 4
%load1 = load volatile i32, i32* @is_really_as1_gv_other_type, align 4 %load1 = load volatile i32, ptr @is_really_as1_gv_other_type, align 4
ret void ret void
} }

llvm/test/ThinLTO/X86/Inputs/import-ro-constant-bar.ll

source_filename = "bar.c" source_filename = "bar.c"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@foo = external dso_local local_unnamed_addr constant i32, align 4 @foo = external dso_local local_unnamed_addr constant i32, align 4
define dso_local i32 @_Z3barv() local_unnamed_addr { define dso_local i32 @_Z3barv() local_unnamed_addr {
entry: entry:
%0 = load i32, i32* @foo, align 4 %0 = load i32, ptr @foo, align 4
ret i32 %0 ret i32 %0
} }

llvm/test/ThinLTO/X86/Inputs/module_asm.ll

target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define i32 @main({ i64, { i64, i8* }* } %unnamed) #0 { define i32 @main({ i64, ptr } %unnamed) #0 {
%1 = call i32 @_simplefunction() #1 %1 = call i32 @_simplefunction() #1
ret i32 %1 ret i32 %1
} }
declare i32 @_simplefunction() #1 declare i32 @_simplefunction() #1

llvm/test/ThinLTO/X86/autoupgrade.ll

; Verify that auto-upgrading intrinsics works with Lazy loaded bitcode ; Verify that auto-upgrading intrinsics works with Lazy loaded bitcode
; Do setup work for all below tests: generate bitcode and combined index ; Do setup work for all below tests: generate bitcode and combined index
; RUN: opt -module-summary %s -o %t.bc ; RUN: opt -module-summary %s -o %t.bc
; RUN: llvm-lto -thinlto-action=thinlink -o %t3.bc %t.bc %p/Inputs/autoupgrade.bc ; RUN: llvm-lto -thinlto-action=thinlink -o %t3.bc %t.bc %p/Inputs/autoupgrade.bc
; We can't use llvm-dis here, because it would do the autoupgrade itself. ; We can't use llvm-dis here, because it would do the autoupgrade itself.
; RUN: llvm-link -summary-index=%t3.bc \ ; RUN: llvm-link -summary-index=%t3.bc \
; RUN: -import=globalfunc1:%p/Inputs/autoupgrade.bc %t.bc \ ; RUN: -import=globalfunc1:%p/Inputs/autoupgrade.bc %t.bc \
; RUN: | llvm-bcanalyzer -dump | FileCheck %s ; RUN: | llvm-bcanalyzer -dump | FileCheck %s
; CHECK: <STRTAB_BLOCK ; CHECK: <STRTAB_BLOCK
; CHECK-NEXT: blob data = 'mainglobalfunc1llvm.invariant.start.p0i8{{.*}}' ; CHECK-NEXT: blob data = 'mainglobalfunc1llvm.invariant.start.p0{{.*}}'
; Check that the summary is able to print the names despite the lack of ; Check that the summary is able to print the names despite the lack of
; string table in the legacy bitcode. ; string table in the legacy bitcode.
; RUN: llvm-dis %p/Inputs/autoupgrade.bc -o - \ ; RUN: llvm-dis %p/Inputs/autoupgrade.bc -o - \
; RUN: | FileCheck %s --check-prefix=SUMMARYNAMES ; RUN: | FileCheck %s --check-prefix=SUMMARYNAMES
; SUMMARYNAMES: ^2 = gv: (name: "globalfunc2", ; SUMMARYNAMES: ^2 = gv: (name: "globalfunc2",
; SUMMARYNAMES: ^3 = gv: (name: "globalfunc1" ; SUMMARYNAMES: ^3 = gv: (name: "globalfunc1"
Show All 10 Lines

llvm/test/ThinLTO/X86/deadstrip.ll

Show First 20 Lines • Show All 133 Lines • ▼ Show 20 Lines
; We also can't eliminate @baz because it is in the regular LTO partition ; We also can't eliminate @baz because it is in the regular LTO partition
; and called from @dead_func. ; and called from @dead_func.
; CHECK-NM-NOTDEAD: T _baz ; CHECK-NM-NOTDEAD: T _baz
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.11.0" target triple = "x86_64-apple-macosx10.11.0"
@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @_GLOBAL__I_a, i8* null }] @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__I_a, ptr null }]
declare void @baz() declare void @baz()
declare void @boo() declare void @boo()
define internal void @_GLOBAL__I_a() #1 section "__TEXT,__StaticInit,regular,pure_instructions" { define internal void @_GLOBAL__I_a() #1 section "__TEXT,__StaticInit,regular,pure_instructions" {
entry: entry:
call void @boo() call void @boo()
Show All 27 Lines
define available_externally void @live_available_externally_func() { define available_externally void @live_available_externally_func() {
ret void ret void
} }
; This alias will set its base object in this file (linkonceodrfuncwithalias) ; This alias will set its base object in this file (linkonceodrfuncwithalias)
; alive. ; alive.
; We want to make sure the @linkonceodrfuncwithalias copy in Input/deadstrip.ll ; We want to make sure the @linkonceodrfuncwithalias copy in Input/deadstrip.ll
; is also scanned when computing reachability. ; is also scanned when computing reachability.
@linkonceodralias = linkonce_odr alias void (), void ()* @linkonceodrfuncwithalias @linkonceodralias = linkonce_odr alias void (), ptr @linkonceodrfuncwithalias
define linkonce_odr void @linkonceodrfuncwithalias() { define linkonce_odr void @linkonceodrfuncwithalias() {
entry: entry:
ret void ret void
} }
define void @linkonceodrfuncwithalias_caller() { define void @linkonceodrfuncwithalias_caller() {
entry: entry:
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llvm/test/ThinLTO/X86/dot-dumper2.ll

Show All 32 Lines
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@A = external local_unnamed_addr global i32, align 4 @A = external local_unnamed_addr global i32, align 4
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define i32 @main() local_unnamed_addr { define i32 @main() local_unnamed_addr {
store i32 42, i32* @A, align 4 store i32 42, ptr @A, align 4
ret i32 0 ret i32 0
} }

llvm/test/ThinLTO/X86/funcimport-debug.ll

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; CHECK-DAG: edge -> 6699318081062747564 (foo) Threshold:100 ; CHECK-DAG: edge -> 6699318081062747564 (foo) Threshold:100
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.11.0" target triple = "x86_64-apple-macosx10.11.0"
define i32 @main() #0 { define i32 @main() #0 {
entry: entry:
call void (...) @foo() call void (...) @foo()
%0 = load i32, i32* @baz, align 4 %0 = load i32, ptr @baz, align 4
ret i32 %0 ret i32 %0
} }
declare void @foo(...) #1 declare void @foo(...) #1
@baz = external global i32 @baz = external global i32

llvm/test/ThinLTO/X86/globals-import-const-fold.ll

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; OPTIMIZE-NEXT: ret i32 10 ; OPTIMIZE-NEXT: ret i32 10
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-pc-linux-gnu" target triple = "x86_64-pc-linux-gnu"
@baz = external local_unnamed_addr constant i32, align 4 @baz = external local_unnamed_addr constant i32, align 4
define i32 @main() local_unnamed_addr { define i32 @main() local_unnamed_addr {
%1 = load i32, i32* @baz, align 4 %1 = load i32, ptr @baz, align 4
ret i32 %1 ret i32 %1
} }

llvm/test/ThinLTO/X86/import-dsolocal.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Linesdefine i32 @main() {
ret i32 0 ret i32 0
} }
;--- b.ll ;--- b.ll
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@a = dso_local global i32 42, align 4 @a = dso_local global i32 42, align 4
@b = dso_local global i32* @a, align 8 @b = dso_local global ptr @a, align 8
define dso_local void @extern() { define dso_local void @extern() {
call i32 @extern_aux(i32* @a, i32** @b) call i32 @extern_aux(ptr @a, ptr @b)
ret void ret void
} }
define dso_local i32 @extern_aux(i32* %a, i32** %b) { define dso_local i32 @extern_aux(ptr %a, ptr %b) {
%p = load i32*, i32** %b, align 8 %p = load ptr, ptr %b, align 8
store i32 33, i32* %p, align 4 store i32 33, ptr %p, align 4
%v = load i32, i32* %a, align 4 %v = load i32, ptr %a, align 4
ret i32 %v ret i32 %v
} }
define linkonce dso_local void @linkonce() { define linkonce dso_local void @linkonce() {
call i32 @linkonce_aux(i32* @a, i32** @b) call i32 @linkonce_aux(ptr @a, ptr @b)
ret void ret void
} }
define linkonce i32 @linkonce_aux(i32* %a, i32** %b) { define linkonce i32 @linkonce_aux(ptr %a, ptr %b) {
%p = load i32*, i32** %b, align 8 %p = load ptr, ptr %b, align 8
store i32 33, i32* %p, align 4 store i32 33, ptr %p, align 4
%v = load i32, i32* %a, align 4 %v = load i32, ptr %a, align 4
ret i32 %v ret i32 %v
} }
define linkonce_odr dso_local void @linkonceodr() { define linkonce_odr dso_local void @linkonceodr() {
call i32 @linkonceodr_aux(i32* @a, i32** @b) call i32 @linkonceodr_aux(ptr @a, ptr @b)
ret void ret void
} }
define linkonce_odr i32 @linkonceodr_aux(i32* %a, i32** %b) { define linkonce_odr i32 @linkonceodr_aux(ptr %a, ptr %b) {
%p = load i32*, i32** %b, align 8 %p = load ptr, ptr %b, align 8
store i32 33, i32* %p, align 4 store i32 33, ptr %p, align 4
%v = load i32, i32* %a, align 4 %v = load i32, ptr %a, align 4
ret i32 %v ret i32 %v
} }
define weak dso_local void @weak() { define weak dso_local void @weak() {
call i32 @weak_aux(i32* @a, i32** @b) call i32 @weak_aux(ptr @a, ptr @b)
ret void ret void
} }
define weak i32 @weak_aux(i32* %a, i32** %b) { define weak i32 @weak_aux(ptr %a, ptr %b) {
%p = load i32*, i32** %b, align 8 %p = load ptr, ptr %b, align 8
store i32 33, i32* %p, align 4 store i32 33, ptr %p, align 4
%v = load i32, i32* %a, align 4 %v = load i32, ptr %a, align 4
ret i32 %v ret i32 %v
} }
define weak_odr dso_local void @weakodr() { define weak_odr dso_local void @weakodr() {
call i32 @weakodr_aux(i32* @a, i32** @b) call i32 @weakodr_aux(ptr @a, ptr @b)
ret void ret void
} }
define weak_odr i32 @weakodr_aux(i32* %a, i32** %b) { define weak_odr i32 @weakodr_aux(ptr %a, ptr %b) {
%p = load i32*, i32** %b, align 8 %p = load ptr, ptr %b, align 8
store i32 33, i32* %p, align 4 store i32 33, ptr %p, align 4
%v = load i32, i32* %a, align 4 %v = load i32, ptr %a, align 4
ret i32 %v ret i32 %v
} }

llvm/test/ThinLTO/X86/import-ro-constant.ll

Show All 20 Lines
source_filename = "main.c" source_filename = "main.c"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@foo = external dso_local local_unnamed_addr constant i32, align 4 @foo = external dso_local local_unnamed_addr constant i32, align 4
define dso_local i32 @main() local_unnamed_addr { define dso_local i32 @main() local_unnamed_addr {
entry: entry:
%0 = load i32, i32* @foo, align 4 %0 = load i32, ptr @foo, align 4
%call = tail call i32 @_Z3barv() %call = tail call i32 @_Z3barv()
%add = add nsw i32 %call, %0 %add = add nsw i32 %call, %0
ret i32 %add ret i32 %add
} }
declare dso_local i32 @_Z3barv() local_unnamed_addr declare dso_local i32 @_Z3barv() local_unnamed_addr

llvm/test/ThinLTO/X86/index-const-prop-comdat.ll

; RUN: opt -module-summary %s -o %t1.bc ; RUN: opt -module-summary %s -o %t1.bc
; RUN: opt -module-summary %p/Inputs/index-const-prop-comdat.ll -o %t2.bc ; RUN: opt -module-summary %p/Inputs/index-const-prop-comdat.ll -o %t2.bc
; RUN: llvm-lto2 run -save-temps %t2.bc -r=%t2.bc,g,pl %t1.bc -r=%t1.bc,main,plx -r=%t1.bc,g, -o %t3 ; RUN: llvm-lto2 run -save-temps %t2.bc -r=%t2.bc,g,pl %t1.bc -r=%t1.bc,main,plx -r=%t1.bc,g, -o %t3
; RUN: llvm-dis %t3.2.3.import.bc -o - | FileCheck %s ; RUN: llvm-dis %t3.2.3.import.bc -o - | FileCheck %s
; Comdats are not internalized even if they are read only. ; Comdats are not internalized even if they are read only.
; CHECK: @g = available_externally global i32 42 ; CHECK: @g = available_externally global i32 42
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@g = external global i32 @g = external global i32
define i32 @main() { define i32 @main() {
%v = load i32, i32* @g %v = load i32, ptr @g
ret i32 %v ret i32 %v
} }

llvm/test/ThinLTO/X86/index-const-prop-full-lto.ll

Show All 12 Lines
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
declare i32 @foo() declare i32 @foo()
@g = external global i32 @g = external global i32
define i32 @main() { define i32 @main() {
%v = call i32 @foo() %v = call i32 @foo()
%v2 = load i32, i32* @g %v2 = load i32, ptr @g
%v3 = add i32 %v, %v2 %v3 = add i32 %v, %v2
ret i32 %v3 ret i32 %v3
} }

llvm/test/ThinLTO/X86/index-const-prop-ldst.ll

; RUN: opt -module-summary %s -o %t1.bc ; RUN: opt -module-summary %s -o %t1.bc
; RUN: opt -module-summary %p/Inputs/index-const-prop-define-g.ll -o %t2.bc ; RUN: opt -module-summary %p/Inputs/index-const-prop-define-g.ll -o %t2.bc
; RUN: llvm-lto2 run -save-temps %t2.bc -r=%t2.bc,g,pl %t1.bc -r=%t1.bc,main,plx -r=%t1.bc,g, -o %t3 ; RUN: llvm-lto2 run -save-temps %t2.bc -r=%t2.bc,g,pl %t1.bc -r=%t1.bc,main,plx -r=%t1.bc,g, -o %t3
; RUN: llvm-dis %t3.2.3.import.bc -o - | FileCheck %s ; RUN: llvm-dis %t3.2.3.import.bc -o - | FileCheck %s
; The 'store' instruction in @main should prevent internalization ; The 'store' instruction in @main should prevent internalization
; even when there is 'load' instruction before it. ; even when there is 'load' instruction before it.
; CHECK: @g = available_externally global i32 42 ; CHECK: @g = available_externally global i32 42
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@g = external global i32 @g = external global i32
define i32 @main() { define i32 @main() {
%v = load i32, i32* @g %v = load i32, ptr @g
%q = add i32 %v, 1 %q = add i32 %v, 1
store i32 %q, i32* @g store i32 %q, ptr @g
ret i32 %v ret i32 %v
} }

llvm/test/ThinLTO/X86/personality-local.ll

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; CHECK-NEXT: Section: .text ; CHECK-NEXT: Section: .text
; CHECK-NEXT: } ; CHECK-NEXT: }
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-pc-linux-gnu" target triple = "x86_64-pc-linux-gnu"
declare void @foo() declare void @foo()
define void @bar() personality i32 (i32, i32, i64, i8*, i8*)* @personality_routine { define void @bar() personality ptr @personality_routine {
ret void ret void
} }
define internal i32 @personality_routine(i32, i32, i64, i8*, i8*) { define internal i32 @personality_routine(i32, i32, i64, ptr, ptr) {
call void @foo() call void @foo()
ret i32 0 ret i32 0
} }
define i32 @main() { define i32 @main() {
call void @bar() call void @bar()
ret i32 0 ret i32 0
} }

llvm/test/ThinLTO/X86/referenced_by_constant.ll

; Do setup work for all below tests: generate bitcode and combined index ; Do setup work for all below tests: generate bitcode and combined index
; RUN: opt -module-summary %s -o %t.bc ; RUN: opt -module-summary %s -o %t.bc
; RUN: opt -module-summary %p/Inputs/referenced_by_constant.ll -o %t2.bc ; RUN: opt -module-summary %p/Inputs/referenced_by_constant.ll -o %t2.bc
; RUN: llvm-lto -thinlto-action=thinlink -o %t3.bc %t.bc %t2.bc ; RUN: llvm-lto -thinlto-action=thinlink -o %t3.bc %t.bc %t2.bc
; Check the import side: we currently import bar() and also promote/import ; Check the import side: we currently import bar() and also promote/import
; referenced constant objects. There is stll a room for improvement: we ; referenced constant objects. There is stll a room for improvement: we
; can make a local copy of someglobal and someglobal2 because they are both ; can make a local copy of someglobal and someglobal2 because they are both
; 'unnamed_addr' constants. This should eventually be done as well. ; 'unnamed_addr' constants. This should eventually be done as well.
; RUN: llvm-lto -thinlto-action=import -import-constants-with-refs %t.bc -thinlto-index=%t3.bc -o - | llvm-dis -o - | FileCheck %s --check-prefix=IMPORT ; RUN: llvm-lto -thinlto-action=import -import-constants-with-refs %t.bc -thinlto-index=%t3.bc -o - | llvm-dis -o - | FileCheck %s --check-prefix=IMPORT
; IMPORT: @someglobal.llvm.0 = available_externally hidden unnamed_addr constant i8* bitcast (void ()* @referencedbyglobal to i8*) ; IMPORT: @someglobal.llvm.0 = available_externally hidden unnamed_addr constant ptr @referencedbyglobal
; IMPORT: @someglobal2.llvm.0 = available_externally hidden unnamed_addr constant i8* bitcast (void ()* @localreferencedbyglobal.llvm.0 to i8*) ; IMPORT: @someglobal2.llvm.0 = available_externally hidden unnamed_addr constant ptr @localreferencedbyglobal.llvm.0
; IMPORT: define available_externally void @bar() ; IMPORT: define available_externally void @bar()
; Check the export side: we currently only export bar(), which causes ; Check the export side: we currently only export bar(), which causes
; @someglobal and @someglobal2 to be promoted (see above). ; @someglobal and @someglobal2 to be promoted (see above).
; RUN: llvm-lto -thinlto-action=promote -import-constants-with-refs %t2.bc -thinlto-index=%t3.bc -o - | llvm-dis -o - | FileCheck %s --check-prefix=EXPORT ; RUN: llvm-lto -thinlto-action=promote -import-constants-with-refs %t2.bc -thinlto-index=%t3.bc -o - | llvm-dis -o - | FileCheck %s --check-prefix=EXPORT
; EXPORT: @someglobal.llvm.0 = hidden unnamed_addr constant ; EXPORT: @someglobal.llvm.0 = hidden unnamed_addr constant
; EXPORT: @someglobal2.llvm.0 = hidden unnamed_addr constant ; EXPORT: @someglobal2.llvm.0 = hidden unnamed_addr constant
; EXPORT: define void @referencedbyglobal() ; EXPORT: define void @referencedbyglobal()
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llvm/test/ThinLTO/X86/weak_globals_import.ll

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;--- 1.ll ;--- 1.ll
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@G = weak dso_local local_unnamed_addr global i32 0, align 4 @G = weak dso_local local_unnamed_addr global i32 0, align 4
define dso_local i32 @main() local_unnamed_addr { define dso_local i32 @main() local_unnamed_addr {
%1 = load i32, i32* @G, align 4 %1 = load i32, ptr @G, align 4
ret i32 %1 ret i32 %1
} }
;--- 2.ll ;--- 2.ll
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@G = dso_local local_unnamed_addr global i32 42, align 4 @G = dso_local local_unnamed_addr global i32 42, align 4

llvm/test/Transforms/BlockExtractor/extract-blocks-with-groups.ll

; Extract the 'if', 'then', and 'else' blocks into the same function. ; Extract the 'if', 'then', and 'else' blocks into the same function.
; RUN: echo 'foo if;then;else' > %t ; RUN: echo 'foo if;then;else' > %t
; Make sure we can still extract a single basic block ; Make sure we can still extract a single basic block
; RUN: echo 'foo end' >> %t ; RUN: echo 'foo end' >> %t
; RUN: echo 'bar bb14;bb20' >> %t ; RUN: echo 'bar bb14;bb20' >> %t
; RUN: opt -S -extract-blocks -extract-blocks-file=%t %s | FileCheck %s ; RUN: opt -S -extract-blocks -extract-blocks-file=%t %s | FileCheck %s
; CHECK-LABEL: foo ; CHECK-LABEL: foo
; ;
; CHECK: if: ; CHECK: if:
; The diamond will produce an i32 value, make sure we account for that. ; The diamond will produce an i32 value, make sure we account for that.
; CHECK: [[RES_VAL_ADDR:%[^ ]*]] = alloca i32 ; CHECK: [[RES_VAL_ADDR:%[^ ]*]] = alloca i32
; CHECK-NEXT: br label %[[FOO_DIAMOND_LABEL:.*$]] ; CHECK-NEXT: br label %[[FOO_DIAMOND_LABEL:.*$]]
; ;
; The if-then-else blocks should be in just one function. ; The if-then-else blocks should be in just one function.
; CHECK: [[FOO_DIAMOND_LABEL]]: ; CHECK: [[FOO_DIAMOND_LABEL]]:
; CHECK: call void [[FOO_DIAMOND:@[^(]*]](i32 %arg1, i32 %arg, i32* [[RES_VAL_ADDR]]) ; CHECK: call void [[FOO_DIAMOND:@[^(]*]](i32 %arg1, i32 %arg, ptr [[RES_VAL_ADDR]])
; CHECK-NEXT: [[RES_VAL:%[^ ]*]] = load i32, i32* [[RES_VAL_ADDR]] ; CHECK-NEXT: [[RES_VAL:%[^ ]*]] = load i32, ptr [[RES_VAL_ADDR]]
; Then it should directly jump to end. ; Then it should directly jump to end.
; CHECK: br label %[[FOO_END_LABEL:.*$]] ; CHECK: br label %[[FOO_END_LABEL:.*$]]
; ;
; End should have been extracted into its own function. ; End should have been extracted into its own function.
; CHECK: [[FOO_END_LABEL]]: ; CHECK: [[FOO_END_LABEL]]:
; CHECK: [[CMP:%[^ ]*]] = call i1 [[FOO_END:@[^(]*]](i32 [[RES_VAL]], i32 %arg) ; CHECK: [[CMP:%[^ ]*]] = call i1 [[FOO_END:@[^(]*]](i32 [[RES_VAL]], i32 %arg)
; CHECK-NEXT: br i1 [[CMP]], label %ret0, label %ret1 ; CHECK-NEXT: br i1 [[CMP]], label %ret0, label %ret1
define i32 @foo(i32 %arg, i32 %arg1) { define i32 @foo(i32 %arg, i32 %arg1) {
Show All 29 Lines
; CHECK-LABEL: bar ; CHECK-LABEL: bar
; ;
; Check that we extracted bb14 and bb20 in their own (shared) function. ; Check that we extracted bb14 and bb20 in their own (shared) function.
; CHECK: bb ; CHECK: bb
; CHECK: br i1 %or.cond, label %bb9, label %[[BAR_DIAMOND_LABEL:.*$]] ; CHECK: br i1 %or.cond, label %bb9, label %[[BAR_DIAMOND_LABEL:.*$]]
; ;
; CHECK: [[BAR_DIAMOND_LABEL]]: ; CHECK: [[BAR_DIAMOND_LABEL]]:
; CHECK: [[CMP:%[^ ]*]] = call i1 [[BAR_DIAMOND:@[^(]*]](i32 %arg1, i32 %arg, i32* ; CHECK: [[CMP:%[^ ]*]] = call i1 [[BAR_DIAMOND:@[^(]*]](i32 %arg1, i32 %arg, ptr
; CHECK: br i1 [[CMP]], label %bb26, label %bb30 ; CHECK: br i1 [[CMP]], label %bb26, label %bb30
define i32 @bar(i32 %arg, i32 %arg1) { define i32 @bar(i32 %arg, i32 %arg1) {
bb: bb:
%tmp5 = icmp sgt i32 %arg, 0 %tmp5 = icmp sgt i32 %arg, 0
%tmp8 = icmp sgt i32 %arg1, 0 %tmp8 = icmp sgt i32 %arg1, 0
%or.cond = and i1 %tmp5, %tmp8 %or.cond = and i1 %tmp5, %tmp8
br i1 %or.cond, label %bb9, label %bb14 br i1 %or.cond, label %bb9, label %bb14
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/test/Transforms/CodeExtractor/PartialInlineAttributes.ll

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define i32 @caller(i32 %v) ssp { define i32 @caller(i32 %v) ssp {
entry: entry:
%c1 = call i32 @callee_most(i32 %v) %c1 = call i32 @callee_most(i32 %v)
%c2 = call i32 @callee_noinline(i32 %v) %c2 = call i32 @callee_noinline(i32 %v)
%c3 = call i32 @callee_writeonly(i32 %v) %c3 = call i32 @callee_writeonly(i32 %v)
ret i32 %c3 ret i32 %c3
} }
; CHECK: define internal void @callee_writeonly.1.if.then(i32 %v, i32* %sub.out) [[FN_ATTRS0:#[0-9]+]] ; CHECK: define internal void @callee_writeonly.1.if.then(i32 %v, ptr %sub.out) [[FN_ATTRS0:#[0-9]+]]
; CHECK: define internal void @callee_most.2.if.then(i32 %v, i32* %sub.out) [[FN_ATTRS:#[0-9]+]] ; CHECK: define internal void @callee_most.2.if.then(i32 %v, ptr %sub.out) [[FN_ATTRS:#[0-9]+]]
; attributes to preserve ; attributes to preserve
attributes #0 = { attributes #0 = {
inlinehint minsize noduplicate noimplicitfloat norecurse noredzone nounwind inlinehint minsize noduplicate noimplicitfloat norecurse noredzone nounwind
nonlazybind optsize safestack sanitize_address sanitize_hwaddress sanitize_memory nonlazybind optsize safestack sanitize_address sanitize_hwaddress sanitize_memory
sanitize_thread ssp sspreq sspstrong uwtable "foo"="bar" sanitize_thread ssp sspreq sspstrong uwtable "foo"="bar"
"patchable-function"="prologue-short-redirect" "probe-stack"="_foo_guard" "stack-probe-size"="4096" } "patchable-function"="prologue-short-redirect" "probe-stack"="_foo_guard" "stack-probe-size"="4096" }
; CHECK: attributes [[FN_ATTRS0]] = { ssp ; CHECK: attributes [[FN_ATTRS0]] = { ssp
; CHECK: attributes [[FN_ATTRS]] = { inlinehint minsize noduplicate noimplicitfloat norecurse noredzone nounwind nonlazybind optsize safestack sanitize_address sanitize_hwaddress sanitize_memory sanitize_thread ssp sspreq sspstrong uwtable "foo"="bar" "patchable-function"="prologue-short-redirect" "probe-stack"="_foo_guard" "stack-probe-size"="4096" } ; CHECK: attributes [[FN_ATTRS]] = { inlinehint minsize noduplicate noimplicitfloat norecurse noredzone nounwind nonlazybind optsize safestack sanitize_address sanitize_hwaddress sanitize_memory sanitize_thread ssp sspreq sspstrong uwtable "foo"="bar" "patchable-function"="prologue-short-redirect" "probe-stack"="_foo_guard" "stack-probe-size"="4096" }
; attributes to drop ; attributes to drop
attributes #1 = { attributes #1 = {
alignstack=16 convergent inaccessiblememonly inaccessiblemem_or_argmemonly naked alignstack=16 convergent inaccessiblememonly inaccessiblemem_or_argmemonly naked
noreturn readonly argmemonly returns_twice speculatable "thunk" noreturn readonly argmemonly returns_twice speculatable "thunk"
} }

llvm/test/Transforms/CodeExtractor/PartialInlineDebug.ll

Show All 18 Linesif.end: ; preds = %if.then, %entry
%v2 = phi i32 [ %v, %entry ], [ %mul, %if.then2 ] %v2 = phi i32 [ %v, %entry ], [ %mul, %if.then2 ]
%add = add nsw i32 %v2, 200 %add = add nsw i32 %v2, 200
ret i32 %add ret i32 %add
} }
; CHECK-LABEL: @caller ; CHECK-LABEL: @caller
; CHECK: codeRepl.i: ; CHECK: codeRepl.i:
; CHECK-NOT: br label ; CHECK-NOT: br label
; CHECK: call void @callee.2.if.then(i32 %v, i32* %mul.loc.i), !dbg ![[DBG2:[0-9]+]] ; CHECK: call void @callee.2.if.then(i32 %v, ptr %mul.loc.i), !dbg ![[DBG2:[0-9]+]]
define i32 @caller(i32 %v) !dbg !8 { define i32 @caller(i32 %v) !dbg !8 {
entry: entry:
%call = call i32 @callee(i32 %v), !dbg !14 %call = call i32 @callee(i32 %v), !dbg !14
ret i32 %call ret i32 %call
} }
; CHECK-LABEL: @callee2 ; CHECK-LABEL: @callee2
Show All 14 Linesif.end:
%v2 = phi i32 [ %v, %entry ], [ %sub, %if.then2 ] %v2 = phi i32 [ %v, %entry ], [ %sub, %if.then2 ]
%add = add nsw i32 %v2, 200 %add = add nsw i32 %v2, 200
ret i32 %add ret i32 %add
} }
; CHECK-LABEL: @caller2 ; CHECK-LABEL: @caller2
; CHECK: codeRepl.i: ; CHECK: codeRepl.i:
; CHECK-NOT: br label ; CHECK-NOT: br label
; CHECK: call void @callee2.1.if.then(i32 %v, i32* %sub.loc.i), !dbg ![[DBG4:[0-9]+]] ; CHECK: call void @callee2.1.if.then(i32 %v, ptr %sub.loc.i), !dbg ![[DBG4:[0-9]+]]
define i32 @caller2(i32 %v) !dbg !21 { define i32 @caller2(i32 %v) !dbg !21 {
entry: entry:
%call = call i32 @callee2(i32 %v), !dbg !22 %call = call i32 @callee2(i32 %v), !dbg !22
ret i32 %call ret i32 %call
} }
; CHECK-LABEL: define internal void @callee2.1.if.then ; CHECK-LABEL: define internal void @callee2.1.if.then
; CHECK: br label %if.then, !dbg ![[DBG5:[0-9]+]] ; CHECK: br label %if.then, !dbg ![[DBG5:[0-9]+]]
Show All 40 Lines

llvm/test/Transforms/CodeExtractor/PartialInlineVarArgsDebug.ll

Show All 14 Linesif.end: ; preds = %if.then, %entry
%v2 = phi i32 [ %v, %entry ], [ %mul, %if.then ] %v2 = phi i32 [ %v, %entry ], [ %mul, %if.then ]
%add = add nsw i32 %v2, 200, !dbg !22 %add = add nsw i32 %v2, 200, !dbg !22
ret i32 %add, !dbg !23 ret i32 %add, !dbg !23
} }
; CHECK-LABEL: @caller ; CHECK-LABEL: @caller
; CHECK: codeRepl.i: ; CHECK: codeRepl.i:
; CHECK-NOT: br label ; CHECK-NOT: br label
; CHECK: call void (i32, i32*, ...) @callee.1.if.then(i32 %v, i32* %mul.loc.i, i32 99), !dbg ![[DBG2:[0-9]+]] ; CHECK: call void (i32, ptr, ...) @callee.1.if.then(i32 %v, ptr %mul.loc.i, i32 99), !dbg ![[DBG2:[0-9]+]]
define i32 @caller(i32 %v) !dbg !8 { define i32 @caller(i32 %v) !dbg !8 {
entry: entry:
%call = call i32 (i32, ...) @callee(i32 %v, i32 99), !dbg !14 %call = call i32 (i32, ...) @callee(i32 %v, i32 99), !dbg !14
ret i32 %call, !dbg !15 ret i32 %call, !dbg !15
} }
; CHECK-LABEL: define internal void @callee.1.if.then ; CHECK-LABEL: define internal void @callee.1.if.then
; CHECK: br label %if.then, !dbg ![[DBG3:[0-9]+]] ; CHECK: br label %if.then, !dbg ![[DBG3:[0-9]+]]
Show All 37 Lines

llvm/test/Transforms/FunctionImport/Inputs/funcimport.ll

target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.11.0" target triple = "x86_64-apple-macosx10.11.0"
@globalvar = global i32 1, align 4 @globalvar = global i32 1, align 4
@staticvar = internal global i32 1, align 4 @staticvar = internal global i32 1, align 4
@staticconstvar = internal unnamed_addr constant [2 x i32] [i32 10, i32 20], align 4 @staticconstvar = internal unnamed_addr constant [2 x i32] [i32 10, i32 20], align 4
@commonvar = common global i32 0, align 4 @commonvar = common global i32 0, align 4
@P = internal global void ()* null, align 8 @P = internal global ptr null, align 8
@weakalias = weak alias void (...), bitcast (void ()* @globalfunc1 to void (...)*) @weakalias = weak alias void (...), ptr @globalfunc1
@analias = alias void (...), bitcast (void ()* @globalfunc2 to void (...)*) @analias = alias void (...), ptr @globalfunc2
@linkoncealias = alias void (...), bitcast (void ()* @linkoncefunc to void (...)*) @linkoncealias = alias void (...), ptr @linkoncefunc
define void @globalfunc1() #0 { define void @globalfunc1() #0 {
entry: entry:
call void @funcwithpersonality() call void @funcwithpersonality()
call void (...) @variadic_va_start() call void (...) @variadic_va_start()
ret void ret void
} }
define void @globalfunc2() #0 { define void @globalfunc2() #0 {
entry: entry:
ret void ret void
} }
define linkonce_odr void @linkoncefunc() #0 { define linkonce_odr void @linkoncefunc() #0 {
entry: entry:
ret void ret void
} }
define i32 @referencestatics(i32 %i) #0 { define i32 @referencestatics(i32 %i) #0 {
entry: entry:
%i.addr = alloca i32, align 4 %i.addr = alloca i32, align 4
store i32 %i, i32* %i.addr, align 4 store i32 %i, ptr %i.addr, align 4
%call = call i32 @staticfunc() %call = call i32 @staticfunc()
%0 = load i32, i32* @staticvar, align 4 %0 = load i32, ptr @staticvar, align 4
%add = add nsw i32 %call, %0 %add = add nsw i32 %call, %0
%1 = load i32, i32* %i.addr, align 4 %1 = load i32, ptr %i.addr, align 4
%idxprom = sext i32 %1 to i64 %idxprom = sext i32 %1 to i64
%arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* @staticconstvar, i64 0, i64 %idxprom %arrayidx = getelementptr inbounds [2 x i32], ptr @staticconstvar, i64 0, i64 %idxprom
%2 = load i32, i32* %arrayidx, align 4 %2 = load i32, ptr %arrayidx, align 4
%add1 = add nsw i32 %add, %2 %add1 = add nsw i32 %add, %2
ret i32 %add1 ret i32 %add1
} }
define i32 @referenceglobals(i32 %i) #0 { define i32 @referenceglobals(i32 %i) #0 {
entry: entry:
%i.addr = alloca i32, align 4 %i.addr = alloca i32, align 4
store i32 %i, i32* %i.addr, align 4 store i32 %i, ptr %i.addr, align 4
call void @globalfunc1() call void @globalfunc1()
%0 = load i32, i32* @globalvar, align 4 %0 = load i32, ptr @globalvar, align 4
ret i32 %0 ret i32 %0
} }
define i32 @referencecommon(i32 %i) #0 { define i32 @referencecommon(i32 %i) #0 {
entry: entry:
%i.addr = alloca i32, align 4 %i.addr = alloca i32, align 4
store i32 %i, i32* %i.addr, align 4 store i32 %i, ptr %i.addr, align 4
%0 = load i32, i32* @commonvar, align 4 %0 = load i32, ptr @commonvar, align 4
ret i32 %0 ret i32 %0
} }
define void @setfuncptr() #0 { define void @setfuncptr() #0 {
entry: entry:
store void ()* @staticfunc2, void ()** @P, align 8 store ptr @staticfunc2, ptr @P, align 8
ret void ret void
} }
define void @callfuncptr() #0 { define void @callfuncptr() #0 {
entry: entry:
%0 = load void ()*, void ()** @P, align 8 %0 = load ptr, ptr @P, align 8
call void %0() call void %0()
ret void ret void
} }
@weakvar = weak global i32 1, align 4 @weakvar = weak global i32 1, align 4
define weak void @weakfunc() #0 { define weak void @weakfunc() #0 {
entry: entry:
ret void ret void
} }
define linkonce void @linkoncefunc2() #0 { define linkonce void @linkoncefunc2() #0 {
entry: entry:
ret void ret void
} }
define internal i32 @staticfunc() #0 { define internal i32 @staticfunc() #0 {
entry: entry:
ret i32 1 ret i32 1
} }
declare i32 @__gxx_personality_v0(...) declare i32 @__gxx_personality_v0(...)
; Add enough instructions to prevent import with inst limit of 5 ; Add enough instructions to prevent import with inst limit of 5
define internal void @funcwithpersonality() #2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { define internal void @funcwithpersonality() #2 personality ptr @__gxx_personality_v0 {
entry: entry:
call void @globalfunc2() call void @globalfunc2()
call void @globalfunc2() call void @globalfunc2()
call void @globalfunc2() call void @globalfunc2()
call void @globalfunc2() call void @globalfunc2()
call void @globalfunc2() call void @globalfunc2()
call void @globalfunc2() call void @globalfunc2()
ret void ret void
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; can handle it. ; can handle it.
define void @variadic_no_va_start(...) { define void @variadic_no_va_start(...) {
ret void ret void
} }
; Variadic function with va_start should not be imported because inliner ; Variadic function with va_start should not be imported because inliner
; doesn't handle it. ; doesn't handle it.
define void @variadic_va_start(...) { define void @variadic_va_start(...) {
%ap = alloca i8*, align 8 %ap = alloca ptr, align 8
%ap.0 = bitcast i8** %ap to i8* call void @llvm.va_start(ptr %ap)
call void @llvm.va_start(i8* %ap.0)
ret void ret void
} }
declare void @llvm.va_start(i8*) nounwind declare void @llvm.va_start(ptr) nounwind

llvm/test/Transforms/FunctionImport/funcimport.ll

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
declare void @setfuncptr(...) #1 declare void @setfuncptr(...) #1
; INSTLIMDEF-DAG: Import callfuncptr ; INSTLIMDEF-DAG: Import callfuncptr
; CHECK-DAG: define available_externally void @callfuncptr() !thinlto_src_module !0 { ; CHECK-DAG: define available_externally void @callfuncptr() !thinlto_src_module !0 {
declare void @callfuncptr(...) #1 declare void @callfuncptr(...) #1
; Ensure that all uses of local variable @P which has used in setfuncptr ; Ensure that all uses of local variable @P which has used in setfuncptr
; and callfuncptr are to the same promoted/renamed global. ; and callfuncptr are to the same promoted/renamed global.
; CHECK-DAG: @P.llvm.{{.*}} = available_externally hidden global void ()* null ; CHECK-DAG: @P.llvm.{{.*}} = available_externally hidden global ptr null
; CHECK-DAG: %0 = load void ()*, void ()** @P.llvm. ; CHECK-DAG: %0 = load ptr, ptr @P.llvm.
; CHECK-DAG: store void ()* @staticfunc2.llvm.{{.*}}, void ()** @P.llvm. ; CHECK-DAG: store ptr @staticfunc2.llvm.{{.*}}, ptr @P.llvm.
; Ensure that @referencelargelinkonce definition is pulled in, but later we ; Ensure that @referencelargelinkonce definition is pulled in, but later we
; also check that the linkonceodr function is not. ; also check that the linkonceodr function is not.
; CHECK-DAG: define available_externally void @referencelargelinkonce() !thinlto_src_module !0 { ; CHECK-DAG: define available_externally void @referencelargelinkonce() !thinlto_src_module !0 {
; INSTLIM5-DAG: declare void @linkonceodr() ; INSTLIM5-DAG: declare void @linkonceodr()
declare void @referencelargelinkonce(...) declare void @referencelargelinkonce(...)
; Won't import weak func ; Won't import weak func
; CHECK-DAG: declare void @weakfunc(...) ; CHECK-DAG: declare void @weakfunc(...)
declare void @weakfunc(...) #1 declare void @weakfunc(...) #1
; Won't import linkonce func ; Won't import linkonce func
; CHECK-DAG: declare void @linkoncefunc2(...) ; CHECK-DAG: declare void @linkoncefunc2(...)
declare void @linkoncefunc2(...) #1 declare void @linkoncefunc2(...) #1
; INSTLIMDEF-DAG: Import funcwithpersonality ; INSTLIMDEF-DAG: Import funcwithpersonality
; INSTLIMDEF-DAG: define available_externally hidden void @funcwithpersonality.llvm.{{.*}}() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !thinlto_src_module !0 { ; INSTLIMDEF-DAG: define available_externally hidden void @funcwithpersonality.llvm.{{.*}}() personality ptr @__gxx_personality_v0 !thinlto_src_module !0 {
; INSTLIM5-DAG: declare hidden void @funcwithpersonality.llvm.{{.*}}() ; INSTLIM5-DAG: declare hidden void @funcwithpersonality.llvm.{{.*}}()
; We can import variadic functions without a va_start, since the inliner ; We can import variadic functions without a va_start, since the inliner
; can handle them. ; can handle them.
; INSTLIMDEF-DAG: Import variadic_no_va_start ; INSTLIMDEF-DAG: Import variadic_no_va_start
; CHECK-DAG: define available_externally void @variadic_no_va_start(...) !thinlto_src_module !0 { ; CHECK-DAG: define available_externally void @variadic_no_va_start(...) !thinlto_src_module !0 {
declare void @variadic_no_va_start(...) declare void @variadic_no_va_start(...)
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/test/Transforms/FunctionImport/funcimport_alias.ll

; Do setup work for all below tests: generate bitcode and combined index ; Do setup work for all below tests: generate bitcode and combined index
; RUN: opt -module-summary %s -o %t.bc ; RUN: opt -module-summary %s -o %t.bc
; RUN: opt -module-summary %p/Inputs/funcimport_alias.ll -o %t2.bc ; RUN: opt -module-summary %p/Inputs/funcimport_alias.ll -o %t2.bc
; RUN: llvm-lto -thinlto -o %t3 %t.bc %t2.bc ; RUN: llvm-lto -thinlto -o %t3 %t.bc %t2.bc
; Do the import now. Ensures that the importer handles an external call ; Do the import now. Ensures that the importer handles an external call
; from imported callanalias() to a function that is defined already in ; from imported callanalias() to a function that is defined already in
; the dest module, but as an alias. ; the dest module, but as an alias.
; RUN: opt -function-import -summary-file %t3.thinlto.bc %t.bc -S | FileCheck %s ; RUN: opt -function-import -summary-file %t3.thinlto.bc %t.bc -S | FileCheck %s
define i32 @main() #0 { define i32 @main() #0 {
entry: entry:
call void @callanalias() call void @callanalias()
ret i32 0 ret i32 0
} }
@analias = alias void (), void ()* @globalfunc @analias = alias void (), ptr @globalfunc
define void @globalfunc() #0 { define void @globalfunc() #0 {
entry: entry:
ret void ret void
} }
declare void @callanalias() #1 declare void @callanalias() #1
; CHECK-DAG: define available_externally void @callanalias() ; CHECK-DAG: define available_externally void @callanalias()

llvm/test/Transforms/GCOVProfiling/atomic-counter.ll

;; -fsanitize=thread requires the (potentially concurrent) counter updates to be atomic. ;; -fsanitize=thread requires the (potentially concurrent) counter updates to be atomic.
; RUN: mkdir -p %t && cd %t ; RUN: mkdir -p %t && cd %t
; RUN: opt < %s -S -passes=insert-gcov-profiling -gcov-atomic-counter | FileCheck %s ; RUN: opt < %s -S -passes=insert-gcov-profiling -gcov-atomic-counter | FileCheck %s
; CHECK-LABEL: void @empty() ; CHECK-LABEL: void @empty()
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: %0 = atomicrmw add i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__llvm_gcov_ctr, i64 0, i64 0), i64 1 monotonic, align 8, !dbg [[DBG:![0-9]+]] ; CHECK-NEXT: %0 = atomicrmw add ptr @__llvm_gcov_ctr, i64 1 monotonic, align 8, !dbg [[DBG:![0-9]+]]
; CHECK-NEXT: ret void, !dbg [[DBG]] ; CHECK-NEXT: ret void, !dbg [[DBG]]
define dso_local void @empty() !dbg !5 { define dso_local void @empty() !dbg !5 {
entry: entry:
ret void, !dbg !8 ret void, !dbg !8
} }
!llvm.dbg.cu = !{!0} !llvm.dbg.cu = !{!0}
Show All 11 Lines

llvm/test/Transforms/GCOVProfiling/function-numbering.ll

Show All 16 Lines
; GCDA-SAME: { i32 1, ; GCDA-SAME: { i32 1,
; ;
; GCDA-LABEL: define internal void @__llvm_gcov_writeout() unnamed_addr #[[#ATTR:]] { ; GCDA-LABEL: define internal void @__llvm_gcov_writeout() unnamed_addr #[[#ATTR:]] {
; GCDA-NEXT: entry: ; GCDA-NEXT: entry:
; GCDA-NEXT: br label %[[FILE_LOOP_HEADER:.*]] ; GCDA-NEXT: br label %[[FILE_LOOP_HEADER:.*]]
; ;
; GCDA: [[FILE_LOOP_HEADER]]: ; GCDA: [[FILE_LOOP_HEADER]]:
; GCDA-NEXT: %[[IV:.*]] = phi i32 [ 0, %entry ], [ %[[NEXT_IV:.*]], %[[FILE_LOOP_LATCH:.*]] ] ; GCDA-NEXT: %[[IV:.*]] = phi i32 [ 0, %entry ], [ %[[NEXT_IV:.*]], %[[FILE_LOOP_LATCH:.*]] ]
; GCDA-NEXT: %[[FILE_INFO:.*]] = getelementptr inbounds {{.*}}, {{.*}}* @__llvm_internal_gcov_emit_file_info, i32 0, i32 %[[IV]] ; GCDA-NEXT: %[[FILE_INFO:.*]] = getelementptr inbounds {{.*}}, ptr @__llvm_internal_gcov_emit_file_info, i32 0, i32 %[[IV]]
; GCDA-NEXT: %[[START_FILE_ARGS:.*]] = getelementptr inbounds {{.*}}, {{.*}}* %[[FILE_INFO]], i32 0, i32 0 ; GCDA-NEXT: %[[START_FILE_ARGS:.*]] = getelementptr inbounds {{.*}}, ptr %[[FILE_INFO]], i32 0, i32 0
; GCDA-NEXT: %[[START_FILE_ARG_0_PTR:.*]] = getelementptr inbounds {{.*}}, {{.*}}* %[[START_FILE_ARGS]], i32 0, i32 0 ; GCDA-NEXT: %[[START_FILE_ARG_0_PTR:.*]] = getelementptr inbounds {{.*}}, ptr %[[START_FILE_ARGS]], i32 0, i32 0
; GCDA-NEXT: %[[START_FILE_ARG_0:.*]] = load i8*, i8** %[[START_FILE_ARG_0_PTR]] ; GCDA-NEXT: %[[START_FILE_ARG_0:.*]] = load ptr, ptr %[[START_FILE_ARG_0_PTR]]
; GCDA-NEXT: %[[START_FILE_ARG_1_PTR:.*]] = getelementptr inbounds {{.*}}, {{.*}}* %[[START_FILE_ARGS]], i32 0, i32 1 ; GCDA-NEXT: %[[START_FILE_ARG_1_PTR:.*]] = getelementptr inbounds {{.*}}, ptr %[[START_FILE_ARGS]], i32 0, i32 1
; GCDA-NEXT: %[[START_FILE_ARG_1:.*]] = load i32, i32* %[[START_FILE_ARG_1_PTR]] ; GCDA-NEXT: %[[START_FILE_ARG_1:.*]] = load i32, ptr %[[START_FILE_ARG_1_PTR]]
; GCDA-NEXT: %[[START_FILE_ARG_2_PTR:.*]] = getelementptr inbounds {{.*}}, {{.*}}* %[[START_FILE_ARGS]], i32 0, i32 2 ; GCDA-NEXT: %[[START_FILE_ARG_2_PTR:.*]] = getelementptr inbounds {{.*}}, ptr %[[START_FILE_ARGS]], i32 0, i32 2
; GCDA-NEXT: %[[START_FILE_ARG_2:.*]] = load i32, i32* %[[START_FILE_ARG_2_PTR]] ; GCDA-NEXT: %[[START_FILE_ARG_2:.*]] = load i32, ptr %[[START_FILE_ARG_2_PTR]]
; GCDA-NEXT: call void @llvm_gcda_start_file(i8* %[[START_FILE_ARG_0]], i32 %[[START_FILE_ARG_1]], i32 %[[START_FILE_ARG_2]]) ; GCDA-NEXT: call void @llvm_gcda_start_file(ptr %[[START_FILE_ARG_0]], i32 %[[START_FILE_ARG_1]], i32 %[[START_FILE_ARG_2]])
; GCDA-NEXT: %[[NUM_COUNTERS_PTR:.*]] = getelementptr inbounds {{.*}}, {{.*}}* %[[FILE_INFO]], i32 0, i32 1 ; GCDA-NEXT: %[[NUM_COUNTERS_PTR:.*]] = getelementptr inbounds {{.*}}, ptr %[[FILE_INFO]], i32 0, i32 1
; GCDA-NEXT: %[[NUM_COUNTERS:.*]] = load i32, i32* %[[NUM_COUNTERS_PTR]] ; GCDA-NEXT: %[[NUM_COUNTERS:.*]] = load i32, ptr %[[NUM_COUNTERS_PTR]]
; GCDA-NEXT: %[[EMIT_FUN_ARGS_ARRAY_PTR:.*]] = getelementptr inbounds {{.*}}, {{.*}}* %[[FILE_INFO]], i32 0, i32 2 ; GCDA-NEXT: %[[EMIT_FUN_ARGS_ARRAY_PTR:.*]] = getelementptr inbounds {{.*}}, ptr %[[FILE_INFO]], i32 0, i32 2
; GCDA-NEXT: %[[EMIT_FUN_ARGS_ARRAY:.*]] = load {{.*}}*, {{.*}}** %[[EMIT_FUN_ARGS_ARRAY_PTR]] ; GCDA-NEXT: %[[EMIT_FUN_ARGS_ARRAY:.*]] = load ptr, ptr %[[EMIT_FUN_ARGS_ARRAY_PTR]]
; GCDA-NEXT: %[[EMIT_ARCS_ARGS_ARRAY_PTR:.*]] = getelementptr inbounds {{.*}}, {{.*}}* %[[FILE_INFO]], i32 0, i32 3 ; GCDA-NEXT: %[[EMIT_ARCS_ARGS_ARRAY_PTR:.*]] = getelementptr inbounds {{.*}}, ptr %[[FILE_INFO]], i32 0, i32 3
; GCDA-NEXT: %[[EMIT_ARCS_ARGS_ARRAY:.*]] = load {{.*}}*, {{.*}}** %[[EMIT_ARCS_ARGS_ARRAY_PTR]] ; GCDA-NEXT: %[[EMIT_ARCS_ARGS_ARRAY:.*]] = load ptr, ptr %[[EMIT_ARCS_ARGS_ARRAY_PTR]]
; GCDA-NEXT: %[[ENTER_COUNTER_LOOP_COND:.*]] = icmp slt i32 0, %[[NUM_COUNTERS]] ; GCDA-NEXT: %[[ENTER_COUNTER_LOOP_COND:.*]] = icmp slt i32 0, %[[NUM_COUNTERS]]
; GCDA-NEXT: br i1 %[[ENTER_COUNTER_LOOP_COND]], label %[[COUNTER_LOOP:.*]], label %[[FILE_LOOP_LATCH]] ; GCDA-NEXT: br i1 %[[ENTER_COUNTER_LOOP_COND]], label %[[COUNTER_LOOP:.*]], label %[[FILE_LOOP_LATCH]]
; ;
; GCDA: [[COUNTER_LOOP]]: ; GCDA: [[COUNTER_LOOP]]:
; GCDA-NEXT: %[[JV:.*]] = phi i32 [ 0, %[[FILE_LOOP_HEADER]] ], [ %[[NEXT_JV:.*]], %[[COUNTER_LOOP]] ] ; GCDA-NEXT: %[[JV:.*]] = phi i32 [ 0, %[[FILE_LOOP_HEADER]] ], [ %[[NEXT_JV:.*]], %[[COUNTER_LOOP]] ]
; GCDA-NEXT: %[[EMIT_FUN_ARGS:.*]] = getelementptr inbounds {{.*}}, {{.*}}* %[[EMIT_FUN_ARGS_ARRAY]], i32 %[[JV]] ; GCDA-NEXT: %[[EMIT_FUN_ARGS:.*]] = getelementptr inbounds {{.*}}, ptr %[[EMIT_FUN_ARGS_ARRAY]], i32 %[[JV]]
; GCDA-NEXT: %[[EMIT_FUN_ARG_0_PTR:.*]] = getelementptr inbounds {{.*}}, {{.*}}* %[[EMIT_FUN_ARGS]], i32 0, i32 0 ; GCDA-NEXT: %[[EMIT_FUN_ARG_0_PTR:.*]] = getelementptr inbounds {{.*}}, ptr %[[EMIT_FUN_ARGS]], i32 0, i32 0
; GCDA-NEXT: %[[EMIT_FUN_ARG_0:.*]] = load i32, i32* %[[EMIT_FUN_ARG_0_PTR]] ; GCDA-NEXT: %[[EMIT_FUN_ARG_0:.*]] = load i32, ptr %[[EMIT_FUN_ARG_0_PTR]]
; GCDA-NEXT: %[[EMIT_FUN_ARG_1_PTR:.*]] = getelementptr inbounds {{.*}}, {{.*}}* %[[EMIT_FUN_ARGS]], i32 0, i32 1 ; GCDA-NEXT: %[[EMIT_FUN_ARG_1_PTR:.*]] = getelementptr inbounds {{.*}}, ptr %[[EMIT_FUN_ARGS]], i32 0, i32 1
; GCDA-NEXT: %[[EMIT_FUN_ARG_1:.*]] = load i32, i32* %[[EMIT_FUN_ARG_1_PTR]] ; GCDA-NEXT: %[[EMIT_FUN_ARG_1:.*]] = load i32, ptr %[[EMIT_FUN_ARG_1_PTR]]
; GCDA-NEXT: %[[EMIT_FUN_ARG_2_PTR:.*]] = getelementptr inbounds {{.*}}, {{.*}}* %[[EMIT_FUN_ARGS]], i32 0, i32 2 ; GCDA-NEXT: %[[EMIT_FUN_ARG_2_PTR:.*]] = getelementptr inbounds {{.*}}, ptr %[[EMIT_FUN_ARGS]], i32 0, i32 2
; GCDA-NEXT: %[[EMIT_FUN_ARG_2:.*]] = load i32, i32* %[[EMIT_FUN_ARG_2_PTR]] ; GCDA-NEXT: %[[EMIT_FUN_ARG_2:.*]] = load i32, ptr %[[EMIT_FUN_ARG_2_PTR]]
; GCDA-NEXT: call void @llvm_gcda_emit_function(i32 %[[EMIT_FUN_ARG_0]], ; GCDA-NEXT: call void @llvm_gcda_emit_function(i32 %[[EMIT_FUN_ARG_0]],
; GCDA-SAME: i32 %[[EMIT_FUN_ARG_1]], ; GCDA-SAME: i32 %[[EMIT_FUN_ARG_1]],
; GCDA-SAME: i32 %[[EMIT_FUN_ARG_2]]) ; GCDA-SAME: i32 %[[EMIT_FUN_ARG_2]])
; GCDA-NEXT: %[[EMIT_ARCS_ARGS:.*]] = getelementptr inbounds {{.*}}, {{.*}}* %[[EMIT_ARCS_ARGS_ARRAY]], i32 %[[JV]] ; GCDA-NEXT: %[[EMIT_ARCS_ARGS:.*]] = getelementptr inbounds {{.*}}, ptr %[[EMIT_ARCS_ARGS_ARRAY]], i32 %[[JV]]
; GCDA-NEXT: %[[EMIT_ARCS_ARG_0_PTR:.*]] = getelementptr inbounds {{.*}}, {{.*}}* %[[EMIT_ARCS_ARGS]], i32 0, i32 0 ; GCDA-NEXT: %[[EMIT_ARCS_ARG_0_PTR:.*]] = getelementptr inbounds {{.*}}, ptr %[[EMIT_ARCS_ARGS]], i32 0, i32 0
; GCDA-NEXT: %[[EMIT_ARCS_ARG_0:.*]] = load i32, i32* %[[EMIT_ARCS_ARG_0_PTR]] ; GCDA-NEXT: %[[EMIT_ARCS_ARG_0:.*]] = load i32, ptr %[[EMIT_ARCS_ARG_0_PTR]]
; GCDA-NEXT: %[[EMIT_ARCS_ARG_1_PTR:.*]] = getelementptr inbounds {{.*}}, {{.*}}* %[[EMIT_ARCS_ARGS]], i32 0, i32 1 ; GCDA-NEXT: %[[EMIT_ARCS_ARG_1_PTR:.*]] = getelementptr inbounds {{.*}}, ptr %[[EMIT_ARCS_ARGS]], i32 0, i32 1
; GCDA-NEXT: %[[EMIT_ARCS_ARG_1:.*]] = load i64*, i64** %[[EMIT_ARCS_ARG_1_PTR]] ; GCDA-NEXT: %[[EMIT_ARCS_ARG_1:.*]] = load ptr, ptr %[[EMIT_ARCS_ARG_1_PTR]]
; GCDA-NEXT: call void @llvm_gcda_emit_arcs(i32 %[[EMIT_ARCS_ARG_0]], ; GCDA-NEXT: call void @llvm_gcda_emit_arcs(i32 %[[EMIT_ARCS_ARG_0]],
; GCDA-SAME: i64* %[[EMIT_ARCS_ARG_1]]) ; GCDA-SAME: ptr %[[EMIT_ARCS_ARG_1]])
; GCDA-NEXT: %[[NEXT_JV]] = add i32 %[[JV]], 1 ; GCDA-NEXT: %[[NEXT_JV]] = add i32 %[[JV]], 1
; GCDA-NEXT: %[[COUNTER_LOOP_COND:.*]] = icmp slt i32 %[[NEXT_JV]], %[[NUM_COUNTERS]] ; GCDA-NEXT: %[[COUNTER_LOOP_COND:.*]] = icmp slt i32 %[[NEXT_JV]], %[[NUM_COUNTERS]]
; GCDA-NEXT: br i1 %[[COUNTER_LOOP_COND]], label %[[COUNTER_LOOP]], label %[[FILE_LOOP_LATCH]] ; GCDA-NEXT: br i1 %[[COUNTER_LOOP_COND]], label %[[COUNTER_LOOP]], label %[[FILE_LOOP_LATCH]]
; ;
; GCDA: [[FILE_LOOP_LATCH]]: ; GCDA: [[FILE_LOOP_LATCH]]:
; GCDA-NEXT: call void @llvm_gcda_summary_info() ; GCDA-NEXT: call void @llvm_gcda_summary_info()
; GCDA-NEXT: call void @llvm_gcda_end_file() ; GCDA-NEXT: call void @llvm_gcda_end_file()
; GCDA-NEXT: %[[NEXT_IV]] = add i32 %[[IV]], 1 ; GCDA-NEXT: %[[NEXT_IV]] = add i32 %[[IV]], 1
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/Transforms/GCOVProfiling/noprofile.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: mkdir -p %t && cd %t ; RUN: mkdir -p %t && cd %t
; RUN: opt < %s -passes=insert-gcov-profiling -S | FileCheck %s ; RUN: opt < %s -passes=insert-gcov-profiling -S | FileCheck %s
; Test that the noprofile attribute disables profiling. ; Test that the noprofile attribute disables profiling.
define dso_local i32 @no_instr(i32 %a) noprofile !dbg !9 { define dso_local i32 @no_instr(i32 %a) noprofile !dbg !9 {
; CHECK-LABEL: @no_instr( ; CHECK-LABEL: @no_instr(
; CHECK-NEXT: ret i32 42, !dbg [[DBG6:![0-9]+]] ; CHECK-NEXT: ret i32 42, !dbg [[DBG6:![0-9]+]]
; ;
ret i32 42, !dbg !27 ret i32 42, !dbg !27
} }
define dso_local i32 @instr(i32 %a) !dbg !28 { define dso_local i32 @instr(i32 %a) !dbg !28 {
; CHECK-LABEL: @instr( ; CHECK-LABEL: @instr(
; CHECK-NEXT: [[GCOV_CTR:%.*]] = load i64, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__llvm_gcov_ctr, i64 0, i64 0), align 4, !dbg [[DBG8:![0-9]+]] ; CHECK-NEXT: [[GCOV_CTR:%.*]] = load i64, ptr @__llvm_gcov_ctr, align 4, !dbg [[DBG8:![0-9]+]]
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[GCOV_CTR]], 1, !dbg [[DBG8]] ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[GCOV_CTR]], 1, !dbg [[DBG8]]
; CHECK-NEXT: store i64 [[TMP1]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__llvm_gcov_ctr, i64 0, i64 0), align 4, !dbg [[DBG8]] ; CHECK-NEXT: store i64 [[TMP1]], ptr @__llvm_gcov_ctr, align 4, !dbg [[DBG8]]
; CHECK-NEXT: ret i32 42, !dbg [[DBG8]] ; CHECK-NEXT: ret i32 42, !dbg [[DBG8]]
; ;
ret i32 42, !dbg !44 ret i32 42, !dbg !44
} }
!llvm.dbg.cu = !{!0} !llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3} !llvm.module.flags = !{!3}
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llvm/test/Transforms/GCOVProfiling/reset.ll

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define void @bar() !dbg !13 { define void @bar() !dbg !13 {
entry: entry:
ret void, !dbg !14 ret void, !dbg !14
} }
; CHECK: define internal void @__llvm_gcov_reset() ; CHECK: define internal void @__llvm_gcov_reset()
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* bitcast ([1 x i64]* @__llvm_gcov_ctr to i8*), i8 0, i64 8, i1 false) ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr @__llvm_gcov_ctr, i8 0, i64 8, i1 false)
; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* bitcast ([1 x i64]* @__llvm_gcov_ctr.1 to i8*), i8 0, i64 8, i1 false) ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr @__llvm_gcov_ctr.1, i8 0, i64 8, i1 false)
!llvm.dbg.cu = !{!0} !llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4, !5, !6} !llvm.module.flags = !{!3, !4, !5, !6}
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 14.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None) !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 14.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None)
!1 = !DIFile(filename: "/tmp/a.c", directory: "/tmp") !1 = !DIFile(filename: "/tmp/a.c", directory: "/tmp")
!2 = !{} !2 = !{}
!3 = !{i32 7, !"Dwarf Version", i32 4} !3 = !{i32 7, !"Dwarf Version", i32 4}
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llvm/test/Transforms/HotColdSplit/phi-with-distinct-outlined-values.ll

; RUN: opt -S -hotcoldsplit -hotcoldsplit-threshold=0 < %s | FileCheck %s ; RUN: opt -S -hotcoldsplit -hotcoldsplit-threshold=0 < %s | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.14.0" target triple = "x86_64-apple-macosx10.14.0"
; CHECK-LABEL: define {{.*}}@foo( ; CHECK-LABEL: define {{.*}}@foo(
; CHECK: phi i32 [ 0, %entry ], [ %p.ce.reload, %codeRepl ] ; CHECK: phi i32 [ 0, %entry ], [ %p.ce.reload, %codeRepl ]
; CHECK-LABEL: define {{.*}}@foo.cold.1( ; CHECK-LABEL: define {{.*}}@foo.cold.1(
; CHECK: call {{.*}}@sink ; CHECK: call {{.*}}@sink
; CHECK: %p.ce = phi i32 [ 1, %coldbb ], [ 3, %coldbb2 ] ; CHECK: %p.ce = phi i32 [ 1, %coldbb ], [ 3, %coldbb2 ]
; CHECK-NEXT: store i32 %p.ce, i32* %p.ce.out ; CHECK-NEXT: store i32 %p.ce, ptr %p.ce.out
define void @foo(i32 %cond) { define void @foo(i32 %cond) {
entry: entry:
%tobool = icmp eq i32 %cond, 0 %tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %if.end, label %coldbb br i1 %tobool, label %if.end, label %coldbb
coldbb: coldbb:
call void @sink() call void @sink()
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llvm/test/Transforms/HotColdSplit/split-phis-in-exit-blocks.ll

; RUN: opt -hotcoldsplit-threshold=0 -hotcoldsplit -S < %s | FileCheck %s ; RUN: opt -hotcoldsplit-threshold=0 -hotcoldsplit -S < %s | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.14.0" target triple = "x86_64-apple-macosx10.14.0"
; CHECK-LABEL: define {{.*}}@pluto( ; CHECK-LABEL: define {{.*}}@pluto(
; CHECK-NEXT: bb: ; CHECK-NEXT: bb:
; CHECK-NEXT: %tmp8.ce.loc = alloca i1 ; CHECK-NEXT: %tmp8.ce.loc = alloca i1
; CHECK-NEXT: switch i8 undef, label %codeRepl [ ; CHECK-NEXT: switch i8 undef, label %codeRepl [
; CHECK-NEXT: i8 0, label %bb7 ; CHECK-NEXT: i8 0, label %bb7
; CHECK-NEXT: i8 1, label %bb7 ; CHECK-NEXT: i8 1, label %bb7
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; ;
; CHECK: codeRepl: ; CHECK: codeRepl:
; CHECK-NEXT: bitcast
; CHECK-NEXT: lifetime.start ; CHECK-NEXT: lifetime.start
; CHECK-NEXT: call void @pluto.cold.1(i1* %tmp8.ce.loc) ; CHECK-NEXT: call void @pluto.cold.1(ptr %tmp8.ce.loc)
; CHECK-NEXT: %tmp8.ce.reload = load i1, i1* %tmp8.ce.loc ; CHECK-NEXT: %tmp8.ce.reload = load i1, ptr %tmp8.ce.loc
; CHECK-NEXT: lifetime.end ; CHECK-NEXT: lifetime.end
; CHECK-NEXT: br label %bb7 ; CHECK-NEXT: br label %bb7
; ;
; CHECK: bb7: ; CHECK: bb7:
; CHECK: %tmp8 = phi i1 [ true, %bb ], [ true, %bb ], [ %tmp8.ce.reload, %codeRepl ] ; CHECK: %tmp8 = phi i1 [ true, %bb ], [ true, %bb ], [ %tmp8.ce.reload, %codeRepl ]
; CHECK: ret void ; CHECK: ret void
; CHECK-LABEL: define {{.*}}@pluto.cold.1( ; CHECK-LABEL: define {{.*}}@pluto.cold.1(
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/test/Transforms/IROutliner/different-order-phi-merges.ll

Show All 40 Lines
bb5: bb5:
%phinode = phi i32 [%2, %bb1], [%3, %bb2] %phinode = phi i32 [%2, %bb1], [%3, %bb2]
ret void ret void
} }
; CHECK-LABEL: @f1( ; CHECK-LABEL: @f1(
; CHECK-NEXT: bb1: ; CHECK-NEXT: bb1:
; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[PHINODE_CE_LOC]] to i8* ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[PHINODE_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]]) ; CHECK-NEXT: [[TMP0:%.*]] = call i1 @outlined_ir_func_0(ptr [[PHINODE_CE_LOC]], i32 0)
; CHECK-NEXT: [[TMP0:%.*]] = call i1 @outlined_ir_func_0(i32* [[PHINODE_CE_LOC]], i32 0) ; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, ptr [[PHINODE_CE_LOC]], align 4
; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, i32* [[PHINODE_CE_LOC]], align 4 ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[PHINODE_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
; CHECK-NEXT: br i1 [[TMP0]], label [[BB5:%.*]], label [[BB1_AFTER_OUTLINE:%.*]] ; CHECK-NEXT: br i1 [[TMP0]], label [[BB5:%.*]], label [[BB1_AFTER_OUTLINE:%.*]]
; CHECK: bb1_after_outline: ; CHECK: bb1_after_outline:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ] ; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ]
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; ;
; CHECK-LABEL: @f2( ; CHECK-LABEL: @f2(
; CHECK-NEXT: bb1: ; CHECK-NEXT: bb1:
; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[PHINODE_CE_LOC]] to i8* ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[PHINODE_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]]) ; CHECK-NEXT: [[TMP0:%.*]] = call i1 @outlined_ir_func_0(ptr [[PHINODE_CE_LOC]], i32 1)
; CHECK-NEXT: [[TMP0:%.*]] = call i1 @outlined_ir_func_0(i32* [[PHINODE_CE_LOC]], i32 1) ; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, ptr [[PHINODE_CE_LOC]], align 4
; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, i32* [[PHINODE_CE_LOC]], align 4 ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[PHINODE_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
; CHECK-NEXT: br i1 [[TMP0]], label [[BB5:%.*]], label [[BB1_AFTER_OUTLINE:%.*]] ; CHECK-NEXT: br i1 [[TMP0]], label [[BB5:%.*]], label [[BB1_AFTER_OUTLINE:%.*]]
; CHECK: bb1_after_outline: ; CHECK: bb1_after_outline:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ] ; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ]
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; ;
Show All 20 Lines
; CHECK-NEXT: switch i32 [[TMP1:%.*]], label [[FINAL_BLOCK_1:%.*]] [ ; CHECK-NEXT: switch i32 [[TMP1:%.*]], label [[FINAL_BLOCK_1:%.*]] [
; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_1:%.*]] ; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_1:%.*]]
; CHECK-NEXT: i32 1, label [[OUTPUT_BLOCK_1_1:%.*]] ; CHECK-NEXT: i32 1, label [[OUTPUT_BLOCK_1_1:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: bb1_after_outline.exitStub: ; CHECK: bb1_after_outline.exitStub:
; CHECK-NEXT: switch i32 [[TMP1]], label [[FINAL_BLOCK_0:%.*]] [ ; CHECK-NEXT: switch i32 [[TMP1]], label [[FINAL_BLOCK_0:%.*]] [
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: output_block_0_1: ; CHECK: output_block_0_1:
; CHECK-NEXT: store i32 [[PHINODE_CE]], i32* [[TMP0:%.*]], align 4 ; CHECK-NEXT: store i32 [[PHINODE_CE]], ptr [[TMP0:%.*]], align 4
; CHECK-NEXT: br label [[FINAL_BLOCK_1]] ; CHECK-NEXT: br label [[FINAL_BLOCK_1]]
; CHECK: output_block_1_1: ; CHECK: output_block_1_1:
; CHECK-NEXT: store i32 [[TMP7]], i32* [[TMP0]], align 4 ; CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP0]], align 4
; CHECK-NEXT: br label [[FINAL_BLOCK_1]] ; CHECK-NEXT: br label [[FINAL_BLOCK_1]]
; CHECK: final_block_0: ; CHECK: final_block_0:
; CHECK-NEXT: ret i1 false ; CHECK-NEXT: ret i1 false
; CHECK: final_block_1: ; CHECK: final_block_1:
; CHECK-NEXT: ret i1 true ; CHECK-NEXT: ret i1 true
; ;

llvm/test/Transforms/IROutliner/duplicate-merging-phis.ll

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Linesbb5:
%phinode = phi i32 [5, %bb1], [5, %bb2] %phinode = phi i32 [5, %bb1], [5, %bb2]
%phinode1 = phi i32 [5, %bb1], [5, %bb2] %phinode1 = phi i32 [5, %bb1], [5, %bb2]
ret void ret void
} }
; CHECK-LABEL: @f1( ; CHECK-LABEL: @f1(
; CHECK-NEXT: bb1: ; CHECK-NEXT: bb1:
; CHECK-NEXT: [[PHINODE1_CE_LOC:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[PHINODE1_CE_LOC:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[PHINODE_CE_LOC]] to i8* ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[PHINODE_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]]) ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[PHINODE1_CE_LOC]])
; CHECK-NEXT: [[LT_CAST1:%.*]] = bitcast i32* [[PHINODE1_CE_LOC]] to i8* ; CHECK-NEXT: [[TARGETBLOCK:%.*]] = call i1 @outlined_ir_func_0(ptr [[PHINODE_CE_LOC]], ptr [[PHINODE1_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST1]]) ; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, ptr [[PHINODE_CE_LOC]], align 4
; CHECK-NEXT: [[TARGETBLOCK:%.*]] = call i1 @outlined_ir_func_0(i32* [[PHINODE_CE_LOC]], i32* [[PHINODE1_CE_LOC]]) ; CHECK-NEXT: [[PHINODE1_CE_RELOAD:%.*]] = load i32, ptr [[PHINODE1_CE_LOC]], align 4
; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, i32* [[PHINODE_CE_LOC]], align 4 ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[PHINODE_CE_LOC]])
; CHECK-NEXT: [[PHINODE1_CE_RELOAD:%.*]] = load i32, i32* [[PHINODE1_CE_LOC]], align 4 ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[PHINODE1_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST1]])
; CHECK-NEXT: br i1 [[TARGETBLOCK]], label [[BB5:%.*]], label [[BB1_AFTER_OUTLINE:%.*]] ; CHECK-NEXT: br i1 [[TARGETBLOCK]], label [[BB5:%.*]], label [[BB1_AFTER_OUTLINE:%.*]]
; CHECK: bb1_after_outline: ; CHECK: bb1_after_outline:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ] ; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ]
; CHECK-NEXT: [[PHINODE1:%.*]] = phi i32 [ [[PHINODE1_CE_RELOAD]], [[BB1]] ] ; CHECK-NEXT: [[PHINODE1:%.*]] = phi i32 [ [[PHINODE1_CE_RELOAD]], [[BB1]] ]
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; ;
; CHECK-LABEL: @f2( ; CHECK-LABEL: @f2(
; CHECK-NEXT: bb1: ; CHECK-NEXT: bb1:
; CHECK-NEXT: [[PHINODE1_CE_LOC:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[PHINODE1_CE_LOC:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[PHINODE_CE_LOC]] to i8* ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[PHINODE_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]]) ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[PHINODE1_CE_LOC]])
; CHECK-NEXT: [[LT_CAST1:%.*]] = bitcast i32* [[PHINODE1_CE_LOC]] to i8* ; CHECK-NEXT: [[TARGETBLOCK:%.*]] = call i1 @outlined_ir_func_0(ptr [[PHINODE_CE_LOC]], ptr [[PHINODE1_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST1]]) ; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, ptr [[PHINODE_CE_LOC]], align 4
; CHECK-NEXT: [[TARGETBLOCK:%.*]] = call i1 @outlined_ir_func_0(i32* [[PHINODE_CE_LOC]], i32* [[PHINODE1_CE_LOC]]) ; CHECK-NEXT: [[PHINODE1_CE_RELOAD:%.*]] = load i32, ptr [[PHINODE1_CE_LOC]], align 4
; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, i32* [[PHINODE_CE_LOC]], align 4 ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[PHINODE_CE_LOC]])
; CHECK-NEXT: [[PHINODE1_CE_RELOAD:%.*]] = load i32, i32* [[PHINODE1_CE_LOC]], align 4 ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[PHINODE1_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST1]])
; CHECK-NEXT: br i1 [[TARGETBLOCK]], label [[BB5:%.*]], label [[BB1_AFTER_OUTLINE:%.*]] ; CHECK-NEXT: br i1 [[TARGETBLOCK]], label [[BB5:%.*]], label [[BB1_AFTER_OUTLINE:%.*]]
; CHECK: bb1_after_outline: ; CHECK: bb1_after_outline:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ] ; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ]
; CHECK-NEXT: [[PHINODE1:%.*]] = phi i32 [ [[PHINODE1_CE_RELOAD]], [[BB1]] ] ; CHECK-NEXT: [[PHINODE1:%.*]] = phi i32 [ [[PHINODE1_CE_RELOAD]], [[BB1]] ]
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
Show All 13 Lines
; CHECK: placeholder: ; CHECK: placeholder:
; CHECK-NEXT: [[A:%.*]] = sub i32 5, 4 ; CHECK-NEXT: [[A:%.*]] = sub i32 5, 4
; CHECK-NEXT: br label [[BB1_AFTER_OUTLINE_EXITSTUB:%.*]] ; CHECK-NEXT: br label [[BB1_AFTER_OUTLINE_EXITSTUB:%.*]]
; CHECK: bb5.split: ; CHECK: bb5.split:
; CHECK-NEXT: [[PHINODE_CE:%.*]] = phi i32 [ 5, [[BB1_TO_OUTLINE]] ], [ 5, [[BB2:%.*]] ] ; CHECK-NEXT: [[PHINODE_CE:%.*]] = phi i32 [ 5, [[BB1_TO_OUTLINE]] ], [ 5, [[BB2:%.*]] ]
; CHECK-NEXT: [[PHINODE1_CE:%.*]] = phi i32 [ 5, [[BB1_TO_OUTLINE]] ], [ 5, [[BB2]] ] ; CHECK-NEXT: [[PHINODE1_CE:%.*]] = phi i32 [ 5, [[BB1_TO_OUTLINE]] ], [ 5, [[BB2]] ]
; CHECK-NEXT: br label [[BB5_EXITSTUB:%.*]] ; CHECK-NEXT: br label [[BB5_EXITSTUB:%.*]]
; CHECK: bb5.exitStub: ; CHECK: bb5.exitStub:
; CHECK-NEXT: store i32 [[PHINODE_CE]], i32* [[TMP0:%.*]], align 4 ; CHECK-NEXT: store i32 [[PHINODE_CE]], ptr [[TMP0:%.*]], align 4
; CHECK-NEXT: store i32 [[PHINODE1_CE]], i32* [[TMP1:%.*]], align 4 ; CHECK-NEXT: store i32 [[PHINODE1_CE]], ptr [[TMP1:%.*]], align 4
; CHECK-NEXT: ret i1 true ; CHECK-NEXT: ret i1 true
; CHECK: bb1_after_outline.exitStub: ; CHECK: bb1_after_outline.exitStub:
; CHECK-NEXT: ret i1 false ; CHECK-NEXT: ret i1 false
; ;

llvm/test/Transforms/IROutliner/exit-block-phi-node-value-attribution.ll

Show All 36 Lines
bb5: bb5:
%phinode = phi i32 [5, %placeholder], [5, %bb1], [5, %bb2], [4, %bb3], [4, %bb4] %phinode = phi i32 [5, %placeholder], [5, %bb1], [5, %bb2], [4, %bb3], [4, %bb4]
ret void ret void
} }
; CHECK-LABEL: @f1( ; CHECK-LABEL: @f1(
; CHECK-NEXT: bb1: ; CHECK-NEXT: bb1:
; CHECK-NEXT: [[PHINODE_CE_LOC1:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[PHINODE_CE_LOC1:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[PHINODE_CE_LOC]] to i8* ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[PHINODE_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]]) ; CHECK-NEXT: call void @outlined_ir_func_0(ptr [[PHINODE_CE_LOC]], i32 0)
; CHECK-NEXT: call void @outlined_ir_func_0(i32* [[PHINODE_CE_LOC]], i32 0) ; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, ptr [[PHINODE_CE_LOC]], align 4
; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, i32* [[PHINODE_CE_LOC]], align 4 ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[PHINODE_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: placeholder: ; CHECK: placeholder:
; CHECK-NEXT: [[A:%.*]] = sub i32 5, 4 ; CHECK-NEXT: [[A:%.*]] = sub i32 5, 4
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: [[LT_CAST3:%.*]] = bitcast i32* [[PHINODE_CE_LOC1]] to i8* ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[PHINODE_CE_LOC1]])
; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST3]]) ; CHECK-NEXT: call void @outlined_ir_func_0(ptr [[PHINODE_CE_LOC1]], i32 1)
; CHECK-NEXT: call void @outlined_ir_func_0(i32* [[PHINODE_CE_LOC1]], i32 1) ; CHECK-NEXT: [[PHINODE_CE_RELOAD2:%.*]] = load i32, ptr [[PHINODE_CE_LOC1]], align 4
; CHECK-NEXT: [[PHINODE_CE_RELOAD2:%.*]] = load i32, i32* [[PHINODE_CE_LOC1]], align 4 ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[PHINODE_CE_LOC1]])
; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST3]])
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: placeholder1: ; CHECK: placeholder1:
; CHECK-NEXT: [[B:%.*]] = add i32 5, 4 ; CHECK-NEXT: [[B:%.*]] = add i32 5, 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ 5, [[PLACEHOLDER:%.*]] ], [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ], [ [[PHINODE_CE_RELOAD2]], [[BB3:%.*]] ] ; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ 5, [[PLACEHOLDER:%.*]] ], [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ], [ [[PHINODE_CE_RELOAD2]], [[BB3:%.*]] ]
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
Show All 15 Lines
; CHECK-NEXT: [[PHINODE_CE:%.*]] = phi i32 [ 5, [[BB1_TO_OUTLINE]] ], [ 5, [[BB2]] ] ; CHECK-NEXT: [[PHINODE_CE:%.*]] = phi i32 [ 5, [[BB1_TO_OUTLINE]] ], [ 5, [[BB2]] ]
; CHECK-NEXT: br label [[BB5_EXITSTUB:%.*]] ; CHECK-NEXT: br label [[BB5_EXITSTUB:%.*]]
; CHECK: bb5.exitStub: ; CHECK: bb5.exitStub:
; CHECK-NEXT: switch i32 [[TMP1:%.*]], label [[FINAL_BLOCK_0:%.*]] [ ; CHECK-NEXT: switch i32 [[TMP1:%.*]], label [[FINAL_BLOCK_0:%.*]] [
; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_0:%.*]] ; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_0:%.*]]
; CHECK-NEXT: i32 1, label [[OUTPUT_BLOCK_1_0:%.*]] ; CHECK-NEXT: i32 1, label [[OUTPUT_BLOCK_1_0:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: output_block_0_0: ; CHECK: output_block_0_0:
; CHECK-NEXT: store i32 [[PHINODE_CE]], i32* [[TMP0:%.*]], align 4 ; CHECK-NEXT: store i32 [[PHINODE_CE]], ptr [[TMP0:%.*]], align 4
; CHECK-NEXT: br label [[FINAL_BLOCK_0]] ; CHECK-NEXT: br label [[FINAL_BLOCK_0]]
; CHECK: output_block_1_0: ; CHECK: output_block_1_0:
; CHECK-NEXT: store i32 [[TMP7]], i32* [[TMP0]], align 4 ; CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP0]], align 4
; CHECK-NEXT: br label [[FINAL_BLOCK_0]] ; CHECK-NEXT: br label [[FINAL_BLOCK_0]]
; CHECK: final_block_0: ; CHECK: final_block_0:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;

llvm/test/Transforms/IROutliner/exit-phi-nodes-incoming-value-constant-argument.ll

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Linesbb5:
%f = phi i32 [ 0, %bb1 ], [ 1, %bb2 ], [ 1, %bb3 ] %f = phi i32 [ 0, %bb1 ], [ 1, %bb2 ], [ 1, %bb3 ]
ret void ret void
} }
; CHECK-LABEL: @func1( ; CHECK-LABEL: @func1(
; CHECK-NEXT: bb1: ; CHECK-NEXT: bb1:
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: [[A:%.*]] = add i32 [[TMP0:%.*]], [[TMP1:%.*]] ; CHECK-NEXT: [[A:%.*]] = add i32 [[TMP0:%.*]], [[TMP1:%.*]]
; CHECK-NEXT: call void @outlined_ir_func_0(i32 [[TMP0]], i32 [[TMP1]], i32 [[A]], i32* null, i32 -1) ; CHECK-NEXT: call void @outlined_ir_func_0(i32 [[TMP0]], i32 [[TMP1]], i32 [[A]], ptr null, i32 -1)
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb4: ; CHECK: bb4:
; CHECK-NEXT: [[E:%.*]] = sub i32 [[TMP0]], [[TMP1]] ; CHECK-NEXT: [[E:%.*]] = sub i32 [[TMP0]], [[TMP1]]
; CHECK-NEXT: br label [[BB2:%.*]] ; CHECK-NEXT: br label [[BB2:%.*]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; ;
; CHECK-LABEL: @func2( ; CHECK-LABEL: @func2(
; CHECK-NEXT: bb1: ; CHECK-NEXT: bb1:
; CHECK-NEXT: [[F_CE_LOC:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[F_CE_LOC:%.*]] = alloca i32, align 4
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: [[A:%.*]] = sub i32 [[TMP0:%.*]], [[TMP1:%.*]] ; CHECK-NEXT: [[A:%.*]] = sub i32 [[TMP0:%.*]], [[TMP1:%.*]]
; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[F_CE_LOC]] to i8* ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[F_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]]) ; CHECK-NEXT: call void @outlined_ir_func_0(i32 [[TMP0]], i32 [[TMP1]], i32 1, ptr [[F_CE_LOC]], i32 0)
; CHECK-NEXT: call void @outlined_ir_func_0(i32 [[TMP0]], i32 [[TMP1]], i32 1, i32* [[F_CE_LOC]], i32 0) ; CHECK-NEXT: [[F_CE_RELOAD:%.*]] = load i32, ptr [[F_CE_LOC]], align 4
; CHECK-NEXT: [[F_CE_RELOAD:%.*]] = load i32, i32* [[F_CE_LOC]], align 4 ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[F_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb4: ; CHECK: bb4:
; CHECK-NEXT: [[E:%.*]] = add i32 [[TMP0]], [[TMP1]] ; CHECK-NEXT: [[E:%.*]] = add i32 [[TMP0]], [[TMP1]]
; CHECK-NEXT: br label [[BB2:%.*]] ; CHECK-NEXT: br label [[BB2:%.*]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: [[F:%.*]] = phi i32 [ 0, [[BB1:%.*]] ], [ [[F_CE_RELOAD]], [[BB2]] ] ; CHECK-NEXT: [[F:%.*]] = phi i32 [ 0, [[BB1:%.*]] ], [ [[F_CE_RELOAD]], [[BB2]] ]
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; ;
; CHECK-LABEL: define internal void @outlined_ir_func_0( ; CHECK-LABEL: define internal void @outlined_ir_func_0(
; CHECK-NEXT: newFuncRoot: ; CHECK-NEXT: newFuncRoot:
; CHECK-NEXT: br label [[BB2_TO_OUTLINE:%.*]] ; CHECK-NEXT: br label [[BB2_TO_OUTLINE:%.*]]
; CHECK: bb2_to_outline: ; CHECK: bb2_to_outline:
; CHECK-NEXT: [[B:%.*]] = add i32 [[TMP0:%.*]], [[TMP1:%.*]] ; CHECK-NEXT: [[B:%.*]] = add i32 [[TMP0:%.*]], [[TMP1:%.*]]
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[B]], [[TMP2:%.*]] ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[B]], [[TMP2:%.*]]
; CHECK-NEXT: br i1 [[C]], label [[PHI_BLOCK:%.*]], label [[BB3:%.*]] ; CHECK-NEXT: br i1 [[C]], label [[PHI_BLOCK:%.*]], label [[BB3:%.*]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: [[D:%.*]] = add i32 [[TMP0]], [[TMP1]] ; CHECK-NEXT: [[D:%.*]] = add i32 [[TMP0]], [[TMP1]]
; CHECK-NEXT: br label [[PHI_BLOCK]] ; CHECK-NEXT: br label [[PHI_BLOCK]]
; CHECK: bb5.exitStub: ; CHECK: bb5.exitStub:
; CHECK-NEXT: switch i32 [[TMP4:%.*]], label [[FINAL_BLOCK_0:%.*]] [ ; CHECK-NEXT: switch i32 [[TMP4:%.*]], label [[FINAL_BLOCK_0:%.*]] [
; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_1_0:%.*]] ; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_1_0:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: output_block_1_0: ; CHECK: output_block_1_0:
; CHECK-NEXT: store i32 [[TMP5:%.*]], i32* [[TMP3:%.*]], align 4 ; CHECK-NEXT: store i32 [[TMP5:%.*]], ptr [[TMP3:%.*]], align 4
; CHECK-NEXT: br label [[FINAL_BLOCK_0]] ; CHECK-NEXT: br label [[FINAL_BLOCK_0]]
; CHECK: phi_block: ; CHECK: phi_block:
; CHECK-NEXT: [[TMP5]] = phi i32 [ [[TMP2]], [[BB2_TO_OUTLINE]] ], [ [[TMP2]], [[BB3]] ] ; CHECK-NEXT: [[TMP5]] = phi i32 [ [[TMP2]], [[BB2_TO_OUTLINE]] ], [ [[TMP2]], [[BB3]] ]
; CHECK-NEXT: br label [[BB5_EXITSTUB:%.*]] ; CHECK-NEXT: br label [[BB5_EXITSTUB:%.*]]
; CHECK: final_block_0: ; CHECK: final_block_0:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;

llvm/test/Transforms/IROutliner/no-external-block-entries.ll

Show All 29 Linesblock_5:
br i1 0, label %block_6, label %block_4 br i1 0, label %block_6, label %block_4
block_6: block_6:
unreachable unreachable
} }
; CHECK-LABEL: @fn1( ; CHECK-LABEL: @fn1(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[B_CE_LOC:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[B_CE_LOC:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[B_CE_LOC]] to i8* ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[B_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]]) ; CHECK-NEXT: call void @outlined_ir_func_0(ptr [[B_CE_LOC]], i32 0)
; CHECK-NEXT: call void @outlined_ir_func_0(i32* [[B_CE_LOC]], i32 0) ; CHECK-NEXT: [[B_CE_RELOAD:%.*]] = load i32, ptr [[B_CE_LOC]], align 4
; CHECK-NEXT: [[B_CE_RELOAD:%.*]] = load i32, i32* [[B_CE_LOC]], align 4 ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[B_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
; CHECK-NEXT: br label [[BLOCK_3:%.*]] ; CHECK-NEXT: br label [[BLOCK_3:%.*]]
; CHECK: block_3: ; CHECK: block_3:
; CHECK-NEXT: [[B:%.*]] = phi i32 [ [[B_CE_RELOAD]], [[ENTRY:%.*]] ] ; CHECK-NEXT: [[B:%.*]] = phi i32 [ [[B_CE_RELOAD]], [[ENTRY:%.*]] ]
; CHECK-NEXT: call void @outlined_ir_func_0(i32* null, i32 -1) ; CHECK-NEXT: call void @outlined_ir_func_0(ptr null, i32 -1)
; CHECK-NEXT: br label [[BLOCK_6:%.*]] ; CHECK-NEXT: br label [[BLOCK_6:%.*]]
; CHECK: block_6: ; CHECK: block_6:
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; ;
; ;
; CHECK-LABEL: define internal void @outlined_ir_func_0( ; CHECK-LABEL: define internal void @outlined_ir_func_0(
; CHECK-NEXT: newFuncRoot: ; CHECK-NEXT: newFuncRoot:
; CHECK-NEXT: br label [[ENTRY_TO_OUTLINE:%.*]] ; CHECK-NEXT: br label [[ENTRY_TO_OUTLINE:%.*]]
Show All 9 Lines
; CHECK: block_3.split: ; CHECK: block_3.split:
; CHECK-NEXT: [[B_CE:%.*]] = phi i32 [ 0, [[BLOCK_2]] ], [ 1, [[BLOCK_1]] ] ; CHECK-NEXT: [[B_CE:%.*]] = phi i32 [ 0, [[BLOCK_2]] ], [ 1, [[BLOCK_1]] ]
; CHECK-NEXT: br label [[BLOCK_3_EXITSTUB:%.*]] ; CHECK-NEXT: br label [[BLOCK_3_EXITSTUB:%.*]]
; CHECK: block_3.exitStub: ; CHECK: block_3.exitStub:
; CHECK-NEXT: switch i32 [[TMP1:%.*]], label [[FINAL_BLOCK_0:%.*]] [ ; CHECK-NEXT: switch i32 [[TMP1:%.*]], label [[FINAL_BLOCK_0:%.*]] [
; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_0:%.*]] ; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_0:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: output_block_0_0: ; CHECK: output_block_0_0:
; CHECK-NEXT: store i32 [[B_CE]], i32* [[TMP0:%.*]], align 4 ; CHECK-NEXT: store i32 [[B_CE]], ptr [[TMP0:%.*]], align 4
; CHECK-NEXT: br label [[FINAL_BLOCK_0]] ; CHECK-NEXT: br label [[FINAL_BLOCK_0]]
; CHECK: final_block_0: ; CHECK: final_block_0:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;

llvm/test/Transforms/IROutliner/one-external-incoming-block-phi-node.ll

Show All 27 Linesblock_5:
br i1 0, label %block_6, label %block_4 br i1 0, label %block_6, label %block_4
block_6: block_6:
unreachable unreachable
} }
; CHECK-LABEL: @fn1( ; CHECK-LABEL: @fn1(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[B_CE_LOC:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[B_CE_LOC:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[B_CE_LOC]] to i8* ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[B_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]]) ; CHECK-NEXT: call void @outlined_ir_func_0(ptr [[B_CE_LOC]], i32 0)
; CHECK-NEXT: call void @outlined_ir_func_0(i32* [[B_CE_LOC]], i32 0) ; CHECK-NEXT: [[B_CE_RELOAD:%.*]] = load i32, ptr [[B_CE_LOC]], align 4
; CHECK-NEXT: [[B_CE_RELOAD:%.*]] = load i32, i32* [[B_CE_LOC]], align 4 ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[B_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
; CHECK-NEXT: br label [[BLOCK_3:%.*]] ; CHECK-NEXT: br label [[BLOCK_3:%.*]]
; CHECK: block_3: ; CHECK: block_3:
; CHECK-NEXT: [[B:%.*]] = phi i32 [ [[B_CE_RELOAD]], [[ENTRY:%.*]] ] ; CHECK-NEXT: [[B:%.*]] = phi i32 [ [[B_CE_RELOAD]], [[ENTRY:%.*]] ]
; CHECK-NEXT: call void @outlined_ir_func_0(i32* null, i32 -1) ; CHECK-NEXT: call void @outlined_ir_func_0(ptr null, i32 -1)
; CHECK-NEXT: br label [[BLOCK_6:%.*]] ; CHECK-NEXT: br label [[BLOCK_6:%.*]]
; CHECK: block_6: ; CHECK: block_6:
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; ;
; ;
; CHECK-LABEL: define internal void @outlined_ir_func_0( ; CHECK-LABEL: define internal void @outlined_ir_func_0(
; CHECK-NEXT: newFuncRoot: ; CHECK-NEXT: newFuncRoot:
; CHECK-NEXT: br label [[ENTRY_TO_OUTLINE:%.*]] ; CHECK-NEXT: br label [[ENTRY_TO_OUTLINE:%.*]]
; CHECK: entry_to_outline: ; CHECK: entry_to_outline:
; CHECK-NEXT: br label [[BLOCK_1:%.*]] ; CHECK-NEXT: br label [[BLOCK_1:%.*]]
; CHECK: block_1: ; CHECK: block_1:
; CHECK-NEXT: [[A:%.*]] = phi i32 [ 0, [[BLOCK_2:%.*]] ], [ 1, [[ENTRY_TO_OUTLINE]] ] ; CHECK-NEXT: [[A:%.*]] = phi i32 [ 0, [[BLOCK_2:%.*]] ], [ 1, [[ENTRY_TO_OUTLINE]] ]
; CHECK-NEXT: br i1 false, label [[BLOCK_3_SPLIT:%.*]], label [[BLOCK_2]] ; CHECK-NEXT: br i1 false, label [[BLOCK_3_SPLIT:%.*]], label [[BLOCK_2]]
; CHECK: block_2: ; CHECK: block_2:
; CHECK-NEXT: br i1 false, label [[BLOCK_3_SPLIT]], label [[BLOCK_1]] ; CHECK-NEXT: br i1 false, label [[BLOCK_3_SPLIT]], label [[BLOCK_1]]
; CHECK: block_3.split: ; CHECK: block_3.split:
; CHECK-NEXT: [[B_CE:%.*]] = phi i32 [ 0, [[BLOCK_2]] ], [ 1, [[BLOCK_1]] ] ; CHECK-NEXT: [[B_CE:%.*]] = phi i32 [ 0, [[BLOCK_2]] ], [ 1, [[BLOCK_1]] ]
; CHECK-NEXT: br label [[BLOCK_3_EXITSTUB:%.*]] ; CHECK-NEXT: br label [[BLOCK_3_EXITSTUB:%.*]]
; CHECK: block_3.exitStub: ; CHECK: block_3.exitStub:
; CHECK-NEXT: switch i32 [[TMP1:%.*]], label [[FINAL_BLOCK_0:%.*]] [ ; CHECK-NEXT: switch i32 [[TMP1:%.*]], label [[FINAL_BLOCK_0:%.*]] [
; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_0:%.*]] ; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_0:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: output_block_0_0: ; CHECK: output_block_0_0:
; CHECK-NEXT: store i32 [[B_CE]], i32* [[TMP0:%.*]], align 4 ; CHECK-NEXT: store i32 [[B_CE]], ptr [[TMP0:%.*]], align 4
; CHECK-NEXT: br label [[FINAL_BLOCK_0]] ; CHECK-NEXT: br label [[FINAL_BLOCK_0]]
; CHECK: final_block_0: ; CHECK: final_block_0:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;

llvm/test/Transforms/IROutliner/phi-node-exit-path-order.ll

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Linesbb5:
ret void ret void
} }
; CHECK-LABEL: @func1( ; CHECK-LABEL: @func1(
; CHECK-NEXT: bb1: ; CHECK-NEXT: bb1:
; CHECK-NEXT: [[F_CE_LOC:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[F_CE_LOC:%.*]] = alloca i32, align 4
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: [[A:%.*]] = add i32 [[TMP0:%.*]], [[TMP1:%.*]] ; CHECK-NEXT: [[A:%.*]] = add i32 [[TMP0:%.*]], [[TMP1:%.*]]
; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[F_CE_LOC]] to i8* ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[F_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]]) ; CHECK-NEXT: call void @outlined_ir_func_0(i32 [[TMP0]], i32 [[TMP1]], ptr [[F_CE_LOC]], i32 0)
; CHECK-NEXT: call void @outlined_ir_func_0(i32 [[TMP0]], i32 [[TMP1]], i32* [[F_CE_LOC]], i32 0) ; CHECK-NEXT: [[F_CE_RELOAD:%.*]] = load i32, ptr [[F_CE_LOC]], align 4
; CHECK-NEXT: [[F_CE_RELOAD:%.*]] = load i32, i32* [[F_CE_LOC]], align 4 ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[F_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb4: ; CHECK: bb4:
; CHECK-NEXT: [[E:%.*]] = sub i32 [[TMP0]], [[TMP1]] ; CHECK-NEXT: [[E:%.*]] = sub i32 [[TMP0]], [[TMP1]]
; CHECK-NEXT: br label [[BB2:%.*]] ; CHECK-NEXT: br label [[BB2:%.*]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: [[F:%.*]] = phi i32 [ 0, [[BB1:%.*]] ], [ [[F_CE_RELOAD]], [[BB2]] ] ; CHECK-NEXT: [[F:%.*]] = phi i32 [ 0, [[BB1:%.*]] ], [ [[F_CE_RELOAD]], [[BB2]] ]
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; ;
; CHECK-LABEL: @func2( ; CHECK-LABEL: @func2(
; CHECK-NEXT: bb1: ; CHECK-NEXT: bb1:
; CHECK-NEXT: [[F_CE_LOC:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[F_CE_LOC:%.*]] = alloca i32, align 4
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: [[A:%.*]] = sub i32 [[TMP0:%.*]], [[TMP1:%.*]] ; CHECK-NEXT: [[A:%.*]] = sub i32 [[TMP0:%.*]], [[TMP1:%.*]]
; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[F_CE_LOC]] to i8* ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[F_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]]) ; CHECK-NEXT: call void @outlined_ir_func_0(i32 [[TMP0]], i32 [[TMP1]], ptr [[F_CE_LOC]], i32 1)
; CHECK-NEXT: call void @outlined_ir_func_0(i32 [[TMP0]], i32 [[TMP1]], i32* [[F_CE_LOC]], i32 1) ; CHECK-NEXT: [[F_CE_RELOAD:%.*]] = load i32, ptr [[F_CE_LOC]], align 4
; CHECK-NEXT: [[F_CE_RELOAD:%.*]] = load i32, i32* [[F_CE_LOC]], align 4 ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[F_CE_LOC]])
; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb4: ; CHECK: bb4:
; CHECK-NEXT: [[E:%.*]] = add i32 [[TMP0]], [[TMP1]] ; CHECK-NEXT: [[E:%.*]] = add i32 [[TMP0]], [[TMP1]]
; CHECK-NEXT: br label [[BB2:%.*]] ; CHECK-NEXT: br label [[BB2:%.*]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: [[F:%.*]] = phi i32 [ 0, [[BB1:%.*]] ], [ [[F_CE_RELOAD]], [[BB2]] ] ; CHECK-NEXT: [[F:%.*]] = phi i32 [ 0, [[BB1:%.*]] ], [ [[F_CE_RELOAD]], [[BB2]] ]
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
Show All 13 Lines
; CHECK-NEXT: [[F_CE:%.*]] = phi i32 [ 1, [[BB2_TO_OUTLINE]] ], [ 1, [[BB3]] ] ; CHECK-NEXT: [[F_CE:%.*]] = phi i32 [ 1, [[BB2_TO_OUTLINE]] ], [ 1, [[BB3]] ]
; CHECK-NEXT: br label [[BB5_EXITSTUB:%.*]] ; CHECK-NEXT: br label [[BB5_EXITSTUB:%.*]]
; CHECK: bb5.exitStub: ; CHECK: bb5.exitStub:
; CHECK-NEXT: switch i32 [[TMP3:%.*]], label [[FINAL_BLOCK_0:%.*]] [ ; CHECK-NEXT: switch i32 [[TMP3:%.*]], label [[FINAL_BLOCK_0:%.*]] [
; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_0:%.*]] ; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_0:%.*]]
; CHECK-NEXT: i32 1, label [[OUTPUT_BLOCK_1_0:%.*]] ; CHECK-NEXT: i32 1, label [[OUTPUT_BLOCK_1_0:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: output_block_0_0: ; CHECK: output_block_0_0:
; CHECK-NEXT: store i32 [[F_CE]], i32* [[TMP2:%.*]], align 4 ; CHECK-NEXT: store i32 [[F_CE]], ptr [[TMP2:%.*]], align 4
; CHECK-NEXT: br label [[FINAL_BLOCK_0]] ; CHECK-NEXT: br label [[FINAL_BLOCK_0]]
; CHECK: output_block_1_0: ; CHECK: output_block_1_0:
; CHECK-NEXT: store i32 [[TMP4]], i32* [[TMP2]], align 4 ; CHECK-NEXT: store i32 [[TMP4]], ptr [[TMP2]], align 4
; CHECK-NEXT: br label [[FINAL_BLOCK_0]] ; CHECK-NEXT: br label [[FINAL_BLOCK_0]]
; CHECK: final_block_0: ; CHECK: final_block_0:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;

llvm/test/Transforms/LowerTypeTests/export-alias.ll

; RUN: opt -S %s -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/exported-funcs.yaml | FileCheck %s ; RUN: opt -S %s -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/exported-funcs.yaml | FileCheck %s
; ;
; CHECK: @alias1 = weak alias void (), void ()* @external_addrtaken ; CHECK: @alias1 = weak alias void (), ptr @external_addrtaken
; CHECK: @alias2 = hidden alias void (), void ()* @external_addrtaken ; CHECK: @alias2 = hidden alias void (), ptr @external_addrtaken
; CHECK-NOT: @alias3 = alias ; CHECK-NOT: @alias3 = alias
; CHECK-NOT: @not_present ; CHECK-NOT: @not_present
target triple = "x86_64-unknown-linux" target triple = "x86_64-unknown-linux"
!cfi.functions = !{!0, !2, !3} !cfi.functions = !{!0, !2, !3}
!aliases = !{!4, !5, !6} !aliases = !{!4, !5, !6}
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llvm/test/Transforms/LowerTypeTests/export-allones.ll

Show First 20 Lines • Show All 135 Lines • ▼ Show 20 Lines
!126 = !{i32 500, !"typeid2"} !126 = !{i32 500, !"typeid2"}
!127 = !{i32 504, !"typeid2"} !127 = !{i32 504, !"typeid2"}
!128 = !{i32 508, !"typeid2"} !128 = !{i32 508, !"typeid2"}
!129 = !{i32 512, !"typeid2"} !129 = !{i32 512, !"typeid2"}
!130 = !{i32 516, !"typeid2"} !130 = !{i32 516, !"typeid2"}
; CHECK: [[G:@[0-9]+]] = private constant { [2048 x i8] } zeroinitializer ; CHECK: [[G:@[0-9]+]] = private constant { [2048 x i8] } zeroinitializer
; CHECK: @__typeid_typeid1_global_addr = hidden alias i8, getelementptr inbounds ({ [2048 x i8] }, { [2048 x i8] }* [[G]], i32 0, i32 0, i32 0) ; CHECK: @__typeid_typeid1_global_addr = hidden alias i8, ptr [[G]]
; X86: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 1 to i8*) ; X86: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 1 to ptr)
; X86: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 1 to i8*) ; X86: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 1 to ptr)
; CHECK: @__typeid_typeid2_global_addr = hidden alias i8, getelementptr inbounds ({ [2048 x i8] }, { [2048 x i8] }* [[G]], i32 0, i32 0, i64 4) ; CHECK: @__typeid_typeid2_global_addr = hidden alias i8, getelementptr (i8, ptr [[G]], i64 4)
; X86: @__typeid_typeid2_align = hidden alias i8, inttoptr (i8 2 to i8*) ; X86: @__typeid_typeid2_align = hidden alias i8, inttoptr (i8 2 to ptr)
; X86: @__typeid_typeid2_size_m1 = hidden alias i8, inttoptr (i64 128 to i8*) ; X86: @__typeid_typeid2_size_m1 = hidden alias i8, inttoptr (i64 128 to ptr)
; ARM-NOT: alias {{.*}} inttoptr ; ARM-NOT: alias {{.*}} inttoptr
; CHECK: @foo = alias [2048 x i8], getelementptr inbounds ({ [2048 x i8] }, { [2048 x i8] }* [[G]], i32 0, i32 0) ; CHECK: @foo = alias [2048 x i8], ptr [[G]]
; SUMMARY: TypeIdMap: ; SUMMARY: TypeIdMap:
; SUMMARY-NEXT: typeid1: ; SUMMARY-NEXT: typeid1:
; SUMMARY-NEXT: TTRes: ; SUMMARY-NEXT: TTRes:
; SUMMARY-NEXT: Kind: AllOnes ; SUMMARY-NEXT: Kind: AllOnes
; SUMMARY-NEXT: SizeM1BitWidth: 7 ; SUMMARY-NEXT: SizeM1BitWidth: 7
; SUMMARY-X86-NEXT: AlignLog2: 0 ; SUMMARY-X86-NEXT: AlignLog2: 0
; SUMMARY-X86-NEXT: SizeM1: 0 ; SUMMARY-X86-NEXT: SizeM1: 0
Show All 20 Lines

llvm/test/Transforms/LowerTypeTests/export-bytearray.ll

; RUN: opt -mtriple=x86_64-unknown-linux -S -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/use-typeid1-typeid2.yaml -lowertypetests-write-summary=%t < %s | FileCheck --check-prefixes=CHECK,X86 %s ; RUN: opt -mtriple=x86_64-unknown-linux -S -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/use-typeid1-typeid2.yaml -lowertypetests-write-summary=%t < %s | FileCheck --check-prefixes=CHECK,X86 %s
; RUN: FileCheck --check-prefixes=SUMMARY,SUMMARY-X86 %s < %t ; RUN: FileCheck --check-prefixes=SUMMARY,SUMMARY-X86 %s < %t
; RUN: opt -mtriple=aarch64-unknown-linux -S -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/use-typeid1-typeid2.yaml -lowertypetests-write-summary=%t < %s | FileCheck --check-prefixes=CHECK,ARM %s ; RUN: opt -mtriple=aarch64-unknown-linux -S -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/use-typeid1-typeid2.yaml -lowertypetests-write-summary=%t < %s | FileCheck --check-prefixes=CHECK,ARM %s
; RUN: FileCheck --check-prefixes=SUMMARY,SUMMARY-ARM %s < %t ; RUN: FileCheck --check-prefixes=SUMMARY,SUMMARY-ARM %s < %t
@foo = constant [2048 x i8] zeroinitializer, !type !0, !type !1, !type !2, !type !3 @foo = constant [2048 x i8] zeroinitializer, !type !0, !type !1, !type !2, !type !3
!0 = !{i32 0, !"typeid1"} !0 = !{i32 0, !"typeid1"}
!1 = !{i32 130, !"typeid1"} !1 = !{i32 130, !"typeid1"}
!2 = !{i32 4, !"typeid2"} !2 = !{i32 4, !"typeid2"}
!3 = !{i32 1032, !"typeid2"} !3 = !{i32 1032, !"typeid2"}
; CHECK: [[G:@[0-9]+]] = private constant { [2048 x i8] } zeroinitializer ; CHECK: [[G:@[0-9]+]] = private constant { [2048 x i8] } zeroinitializer
; CHECK: [[B:@[0-9]+]] = private constant [258 x i8] c"\03\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\02\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\01" ; CHECK: [[B:@[0-9]+]] = private constant [258 x i8] c"\03\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\02\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\01"
; CHECK: @__typeid_typeid1_global_addr = hidden alias i8, getelementptr inbounds ({ [2048 x i8] }, { [2048 x i8] }* [[G]], i32 0, i32 0, i32 0) ; CHECK: @__typeid_typeid1_global_addr = hidden alias i8, ptr [[G]]
; X86: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 1 to i8*) ; X86: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 1 to ptr)
; X86: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 65 to i8*) ; X86: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 65 to ptr)
; CHECK: @__typeid_typeid1_byte_array = hidden alias i8, i8* @bits.1 ; CHECK: @__typeid_typeid1_byte_array = hidden alias i8, ptr @bits.1
; X86: @__typeid_typeid1_bit_mask = hidden alias i8, inttoptr (i8 2 to i8*) ; X86: @__typeid_typeid1_bit_mask = hidden alias i8, inttoptr (i8 2 to ptr)
; CHECK: @__typeid_typeid2_global_addr = hidden alias i8, getelementptr inbounds ({ [2048 x i8] }, { [2048 x i8] }* [[G]], i32 0, i32 0, i64 4) ; CHECK: @__typeid_typeid2_global_addr = hidden alias i8, getelementptr (i8, ptr [[G]], i64 4)
; X86: @__typeid_typeid2_align = hidden alias i8, inttoptr (i8 2 to i8*) ; X86: @__typeid_typeid2_align = hidden alias i8, inttoptr (i8 2 to ptr)
; X86: @__typeid_typeid2_size_m1 = hidden alias i8, inttoptr (i64 257 to i8*) ; X86: @__typeid_typeid2_size_m1 = hidden alias i8, inttoptr (i64 257 to ptr)
; CHECK: @__typeid_typeid2_byte_array = hidden alias i8, i8* @bits ; CHECK: @__typeid_typeid2_byte_array = hidden alias i8, ptr @bits
; X86: @__typeid_typeid2_bit_mask = hidden alias i8, inttoptr (i8 1 to i8*) ; X86: @__typeid_typeid2_bit_mask = hidden alias i8, inttoptr (i8 1 to ptr)
; ARM-NOT: alias {{.*}} inttoptr ; ARM-NOT: alias {{.*}} inttoptr
; CHECK: @foo = alias [2048 x i8], getelementptr inbounds ({ [2048 x i8] }, { [2048 x i8] }* [[G]], i32 0, i32 0) ; CHECK: @foo = alias [2048 x i8], ptr [[G]]
; CHECK: @bits = private alias i8, getelementptr inbounds ([258 x i8], [258 x i8]* [[B]], i64 0, i64 0) ; CHECK: @bits = private alias i8, ptr [[B]]
; CHECK: @bits.1 = private alias i8, getelementptr inbounds ([258 x i8], [258 x i8]* [[B]], i64 0, i64 0) ; CHECK: @bits.1 = private alias i8, ptr [[B]]
; SUMMARY: TypeIdMap: ; SUMMARY: TypeIdMap:
; SUMMARY-NEXT: typeid1: ; SUMMARY-NEXT: typeid1:
; SUMMARY-NEXT: TTRes: ; SUMMARY-NEXT: TTRes:
; SUMMARY-NEXT: Kind: ByteArray ; SUMMARY-NEXT: Kind: ByteArray
; SUMMARY-NEXT: SizeM1BitWidth: 7 ; SUMMARY-NEXT: SizeM1BitWidth: 7
; SUMMARY-X86-NEXT: AlignLog2: 0 ; SUMMARY-X86-NEXT: AlignLog2: 0
; SUMMARY-X86-NEXT: SizeM1: 0 ; SUMMARY-X86-NEXT: SizeM1: 0
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llvm/test/Transforms/LowerTypeTests/export-icall.ll

Show All 30 Lines
!10 = !{!"f3", i8 0, !2} !10 = !{!"f3", i8 0, !2}
!4 = !{!"external", i8 1, !2} !4 = !{!"external", i8 1, !2}
!5 = !{!"external_weak", i8 2, !2} !5 = !{!"external_weak", i8 2, !2}
!6 = !{!"g", i8 0, !7} !6 = !{!"g", i8 0, !7}
!7 = !{i64 0, !"typeid2"} !7 = !{i64 0, !"typeid2"}
!8 = !{i64 0, !"typeid3"} !8 = !{i64 0, !"typeid3"}
; CHECK-DAG: @__typeid_typeid1_global_addr = hidden alias i8, bitcast (void ()* [[JT1:.*]] to i8*) ; CHECK-DAG: @__typeid_typeid1_global_addr = hidden alias i8, ptr [[JT1:.*]]
; CHECK-DAG: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 3 to i8*) ; CHECK-DAG: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 3 to ptr)
; CHECK-DAG: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 4 to i8*) ; CHECK-DAG: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 4 to ptr)
; CHECK-DAG: @h = alias void (i8), bitcast (void ()* [[JT1]] to void (i8)*) ; CHECK-DAG: @h = alias void (i8), ptr [[JT1]]
; CHECK-DAG: @f = alias void (i32), {{.*}}getelementptr {{.*}}void ()* [[JT1]] ; CHECK-DAG: @f = alias void (i32), {{.*}}getelementptr {{.*}}ptr [[JT1]]
; CHECK-DAG: @f2 = alias void (i32), {{.*}}getelementptr {{.*}}void ()* [[JT1]] ; CHECK-DAG: @f2 = alias void (i32), {{.*}}getelementptr {{.*}}ptr [[JT1]]
; CHECK-DAG: @external.cfi_jt = hidden alias void (), {{.*}}getelementptr {{.*}}void ()* [[JT1]] ; CHECK-DAG: @external.cfi_jt = hidden alias void (), {{.*}}getelementptr {{.*}}ptr [[JT1]]
; CHECK-DAG: @external_weak.cfi_jt = hidden alias void (), {{.*}}getelementptr {{.*}}void ()* [[JT1]] ; CHECK-DAG: @external_weak.cfi_jt = hidden alias void (), {{.*}}getelementptr {{.*}}ptr [[JT1]]
; CHECK-DAG: @__typeid_typeid2_global_addr = hidden alias i8, bitcast (void ()* [[JT2:.*]] to i8*) ; CHECK-DAG: @__typeid_typeid2_global_addr = hidden alias i8, ptr [[JT2:.*]]
; CHECK-DAG: @g = alias void (), void ()* [[JT2]] ; CHECK-DAG: @g = alias void (), ptr [[JT2]]
; CHECK-DAG: define hidden void @h.cfi(i8 {{.*}}) !type !{{.*}} ; CHECK-DAG: define hidden void @h.cfi(i8 {{.*}}) !type !{{.*}}
; CHECK-DAG: declare !type !{{.*}} void @external() ; CHECK-DAG: declare !type !{{.*}} void @external()
; CHECK-DAG: declare !type !{{.*}} void @external_weak() ; CHECK-DAG: declare !type !{{.*}} void @external_weak()
; CHECK-DAG: declare !type !{{.*}} void @f.cfi(i32) ; CHECK-DAG: declare !type !{{.*}} void @f.cfi(i32)
; CHECK-DAG: declare !type !{{.*}} void @f2.cfi(i32) ; CHECK-DAG: declare !type !{{.*}} void @f2.cfi(i32)
; CHECK-DAG: define void @f3(i32 {{.*}}) !type !3 ; CHECK-DAG: define void @f3(i32 {{.*}}) !type !3
; CHECK-DAG: !3 = !{i64 0, !"typeid3"} ; CHECK-DAG: !3 = !{i64 0, !"typeid3"}
Show All 32 Lines

llvm/test/Transforms/LowerTypeTests/export-inline.ll

; RUN: opt -mtriple=x86_64-unknown-linux -S -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/use-typeid1-typeid2.yaml -lowertypetests-write-summary=%t < %s | FileCheck --check-prefix=CHECK %s ; RUN: opt -mtriple=x86_64-unknown-linux -S -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/use-typeid1-typeid2.yaml -lowertypetests-write-summary=%t < %s | FileCheck --check-prefix=CHECK %s
; RUN: FileCheck --check-prefixes=SUMMARY,SUMMARY-X86 %s < %t ; RUN: FileCheck --check-prefixes=SUMMARY,SUMMARY-X86 %s < %t
; RUN: opt -mtriple=aarch64-unknown-linux -S -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/use-typeid1-typeid2.yaml -lowertypetests-write-summary=%t < %s | FileCheck --check-prefix=CHECK %s ; RUN: opt -mtriple=aarch64-unknown-linux -S -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/use-typeid1-typeid2.yaml -lowertypetests-write-summary=%t < %s | FileCheck --check-prefix=CHECK %s
; RUN: FileCheck --check-prefixes=SUMMARY,SUMMARY-ARM %s < %t ; RUN: FileCheck --check-prefixes=SUMMARY,SUMMARY-ARM %s < %t
@foo = constant [2048 x i8] zeroinitializer, !type !0, !type !1, !type !2, !type !3 @foo = constant [2048 x i8] zeroinitializer, !type !0, !type !1, !type !2, !type !3
!0 = !{i32 0, !"typeid1"} !0 = !{i32 0, !"typeid1"}
!1 = !{i32 6, !"typeid1"} !1 = !{i32 6, !"typeid1"}
!2 = !{i32 4, !"typeid2"} !2 = !{i32 4, !"typeid2"}
!3 = !{i32 136, !"typeid2"} !3 = !{i32 136, !"typeid2"}
; CHECK: [[G:@[0-9]+]] = private constant { [2048 x i8] } zeroinitializer ; CHECK: [[G:@[0-9]+]] = private constant { [2048 x i8] } zeroinitializer
; CHECK: @__typeid_typeid1_global_addr = hidden alias i8, getelementptr inbounds ({ [2048 x i8] }, { [2048 x i8] }* [[G]], i32 0, i32 0, i32 0) ; CHECK: @__typeid_typeid1_global_addr = hidden alias i8, ptr [[G]]
; CHECK-X86: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 1 to i8*) ; CHECK-X86: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 1 to ptr)
; CHECK-X86: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 3 to i8*) ; CHECK-X86: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 3 to ptr)
; CHECK-X86: @__typeid_typeid1_inline_bits = hidden alias i8, inttoptr (i32 9 to i8*) ; CHECK-X86: @__typeid_typeid1_inline_bits = hidden alias i8, inttoptr (i32 9 to ptr)
; CHECK: @__typeid_typeid2_global_addr = hidden alias i8, getelementptr inbounds ({ [2048 x i8] }, { [2048 x i8] }* [[G]], i32 0, i32 0, i64 4) ; CHECK: @__typeid_typeid2_global_addr = hidden alias i8, getelementptr (i8, ptr [[G]], i64 4)
; CHECK-X86: @__typeid_typeid2_align = hidden alias i8, inttoptr (i8 2 to i8*) ; CHECK-X86: @__typeid_typeid2_align = hidden alias i8, inttoptr (i8 2 to ptr)
; CHECK-X86: @__typeid_typeid2_size_m1 = hidden alias i8, inttoptr (i64 33 to i8*) ; CHECK-X86: @__typeid_typeid2_size_m1 = hidden alias i8, inttoptr (i64 33 to ptr)
; CHECK-X86: @__typeid_typeid2_inline_bits = hidden alias i8, inttoptr (i64 8589934593 to i8*) ; CHECK-X86: @__typeid_typeid2_inline_bits = hidden alias i8, inttoptr (i64 8589934593 to ptr)
; CHECK: @foo = alias [2048 x i8], getelementptr inbounds ({ [2048 x i8] }, { [2048 x i8] }* [[G]], i32 0, i32 0) ; CHECK: @foo = alias [2048 x i8], ptr [[G]]
; SUMMARY: TypeIdMap: ; SUMMARY: TypeIdMap:
; SUMMARY-NEXT: typeid1: ; SUMMARY-NEXT: typeid1:
; SUMMARY-NEXT: TTRes: ; SUMMARY-NEXT: TTRes:
; SUMMARY-NEXT: Kind: Inline ; SUMMARY-NEXT: Kind: Inline
; SUMMARY-NEXT: SizeM1BitWidth: 5 ; SUMMARY-NEXT: SizeM1BitWidth: 5
; SUMMARY-X86-NEXT: AlignLog2: 0 ; SUMMARY-X86-NEXT: AlignLog2: 0
; SUMMARY-X86-NEXT: SizeM1: 0 ; SUMMARY-X86-NEXT: SizeM1: 0
Show All 20 Lines

llvm/test/Transforms/LowerTypeTests/export-single.ll

; RUN: opt -S -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/use-typeid1-typeid2.yaml -lowertypetests-write-summary=%t < %s | FileCheck %s ; RUN: opt -S -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/use-typeid1-typeid2.yaml -lowertypetests-write-summary=%t < %s | FileCheck %s
; RUN: FileCheck --check-prefix=SUMMARY %s < %t ; RUN: FileCheck --check-prefix=SUMMARY %s < %t
@foo = constant i32 42, !type !0 @foo = constant i32 42, !type !0
!0 = !{i32 0, !"typeid1"} !0 = !{i32 0, !"typeid1"}
; CHECK: [[G:@[0-9]+]] = private constant { i32 } { i32 42 } ; CHECK: [[G:@[0-9]+]] = private constant { i32 } { i32 42 }
; CHECK: @__typeid_typeid1_global_addr = hidden alias i8, bitcast ({ i32 }* [[G]] to i8*) ; CHECK: @__typeid_typeid1_global_addr = hidden alias i8, ptr [[G]]
; CHECK: @foo = alias i32, getelementptr inbounds ({ i32 }, { i32 }* [[G]], i32 0, i32 0) ; CHECK: @foo = alias i32, ptr [[G]]
; SUMMARY: TypeIdMap: ; SUMMARY: TypeIdMap:
; SUMMARY-NEXT: typeid1: ; SUMMARY-NEXT: typeid1:
; SUMMARY-NEXT: TTRes: ; SUMMARY-NEXT: TTRes:
; SUMMARY-NEXT: Kind: Single ; SUMMARY-NEXT: Kind: Single
; SUMMARY-NEXT: SizeM1BitWidth: 0 ; SUMMARY-NEXT: SizeM1BitWidth: 0

llvm/test/Transforms/LowerTypeTests/pr37625.ll

; RUN: opt -S -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/exported-funcs.yaml -lowertypetests-write-summary=%t < %s | FileCheck %s ; RUN: opt -S -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/exported-funcs.yaml -lowertypetests-write-summary=%t < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
declare !type !2 extern_weak void @external_addrtaken(i8) declare !type !2 extern_weak void @external_addrtaken(i8)
!cfi.functions = !{!0, !1} !cfi.functions = !{!0, !1}
!0 = !{!"external_addrtaken", i8 2, !2} !0 = !{!"external_addrtaken", i8 2, !2}
!1 = !{!"external_addrtaken", i8 0, !2} !1 = !{!"external_addrtaken", i8 0, !2}
!2 = !{i64 0, !"typeid1"} !2 = !{i64 0, !"typeid1"}
; CHECK-DAG: @external_addrtaken = alias void (i8), bitcast ; CHECK-DAG: @external_addrtaken = alias void (i8), ptr @.cfi.jumptable

llvm/test/Transforms/NewGVN/phi-of-ops-simplified-to-existing-value-then-changes-again.ll

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
; CHECK: bb11: ; CHECK: bb11:
; CHECK-NEXT: [[TMP12]] = add nsw i64 [[TMP9]], 1 ; CHECK-NEXT: [[TMP12]] = add nsw i64 [[TMP9]], 1
; CHECK-NEXT: br label [[BB8]] ; CHECK-NEXT: br label [[BB8]]
; CHECK: bb13: ; CHECK: bb13:
; CHECK-NEXT: br i1 true, label [[BB14:%.*]], label [[BB15:%.*]] ; CHECK-NEXT: br i1 true, label [[BB14:%.*]], label [[BB15:%.*]]
; CHECK: bb14: ; CHECK: bb14:
; CHECK-NEXT: br label [[BB16]] ; CHECK-NEXT: br label [[BB16]]
; CHECK: bb15: ; CHECK: bb15:
; CHECK-NEXT: store i8 poison, i8* null, align 1 ; CHECK-NEXT: store i8 poison, ptr null, align 1
; CHECK-NEXT: br label [[BB16]] ; CHECK-NEXT: br label [[BB16]]
; CHECK: bb16: ; CHECK: bb16:
; CHECK-NEXT: [[TMP17:%.*]] = phi i32 [ poison, [[BB15]] ], [ 1, [[BB14]] ], [ 9, [[BB7]] ] ; CHECK-NEXT: [[TMP17:%.*]] = phi i32 [ poison, [[BB15]] ], [ 1, [[BB14]] ], [ 9, [[BB7]] ]
; CHECK-NEXT: switch i32 [[TMP17]], label [[BB19]] [ ; CHECK-NEXT: switch i32 [[TMP17]], label [[BB19]] [
; CHECK-NEXT: i32 0, label [[BB6]] ; CHECK-NEXT: i32 0, label [[BB6]]
; CHECK-NEXT: i32 9, label [[BB18:%.*]] ; CHECK-NEXT: i32 9, label [[BB18:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: bb18: ; CHECK: bb18:
▲ Show 20 Lines • Show All 145 Lines • Show Last 20 Lines

llvm/test/Transforms/NewGVN/pr42422-phi-of-ops.ll

Show All 29 Lines
; CHECK: for.inc: ; CHECK: for.inc:
; CHECK-NEXT: [[INC]] = add nsw i64 [[TMP1]], 1 ; CHECK-NEXT: [[INC]] = add nsw i64 [[TMP1]], 1
; CHECK-NEXT: br label [[FOR_COND6]] ; CHECK-NEXT: br label [[FOR_COND6]]
; CHECK: for.end9: ; CHECK: for.end9:
; CHECK-NEXT: br i1 true, label [[IF_THEN11:%.*]], label [[IF_END12:%.*]] ; CHECK-NEXT: br i1 true, label [[IF_THEN11:%.*]], label [[IF_END12:%.*]]
; CHECK: if.then11: ; CHECK: if.then11:
; CHECK-NEXT: br label [[CLEANUP]] ; CHECK-NEXT: br label [[CLEANUP]]
; CHECK: if.end12: ; CHECK: if.end12:
; CHECK-NEXT: store i8 poison, i8* null, align 1 ; CHECK-NEXT: store i8 poison, ptr null, align 1
; CHECK-NEXT: br label [[CLEANUP]] ; CHECK-NEXT: br label [[CLEANUP]]
; CHECK: cleanup: ; CHECK: cleanup:
; CHECK-NEXT: [[CLEANUP_DEST:%.*]] = phi i32 [ poison, [[IF_END12]] ], [ 1, [[IF_THEN11]] ], [ 9, [[IF_THEN]] ] ; CHECK-NEXT: [[CLEANUP_DEST:%.*]] = phi i32 [ poison, [[IF_END12]] ], [ 1, [[IF_THEN11]] ], [ 9, [[IF_THEN]] ]
; CHECK-NEXT: switch i32 [[CLEANUP_DEST]], label [[CLEANUP14]] [ ; CHECK-NEXT: switch i32 [[CLEANUP_DEST]], label [[CLEANUP14]] [
; CHECK-NEXT: i32 0, label [[FOR_COND4]] ; CHECK-NEXT: i32 0, label [[FOR_COND4]]
; CHECK-NEXT: i32 9, label [[FOR_END13:%.*]] ; CHECK-NEXT: i32 9, label [[FOR_END13:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: for.end13: ; CHECK: for.end13:
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

llvm/test/Transforms/PGOProfile/branch1.ll

Show All 17 Lines
; GEN-LINKONCE: @__llvm_profile_raw_version = linkonce constant i64 {{[0-9]+}} ; GEN-LINKONCE: @__llvm_profile_raw_version = linkonce constant i64 {{[0-9]+}}
; GEN: @__profn_test_br_1 = private constant [9 x i8] c"test_br_1" ; GEN: @__profn_test_br_1 = private constant [9 x i8] c"test_br_1"
define i32 @test_br_1(i32 %i) { define i32 @test_br_1(i32 %i) {
; USE-LABEL: @test_br_1 ; USE-LABEL: @test_br_1
; USE-SAME: !prof ![[FUNC_ENTRY_COUNT:[0-9]+]] ; USE-SAME: !prof ![[FUNC_ENTRY_COUNT:[0-9]+]]
entry: entry:
; GEN: entry: ; GEN: entry:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @__profn_test_br_1, i32 0, i32 0), i64 {{[0-9]+}}, i32 2, i32 0) ; GEN: call void @llvm.instrprof.increment(ptr @__profn_test_br_1, i64 {{[0-9]+}}, i32 2, i32 0)
%cmp = icmp sgt i32 %i, 0 %cmp = icmp sgt i32 %i, 0
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
; USE: br i1 %cmp, label %if.then, label %if.end ; USE: br i1 %cmp, label %if.then, label %if.end
; USE-SAME: !prof ![[BW_ENTRY:[0-9]+]] ; USE-SAME: !prof ![[BW_ENTRY:[0-9]+]]
; USE-DAG: ![[BW_ENTRY]] = !{!"branch_weights", i32 2, i32 1} ; USE-DAG: ![[BW_ENTRY]] = !{!"branch_weights", i32 2, i32 1}
; USE-LARGE: br i1 %cmp, label %if.then, label %if.end ; USE-LARGE: br i1 %cmp, label %if.then, label %if.end
; USE-LARGE-SAME: !prof ![[BW_L_ENTRY:[0-9]+]] ; USE-LARGE-SAME: !prof ![[BW_L_ENTRY:[0-9]+]]
; USE-LARGE-DAG: ![[BW_L_ENTRY]] = !{!"branch_weights", i32 -1431655766, i32 1431655765} ; USE-LARGE-DAG: ![[BW_L_ENTRY]] = !{!"branch_weights", i32 -1431655766, i32 1431655765}
if.then: if.then:
; GEN: if.then: ; GEN: if.then:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @__profn_test_br_1, i32 0, i32 0), i64 {{[0-9]+}}, i32 2, i32 1) ; GEN: call void @llvm.instrprof.increment(ptr @__profn_test_br_1, i64 {{[0-9]+}}, i32 2, i32 1)
%add = add nsw i32 %i, 2 %add = add nsw i32 %i, 2
br label %if.end br label %if.end
if.end: if.end:
; GEN: if.end: ; GEN: if.end:
; GEN-NOT: llvm.instrprof.increment ; GEN-NOT: llvm.instrprof.increment
; GEN: ret i32 ; GEN: ret i32
%retv = phi i32 [ %add, %if.then ], [ %i, %entry ] %retv = phi i32 [ %add, %if.then ], [ %i, %entry ]
ret i32 %retv ret i32 %retv
} }
; USE-DAG: {{![0-9]+}} = !{i32 1, !"ProfileSummary", {{![0-9]+}}} ; USE-DAG: {{![0-9]+}} = !{i32 1, !"ProfileSummary", {{![0-9]+}}}
; USE-DAG: {{![0-9]+}} = !{!"DetailedSummary", {{![0-9]+}}} ; USE-DAG: {{![0-9]+}} = !{!"DetailedSummary", {{![0-9]+}}}
; USE-DAG: ![[FUNC_ENTRY_COUNT]] = !{!"function_entry_count", i64 3} ; USE-DAG: ![[FUNC_ENTRY_COUNT]] = !{!"function_entry_count", i64 3}
; ANALYSIS:remark: <unknown>:0:0: sgt_i32_Zero {{.*}}66.67% (total count : 3) ; ANALYSIS:remark: <unknown>:0:0: sgt_i32_Zero {{.*}}66.67% (total count : 3)

llvm/test/Transforms/PGOProfile/branch2.ll

Show All 10 Lines
; GEN: $__llvm_profile_raw_version = comdat any ; GEN: $__llvm_profile_raw_version = comdat any
; GEN: @__llvm_profile_raw_version = constant i64 {{[0-9]+}}, comdat ; GEN: @__llvm_profile_raw_version = constant i64 {{[0-9]+}}, comdat
; GEN: @__profn_test_br_2 = private constant [9 x i8] c"test_br_2" ; GEN: @__profn_test_br_2 = private constant [9 x i8] c"test_br_2"
define i32 @test_br_2(i32 %i) { define i32 @test_br_2(i32 %i) {
entry: entry:
; GEN: entry: ; GEN: entry:
; NOTENTRY-NOT: llvm.instrprof.increment ; NOTENTRY-NOT: llvm.instrprof.increment
; ENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @__profn_test_br_2, i32 0, i32 0), i64 {{[0-9]+}}, i32 2, i32 0) ; ENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_br_2, i64 {{[0-9]+}}, i32 2, i32 0)
%cmp = icmp sgt i32 %i, 0 %cmp = icmp sgt i32 %i, 0
br i1 %cmp, label %if.then, label %if.else br i1 %cmp, label %if.then, label %if.else
; USE: br i1 %cmp, label %if.then, label %if.else ; USE: br i1 %cmp, label %if.then, label %if.else
; USE-SAME: !prof ![[BW_ENTRY:[0-9]+]] ; USE-SAME: !prof ![[BW_ENTRY:[0-9]+]]
; USE: ![[BW_ENTRY]] = !{!"branch_weights", i32 1, i32 1} ; USE: ![[BW_ENTRY]] = !{!"branch_weights", i32 1, i32 1}
if.then: if.then:
; GEN: if.then: ; GEN: if.then:
; NOTENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @__profn_test_br_2, i32 0, i32 0), i64 {{[0-9]+}}, i32 2, i32 0) ; NOTENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_br_2, i64 {{[0-9]+}}, i32 2, i32 0)
; ENTRY-NOT: llvm.instrprof.increment ; ENTRY-NOT: llvm.instrprof.increment
%add = add nsw i32 %i, 2 %add = add nsw i32 %i, 2
br label %if.end br label %if.end
if.else: if.else:
; GEN: if.else: ; GEN: if.else:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @__profn_test_br_2, i32 0, i32 0), i64 {{[0-9]+}}, i32 2, i32 1) ; GEN: call void @llvm.instrprof.increment(ptr @__profn_test_br_2, i64 {{[0-9]+}}, i32 2, i32 1)
%sub = sub nsw i32 %i, 2 %sub = sub nsw i32 %i, 2
br label %if.end br label %if.end
if.end: if.end:
; GEN: if.end: ; GEN: if.end:
; GEN-NOT: llvm.instrprof.increment ; GEN-NOT: llvm.instrprof.increment
%retv = phi i32 [ %add, %if.then ], [ %sub, %if.else ] %retv = phi i32 [ %add, %if.then ], [ %sub, %if.else ]
ret i32 %retv ret i32 %retv
; GEN: ret ; GEN: ret
} }

llvm/test/Transforms/PGOProfile/counter_promo.ll

Show All 40 Lines
; PROMO-NEXT: %[[LIVEOUT2:[a-z0-9]+]] = phi {{.*}} ; PROMO-NEXT: %[[LIVEOUT2:[a-z0-9]+]] = phi {{.*}}
; PROMO-NEXT: %[[LIVEOUT1:[a-z0-9]+]] = phi {{.*}} ; PROMO-NEXT: %[[LIVEOUT1:[a-z0-9]+]] = phi {{.*}}
%tmp10 = add nsw i32 %i.0, 1 %tmp10 = add nsw i32 %i.0, 1
%tmp11 = icmp slt i32 %tmp10, %N %tmp11 = icmp slt i32 %tmp10, %N
br i1 %tmp11, label %bb2, label %bb12 br i1 %tmp11, label %bb2, label %bb12
bb12: ; preds = %bb9 bb12: ; preds = %bb9
ret void ret void
; NONATOMIC_PROMO: %[[PROMO1:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}} 0) ; NONATOMIC_PROMO: %[[PROMO1:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}}
; NONATOMIC_PROMO-NEXT: add {{.*}} %[[PROMO1]], %[[LIVEOUT1]] ; NONATOMIC_PROMO-NEXT: add {{.*}} %[[PROMO1]], %[[LIVEOUT1]]
; NONATOMIC_PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}0) ; NONATOMIC_PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}
; NONATOMIC_PROMO-NEXT: %[[PROMO2:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}} 1) ; NONATOMIC_PROMO-NEXT: %[[PROMO2:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}} 1)
; NONATOMIC_PROMO-NEXT: add {{.*}} %[[PROMO2]], %[[LIVEOUT2]] ; NONATOMIC_PROMO-NEXT: add {{.*}} %[[PROMO2]], %[[LIVEOUT2]]
; NONATOMIC_PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}1) ; NONATOMIC_PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}1)
; NONATOMIC_PROMO-NEXT: %[[PROMO3:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}} 2) ; NONATOMIC_PROMO-NEXT: %[[PROMO3:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}} 2)
; NONATOMIC_PROMO-NEXT: add {{.*}} %[[PROMO3]], %[[LIVEOUT3]] ; NONATOMIC_PROMO-NEXT: add {{.*}} %[[PROMO3]], %[[LIVEOUT3]]
; NONATOMIC_PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}2) ; NONATOMIC_PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}2)
; ATOMIC_PROMO: atomicrmw add {{.*}} @__profc_foo{{.*}}0), i64 %[[LIVEOUT1]] seq_cst ; ATOMIC_PROMO: atomicrmw add {{.*}} @__profc_foo{{.*}}, i64 %[[LIVEOUT1]] seq_cst
; ATOMIC_PROMO-NEXT: atomicrmw add {{.*}} @__profc_foo{{.*}}1), i64 %[[LIVEOUT2]] seq_cst ; ATOMIC_PROMO-NEXT: atomicrmw add {{.*}} @__profc_foo{{.*}}1), i64 %[[LIVEOUT2]] seq_cst
; ATOMIC_PROMO-NEXT: atomicrmw add {{.*}} @__profc_foo{{.*}}2), i64 %[[LIVEOUT3]] seq_cst ; ATOMIC_PROMO-NEXT: atomicrmw add {{.*}} @__profc_foo{{.*}}2), i64 %[[LIVEOUT3]] seq_cst
; PROMO-NOT: @__profc_foo{{.*}}) ; PROMO-NOT: @__profc_foo{{.*}})
} }
declare void @bar(i32) declare void @bar(i32)

llvm/test/Transforms/PGOProfile/criticaledge.ll

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; GEN: @__llvm_profile_raw_version = constant i64 {{[0-9]+}}, comdat ; GEN: @__llvm_profile_raw_version = constant i64 {{[0-9]+}}, comdat
; GEN: @__profn_test_criticalEdge = private constant [17 x i8] c"test_criticalEdge" ; GEN: @__profn_test_criticalEdge = private constant [17 x i8] c"test_criticalEdge"
; GEN: @__profn__stdin__bar = private constant [11 x i8] c"<stdin>:bar" ; GEN: @__profn__stdin__bar = private constant [11 x i8] c"<stdin>:bar"
define i32 @test_criticalEdge(i32 %i, i32 %j) { define i32 @test_criticalEdge(i32 %i, i32 %j) {
entry: entry:
; CHECK: entry: ; CHECK: entry:
; NOTENTRY-NOT: call void @llvm.instrprof.increment ; NOTENTRY-NOT: call void @llvm.instrprof.increment
; ENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @__profn_test_criticalEdge, i32 0, i32 0), i64 {{[0-9]+}}, i32 8, i32 0) ; ENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_criticalEdge, i64 {{[0-9]+}}, i32 8, i32 0)
switch i32 %i, label %sw.default [ switch i32 %i, label %sw.default [
i32 1, label %sw.bb i32 1, label %sw.bb
i32 2, label %sw.bb1 i32 2, label %sw.bb1
i32 3, label %sw.bb2 i32 3, label %sw.bb2
i32 4, label %sw.bb2 i32 4, label %sw.bb2
; CHECK: i32 3, label %entry.sw.bb2_crit_edge ; CHECK: i32 3, label %entry.sw.bb2_crit_edge
; CHECK: i32 4, label %entry.sw.bb2_crit_edge1 ; CHECK: i32 4, label %entry.sw.bb2_crit_edge1
i32 5, label %sw.bb2 i32 5, label %sw.bb2
] ]
; USE: ] ; USE: ]
; USE-SAME: !prof ![[BW_SWITCH:[0-9]+]] ; USE-SAME: !prof ![[BW_SWITCH:[0-9]+]]
; CHECK: entry.sw.bb2_crit_edge1: ; CHECK: entry.sw.bb2_crit_edge1:
; NOTENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @__profn_test_criticalEdge, i32 0, i32 0), i64 {{[0-9]+}}, i32 8, i32 1) ; NOTENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_criticalEdge, i64 {{[0-9]+}}, i32 8, i32 1)
; ENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @__profn_test_criticalEdge, i32 0, i32 0), i64 {{[0-9]+}}, i32 8, i32 2) ; ENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_criticalEdge, i64 {{[0-9]+}}, i32 8, i32 2)
; CHECK: br label %sw.bb2 ; CHECK: br label %sw.bb2
; CHECK: entry.sw.bb2_crit_edge: ; CHECK: entry.sw.bb2_crit_edge:
; NOTENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @__profn_test_criticalEdge, i32 0, i32 0), i64 {{[0-9]+}}, i32 8, i32 0) ; NOTENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_criticalEdge, i64 {{[0-9]+}}, i32 8, i32 0)
; TENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @__profn_test_criticalEdge, i32 0, i32 0), i64 {{[0-9]+}}, i32 8, i32 1) ; TENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_criticalEdge, i64 {{[0-9]+}}, i32 8, i32 1)
; CHECK: br label %sw.bb2 ; CHECK: br label %sw.bb2
sw.bb: sw.bb:
; GEN: sw.bb: ; GEN: sw.bb:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @__profn_test_criticalEdge, i32 0, i32 0), i64 {{[0-9]+}}, i32 8, i32 5) ; GEN: call void @llvm.instrprof.increment(ptr @__profn_test_criticalEdge, i64 {{[0-9]+}}, i32 8, i32 5)
%call = call i32 @bar(i32 2) %call = call i32 @bar(i32 2)
br label %sw.epilog br label %sw.epilog
sw.bb1: sw.bb1:
; GEN: sw.bb1: ; GEN: sw.bb1:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @__profn_test_criticalEdge, i32 0, i32 0), i64 {{[0-9]+}}, i32 8, i32 4) ; GEN: call void @llvm.instrprof.increment(ptr @__profn_test_criticalEdge, i64 {{[0-9]+}}, i32 8, i32 4)
%call2 = call i32 @bar(i32 1024) %call2 = call i32 @bar(i32 1024)
br label %sw.epilog br label %sw.epilog
sw.bb2: sw.bb2:
; GEN: sw.bb2: ; GEN: sw.bb2:
; GEN-NOT: call void @llvm.instrprof.increment ; GEN-NOT: call void @llvm.instrprof.increment
%cmp = icmp eq i32 %j, 2 %cmp = icmp eq i32 %j, 2
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
; USE: br i1 %cmp, label %if.then, label %if.end ; USE: br i1 %cmp, label %if.then, label %if.end
; USE-SAME: !prof ![[BW_SW_BB2:[0-9]+]] ; USE-SAME: !prof ![[BW_SW_BB2:[0-9]+]]
if.then: if.then:
; GEN: if.then: ; GEN: if.then:
; NOTENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @__profn_test_criticalEdge, i32 0, i32 0), i64 {{[0-9]+}}, i32 8, i32 2) ; NOTENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_criticalEdge, i64 {{[0-9]+}}, i32 8, i32 2)
; ENTRY-NOT: call void @llvm.instrprof.increment ; ENTRY-NOT: call void @llvm.instrprof.increment
%call4 = call i32 @bar(i32 4) %call4 = call i32 @bar(i32 4)
br label %return br label %return
if.end: if.end:
; GEN: if.end: ; GEN: if.end:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @__profn_test_criticalEdge, i32 0, i32 0), i64 {{[0-9]+}}, i32 8, i32 3) ; GEN: call void @llvm.instrprof.increment(ptr @__profn_test_criticalEdge, i64 {{[0-9]+}}, i32 8, i32 3)
%call5 = call i32 @bar(i32 8) %call5 = call i32 @bar(i32 8)
br label %sw.epilog br label %sw.epilog
sw.default: sw.default:
; GEN: sw.default: ; GEN: sw.default:
; GEN-NOT: call void @llvm.instrprof.increment ; GEN-NOT: call void @llvm.instrprof.increment
%call6 = call i32 @bar(i32 32) %call6 = call i32 @bar(i32 32)
%cmp7 = icmp sgt i32 %j, 10 %cmp7 = icmp sgt i32 %j, 10
br i1 %cmp7, label %if.then8, label %if.end9 br i1 %cmp7, label %if.then8, label %if.end9
; USE: br i1 %cmp7, label %if.then8, label %if.end9 ; USE: br i1 %cmp7, label %if.then8, label %if.end9
; USE-SAME: !prof ![[BW_SW_DEFAULT:[0-9]+]] ; USE-SAME: !prof ![[BW_SW_DEFAULT:[0-9]+]]
if.then8: if.then8:
; GEN: if.then8: ; GEN: if.then8:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @__profn_test_criticalEdge, i32 0, i32 0), i64 {{[0-9]+}}, i32 8, i32 7) ; GEN: call void @llvm.instrprof.increment(ptr @__profn_test_criticalEdge, i64 {{[0-9]+}}, i32 8, i32 7)
%add = add nsw i32 %call6, 10 %add = add nsw i32 %call6, 10
br label %if.end9 br label %if.end9
if.end9: if.end9:
; GEN: if.end9: ; GEN: if.end9:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @__profn_test_criticalEdge, i32 0, i32 0), i64 {{[0-9]+}}, i32 8, i32 6) ; GEN: call void @llvm.instrprof.increment(ptr @__profn_test_criticalEdge, i64 {{[0-9]+}}, i32 8, i32 6)
%res.0 = phi i32 [ %add, %if.then8 ], [ %call6, %sw.default ] %res.0 = phi i32 [ %add, %if.then8 ], [ %call6, %sw.default ]
br label %sw.epilog br label %sw.epilog
sw.epilog: sw.epilog:
; GEN: sw.epilog: ; GEN: sw.epilog:
; GEN-NOT: call void @llvm.instrprof.increment ; GEN-NOT: call void @llvm.instrprof.increment
%res.1 = phi i32 [ %res.0, %if.end9 ], [ %call5, %if.end ], [ %call2, %sw.bb1 ], [ %call, %sw.bb ] %res.1 = phi i32 [ %res.0, %if.end9 ], [ %call5, %if.end ], [ %call2, %sw.bb1 ], [ %call, %sw.bb ]
br label %return br label %return
return: return:
; GEN: return: ; GEN: return:
; GEN-NOT: call void @llvm.instrprof.increment ; GEN-NOT: call void @llvm.instrprof.increment
%retval = phi i32 [ %res.1, %sw.epilog ], [ %call4, %if.then ] %retval = phi i32 [ %res.1, %sw.epilog ], [ %call4, %if.then ]
ret i32 %retval ret i32 %retval
} }
define internal i32 @bar(i32 %i) { define internal i32 @bar(i32 %i) {
entry: entry:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @__profn__stdin__bar, i32 0, i32 0), i64 {{[0-9]+}}, i32 1, i32 0) ; GEN: call void @llvm.instrprof.increment(ptr @__profn__stdin__bar, i64 {{[0-9]+}}, i32 1, i32 0)
ret i32 %i ret i32 %i
} }
; USE: ![[BW_SWITCH]] = !{!"branch_weights", i32 2, i32 1, i32 0, i32 2, i32 1, i32 1} ; USE: ![[BW_SWITCH]] = !{!"branch_weights", i32 2, i32 1, i32 0, i32 2, i32 1, i32 1}
; USE: ![[BW_SW_BB2]] = !{!"branch_weights", i32 2, i32 2} ; USE: ![[BW_SW_BB2]] = !{!"branch_weights", i32 2, i32 2}
; USE: ![[BW_SW_DEFAULT]] = !{!"branch_weights", i32 1, i32 1} ; USE: ![[BW_SW_DEFAULT]] = !{!"branch_weights", i32 1, i32 1}

llvm/test/Transforms/PGOProfile/instr_entry_bb.ll

; RUN: opt < %s -passes=pgo-instr-gen -pgo-instrument-entry -S | FileCheck %s --check-prefix=GEN ; RUN: opt < %s -passes=pgo-instr-gen -pgo-instrument-entry -S | FileCheck %s --check-prefix=GEN
; RUN: opt < %s -passes=pgo-instr-gen,instrprof -pgo-instrument-entry -atomic-first-counter -S | FileCheck %s --check-prefix=GENA ; RUN: opt < %s -passes=pgo-instr-gen,instrprof -pgo-instrument-entry -atomic-first-counter -S | FileCheck %s --check-prefix=GENA
; RUN: llvm-profdata merge %S/Inputs/branch2.proftext -o %t.profdata ; RUN: llvm-profdata merge %S/Inputs/branch2.proftext -o %t.profdata
; RUN: opt < %s -passes=pgo-instr-use -pgo-test-profile-file=%t.profdata -pgo-instrument-entry -S | FileCheck %s --check-prefix=USE ; RUN: opt < %s -passes=pgo-instr-use -pgo-test-profile-file=%t.profdata -pgo-instrument-entry -S | FileCheck %s --check-prefix=USE
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; GEN: $__llvm_profile_raw_version = comdat any ; GEN: $__llvm_profile_raw_version = comdat any
; GEN: @__llvm_profile_raw_version = constant i64 {{[0-9]+}}, comdat ; GEN: @__llvm_profile_raw_version = constant i64 {{[0-9]+}}, comdat
; GEN: @__profn_test_br_2 = private constant [9 x i8] c"test_br_2" ; GEN: @__profn_test_br_2 = private constant [9 x i8] c"test_br_2"
define i32 @test_br_2(i32 %i) { define i32 @test_br_2(i32 %i) {
entry: entry:
; GEN: entry: ; GEN: entry:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @__profn_test_br_2, i32 0, i32 0), i64 {{[0-9]+}}, i32 2, i32 0) ; GEN: call void @llvm.instrprof.increment(ptr @__profn_test_br_2, i64 {{[0-9]+}}, i32 2, i32 0)
; GENA: entry: ; GENA: entry:
; GENA: %{{[0-9+]}} = atomicrmw add i64* getelementptr inbounds ([2 x i64], [2 x i64]* @__profc_test_br_2, i32 0, i32 0), i64 1 monotonic ; GENA: %{{[0-9+]}} = atomicrmw add ptr @__profc_test_br_2, i64 1 monotonic
; USE: br i1 %cmp, label %if.then, label %if.else ; USE: br i1 %cmp, label %if.then, label %if.else
; USE-SAME: !prof ![[BW_ENTRY:[0-9]+]] ; USE-SAME: !prof ![[BW_ENTRY:[0-9]+]]
; USE: ![[BW_ENTRY]] = !{!"branch_weights", i32 0, i32 1} ; USE: ![[BW_ENTRY]] = !{!"branch_weights", i32 0, i32 1}
%cmp = icmp sgt i32 %i, 0 %cmp = icmp sgt i32 %i, 0
br i1 %cmp, label %if.then, label %if.else br i1 %cmp, label %if.then, label %if.else
if.then: if.then:
; GEN: if.then: ; GEN: if.then:
; GEN-NOT: llvm.instrprof.increment ; GEN-NOT: llvm.instrprof.increment
%add = add nsw i32 %i, 2 %add = add nsw i32 %i, 2
br label %if.end br label %if.end
if.else: if.else:
; GEN: if.else: ; GEN: if.else:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @__profn_test_br_2, i32 0, i32 0), i64 {{[0-9]+}}, i32 2, i32 1) ; GEN: call void @llvm.instrprof.increment(ptr @__profn_test_br_2, i64 {{[0-9]+}}, i32 2, i32 1)
; GENA: if.else: ; GENA: if.else:
; GENA: %pgocount = load i64, i64* getelementptr inbounds ([2 x i64], [2 x i64]* @__profc_test_br_2, i32 0, i32 1), align 8 ; GENA: %pgocount = load i64, ptr getelementptr inbounds ([2 x i64], ptr @__profc_test_br_2, i32 0, i32 1), align 8
; GENA: [[V:%[0-9]*]] = add i64 %pgocount, 1 ; GENA: [[V:%[0-9]*]] = add i64 %pgocount, 1
; GENA: store i64 [[V]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @__profc_test_br_2, i32 0, i32 1), align 8 ; GENA: store i64 [[V]], ptr getelementptr inbounds ([2 x i64], ptr @__profc_test_br_2, i32 0, i32 1), align 8
%sub = sub nsw i32 %i, 2 %sub = sub nsw i32 %i, 2
br label %if.end br label %if.end
if.end: if.end:
; GEN: if.end: ; GEN: if.end:
; GEN-NOT: llvm.instrprof.increment ; GEN-NOT: llvm.instrprof.increment
%retv = phi i32 [ %add, %if.then ], [ %sub, %if.else ] %retv = phi i32 [ %add, %if.then ], [ %sub, %if.else ]
ret i32 %retv ret i32 %retv
; GEN: ret ; GEN: ret
} }

llvm/test/Transforms/PGOProfile/loop1.ll

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; GEN: $__llvm_profile_raw_version = comdat any ; GEN: $__llvm_profile_raw_version = comdat any
; GEN: @__llvm_profile_raw_version = constant i64 {{[0-9]+}}, comdat ; GEN: @__llvm_profile_raw_version = constant i64 {{[0-9]+}}, comdat
; GEN: @__profn_test_simple_for = private constant [15 x i8] c"test_simple_for" ; GEN: @__profn_test_simple_for = private constant [15 x i8] c"test_simple_for"
define i32 @test_simple_for(i32 %n) { define i32 @test_simple_for(i32 %n) {
entry: entry:
; GEN: entry: ; GEN: entry:
; NOTENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @__profn_test_simple_for, i32 0, i32 0), i64 {{[0-9]+}}, i32 2, i32 1) ; NOTENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_simple_for, i64 {{[0-9]+}}, i32 2, i32 1)
; ENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @__profn_test_simple_for, i32 0, i32 0), i64 {{[0-9]+}}, i32 2, i32 0) ; ENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_simple_for, i64 {{[0-9]+}}, i32 2, i32 0)
br label %for.cond br label %for.cond
for.cond: for.cond:
; GEN: for.cond: ; GEN: for.cond:
; GEN-NOT: call void @llvm.instrprof.increment ; GEN-NOT: call void @llvm.instrprof.increment
%i = phi i32 [ 0, %entry ], [ %inc1, %for.inc ] %i = phi i32 [ 0, %entry ], [ %inc1, %for.inc ]
%sum = phi i32 [ 1, %entry ], [ %inc, %for.inc ] %sum = phi i32 [ 1, %entry ], [ %inc, %for.inc ]
%cmp = icmp slt i32 %i, %n %cmp = icmp slt i32 %i, %n
br i1 %cmp, label %for.body, label %for.end br i1 %cmp, label %for.body, label %for.end
; USE: br i1 %cmp, label %for.body, label %for.end ; USE: br i1 %cmp, label %for.body, label %for.end
; USE-SAME: !prof ![[BW_FOR_COND:[0-9]+]] ; USE-SAME: !prof ![[BW_FOR_COND:[0-9]+]]
; USE: ![[BW_FOR_COND]] = !{!"branch_weights", i32 96, i32 4} ; USE: ![[BW_FOR_COND]] = !{!"branch_weights", i32 96, i32 4}
for.body: for.body:
; GEN: for.body: ; GEN: for.body:
; GEN-NOT: call void @llvm.instrprof.increment ; GEN-NOT: call void @llvm.instrprof.increment
%inc = add nsw i32 %sum, 1 %inc = add nsw i32 %sum, 1
br label %for.inc br label %for.inc
for.inc: for.inc:
; GEN: for.inc: ; GEN: for.inc:
; NOTENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @__profn_test_simple_for, i32 0, i32 0), i64 {{[0-9]+}}, i32 2, i32 0) ; NOTENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_simple_for, i64 {{[0-9]+}}, i32 2, i32 0)
; ENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @__profn_test_simple_for, i32 0, i32 0), i64 {{[0-9]+}}, i32 2, i32 1) ; ENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_simple_for, i64 {{[0-9]+}}, i32 2, i32 1)
%inc1 = add nsw i32 %i, 1 %inc1 = add nsw i32 %i, 1
br label %for.cond br label %for.cond
for.end: for.end:
; GEN: for.end: ; GEN: for.end:
; GEN-NOT: call void @llvm.instrprof.increment ; GEN-NOT: call void @llvm.instrprof.increment
; GEN: ret i32 ; GEN: ret i32
ret i32 %sum ret i32 %sum
} }

llvm/test/Transforms/PGOProfile/loop2.ll

; RUN: opt < %s -passes=pgo-instr-gen -pgo-instrument-entry=false -S | FileCheck %s --check-prefixes=GEN,NOTENTRY ; RUN: opt < %s -passes=pgo-instr-gen -pgo-instrument-entry=false -S | FileCheck %s --check-prefixes=GEN,NOTENTRY
; RUN: llvm-profdata merge %S/Inputs/loop2.proftext -o %t.profdata ; RUN: llvm-profdata merge %S/Inputs/loop2.proftext -o %t.profdata
; RUN: opt < %s -passes=pgo-instr-use -pgo-instrument-entry=false -pgo-test-profile-file=%t.profdata -S | FileCheck %s --check-prefix=USE ; RUN: opt < %s -passes=pgo-instr-use -pgo-instrument-entry=false -pgo-test-profile-file=%t.profdata -S | FileCheck %s --check-prefix=USE
; RUN: opt < %s -passes=pgo-instr-gen -pgo-instrument-entry=true -S | FileCheck %s --check-prefixes=GEN,ENTRY ; RUN: opt < %s -passes=pgo-instr-gen -pgo-instrument-entry=true -S | FileCheck %s --check-prefixes=GEN,ENTRY
; RUN: llvm-profdata merge %S/Inputs/loop2_entry.proftext -o %t.profdata ; RUN: llvm-profdata merge %S/Inputs/loop2_entry.proftext -o %t.profdata
; RUN: opt < %s -passes=pgo-instr-use -pgo-instrument-entry=true -pgo-test-profile-file=%t.profdata -S | FileCheck %s --check-prefix=USE ; RUN: opt < %s -passes=pgo-instr-use -pgo-instrument-entry=true -pgo-test-profile-file=%t.profdata -S | FileCheck %s --check-prefix=USE
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; GEN: $__llvm_profile_raw_version = comdat any ; GEN: $__llvm_profile_raw_version = comdat any
; GEN: @__llvm_profile_raw_version = constant i64 {{[0-9]+}}, comdat ; GEN: @__llvm_profile_raw_version = constant i64 {{[0-9]+}}, comdat
; GEN: @__profn_test_nested_for = private constant [15 x i8] c"test_nested_for" ; GEN: @__profn_test_nested_for = private constant [15 x i8] c"test_nested_for"
define i32 @test_nested_for(i32 %r, i32 %s) { define i32 @test_nested_for(i32 %r, i32 %s) {
entry: entry:
; GEN: entry: ; GEN: entry:
; NOTENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @__profn_test_nested_for, i32 0, i32 0), i64 {{[0-9]+}}, i32 3, i32 2) ; NOTENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_nested_for, i64 {{[0-9]+}}, i32 3, i32 2)
; ENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @__profn_test_nested_for, i32 0, i32 0), i64 {{[0-9]+}}, i32 3, i32 0) ; ENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_nested_for, i64 {{[0-9]+}}, i32 3, i32 0)
br label %for.cond.outer br label %for.cond.outer
for.cond.outer: for.cond.outer:
; GEN: for.cond.outer: ; GEN: for.cond.outer:
; GEN-NOT: call void @llvm.instrprof.increment ; GEN-NOT: call void @llvm.instrprof.increment
%i.0 = phi i32 [ 0, %entry ], [ %inc.2, %for.inc.outer ] %i.0 = phi i32 [ 0, %entry ], [ %inc.2, %for.inc.outer ]
%sum.0 = phi i32 [ 1, %entry ], [ %sum.1, %for.inc.outer ] %sum.0 = phi i32 [ 1, %entry ], [ %sum.1, %for.inc.outer ]
%cmp = icmp slt i32 %i.0, %r %cmp = icmp slt i32 %i.0, %r
Show All 19 Lines
for.body.inner: for.body.inner:
; GEN: for.body.inner: ; GEN: for.body.inner:
; GEN-NOT: call void @llvm.instrprof.increment ; GEN-NOT: call void @llvm.instrprof.increment
%inc = add nsw i32 %sum.1, 1 %inc = add nsw i32 %sum.1, 1
br label %for.inc.inner br label %for.inc.inner
for.inc.inner: for.inc.inner:
; GEN: for.inc.inner: ; GEN: for.inc.inner:
; NOTENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @__profn_test_nested_for, i32 0, i32 0), i64 {{[0-9]+}}, i32 3, i32 0) ; NOTENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_nested_for, i64 {{[0-9]+}}, i32 3, i32 0)
; ENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @__profn_test_nested_for, i32 0, i32 0), i64 {{[0-9]+}}, i32 3, i32 1) ; ENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_nested_for, i64 {{[0-9]+}}, i32 3, i32 1)
%inc.1 = add nsw i32 %j.0, 1 %inc.1 = add nsw i32 %j.0, 1
br label %for.cond.inner br label %for.cond.inner
for.end.inner: for.end.inner:
; GEN: for.end.inner: ; GEN: for.end.inner:
br label %for.inc.outer br label %for.inc.outer
for.inc.outer: for.inc.outer:
; GEN: for.inc.outer: ; GEN: for.inc.outer:
; NOTENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @__profn_test_nested_for, i32 0, i32 0), i64 {{[0-9]+}}, i32 3, i32 1) ; NOTENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_nested_for, i64 {{[0-9]+}}, i32 3, i32 1)
; ENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @__profn_test_nested_for, i32 0, i32 0), i64 {{[0-9]+}}, i32 3, i32 2) ; ENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_nested_for, i64 {{[0-9]+}}, i32 3, i32 2)
%inc.2 = add nsw i32 %i.0, 1 %inc.2 = add nsw i32 %i.0, 1
br label %for.cond.outer br label %for.cond.outer
for.end.outer: for.end.outer:
; GEN: for.end.outer: ; GEN: for.end.outer:
; GEN-NOT: call void @llvm.instrprof.increment ; GEN-NOT: call void @llvm.instrprof.increment
; GEN: ret i32 ; GEN: ret i32
ret i32 %sum.0 ret i32 %sum.0
} }
; USE-DAG: ![[BW_FOR_COND_OUTER]] = !{!"branch_weights", i32 10, i32 6} ; USE-DAG: ![[BW_FOR_COND_OUTER]] = !{!"branch_weights", i32 10, i32 6}
; USE-DAG: ![[BW_FOR_COND_INNER]] = !{!"branch_weights", i32 33, i32 10} ; USE-DAG: ![[BW_FOR_COND_INNER]] = !{!"branch_weights", i32 33, i32 10}

llvm/test/Transforms/PGOProfile/preinline.ll

; RUN: opt < %s -O2 -pgo-kind=pgo-instr-gen-pipeline -S | FileCheck %s --check-prefix=GEN ; RUN: opt < %s -O2 -pgo-kind=pgo-instr-gen-pipeline -S | FileCheck %s --check-prefix=GEN
; RUN: opt < %s -O2 -pgo-kind=pgo-instr-gen-pipeline -profile-file=default.profraw -S | FileCheck %s --check-prefix=GEN ; RUN: opt < %s -O2 -pgo-kind=pgo-instr-gen-pipeline -profile-file=default.profraw -S | FileCheck %s --check-prefix=GEN
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define i32 @foo(i32 %i) { define i32 @foo(i32 %i) {
entry: entry:
; GEN: %pgocount = load i64, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__profc_foo ; GEN: %pgocount = load i64, ptr @__profc_foo
; GEN-NOT: %pgocount.i = load i64, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__profc__stdin__bar ; GEN-NOT: %pgocount.i = load i64, ptr @__profc__stdin__bar
%call = call i32 @bar() %call = call i32 @bar()
%add = add nsw i32 %i, %call %add = add nsw i32 %i, %call
ret i32 %add ret i32 %add
} }
define internal i32 @bar() { define internal i32 @bar() {
; check that bar is inlined into foo and eliminiated from IR. ; check that bar is inlined into foo and eliminiated from IR.
; GEN-NOT: define internal i32 @bar ; GEN-NOT: define internal i32 @bar
entry: entry:
%call = call i32 (...) @bar1() %call = call i32 (...) @bar1()
ret i32 %call ret i32 %call
} }
declare i32 @bar1(...) declare i32 @bar1(...)

llvm/test/Transforms/PGOProfile/single_bb.ll

; RUN: opt < %s -passes=pgo-instr-gen -S | FileCheck %s --check-prefix=GEN ; RUN: opt < %s -passes=pgo-instr-gen -S | FileCheck %s --check-prefix=GEN
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; GEN: $__llvm_profile_raw_version = comdat any ; GEN: $__llvm_profile_raw_version = comdat any
; GEN: @__llvm_profile_raw_version = constant i64 {{[0-9]+}}, comdat ; GEN: @__llvm_profile_raw_version = constant i64 {{[0-9]+}}, comdat
; GEN: @__profn_single_bb = private constant [9 x i8] c"single_bb" ; GEN: @__profn_single_bb = private constant [9 x i8] c"single_bb"
define i32 @single_bb() { define i32 @single_bb() {
entry: entry:
; GEN: entry: ; GEN: entry:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @__profn_single_bb, i32 0, i32 0), i64 {{[0-9]+}}, i32 1, i32 0) ; GEN: call void @llvm.instrprof.increment(ptr @__profn_single_bb, i64 {{[0-9]+}}, i32 1, i32 0)
ret i32 0 ret i32 0
} }

llvm/test/Transforms/PGOProfile/switch.ll

Show All 9 Lines
; GEN: $__llvm_profile_raw_version = comdat any ; GEN: $__llvm_profile_raw_version = comdat any
; GEN: @__llvm_profile_raw_version = constant i64 {{[0-9]+}}, comdat ; GEN: @__llvm_profile_raw_version = constant i64 {{[0-9]+}}, comdat
; GEN: @__profn_test_switch = private constant [11 x i8] c"test_switch" ; GEN: @__profn_test_switch = private constant [11 x i8] c"test_switch"
define void @test_switch(i32 %i) { define void @test_switch(i32 %i) {
entry: entry:
; GEN: entry: ; GEN: entry:
; NOTENTRY-NOT: call void @llvm.instrprof.increment ; NOTENTRY-NOT: call void @llvm.instrprof.increment
; ENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @__profn_test_switch, i32 0, i32 0), i64 {{[0-9]+}}, i32 4, i32 0) ; ENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_switch, i64 {{[0-9]+}}, i32 4, i32 0)
switch i32 %i, label %sw.default [ switch i32 %i, label %sw.default [
i32 1, label %sw.bb i32 1, label %sw.bb
i32 2, label %sw.bb1 i32 2, label %sw.bb1
i32 3, label %sw.bb2 i32 3, label %sw.bb2
] ]
; USE: ] ; USE: ]
; USE-SAME: !prof ![[BW_SWITCH:[0-9]+]] ; USE-SAME: !prof ![[BW_SWITCH:[0-9]+]]
; USE: ![[BW_SWITCH]] = !{!"branch_weights", i32 3, i32 2, i32 0, i32 5} ; USE: ![[BW_SWITCH]] = !{!"branch_weights", i32 3, i32 2, i32 0, i32 5}
sw.bb: sw.bb:
; GEN: sw.bb: ; GEN: sw.bb:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @__profn_test_switch, i32 0, i32 0), i64 {{[0-9]+}}, i32 4, i32 2) ; GEN: call void @llvm.instrprof.increment(ptr @__profn_test_switch, i64 {{[0-9]+}}, i32 4, i32 2)
br label %sw.epilog br label %sw.epilog
sw.bb1: sw.bb1:
; GEN: sw.bb1: ; GEN: sw.bb1:
; NOTENTRY: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @__profn_test_switch, i32 0, i32 0), i64 {{[0-9]+}}, i32 4, i32 0) ; NOTENTRY: call void @llvm.instrprof.increment(ptr @__profn_test_switch, i64 {{[0-9]+}}, i32 4, i32 0)
; ENTRY-NOT: call void @llvm.instrprof.increment ; ENTRY-NOT: call void @llvm.instrprof.increment
br label %sw.epilog br label %sw.epilog
sw.bb2: sw.bb2:
; GEN: sw.bb2: ; GEN: sw.bb2:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @__profn_test_switch, i32 0, i32 0), i64 {{[0-9]+}}, i32 4, i32 1) ; GEN: call void @llvm.instrprof.increment(ptr @__profn_test_switch, i64 {{[0-9]+}}, i32 4, i32 1)
br label %sw.epilog br label %sw.epilog
sw.default: sw.default:
; GEN: sw.default: ; GEN: sw.default:
; GEN: call void @llvm.instrprof.increment(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @__profn_test_switch, i32 0, i32 0), i64 {{[0-9]+}}, i32 4, i32 3) ; GEN: call void @llvm.instrprof.increment(ptr @__profn_test_switch, i64 {{[0-9]+}}, i32 4, i32 3)
br label %sw.epilog br label %sw.epilog
sw.epilog: sw.epilog:
; GEN: sw.epilog: ; GEN: sw.epilog:
; GEN-NOT: call void @llvm.instrprof.increment ; GEN-NOT: call void @llvm.instrprof.increment
ret void ret void
; GEN: ret void ; GEN: ret void
} }

llvm/test/Transforms/PGOProfile/thinlto_indirect_call_promotion.ll

Show All 9 Lines
; RUN: opt %t4.bc -icp-lto -passes=pgo-icall-prom -S | FileCheck %s --check-prefix=ICALL-PROM ; RUN: opt %t4.bc -icp-lto -passes=pgo-icall-prom -S | FileCheck %s --check-prefix=ICALL-PROM
; RUN: opt %t4.bc -icp-lto -passes=pgo-icall-prom -S -pass-remarks=pgo-icall-prom 2>&1 | FileCheck %s --check-prefix=PASS-REMARK ; RUN: opt %t4.bc -icp-lto -passes=pgo-icall-prom -S -pass-remarks=pgo-icall-prom 2>&1 | FileCheck %s --check-prefix=PASS-REMARK
; PASS-REMARK: Promote indirect call to a with count 1 out of 1 ; PASS-REMARK: Promote indirect call to a with count 1 out of 1
; PASS-REMARK: Promote indirect call to c.llvm.0 with count 1 out of 1 ; PASS-REMARK: Promote indirect call to c.llvm.0 with count 1 out of 1
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@foo = external local_unnamed_addr global void ()*, align 8 @foo = external local_unnamed_addr global ptr, align 8
@bar = external local_unnamed_addr global void ()*, align 8 @bar = external local_unnamed_addr global ptr, align 8
define i32 @main() local_unnamed_addr { define i32 @main() local_unnamed_addr {
entry: entry:
%0 = load void ()*, void ()** @foo, align 8 %0 = load ptr, ptr @foo, align 8
; ICALL-PROM: br i1 %{{[0-9]+}}, label %if.true.direct_targ, label %if.false.orig_indirect, !prof [[BRANCH_WEIGHT:![0-9]+]] ; ICALL-PROM: br i1 %{{[0-9]+}}, label %if.true.direct_targ, label %if.false.orig_indirect, !prof [[BRANCH_WEIGHT:![0-9]+]]
tail call void %0(), !prof !1 tail call void %0(), !prof !1
%1 = load void ()*, void ()** @bar, align 8 %1 = load ptr, ptr @bar, align 8
; ICALL-PROM: br i1 %{{[0-9]+}}, label %if.true.direct_targ1, label %if.false.orig_indirect2, !prof [[BRANCH_WEIGHT:![0-9]+]] ; ICALL-PROM: br i1 %{{[0-9]+}}, label %if.true.direct_targ1, label %if.false.orig_indirect2, !prof [[BRANCH_WEIGHT:![0-9]+]]
tail call void %1(), !prof !2 tail call void %1(), !prof !2
ret i32 0 ret i32 0
} }
!1 = !{!"VP", i32 0, i64 1, i64 -6289574019528802036, i64 1} !1 = !{!"VP", i32 0, i64 1, i64 -6289574019528802036, i64 1}
!2 = !{!"VP", i32 0, i64 1, i64 591260329866125152, i64 1} !2 = !{!"VP", i32 0, i64 1, i64 591260329866125152, i64 1}
; Should not have a VP annotation on new indirect call (check before and after ; Should not have a VP annotation on new indirect call (check before and after
; branch_weights annotation). ; branch_weights annotation).
; ICALL-PROM-NOT: !"VP" ; ICALL-PROM-NOT: !"VP"
; ICALL-PROM: [[BRANCH_WEIGHT]] = !{!"branch_weights", i32 1, i32 0} ; ICALL-PROM: [[BRANCH_WEIGHT]] = !{!"branch_weights", i32 1, i32 0}
; ICALL-PROM-NOT: !"VP" ; ICALL-PROM-NOT: !"VP"

llvm/test/Transforms/PGOProfile/thinlto_samplepgo_icp2.ll

Show All 21 Lines
; RUN: llvm-nm %t3.2 | FileCheck %s --check-prefix=NM ; RUN: llvm-nm %t3.2 | FileCheck %s --check-prefix=NM
; NM: _ZL3barv ; NM: _ZL3barv
; RUN: llvm-dis < %t3.3.2.internalize.bc | FileCheck %s --check-prefix=INTERNALIZE ; RUN: llvm-dis < %t3.3.2.internalize.bc | FileCheck %s --check-prefix=INTERNALIZE
; INTERNALIZE: define dso_local void @_ZL3barv ; INTERNALIZE: define dso_local void @_ZL3barv
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@fptr = local_unnamed_addr global void ()* null, align 8 @fptr = local_unnamed_addr global ptr null, align 8
; Function Attrs: norecurse uwtable ; Function Attrs: norecurse uwtable
define i32 @main() local_unnamed_addr #0 !prof !34 { define i32 @main() local_unnamed_addr #0 !prof !34 {
entry: entry:
%0 = load void ()*, void ()** @fptr, align 8 %0 = load ptr, ptr @fptr, align 8
; ICALL-PROM: br i1 %{{[0-9]+}}, label %if.true.direct_targ, label %if.false.orig_indirect ; ICALL-PROM: br i1 %{{[0-9]+}}, label %if.true.direct_targ, label %if.false.orig_indirect
tail call void %0(), !prof !40 tail call void %0(), !prof !40
ret i32 0 ret i32 0
} }
!llvm.dbg.cu = !{!0} !llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3,!4} !llvm.module.flags = !{!3,!4}
!llvm.ident = !{!31} !llvm.ident = !{!31}
Show All 35 Lines

llvm/test/Transforms/PhaseOrdering/X86/simplifycfg-late.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes="lto<O2>" -S | FileCheck %s ; RUN: opt < %s -passes="lto<O2>" -S | FileCheck %s
target datalayout = "i32:32:32-i64:64:64" target datalayout = "i32:32:32-i64:64:64"
target triple = "x86_64--" target triple = "x86_64--"
; Verify that the "late" simplifycfg options are set. This should get converted into a lookup table. ; Verify that the "late" simplifycfg options are set. This should get converted into a lookup table.
define i32 @f(i32 %c) { define i32 @f(i32 %c) {
; CHECK-LABEL: @f( ; CHECK-LABEL: @f(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = add i32 [[C:%.*]], -42 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = add i32 [[C:%.*]], -42
; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 7 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 7
; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
; CHECK: switch.lookup: ; CHECK: switch.lookup:
; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[SWITCH_TABLEIDX]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[SWITCH_TABLEIDX]] to i64
; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table.f, i64 0, i64 [[TMP1]] ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], ptr @switch.table.f, i64 0, i64 [[TMP1]]
; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
; CHECK-NEXT: br label [[RETURN]] ; CHECK-NEXT: br label [[RETURN]]
; CHECK: return: ; CHECK: return:
; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 15, [[ENTRY:%.*]] ] ; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 15, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i32 [[R]] ; CHECK-NEXT: ret i32 [[R]]
; ;
entry: entry:
switch i32 %c, label %sw.default [ switch i32 %c, label %sw.default [
i32 42, label %return i32 42, label %return
Show All 26 Lines

llvm/test/Transforms/RewriteStatepointsForGC/call-gc-result.ll

Show All 15 Lines
; CHECK-NEXT: br i1 [[COND:%.*]], label [[BRANCH1:%.*]], label [[BRANCH2:%.*]] ; CHECK-NEXT: br i1 [[COND:%.*]], label [[BRANCH1:%.*]], label [[BRANCH2:%.*]]
; CHECK: branch1: ; CHECK: branch1:
; CHECK-NEXT: [[B:%.*]] = add i32 [[A:%.*]], 1 ; CHECK-NEXT: [[B:%.*]] = add i32 [[A:%.*]], 1
; CHECK-NEXT: br label [[MERGE:%.*]] ; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: branch2: ; CHECK: branch2:
; CHECK-NEXT: br label [[MERGE]] ; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge: ; CHECK: merge:
; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[A]], [[BRANCH2]] ], [ [[B]], [[BRANCH1]] ] ; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[A]], [[BRANCH2]] ], [ [[B]], [[BRANCH1]] ]
; CHECK-NEXT: [[STATEPOINT_TOKEN:%.*]] = call token (i64, i32, i32 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i32f(i64 2882400000, i32 0, i32 ()* elementtype(i32 ()) @foo, i32 0, i32 0, i32 0, i32 0) ; CHECK-NEXT: [[STATEPOINT_TOKEN:%.*]] = call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 2882400000, i32 0, ptr elementtype(i32 ()) @foo, i32 0, i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET1:%.*]] = call i32 @llvm.experimental.gc.result.i32(token [[STATEPOINT_TOKEN]]) ; CHECK-NEXT: [[RET1:%.*]] = call i32 @llvm.experimental.gc.result.i32(token [[STATEPOINT_TOKEN]])
; CHECK-NEXT: ret i32 [[RET1]] ; CHECK-NEXT: ret i32 [[RET1]]
; ;
entry: entry:
br i1 %cond, label %branch1, label %branch2 br i1 %cond, label %branch1, label %branch2
branch1: branch1:
%b = add i32 %a, 1 %b = add i32 %a, 1
Show All 23 Lines

llvm/test/Transforms/RewriteStatepointsForGC/deopt-intrinsic-cconv.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -rewrite-statepoints-for-gc -S < %s | FileCheck %s ; RUN: opt -rewrite-statepoints-for-gc -S < %s | FileCheck %s
; RUN: opt -passes=rewrite-statepoints-for-gc -S < %s | FileCheck %s ; RUN: opt -passes=rewrite-statepoints-for-gc -S < %s | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.11.0" target triple = "x86_64-apple-macosx10.11.0"
declare cc42 double @llvm.experimental.deoptimize.f64(...) declare cc42 double @llvm.experimental.deoptimize.f64(...)
define double @caller_3() gc "statepoint-example" { define double @caller_3() gc "statepoint-example" {
; CHECK-LABEL: @caller_3( ; CHECK-LABEL: @caller_3(
; CHECK: call cc42 token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint ; CHECK-NEXT: entry:
; CHECK: unreachable ; CHECK-NEXT: [[SAFEPOINT_TOKEN:%.*]] = call cc42 token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 2882400000, i32 0, ptr elementtype(void ()) @__llvm_deoptimize, i32 0, i32 0, i32 0, i32 0) [ "deopt"() ]
; CHECK-NEXT: unreachable
;
entry: entry:
%val = call cc42 double(...) @llvm.experimental.deoptimize.f64() [ "deopt"() ] %val = call cc42 double(...) @llvm.experimental.deoptimize.f64() [ "deopt"() ]
ret double %val ret double %val
} }

llvm/test/Transforms/RewriteStatepointsForGC/deopt-lowering-attrs.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -rewrite-statepoints-for-gc -S < %s | FileCheck %s ; RUN: opt -rewrite-statepoints-for-gc -S < %s | FileCheck %s
; RUN: opt -passes=rewrite-statepoints-for-gc -S < %s | FileCheck %s ; RUN: opt -passes=rewrite-statepoints-for-gc -S < %s | FileCheck %s
; Check that the "deopt-lowering" function attribute gets transcoded into ; Check that the "deopt-lowering" function attribute gets transcoded into
; flags on the resulting statepoint ; flags on the resulting statepoint
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.11.0" target triple = "x86_64-apple-macosx10.11.0"
declare void @foo() declare void @foo()
declare void @bar() "deopt-lowering"="live-in" declare void @bar() "deopt-lowering"="live-in"
declare void @baz() "deopt-lowering"="live-through" declare void @baz() "deopt-lowering"="live-through"
define void @test1() gc "statepoint-example" { define void @test1() gc "statepoint-example" {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[STATEPOINT_TOKEN:%.*]] = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* elementtype(void ()) @foo, i32 0, i32 0, i32 0, i32 0) [ "deopt"(i32 57) ] ; CHECK-NEXT: [[STATEPOINT_TOKEN:%.*]] = call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 2882400000, i32 0, ptr elementtype(void ()) @foo, i32 0, i32 0, i32 0, i32 0) [ "deopt"(i32 57) ]
; CHECK-NEXT: [[STATEPOINT_TOKEN1:%.*]] = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* elementtype(void ()) @bar, i32 0, i32 2, i32 0, i32 0) [ "deopt"(i32 42) ] ; CHECK-NEXT: [[STATEPOINT_TOKEN1:%.*]] = call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 2882400000, i32 0, ptr elementtype(void ()) @bar, i32 0, i32 2, i32 0, i32 0) [ "deopt"(i32 42) ]
; CHECK-NEXT: [[STATEPOINT_TOKEN2:%.*]] = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* elementtype(void ()) @baz, i32 0, i32 0, i32 0, i32 0) [ "deopt"(i32 13) ] ; CHECK-NEXT: [[STATEPOINT_TOKEN2:%.*]] = call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 2882400000, i32 0, ptr elementtype(void ()) @baz, i32 0, i32 0, i32 0, i32 0) [ "deopt"(i32 13) ]
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
call void @foo() [ "deopt"(i32 57) ] call void @foo() [ "deopt"(i32 57) ]
call void @bar() [ "deopt"(i32 42) ] call void @bar() [ "deopt"(i32 42) ]
call void @baz() [ "deopt"(i32 13) ] call void @baz() [ "deopt"(i32 13) ]
ret void ret void
} }
; add deopt-lowering attribute as part of callsite ; add deopt-lowering attribute as part of callsite
define void @test2() gc "statepoint-example" { define void @test2() gc "statepoint-example" {
; CHECK-LABEL: @test2( ; CHECK-LABEL: @test2(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[STATEPOINT_TOKEN:%.*]] = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* elementtype(void ()) @foo, i32 0, i32 2, i32 0, i32 0) #[[ATTR0:[0-9]+]] [ "deopt"(i32 57) ] ; CHECK-NEXT: [[STATEPOINT_TOKEN:%.*]] = call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 2882400000, i32 0, ptr elementtype(void ()) @foo, i32 0, i32 2, i32 0, i32 0) #[[ATTR0:[0-9]+]] [ "deopt"(i32 57) ]
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
call void @foo() "deopt-lowering"="live-in" [ "deopt"(i32 57) ] call void @foo() "deopt-lowering"="live-in" [ "deopt"(i32 57) ]
ret void ret void
} }

llvm/test/Transforms/SimplifyCFG/X86/disable-lookup-table.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
define i32 @bar(i32 %c) { define i32 @bar(i32 %c) {
; CHECK-LABEL: @bar( ; CHECK-LABEL: @bar(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 42 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 42
; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 4 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 4
; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
; CHECK: switch.lookup: ; CHECK: switch.lookup:
; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.bar, i32 0, i32 [[SWITCH_TABLEIDX]] ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], ptr @switch.table.bar, i32 0, i32 [[SWITCH_TABLEIDX]]
; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
; CHECK-NEXT: br label [[RETURN]] ; CHECK-NEXT: br label [[RETURN]]
; CHECK: return: ; CHECK: return:
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 15, [[ENTRY:%.*]] ] ; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 15, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i32 [[RETVAL_0]] ; CHECK-NEXT: ret i32 [[RETVAL_0]]
; ;
entry: entry:
switch i32 %c, label %sw.default [ switch i32 %c, label %sw.default [
i32 42, label %return i32 42, label %return
Show All 14 Lines

llvm/test/Transforms/SimplifyCFG/X86/switch-covered-bug.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-to-lookup < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-to-lookup < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s
; RUN: opt -S -passes='simplifycfg<switch-to-lookup>' < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s ; RUN: opt -S -passes='simplifycfg<switch-to-lookup>' < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s
; rdar://17887153 ; rdar://17887153
target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin12.0.0" target triple = "x86_64-apple-darwin12.0.0"
define i64 @test(i3 %arg) { define i64 @test(i3 %arg) {
; CHECK-LABEL: @test( ; CHECK-LABEL: @test(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i3 [[ARG:%.*]], -4 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i3 [[ARG:%.*]], -4
; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i4 ; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i4
; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* @switch.table.test, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]] ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i64], ptr @switch.table.test, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]]
; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i64, i64* [[SWITCH_GEP]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i64, ptr [[SWITCH_GEP]], align 8
; CHECK-NEXT: [[V3:%.*]] = add i64 [[SWITCH_LOAD]], 0 ; CHECK-NEXT: [[V3:%.*]] = add i64 [[SWITCH_LOAD]], 0
; CHECK-NEXT: ret i64 [[V3]] ; CHECK-NEXT: ret i64 [[V3]]
; ;
entry: entry:
switch i3 %arg, label %Default [ switch i3 %arg, label %Default [
i3 -2, label %Label6 i3 -2, label %Label6
i3 1, label %Label1 i3 1, label %Label1
i3 2, label %Label2 i3 2, label %Label2
Show All 29 Lines

llvm/test/Transforms/SimplifyCFG/X86/switch-table-bug.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-to-lookup < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-to-lookup < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s
; RUN: opt -S -passes='simplifycfg<switch-to-lookup>' < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s ; RUN: opt -S -passes='simplifycfg<switch-to-lookup>' < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s
; rdar://17735071 ; rdar://17735071
target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin12.0.0" target triple = "x86_64-apple-darwin12.0.0"
define i64 @_TFO6reduce1E5toRawfS0_FT_Si(i2) { define i64 @_TFO6reduce1E5toRawfS0_FT_Si(i2) {
; CHECK-LABEL: @_TFO6reduce1E5toRawfS0_FT_Si( ; CHECK-LABEL: @_TFO6reduce1E5toRawfS0_FT_Si(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i2 [[TMP0:%.*]], -2 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i2 [[TMP0:%.*]], -2
; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i2 [[SWITCH_TABLEIDX]] to i3 ; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i2 [[SWITCH_TABLEIDX]] to i3
; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* @switch.table._TFO6reduce1E5toRawfS0_FT_Si, i32 0, i3 [[SWITCH_TABLEIDX_ZEXT]] ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i64], ptr @switch.table._TFO6reduce1E5toRawfS0_FT_Si, i32 0, i3 [[SWITCH_TABLEIDX_ZEXT]]
; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i64, i64* [[SWITCH_GEP]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i64, ptr [[SWITCH_GEP]], align 8
; CHECK-NEXT: ret i64 [[SWITCH_LOAD]] ; CHECK-NEXT: ret i64 [[SWITCH_LOAD]]
; ;
entry: entry:
switch i2 %0, label %1 [ switch i2 %0, label %1 [
i2 0, label %2 i2 0, label %2
i2 1, label %3 i2 1, label %3
i2 -2, label %4 i2 -2, label %4
i2 -1, label %5 i2 -1, label %5
Show All 21 Lines

llvm/test/Transforms/SimplifyCFG/X86/switch-to-lookup-large-types.ll

Show All 9 Lines
; CHECK-LABEL: @switch_to_lookup_i64( ; CHECK-LABEL: @switch_to_lookup_i64(
; CHECK-NEXT: start: ; CHECK-NEXT: start:
; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i128 [[X:%.*]], 3 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i128 [[X:%.*]], 3
; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]]
; CHECK: common.ret: ; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i8 [ [[SWITCH_LOAD:%.*]], [[SWITCH_LOOKUP]] ], [ 10, [[START:%.*]] ] ; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i8 [ [[SWITCH_LOAD:%.*]], [[SWITCH_LOOKUP]] ], [ 10, [[START:%.*]] ]
; CHECK-NEXT: ret i8 [[COMMON_RET_OP]] ; CHECK-NEXT: ret i8 [[COMMON_RET_OP]]
; CHECK: switch.lookup: ; CHECK: switch.lookup:
; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [3 x i8], [3 x i8]* @switch.table.switch_to_lookup_i64, i32 0, i128 [[X]] ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [3 x i8], ptr @switch.table.switch_to_lookup_i64, i32 0, i128 [[X]]
; CHECK-NEXT: [[SWITCH_LOAD]] = load i8, i8* [[SWITCH_GEP]], align 1 ; CHECK-NEXT: [[SWITCH_LOAD]] = load i8, ptr [[SWITCH_GEP]], align 1
; CHECK-NEXT: br label [[COMMON_RET]] ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
start: start:
switch i128 %x, label %default [ switch i128 %x, label %default [
i128 0, label %end i128 0, label %end
i128 1, label %bb1 i128 1, label %bb1
i128 2, label %bb2 i128 2, label %bb2
] ]
Show All 16 Lines
; CHECK-LABEL: @switch_to_lookup_i128( ; CHECK-LABEL: @switch_to_lookup_i128(
; CHECK-NEXT: start: ; CHECK-NEXT: start:
; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i128 [[X:%.*]], 3 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i128 [[X:%.*]], 3
; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]]
; CHECK: common.ret: ; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i8 [ [[SWITCH_LOAD:%.*]], [[SWITCH_LOOKUP]] ], [ 10, [[START:%.*]] ] ; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i8 [ [[SWITCH_LOAD:%.*]], [[SWITCH_LOOKUP]] ], [ 10, [[START:%.*]] ]
; CHECK-NEXT: ret i8 [[COMMON_RET_OP]] ; CHECK-NEXT: ret i8 [[COMMON_RET_OP]]
; CHECK: switch.lookup: ; CHECK: switch.lookup:
; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [3 x i8], [3 x i8]* @switch.table.switch_to_lookup_i128, i32 0, i128 [[X]] ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [3 x i8], ptr @switch.table.switch_to_lookup_i128, i32 0, i128 [[X]]
; CHECK-NEXT: [[SWITCH_LOAD]] = load i8, i8* [[SWITCH_GEP]], align 1 ; CHECK-NEXT: [[SWITCH_LOAD]] = load i8, ptr [[SWITCH_GEP]], align 1
; CHECK-NEXT: br label [[COMMON_RET]] ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
start: start:
switch i128 %x, label %default [ switch i128 %x, label %default [
i128 0, label %end i128 0, label %end
i128 1, label %bb1 i128 1, label %bb1
i128 2, label %bb2 i128 2, label %bb2
] ]
Show All 14 Lines

llvm/test/Transforms/SimplifyCFG/rangereduce.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-to-lookup -S | FileCheck %s ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-to-lookup -S | FileCheck %s
; RUN: opt < %s -passes='simplifycfg<switch-to-lookup>' -S | FileCheck %s ; RUN: opt < %s -passes='simplifycfg<switch-to-lookup>' -S | FileCheck %s
target datalayout = "e-n32" target datalayout = "e-n32"
define i32 @test1(i32 %a) { define i32 @test1(i32 %a) {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[A:%.*]], 97 ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[A:%.*]], 97
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2
; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 30 ; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 30
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], 4 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], 4
; CHECK-NEXT: br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] ; CHECK-NEXT: br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]]
; CHECK: switch.lookup: ; CHECK: switch.lookup:
; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.test1, i32 0, i32 [[TMP4]] ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], ptr @switch.table.test1, i32 0, i32 [[TMP4]]
; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
; CHECK-NEXT: br label [[COMMON_RET]] ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: common.ret: ; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 8867, [[TMP0:%.*]] ] ; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 8867, [[TMP0:%.*]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]] ; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; ;
switch i32 %a, label %def [ switch i32 %a, label %def [
i32 97, label %one i32 97, label %one
i32 101, label %two i32 101, label %two
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; Optimization shouldn't trigger; no holes present ; Optimization shouldn't trigger; no holes present
define i32 @test3(i32 %a) { define i32 @test3(i32 %a) {
; CHECK-LABEL: @test3( ; CHECK-LABEL: @test3(
; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[A:%.*]], 97 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[A:%.*]], 97
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 3 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 3
; CHECK-NEXT: br i1 [[TMP1]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] ; CHECK-NEXT: br i1 [[TMP1]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]]
; CHECK: switch.lookup: ; CHECK: switch.lookup:
; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [3 x i32], [3 x i32]* @switch.table.test3, i32 0, i32 [[SWITCH_TABLEIDX]] ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [3 x i32], ptr @switch.table.test3, i32 0, i32 [[SWITCH_TABLEIDX]]
; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
; CHECK-NEXT: br label [[COMMON_RET]] ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: common.ret: ; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 8867, [[TMP0:%.*]] ] ; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 8867, [[TMP0:%.*]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]] ; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; ;
switch i32 %a, label %def [ switch i32 %a, label %def [
i32 97, label %one i32 97, label %one
i32 98, label %two i32 98, label %two
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; CHECK-LABEL: @test6( ; CHECK-LABEL: @test6(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[A:%.*]], -109 ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[A:%.*]], -109
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2
; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 30 ; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 30
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], 4 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], 4
; CHECK-NEXT: br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] ; CHECK-NEXT: br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]]
; CHECK: switch.lookup: ; CHECK: switch.lookup:
; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.test6, i32 0, i32 [[TMP4]] ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], ptr @switch.table.test6, i32 0, i32 [[TMP4]]
; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
; CHECK-NEXT: br label [[COMMON_RET]] ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: common.ret: ; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 8867, [[TMP0:%.*]] ] ; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 8867, [[TMP0:%.*]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]] ; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; ;
switch i32 %a, label %def [ switch i32 %a, label %def [
i32 -97, label %one i32 -97, label %one
i32 -101, label %two i32 -101, label %two
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; CHECK-LABEL: @test8( ; CHECK-LABEL: @test8(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[A:%.*]], 97 ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[A:%.*]], 97
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2
; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 30 ; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 30
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], 5 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], 5
; CHECK-NEXT: br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] ; CHECK-NEXT: br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]]
; CHECK: switch.lookup: ; CHECK: switch.lookup:
; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [5 x i32], [5 x i32]* @switch.table.test8, i32 0, i32 [[TMP4]] ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr @switch.table.test8, i32 0, i32 [[TMP4]]
; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
; CHECK-NEXT: br label [[COMMON_RET]] ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: common.ret: ; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 8867, [[TMP0:%.*]] ] ; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 8867, [[TMP0:%.*]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]] ; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; ;
switch i32 %a, label %def [ switch i32 %a, label %def [
i32 97, label %one i32 97, label %one
i32 101, label %two i32 101, label %two
Show All 16 Lines
; CHECK-LABEL: @test9( ; CHECK-LABEL: @test9(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[A:%.*]], 6 ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[A:%.*]], 6
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 1
; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 31 ; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 31
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], 8 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], 8
; CHECK-NEXT: br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]] ; CHECK-NEXT: br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]]
; CHECK: switch.lookup: ; CHECK: switch.lookup:
; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], [8 x i32]* @switch.table.test9, i32 0, i32 [[TMP4]] ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], ptr @switch.table.test9, i32 0, i32 [[TMP4]]
; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
; CHECK-NEXT: br label [[COMMON_RET]] ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: common.ret: ; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 8867, [[TMP0:%.*]] ] ; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 8867, [[TMP0:%.*]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]] ; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; ;
switch i32 %a, label %def [ switch i32 %a, label %def [
i32 18, label %one i32 18, label %one
i32 20, label %two i32 20, label %two
Show All 15 Lines

llvm/test/Transforms/Util/add-TLI-mappings.ll

; RUN: opt -vector-library=SVML -inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,SVML ; RUN: opt -vector-library=SVML -inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,SVML
; RUN: opt -vector-library=SVML -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,SVML ; RUN: opt -vector-library=SVML -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,SVML
; RUN: opt -vector-library=MASSV -inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,MASSV ; RUN: opt -vector-library=MASSV -inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,MASSV
; RUN: opt -vector-library=MASSV -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,MASSV ; RUN: opt -vector-library=MASSV -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,MASSV
; RUN: opt -vector-library=Accelerate -inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,ACCELERATE ; RUN: opt -vector-library=Accelerate -inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,ACCELERATE
; RUN: opt -vector-library=LIBMVEC-X86 -inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,LIBMVEC-X86 ; RUN: opt -vector-library=LIBMVEC-X86 -inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,LIBMVEC-X86
; RUN: opt -vector-library=LIBMVEC-X86 -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,LIBMVEC-X86 ; RUN: opt -vector-library=LIBMVEC-X86 -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,LIBMVEC-X86
; RUN: opt -vector-library=Accelerate -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,ACCELERATE ; RUN: opt -vector-library=Accelerate -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,ACCELERATE
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; COMMON-LABEL: @llvm.compiler.used = appending global ; COMMON-LABEL: @llvm.compiler.used = appending global
; SVML-SAME: [6 x i8*] [ ; SVML-SAME: [6 x ptr] [
; SVML-SAME: i8* bitcast (<2 x double> (<2 x double>)* @__svml_sin2 to i8*), ; SVML-SAME: ptr @__svml_sin2,
; SVML-SAME: i8* bitcast (<4 x double> (<4 x double>)* @__svml_sin4 to i8*), ; SVML-SAME: ptr @__svml_sin4,
; SVML-SAME: i8* bitcast (<8 x double> (<8 x double>)* @__svml_sin8 to i8*), ; SVML-SAME: ptr @__svml_sin8,
; SVML-SAME: i8* bitcast (<4 x float> (<4 x float>)* @__svml_log10f4 to i8*), ; SVML-SAME: ptr @__svml_log10f4,
; SVML-SAME: i8* bitcast (<8 x float> (<8 x float>)* @__svml_log10f8 to i8*), ; SVML-SAME: ptr @__svml_log10f8,
; SVML-SAME: i8* bitcast (<16 x float> (<16 x float>)* @__svml_log10f16 to i8*) ; SVML-SAME: ptr @__svml_log10f16
; MASSV-SAME: [2 x i8*] [ ; MASSV-SAME: [2 x ptr] [
; MASSV-SAME: i8* bitcast (<2 x double> (<2 x double>)* @__sind2 to i8*), ; MASSV-SAME: ptr @__sind2,
; MASSV-SAME: i8* bitcast (<4 x float> (<4 x float>)* @__log10f4 to i8*) ; MASSV-SAME: ptr @__log10f4
; ACCELERATE-SAME: [1 x i8*] [ ; ACCELERATE-SAME: [1 x ptr] [
; ACCELERATE-SAME: i8* bitcast (<4 x float> (<4 x float>)* @vlog10f to i8*) ; ACCELERATE-SAME: ptr @vlog10f
; LIBMVEC-X86-SAME: [2 x i8*] [ ; LIBMVEC-X86-SAME: [2 x ptr] [
; LIBMVEC-X86-SAME: i8* bitcast (<2 x double> (<2 x double>)* @_ZGVbN2v_sin to i8*), ; LIBMVEC-X86-SAME: ptr @_ZGVbN2v_sin,
; LIBMVEC-X86-SAME: i8* bitcast (<4 x double> (<4 x double>)* @_ZGVdN4v_sin to i8*) ; LIBMVEC-X86-SAME: ptr @_ZGVdN4v_sin
; COMMON-SAME: ], section "llvm.metadata" ; COMMON-SAME: ], section "llvm.metadata"
define double @sin_f64(double %in) { define double @sin_f64(double %in) {
; COMMON-LABEL: @sin_f64( ; COMMON-LABEL: @sin_f64(
; SVML: call double @sin(double %{{.*}}) #[[SIN:[0-9]+]] ; SVML: call double @sin(double %{{.*}}) #[[SIN:[0-9]+]]
; MASSV: call double @sin(double %{{.*}}) #[[SIN:[0-9]+]] ; MASSV: call double @sin(double %{{.*}}) #[[SIN:[0-9]+]]
; ACCELERATE: call double @sin(double %{{.*}}) ; ACCELERATE: call double @sin(double %{{.*}})
; LIBMVEC-X86: call double @sin(double %{{.*}}) #[[SIN:[0-9]+]] ; LIBMVEC-X86: call double @sin(double %{{.*}}) #[[SIN:[0-9]+]]
Show All 40 Lines

llvm/test/Verifier/byval-1.ll

; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s ; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
; CHECK: Attribute 'byval(i32)' applied to incompatible type! ; CHECK: Attribute 'byval(i32)' applied to incompatible type!
; CHECK-NEXT: void (i32)* @h ; CHECK-NEXT: ptr @h
declare void @h(i32 byval(i32) %num) declare void @h(i32 byval(i32) %num)

llvm/test/Verifier/get-active-lane-mask.ll

; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s ; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
declare <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32, i32) declare <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32, i32)
define <4 x i32> @t1(i32 %IV, i32 %TC) { define <4 x i32> @t1(i32 %IV, i32 %TC) {
; CHECK: get_active_lane_mask: element type is not i1 ; CHECK: get_active_lane_mask: element type is not i1
; CHECK-NEXT: %res = call <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32 %IV, i32 %TC) ; CHECK-NEXT: %res = call <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32 %IV, i32 %TC)
%res = call <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32 %IV, i32 %TC) %res = call <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32 %IV, i32 %TC)
ret <4 x i32> %res ret <4 x i32> %res
} }
declare i32 @llvm.get.active.lane.mask.i32.i32(i32, i32) declare i32 @llvm.get.active.lane.mask.i32.i32(i32, i32)
define i32 @t2(i32 %IV, i32 %TC) { define i32 @t2(i32 %IV, i32 %TC) {
; CHECK: Intrinsic has incorrect return type! ; CHECK: Intrinsic has incorrect return type!
; CHECK-NEXT: i32 (i32, i32)* @llvm.get.active.lane.mask.i32.i32 ; CHECK-NEXT: ptr @llvm.get.active.lane.mask.i32.i32
%res = call i32 @llvm.get.active.lane.mask.i32.i32(i32 %IV, i32 %TC) %res = call i32 @llvm.get.active.lane.mask.i32.i32(i32 %IV, i32 %TC)
ret i32 %res ret i32 %res
} }

llvm/test/Verifier/jumptable.ll

; RUN: not llvm-as -disable-output %s 2>&1 | FileCheck %s ; RUN: not llvm-as -disable-output %s 2>&1 | FileCheck %s
define i32 @f() jumptable { define i32 @f() jumptable {
ret i32 0 ret i32 0
} }
; CHECK: Attribute 'jumptable' requires 'unnamed_addr' ; CHECK: Attribute 'jumptable' requires 'unnamed_addr'
; CHECK: i32 ()* @f ; CHECK: ptr @f

llvm/test/Verifier/llvm.compiler_used-invalid-type.ll

; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s ; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
@llvm.compiler.used = appending global [1 x i32] [i32 0], section "llvm.metadata" @llvm.compiler.used = appending global [1 x i32] [i32 0], section "llvm.metadata"
; CHECK: wrong type for intrinsic global variable ; CHECK: wrong type for intrinsic global variable
; CHECK-NEXT: [1 x i32]* @llvm.compiler.used ; CHECK-NEXT: ptr @llvm.compiler.used

llvm/test/Verifier/llvm.used-invalid-type.ll

; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s ; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
@llvm.used = appending global [1 x i32] [i32 0], section "llvm.metadata" @llvm.used = appending global [1 x i32] [i32 0], section "llvm.metadata"
; CHECK: wrong type for intrinsic global variable ; CHECK: wrong type for intrinsic global variable
; CHECK-NEXT: [1 x i32]* @llvm.used ; CHECK-NEXT: ptr @llvm.used

llvm/test/Verifier/llvm.used-invalid-type2.ll

; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s ; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
@llvm.used = appending global i32 0, section "llvm.metadata" @llvm.used = appending global i32 0, section "llvm.metadata"
; CHECK: Only global arrays can have appending linkage! ; CHECK: Only global arrays can have appending linkage!
; CHECK-NEXT: i32* @llvm.used ; CHECK-NEXT: ptr @llvm.used

llvm/test/Verifier/metadata-function-dbg.ll

Show All 17 Lines
; CHECK: DISubprogram attached to more than one function ; CHECK: DISubprogram attached to more than one function
define void @f4() !dbg !4 { define void @f4() !dbg !4 {
unreachable unreachable
} }
; CHECK-NOT: !dbg ; CHECK-NOT: !dbg
; CHECK: function !dbg attachment must be a subprogram ; CHECK: function !dbg attachment must be a subprogram
; CHECK-NEXT: void ()* @bar ; CHECK-NEXT: ptr @bar
; CHECK-NEXT: !{{[0-9]+}} = !{} ; CHECK-NEXT: !{{[0-9]+}} = !{}
define void @bar() !dbg !3 { define void @bar() !dbg !3 {
unreachable unreachable
} }
; CHECK: warning: ignoring invalid debug info ; CHECK: warning: ignoring invalid debug info
!llvm.module.flags = !{!0} !llvm.module.flags = !{!0}
!0 = !{i32 2, !"Debug Info Version", i32 3} !0 = !{i32 2, !"Debug Info Version", i32 3}
!llvm.dbg.cu = !{!1} !llvm.dbg.cu = !{!1}
!1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, retainedTypes: !5) !1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, retainedTypes: !5)
!2 = !DIFile(filename: "t.c", directory: "/path/to/dir") !2 = !DIFile(filename: "t.c", directory: "/path/to/dir")
!3 = !{} !3 = !{}
!4 = distinct !DISubprogram(name: "foo", scope: !1, file: !2, unit: !1) !4 = distinct !DISubprogram(name: "foo", scope: !1, file: !2, unit: !1)
!5 = !{!6} !5 = !{!6}
!6 = !DISubprogram(name: "f5", scope: !1, file: !2, unit: !1, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) !6 = !DISubprogram(name: "f5", scope: !1, file: !2, unit: !1, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized)

llvm/test/tools/llvm-extract/extract-blocks-with-groups.ll

; RUN: llvm-extract -bb 'foo:if;then;else' -bb 'bar:bb14;bb20' -S %s | FileCheck %s ; RUN: llvm-extract -bb 'foo:if;then;else' -bb 'bar:bb14;bb20' -S %s | FileCheck %s
; Extract two groups of basic blocks in two different functions. ; Extract two groups of basic blocks in two different functions.
; The first extracted function is the region composed by the ; The first extracted function is the region composed by the
; blocks if, then, and else from foo. ; blocks if, then, and else from foo.
; CHECK: define dso_local void @foo.if.split(i32 %arg1, i32 %arg, i32* %tmp.0.ce.out) { ; CHECK: define dso_local void @foo.if.split(i32 %arg1, i32 %arg, ptr %tmp.0.ce.out) {
; CHECK: newFuncRoot: ; CHECK: newFuncRoot:
; CHECK: br label %if.split ; CHECK: br label %if.split
; ;
; CHECK: then: ; preds = %if.split ; CHECK: then: ; preds = %if.split
; CHECK: %tmp12 = shl i32 %arg1, 2 ; CHECK: %tmp12 = shl i32 %arg1, 2
; CHECK: %tmp13 = add nsw i32 %tmp12, %arg ; CHECK: %tmp13 = add nsw i32 %tmp12, %arg
; CHECK: br label %end.split ; CHECK: br label %end.split
; ;
; CHECK: else: ; preds = %if.split ; CHECK: else: ; preds = %if.split
; CHECK: %tmp22 = mul nsw i32 %arg, 3 ; CHECK: %tmp22 = mul nsw i32 %arg, 3
; CHECK: %tmp24 = sdiv i32 %arg1, 6 ; CHECK: %tmp24 = sdiv i32 %arg1, 6
; CHECK: %tmp25 = add nsw i32 %tmp24, %tmp22 ; CHECK: %tmp25 = add nsw i32 %tmp24, %tmp22
; CHECK: br label %end.split ; CHECK: br label %end.split
; ;
; CHECK: if.split: ; preds = %newFuncRoot ; CHECK: if.split: ; preds = %newFuncRoot
; CHECK: %tmp5 = icmp sgt i32 %arg, 0 ; CHECK: %tmp5 = icmp sgt i32 %arg, 0
; CHECK: %tmp8 = icmp sgt i32 %arg1, 0 ; CHECK: %tmp8 = icmp sgt i32 %arg1, 0
; CHECK: %or.cond = and i1 %tmp5, %tmp8 ; CHECK: %or.cond = and i1 %tmp5, %tmp8
; CHECK: br i1 %or.cond, label %then, label %else ; CHECK: br i1 %or.cond, label %then, label %else
; ;
; CHECK: end.split: ; preds = %then, %else ; CHECK: end.split: ; preds = %then, %else
; CHECK: %tmp.0.ce = phi i32 [ %tmp13, %then ], [ %tmp25, %else ] ; CHECK: %tmp.0.ce = phi i32 [ %tmp13, %then ], [ %tmp25, %else ]
; CHECK: store i32 %tmp.0.ce, i32* %tmp.0.ce.out ; CHECK: store i32 %tmp.0.ce, ptr %tmp.0.ce.out
; CHECK: br label %end.exitStub ; CHECK: br label %end.exitStub
; ;
; CHECK: end.exitStub: ; preds = %end.split ; CHECK: end.exitStub: ; preds = %end.split
; CHECK: ret void ; CHECK: ret void
; CHECK: } ; CHECK: }
; The second extracted function is the region composed by the blocks ; The second extracted function is the region composed by the blocks
; bb14 and bb20 from bar. ; bb14 and bb20 from bar.
; CHECK: define dso_local i1 @bar.bb14(i32 %arg1, i32 %arg, i32* %tmp25.out) { ; CHECK: define dso_local i1 @bar.bb14(i32 %arg1, i32 %arg, ptr %tmp25.out) {
; CHECK: newFuncRoot: ; CHECK: newFuncRoot:
; CHECK: br label %bb14 ; CHECK: br label %bb14
; ;
; CHECK: bb14: ; preds = %newFuncRoot ; CHECK: bb14: ; preds = %newFuncRoot
; CHECK: %tmp0 = and i32 %arg1, %arg ; CHECK: %tmp0 = and i32 %arg1, %arg
; CHECK: %tmp1 = icmp slt i32 %tmp0, 0 ; CHECK: %tmp1 = icmp slt i32 %tmp0, 0
; CHECK: br i1 %tmp1, label %bb20, label %bb26.exitStub ; CHECK: br i1 %tmp1, label %bb20, label %bb26.exitStub
; ;
; CHECK: bb20: ; preds = %bb14 ; CHECK: bb20: ; preds = %bb14
; CHECK: %tmp22 = mul nsw i32 %arg, 3 ; CHECK: %tmp22 = mul nsw i32 %arg, 3
; CHECK: %tmp24 = sdiv i32 %arg1, 6 ; CHECK: %tmp24 = sdiv i32 %arg1, 6
; CHECK: %tmp25 = add nsw i32 %tmp24, %tmp22 ; CHECK: %tmp25 = add nsw i32 %tmp24, %tmp22
; CHECK: store i32 %tmp25, i32* %tmp25.out ; CHECK: store i32 %tmp25, ptr %tmp25.out
; CHECK: br label %bb30.exitStub ; CHECK: br label %bb30.exitStub
; ;
; CHECK: bb26.exitStub: ; preds = %bb14 ; CHECK: bb26.exitStub: ; preds = %bb14
; CHECK: ret i1 true ; CHECK: ret i1 true
; ;
; CHECK: bb30.exitStub: ; preds = %bb20 ; CHECK: bb30.exitStub: ; preds = %bb20
; CHECK: ret i1 false ; CHECK: ret i1 false
; CHECK: } ; CHECK: }
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

llvm/test/tools/llvm-link/archive-only-needed.ll

; RUN: llvm-as %S/Inputs/f.ll -o %t.f.bc ; RUN: llvm-as %S/Inputs/f.ll -o %t.f.bc
; RUN: llvm-as %S/Inputs/g.ll -o %t.g.bc ; RUN: llvm-as %S/Inputs/g.ll -o %t.g.bc
; RUN: llvm-as %S/Inputs/i.ll -o %t.i.bc ; RUN: llvm-as %S/Inputs/i.ll -o %t.i.bc
; RUN: rm -f %t.lib ; RUN: rm -f %t.lib
; RUN: llvm-ar cr %t.lib %t.f.bc %t.g.bc %t.i.bc ; RUN: llvm-ar cr %t.lib %t.f.bc %t.g.bc %t.i.bc
; RUN: llvm-link %s %t.lib -o %t.linked.bc --only-needed ; RUN: llvm-link %s %t.lib -o %t.linked.bc --only-needed
; RUN: llvm-nm %t.linked.bc | FileCheck %s ; RUN: llvm-nm %t.linked.bc | FileCheck %s
; CHECK: -------- T f ; CHECK: -------- T f
; CHECK: -------- T i ; CHECK: -------- T i
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@i = external global i8* @i = external global ptr
@llvm.used = appending global [1 x i8*] [i8* bitcast (i8** @i to i8*)], section "llvm.metadata" @llvm.used = appending global [1 x ptr] [ptr @i], section "llvm.metadata"

llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp

Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Linesstatic omp::ScheduleKind getSchedKind(omp::OMPScheduleType SchedType) {
default: default:
llvm_unreachable("unknown type for this test"); llvm_unreachable("unknown type for this test");
} }
} }
class OpenMPIRBuilderTest : public testing::Test { class OpenMPIRBuilderTest : public testing::Test {
protected: protected:
void SetUp() override { void SetUp() override {
Ctx.setOpaquePointers(false); // TODO: Update tests for opaque pointers.
M.reset(new Module("MyModule", Ctx)); M.reset(new Module("MyModule", Ctx));
FunctionType *FTy = FunctionType *FTy =
FunctionType::get(Type::getVoidTy(Ctx), {Type::getInt32Ty(Ctx)}, FunctionType::get(Type::getVoidTy(Ctx), {Type::getInt32Ty(Ctx)},
/*isVarArg=*/false); /*isVarArg=*/false);
F = Function::Create(FTy, Function::ExternalLinkage, "", M.get()); F = Function::Create(FTy, Function::ExternalLinkage, "", M.get());
BB = BasicBlock::Create(Ctx, "", F); BB = BasicBlock::Create(Ctx, "", F);
DIBuilder DIB(*M); DIBuilder DIB(*M);
▲ Show 20 Lines • Show All 4,666 Lines • Show Last 20 Lines

llvm/unittests/IR/ConstantsTest.cpp

Show First 20 Lines • Show All 227 Lines • ▼ Show 20 LinesTEST(ConstantsTest, AsInstructionsTest) {
Constant *One = ConstantInt::get(Int32Ty, 1); Constant *One = ConstantInt::get(Int32Ty, 1);
Constant *Two = ConstantInt::get(Int64Ty, 2); Constant *Two = ConstantInt::get(Int64Ty, 2);
Constant *Big = ConstantInt::get(Context, APInt{256, uint64_t(-1), true}); Constant *Big = ConstantInt::get(Context, APInt{256, uint64_t(-1), true});
Constant *Elt = ConstantInt::get(Int16Ty, 2015); Constant *Elt = ConstantInt::get(Int16Ty, 2015);
Constant *Poison16 = PoisonValue::get(Int16Ty); Constant *Poison16 = PoisonValue::get(Int16Ty);
Constant *Undef64 = UndefValue::get(Int64Ty); Constant *Undef64 = UndefValue::get(Int64Ty);
Constant *PoisonV16 = PoisonValue::get(P6->getType()); Constant *PoisonV16 = PoisonValue::get(P6->getType());
#define P0STR "ptrtoint (i32** @dummy to i32)" #define P0STR "ptrtoint (ptr @dummy to i32)"
#define P1STR "uitofp (i32 ptrtoint (i32** @dummy to i32) to float)" #define P1STR "uitofp (i32 ptrtoint (ptr @dummy to i32) to float)"
#define P2STR "uitofp (i32 ptrtoint (i32** @dummy to i32) to double)" #define P2STR "uitofp (i32 ptrtoint (ptr @dummy to i32) to double)"
#define P3STR "ptrtoint (i32** @dummy to i1)" #define P3STR "ptrtoint (ptr @dummy to i1)"
#define P4STR "ptrtoint (i32** @dummy2 to i32)" #define P4STR "ptrtoint (ptr @dummy2 to i32)"
#define P5STR "uitofp (i32 ptrtoint (i32** @dummy2 to i32) to float)" #define P5STR "uitofp (i32 ptrtoint (ptr @dummy2 to i32) to float)"
#define P6STR "bitcast (i32 ptrtoint (i32** @dummy2 to i32) to <2 x i16>)" #define P6STR "bitcast (i32 ptrtoint (ptr @dummy2 to i32) to <2 x i16>)"
CHECK(ConstantExpr::getNeg(P0), "sub i32 0, " P0STR); CHECK(ConstantExpr::getNeg(P0), "sub i32 0, " P0STR);
CHECK(ConstantExpr::getFNeg(P1), "fneg float " P1STR); CHECK(ConstantExpr::getFNeg(P1), "fneg float " P1STR);
CHECK(ConstantExpr::getNot(P0), "xor i32 " P0STR ", -1"); CHECK(ConstantExpr::getNot(P0), "xor i32 " P0STR ", -1");
CHECK(ConstantExpr::getAdd(P0, P0), "add i32 " P0STR ", " P0STR); CHECK(ConstantExpr::getAdd(P0, P0), "add i32 " P0STR ", " P0STR);
CHECK(ConstantExpr::getAdd(P0, P0, false, true), CHECK(ConstantExpr::getAdd(P0, P0, false, true),
"add nsw i32 " P0STR ", " P0STR); "add nsw i32 " P0STR ", " P0STR);
CHECK(ConstantExpr::getAdd(P0, P0, true, true), CHECK(ConstantExpr::getAdd(P0, P0, true, true),
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines#define P6STR "bitcast (i32 ptrtoint (ptr @dummy2 to i32) to <2 x i16>)"
std::vector<Constant *> V; std::vector<Constant *> V;
V.push_back(One); V.push_back(One);
// FIXME: getGetElementPtr() actually creates an inbounds ConstantGEP, // FIXME: getGetElementPtr() actually creates an inbounds ConstantGEP,
// not a normal one! // not a normal one!
// CHECK(ConstantExpr::getGetElementPtr(Global, V, false), // CHECK(ConstantExpr::getGetElementPtr(Global, V, false),
// "getelementptr i32*, i32** @dummy, i32 1"); // "getelementptr i32*, i32** @dummy, i32 1");
CHECK(ConstantExpr::getInBoundsGetElementPtr(PointerType::getUnqual(Int32Ty), CHECK(ConstantExpr::getInBoundsGetElementPtr(PointerType::getUnqual(Int32Ty),
Global, V), Global, V),
"getelementptr inbounds i32*, i32** @dummy, i32 1"); "getelementptr inbounds ptr, ptr @dummy, i32 1");
CHECK(ConstantExpr::getExtractElement(P6, One), CHECK(ConstantExpr::getExtractElement(P6, One),
"extractelement <2 x i16> " P6STR ", i32 1"); "extractelement <2 x i16> " P6STR ", i32 1");
EXPECT_EQ(Poison16, ConstantExpr::getExtractElement(P6, Two)); EXPECT_EQ(Poison16, ConstantExpr::getExtractElement(P6, Two));
EXPECT_EQ(Poison16, ConstantExpr::getExtractElement(P6, Big)); EXPECT_EQ(Poison16, ConstantExpr::getExtractElement(P6, Big));
EXPECT_EQ(Poison16, ConstantExpr::getExtractElement(P6, Undef64)); EXPECT_EQ(Poison16, ConstantExpr::getExtractElement(P6, Undef64));
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llvm/unittests/IR/IRBuilderTest.cpp

Show First 20 Lines • Show All 430 Lines • ▼ Show 20 LinesTEST_F(IRBuilderTest, Lifetime) {
CallInst *Start2 = Builder.CreateLifetimeStart(Var2); CallInst *Start2 = Builder.CreateLifetimeStart(Var2);
CallInst *Start3 = Builder.CreateLifetimeStart(Var3, Builder.getInt64(100)); CallInst *Start3 = Builder.CreateLifetimeStart(Var3, Builder.getInt64(100));
EXPECT_EQ(Start1->getArgOperand(0), Builder.getInt64(-1)); EXPECT_EQ(Start1->getArgOperand(0), Builder.getInt64(-1));
EXPECT_EQ(Start2->getArgOperand(0), Builder.getInt64(-1)); EXPECT_EQ(Start2->getArgOperand(0), Builder.getInt64(-1));
EXPECT_EQ(Start3->getArgOperand(0), Builder.getInt64(100)); EXPECT_EQ(Start3->getArgOperand(0), Builder.getInt64(100));
EXPECT_EQ(Start1->getArgOperand(1), Var1); EXPECT_EQ(Start1->getArgOperand(1), Var1);
EXPECT_NE(Start2->getArgOperand(1), Var2); EXPECT_EQ(Start2->getArgOperand(1)->stripPointerCasts(), Var2);
EXPECT_EQ(Start3->getArgOperand(1), Var3); EXPECT_EQ(Start3->getArgOperand(1), Var3);
Value *End1 = Builder.CreateLifetimeEnd(Var1); Value *End1 = Builder.CreateLifetimeEnd(Var1);
Builder.CreateLifetimeEnd(Var2); Builder.CreateLifetimeEnd(Var2);
Builder.CreateLifetimeEnd(Var3); Builder.CreateLifetimeEnd(Var3);
IntrinsicInst *II_Start1 = dyn_cast<IntrinsicInst>(Start1); IntrinsicInst *II_Start1 = dyn_cast<IntrinsicInst>(Start1);
IntrinsicInst *II_End1 = dyn_cast<IntrinsicInst>(End1); IntrinsicInst *II_End1 = dyn_cast<IntrinsicInst>(End1);
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llvm/unittests/IR/PatternMatch.cpp

Show First 20 Lines • Show All 1,711 Lines • ▼ Show 20 LinesTEST_F(PatternMatchTest, VScale) {
Type *VecTy = ScalableVectorType::get(IRB.getInt8Ty(), 1); Type *VecTy = ScalableVectorType::get(IRB.getInt8Ty(), 1);
Type *VecPtrTy = VecTy->getPointerTo(); Type *VecPtrTy = VecTy->getPointerTo();
Value *NullPtrVec = Constant::getNullValue(VecPtrTy); Value *NullPtrVec = Constant::getNullValue(VecPtrTy);
Value *GEP = IRB.CreateGEP(VecTy, NullPtrVec, IRB.getInt64(1)); Value *GEP = IRB.CreateGEP(VecTy, NullPtrVec, IRB.getInt64(1));
Value *PtrToInt = IRB.CreatePtrToInt(GEP, DL.getIntPtrType(GEP->getType())); Value *PtrToInt = IRB.CreatePtrToInt(GEP, DL.getIntPtrType(GEP->getType()));
EXPECT_TRUE(match(PtrToInt, m_VScale(DL))); EXPECT_TRUE(match(PtrToInt, m_VScale(DL)));
// Prior to this patch, this case would cause assertion failures when attempting to match m_VScale // This used to cause assertion failures when attempting to match m_VScale.
// With opaque pointers the bitcast is no longer present.
Type *VecTy2 = ScalableVectorType::get(IRB.getInt8Ty(), 2); Type *VecTy2 = ScalableVectorType::get(IRB.getInt8Ty(), 2);
Value *NullPtrVec2 = Constant::getNullValue(VecTy2->getPointerTo()); Value *NullPtrVec2 = Constant::getNullValue(VecTy2->getPointerTo());
Value *BitCast = IRB.CreateBitCast(NullPtrVec2, VecPtrTy); Value *BitCast = IRB.CreateBitCast(NullPtrVec2, VecPtrTy);
Value *GEP2 = IRB.CreateGEP(VecTy, BitCast, IRB.getInt64(1)); Value *GEP2 = IRB.CreateGEP(VecTy, BitCast, IRB.getInt64(1));
Value *PtrToInt2 = Value *PtrToInt2 =
IRB.CreatePtrToInt(GEP2, DL.getIntPtrType(GEP2->getType())); IRB.CreatePtrToInt(GEP2, DL.getIntPtrType(GEP2->getType()));
EXPECT_FALSE(match(PtrToInt2, m_VScale(DL))); EXPECT_TRUE(match(PtrToInt2, m_VScale(DL)));
} }
TEST_F(PatternMatchTest, NotForbidUndef) { TEST_F(PatternMatchTest, NotForbidUndef) {
Type *ScalarTy = IRB.getInt8Ty(); Type *ScalarTy = IRB.getInt8Ty();
Type *VectorTy = FixedVectorType::get(ScalarTy, 3); Type *VectorTy = FixedVectorType::get(ScalarTy, 3);
Constant *ScalarUndef = UndefValue::get(ScalarTy); Constant *ScalarUndef = UndefValue::get(ScalarTy);
Constant *ScalarOnes = Constant::getAllOnesValue(ScalarTy); Constant *ScalarOnes = Constant::getAllOnesValue(ScalarTy);
Constant *VectorZero = Constant::getNullValue(VectorTy); Constant *VectorZero = Constant::getNullValue(VectorTy);
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llvm/unittests/IR/TypesTest.cpp

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 LinesTEST(TypesTest, CopyPointerType) {
PointerType *P1C = PointerType::getWithSamePointeeType(P1, 1); PointerType *P1C = PointerType::getWithSamePointeeType(P1, 1);
EXPECT_EQ(P1, P1C); EXPECT_EQ(P1, P1C);
EXPECT_TRUE(P1C->isOpaque()); EXPECT_TRUE(P1C->isOpaque());
PointerType *P1C0 = PointerType::getWithSamePointeeType(P1, 0); PointerType *P1C0 = PointerType::getWithSamePointeeType(P1, 0);
EXPECT_NE(P1, P1C0); EXPECT_NE(P1, P1C0);
EXPECT_TRUE(P1C0->isOpaque()); EXPECT_TRUE(P1C0->isOpaque());
LLVMContext CTypedPointers; LLVMContext CTypedPointers;
CTypedPointers.setOpaquePointers(false);
Type *Int8 = Type::getInt8Ty(CTypedPointers); Type *Int8 = Type::getInt8Ty(CTypedPointers);
PointerType *P2 = PointerType::get(Int8, 1); PointerType *P2 = PointerType::get(Int8, 1);
EXPECT_FALSE(P2->isOpaque()); EXPECT_FALSE(P2->isOpaque());
PointerType *P2C = PointerType::getWithSamePointeeType(P2, 1); PointerType *P2C = PointerType::getWithSamePointeeType(P2, 1);
EXPECT_EQ(P2, P2C); EXPECT_EQ(P2, P2C);
EXPECT_FALSE(P2C->isOpaque()); EXPECT_FALSE(P2C->isOpaque());
PointerType *P2C0 = PointerType::getWithSamePointeeType(P2, 0); PointerType *P2C0 = PointerType::getWithSamePointeeType(P2, 0);
EXPECT_NE(P2, P2C0); EXPECT_NE(P2, P2C0);
EXPECT_FALSE(P2C0->isOpaque()); EXPECT_FALSE(P2C0->isOpaque());
} }
} // end anonymous namespace } // end anonymous namespace

llvm/unittests/IR/ValueTest.cpp

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Lines = new GlobalVariable(*M,
"dummy_cast", "dummy_cast",
nullptr, nullptr,
GlobalVariable::NotThreadLocal, GlobalVariable::NotThreadLocal,
1); 1);
// Make sure the address space isn't dropped when returning this. // Make sure the address space isn't dropped when returning this.
Constant *DummyCast1 = M->getOrInsertGlobal("dummy_cast", Int8Ty); Constant *DummyCast1 = M->getOrInsertGlobal("dummy_cast", Int8Ty);
EXPECT_EQ(1u, DummyCast1->getType()->getPointerAddressSpace()); EXPECT_EQ(1u, DummyCast1->getType()->getPointerAddressSpace());
EXPECT_NE(DummyCast0, DummyCast1) << *DummyCast1;
} }
#ifdef GTEST_HAS_DEATH_TEST #ifdef GTEST_HAS_DEATH_TEST
#ifndef NDEBUG #ifndef NDEBUG
TEST(GlobalTest, AlignDeath) { TEST(GlobalTest, AlignDeath) {
LLVMContext Ctx; LLVMContext Ctx;
std::unique_ptr<Module> M(new Module("TestModule", Ctx)); std::unique_ptr<Module> M(new Module("TestModule", Ctx));
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines do { \
INST->printAsOperand(OS, TYPE, MST); \ INST->printAsOperand(OS, TYPE, MST); \
EXPECT_EQ(StringRef(STR), StringRef(OS.str())); \ EXPECT_EQ(StringRef(STR), StringRef(OS.str())); \
} \ } \
} while (false) } while (false)
CHECK_PRINT_AS_OPERAND(I0, false, "%0"); CHECK_PRINT_AS_OPERAND(I0, false, "%0");
CHECK_PRINT_AS_OPERAND(I1, false, "%1"); CHECK_PRINT_AS_OPERAND(I1, false, "%1");
CHECK_PRINT_AS_OPERAND(I0, true, "i32 %0"); CHECK_PRINT_AS_OPERAND(I0, true, "i32 %0");
CHECK_PRINT_AS_OPERAND(I1, true, "i32 %1"); CHECK_PRINT_AS_OPERAND(I1, true, "i32 %1");
CHECK_PRINT_AS_OPERAND(G0, true, "%0* @g0"); CHECK_PRINT_AS_OPERAND(G0, true, "ptr @g0");
CHECK_PRINT_AS_OPERAND(G1, true, "%1* @g1"); CHECK_PRINT_AS_OPERAND(G1, true, "ptr @g1");
#undef CHECK_PRINT_AS_OPERAND #undef CHECK_PRINT_AS_OPERAND
} }
TEST(ValueTest, getLocalSlots) { TEST(ValueTest, getLocalSlots) {
// Verify that the getLocalSlot method returns the correct slot numbers. // Verify that the getLocalSlot method returns the correct slot numbers.
LLVMContext C; LLVMContext C;
const char *ModuleString = "define void @f(i32 %x, i32 %y) {\n" const char *ModuleString = "define void @f(i32 %x, i32 %y) {\n"
"entry:\n" "entry:\n"
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llvm/unittests/IR/VerifierTest.cpp

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 LinesTEST(VerifierTest, CrossModuleRef) {
ReturnInst::Create(C, ConstZero, Entry1); ReturnInst::Create(C, ConstZero, Entry1);
ReturnInst::Create(C, ConstZero, Entry3); ReturnInst::Create(C, ConstZero, Entry3);
std::string Error; std::string Error;
raw_string_ostream ErrorOS(Error); raw_string_ostream ErrorOS(Error);
EXPECT_TRUE(verifyModule(M2, &ErrorOS)); EXPECT_TRUE(verifyModule(M2, &ErrorOS));
EXPECT_TRUE(StringRef(ErrorOS.str()) EXPECT_TRUE(StringRef(ErrorOS.str())
.equals("Global is referenced in a different module!\n" .equals("Global is referenced in a different module!\n"
"i32 ()* @foo2\n" "ptr @foo2\n"
"; ModuleID = 'M2'\n" "; ModuleID = 'M2'\n"
" %call = call i32 @foo2()\n" " %call = call i32 @foo2()\n"
"i32 ()* @foo1\n" "ptr @foo1\n"
"; ModuleID = 'M1'\n" "; ModuleID = 'M1'\n"
"Global is used by function in a different module\n" "Global is used by function in a different module\n"
"i32 ()* @foo2\n" "ptr @foo2\n"
"; ModuleID = 'M2'\n" "; ModuleID = 'M2'\n"
"i32 ()* @foo3\n" "ptr @foo3\n"
"; ModuleID = 'M3'\n")); "; ModuleID = 'M3'\n"));
Error.clear(); Error.clear();
EXPECT_TRUE(verifyModule(M1, &ErrorOS)); EXPECT_TRUE(verifyModule(M1, &ErrorOS));
EXPECT_TRUE(StringRef(ErrorOS.str()).equals( EXPECT_TRUE(StringRef(ErrorOS.str()).equals(
"Referencing function in another module!\n" "Referencing function in another module!\n"
" %call = call i32 @foo2()\n" " %call = call i32 @foo2()\n"
"; ModuleID = 'M1'\n" "; ModuleID = 'M1'\n"
"i32 ()* @foo2\n" "ptr @foo2\n"
"; ModuleID = 'M2'\n")); "; ModuleID = 'M2'\n"));
Error.clear(); Error.clear();
EXPECT_TRUE(verifyModule(M3, &ErrorOS)); EXPECT_TRUE(verifyModule(M3, &ErrorOS));
EXPECT_TRUE(StringRef(ErrorOS.str()).startswith( EXPECT_TRUE(StringRef(ErrorOS.str()).startswith(
"Referencing personality function in another module!")); "Referencing personality function in another module!"));
// Erase bad methods to avoid triggering an assertion failure on destruction // Erase bad methods to avoid triggering an assertion failure on destruction
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mlir/test/Target/LLVMIR/amx.mlir

// RUN: mlir-translate --mlir-to-llvmir %s | FileCheck %s // RUN: mlir-translate --mlir-to-llvmir %s | FileCheck %s
// CHECK-LABEL: define void @target(i8* %0) // CHECK-LABEL: define void @target(ptr %0)
// CHECK: %[[c:.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 16, i16 16) // CHECK: %[[c:.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 16, i16 16)
// CHECK: call void @llvm.x86.tilestored64.internal(i16 16, i16 16, i8* %0, i64 32, x86_amx %[[c]] // CHECK: call void @llvm.x86.tilestored64.internal(i16 16, i16 16, ptr %0, i64 32, x86_amx %[[c]]
llvm.func @target(%ptr: !llvm.ptr<i8>) { llvm.func @target(%ptr: !llvm.ptr<i8>) {
%c = llvm.mlir.constant(16 : i16) : i16 %c = llvm.mlir.constant(16 : i16) : i16
%s = llvm.mlir.constant(32 : i64) : i64 %s = llvm.mlir.constant(32 : i64) : i64
%0 = "amx.tilezero"(%c, %c) : (i16, i16) -> !llvm.array<16 x vector<16xbf16>> %0 = "amx.tilezero"(%c, %c) : (i16, i16) -> !llvm.array<16 x vector<16xbf16>>
"amx.tilestored64"(%c, %c, %ptr, %s, %0) : (i16, i16, !llvm.ptr<i8>, i64, !llvm.array<16 x vector<16xbf16>>) -> () "amx.tilestored64"(%c, %c, %ptr, %s, %0) : (i16, i16, !llvm.ptr<i8>, i64, !llvm.array<16 x vector<16xbf16>>) -> ()
llvm.return llvm.return
} }

mlir/test/Target/LLVMIR/arm-sve.mlir

Show First 20 Lines • Show All 236 Lines • ▼ Show 20 Linesllvm.func @memcopy(%arg0: !llvm.ptr<f32>, %arg1: !llvm.ptr<f32>,
%14 = "llvm.intr.vscale"() : () -> i64 %14 = "llvm.intr.vscale"() : () -> i64
// CHECK: mul i64 [[VL]], 4 // CHECK: mul i64 [[VL]], 4
%15 = llvm.mul %14, %13 : i64 %15 = llvm.mul %14, %13 : i64
llvm.br ^bb1(%12 : i64) llvm.br ^bb1(%12 : i64)
^bb1(%16: i64): ^bb1(%16: i64):
%17 = llvm.icmp "slt" %16, %arg10 : i64 %17 = llvm.icmp "slt" %16, %arg10 : i64
llvm.cond_br %17, ^bb2, ^bb3 llvm.cond_br %17, ^bb2, ^bb3
^bb2: ^bb2:
// CHECK: extractvalue { float*, float*, i64, [1 x i64], [1 x i64] } // CHECK: extractvalue { ptr, ptr, i64, [1 x i64], [1 x i64] }
%18 = llvm.extractvalue %5[1] : !llvm.struct<(ptr<f32>, ptr<f32>, i64, %18 = llvm.extractvalue %5[1] : !llvm.struct<(ptr<f32>, ptr<f32>, i64,
array<1 x i64>, array<1 x i64>,
array<1 x i64>)> array<1 x i64>)>
// CHECK: etelementptr float, float* // CHECK: getelementptr float, ptr
%19 = llvm.getelementptr %18[%16] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %19 = llvm.getelementptr %18[%16] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
// CHECK: bitcast float* %{{[0-9]+}} to <vscale x 4 x float>*
%20 = llvm.bitcast %19 : !llvm.ptr<f32> to !llvm.ptr<vector<[4]xf32>> %20 = llvm.bitcast %19 : !llvm.ptr<f32> to !llvm.ptr<vector<[4]xf32>>
// CHECK: load <vscale x 4 x float>, <vscale x 4 x float>* // CHECK: load <vscale x 4 x float>, ptr
%21 = llvm.load %20 : !llvm.ptr<vector<[4]xf32>> %21 = llvm.load %20 : !llvm.ptr<vector<[4]xf32>>
// CHECK: extractvalue { float*, float*, i64, [1 x i64], [1 x i64] } // CHECK: extractvalue { ptr, ptr, i64, [1 x i64], [1 x i64] }
%22 = llvm.extractvalue %11[1] : !llvm.struct<(ptr<f32>, ptr<f32>, i64, %22 = llvm.extractvalue %11[1] : !llvm.struct<(ptr<f32>, ptr<f32>, i64,
array<1 x i64>, array<1 x i64>,
array<1 x i64>)> array<1 x i64>)>
// CHECK: getelementptr float, float* %32 // CHECK: getelementptr float, ptr
%23 = llvm.getelementptr %22[%16] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %23 = llvm.getelementptr %22[%16] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
// CHECK: bitcast float* %33 to <vscale x 4 x float>*
%24 = llvm.bitcast %23 : !llvm.ptr<f32> to !llvm.ptr<vector<[4]xf32>> %24 = llvm.bitcast %23 : !llvm.ptr<f32> to !llvm.ptr<vector<[4]xf32>>
// CHECK: store <vscale x 4 x float> %{{[0-9]+}}, <vscale x 4 x float>* %{{[0-9]+}} // CHECK: store <vscale x 4 x float> %{{[0-9]+}}, ptr %{{[0-9]+}}
llvm.store %21, %24 : !llvm.ptr<vector<[4]xf32>> llvm.store %21, %24 : !llvm.ptr<vector<[4]xf32>>
%25 = llvm.add %16, %15 : i64 %25 = llvm.add %16, %15 : i64
llvm.br ^bb1(%25 : i64) llvm.br ^bb1(%25 : i64)
^bb3: ^bb3:
llvm.return llvm.return
} }
// CHECK-LABEL: define i64 @get_vector_scale() // CHECK-LABEL: define i64 @get_vector_scale()
llvm.func @get_vector_scale() -> i64 { llvm.func @get_vector_scale() -> i64 {
// CHECK: call i64 @llvm.vscale.i64() // CHECK: call i64 @llvm.vscale.i64()
%0 = "llvm.intr.vscale"() : () -> i64 %0 = "llvm.intr.vscale"() : () -> i64
llvm.return %0 : i64 llvm.return %0 : i64
} }

mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir

// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s // RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s
// CHECK-LABEL: @intrinsics // CHECK-LABEL: @intrinsics
llvm.func @intrinsics(%arg0: f32, %arg1: f32, %arg2: vector<8xf32>, %arg3: !llvm.ptr<i8>) { llvm.func @intrinsics(%arg0: f32, %arg1: f32, %arg2: vector<8xf32>, %arg3: !llvm.ptr<i8>) {
%c3 = llvm.mlir.constant(3 : i32) : i32 %c3 = llvm.mlir.constant(3 : i32) : i32
%c1 = llvm.mlir.constant(1 : i32) : i32 %c1 = llvm.mlir.constant(1 : i32) : i32
%c0 = llvm.mlir.constant(0 : i32) : i32 %c0 = llvm.mlir.constant(0 : i32) : i32
// CHECK: call float @llvm.fmuladd.f32 // CHECK: call float @llvm.fmuladd.f32
"llvm.intr.fmuladd"(%arg0, %arg1, %arg0) : (f32, f32, f32) -> f32 "llvm.intr.fmuladd"(%arg0, %arg1, %arg0) : (f32, f32, f32) -> f32
// CHECK: call <8 x float> @llvm.fmuladd.v8f32 // CHECK: call <8 x float> @llvm.fmuladd.v8f32
"llvm.intr.fmuladd"(%arg2, %arg2, %arg2) : (vector<8xf32>, vector<8xf32>, vector<8xf32>) -> vector<8xf32> "llvm.intr.fmuladd"(%arg2, %arg2, %arg2) : (vector<8xf32>, vector<8xf32>, vector<8xf32>) -> vector<8xf32>
// CHECK: call float @llvm.fma.f32 // CHECK: call float @llvm.fma.f32
"llvm.intr.fma"(%arg0, %arg1, %arg0) : (f32, f32, f32) -> f32 "llvm.intr.fma"(%arg0, %arg1, %arg0) : (f32, f32, f32) -> f32
// CHECK: call <8 x float> @llvm.fma.v8f32 // CHECK: call <8 x float> @llvm.fma.v8f32
"llvm.intr.fma"(%arg2, %arg2, %arg2) : (vector<8xf32>, vector<8xf32>, vector<8xf32>) -> vector<8xf32> "llvm.intr.fma"(%arg2, %arg2, %arg2) : (vector<8xf32>, vector<8xf32>, vector<8xf32>) -> vector<8xf32>
// CHECK: call void @llvm.prefetch.p0i8(i8* %3, i32 0, i32 3, i32 1) // CHECK: call void @llvm.prefetch.p0(ptr %3, i32 0, i32 3, i32 1)
"llvm.intr.prefetch"(%arg3, %c0, %c3, %c1) : (!llvm.ptr<i8>, i32, i32, i32) -> () "llvm.intr.prefetch"(%arg3, %c0, %c3, %c1) : (!llvm.ptr<i8>, i32, i32, i32) -> ()
llvm.return llvm.return
} }
// CHECK-LABEL: @exp_test // CHECK-LABEL: @exp_test
llvm.func @exp_test(%arg0: f32, %arg1: vector<8xf32>) { llvm.func @exp_test(%arg0: f32, %arg1: vector<8xf32>) {
// CHECK: call float @llvm.exp.f32 // CHECK: call float @llvm.exp.f32
"llvm.intr.exp"(%arg0) : (f32) -> f32 "llvm.intr.exp"(%arg0) : (f32) -> f32
▲ Show 20 Lines • Show All 252 Lines • ▼ Show 20 Linesllvm.func @matrix_intrinsics(%A: vector<64 x f32>, %B: vector<48 x f32>,
%ptr: !llvm.ptr<f32>, %stride: i64) { %ptr: !llvm.ptr<f32>, %stride: i64) {
// CHECK: call <12 x float> @llvm.matrix.multiply.v12f32.v64f32.v48f32(<64 x float> %0, <48 x float> %1, i32 4, i32 16, i32 3) // CHECK: call <12 x float> @llvm.matrix.multiply.v12f32.v64f32.v48f32(<64 x float> %0, <48 x float> %1, i32 4, i32 16, i32 3)
%C = llvm.intr.matrix.multiply %A, %B %C = llvm.intr.matrix.multiply %A, %B
{ lhs_rows = 4: i32, lhs_columns = 16: i32 , rhs_columns = 3: i32} : { lhs_rows = 4: i32, lhs_columns = 16: i32 , rhs_columns = 3: i32} :
(vector<64 x f32>, vector<48 x f32>) -> vector<12 x f32> (vector<64 x f32>, vector<48 x f32>) -> vector<12 x f32>
// CHECK: call <48 x float> @llvm.matrix.transpose.v48f32(<48 x float> %1, i32 3, i32 16) // CHECK: call <48 x float> @llvm.matrix.transpose.v48f32(<48 x float> %1, i32 3, i32 16)
%D = llvm.intr.matrix.transpose %B { rows = 3: i32, columns = 16: i32} : %D = llvm.intr.matrix.transpose %B { rows = 3: i32, columns = 16: i32} :
vector<48 x f32> into vector<48 x f32> vector<48 x f32> into vector<48 x f32>
// CHECK: call <48 x float> @llvm.matrix.column.major.load.v48f32.i64(float* align 4 %2, i64 %3, i1 false, i32 3, i32 16) // CHECK: call <48 x float> @llvm.matrix.column.major.load.v48f32.i64(ptr align 4 %2, i64 %3, i1 false, i32 3, i32 16)
%E = llvm.intr.matrix.column.major.load %ptr, <stride=%stride> %E = llvm.intr.matrix.column.major.load %ptr, <stride=%stride>
{ isVolatile = 0: i1, rows = 3: i32, columns = 16: i32} : { isVolatile = 0: i1, rows = 3: i32, columns = 16: i32} :
vector<48 x f32> from !llvm.ptr<f32> stride i64 vector<48 x f32> from !llvm.ptr<f32> stride i64
// CHECK: call void @llvm.matrix.column.major.store.v48f32.i64(<48 x float> %7, float* align 4 %2, i64 %3, i1 false, i32 3, i32 16) // CHECK: call void @llvm.matrix.column.major.store.v48f32.i64(<48 x float> %7, ptr align 4 %2, i64 %3, i1 false, i32 3, i32 16)
llvm.intr.matrix.column.major.store %E, %ptr, <stride=%stride> llvm.intr.matrix.column.major.store %E, %ptr, <stride=%stride>
{ isVolatile = 0: i1, rows = 3: i32, columns = 16: i32} : { isVolatile = 0: i1, rows = 3: i32, columns = 16: i32} :
vector<48 x f32> to !llvm.ptr<f32> stride i64 vector<48 x f32> to !llvm.ptr<f32> stride i64
llvm.return llvm.return
} }
// CHECK-LABEL: @get_active_lane_mask // CHECK-LABEL: @get_active_lane_mask
llvm.func @get_active_lane_mask(%base: i64, %n: i64) -> (vector<7xi1>) { llvm.func @get_active_lane_mask(%base: i64, %n: i64) -> (vector<7xi1>) {
// CHECK: call <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64 %0, i64 %1) // CHECK: call <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64 %0, i64 %1)
%0 = llvm.intr.get.active.lane.mask %base, %n : i64, i64 to vector<7xi1> %0 = llvm.intr.get.active.lane.mask %base, %n : i64, i64 to vector<7xi1>
llvm.return %0 : vector<7xi1> llvm.return %0 : vector<7xi1>
} }
// CHECK-LABEL: @masked_load_store_intrinsics // CHECK-LABEL: @masked_load_store_intrinsics
llvm.func @masked_load_store_intrinsics(%A: !llvm.ptr<vector<7xf32>>, %mask: vector<7xi1>) { llvm.func @masked_load_store_intrinsics(%A: !llvm.ptr<vector<7xf32>>, %mask: vector<7xi1>) {
// CHECK: call <7 x float> @llvm.masked.load.v7f32.p0v7f32(<7 x float>* %{{.*}}, i32 1, <7 x i1> %{{.*}}, <7 x float> undef) // CHECK: call <7 x float> @llvm.masked.load.v7f32.p0(ptr %{{.*}}, i32 1, <7 x i1> %{{.*}}, <7 x float> undef)
%a = llvm.intr.masked.load %A, %mask { alignment = 1: i32} : %a = llvm.intr.masked.load %A, %mask { alignment = 1: i32} :
(!llvm.ptr<vector<7xf32>>, vector<7xi1>) -> vector<7xf32> (!llvm.ptr<vector<7xf32>>, vector<7xi1>) -> vector<7xf32>
// CHECK: call <7 x float> @llvm.masked.load.v7f32.p0v7f32(<7 x float>* %{{.*}}, i32 1, <7 x i1> %{{.*}}, <7 x float> %{{.*}}) // CHECK: call <7 x float> @llvm.masked.load.v7f32.p0(ptr %{{.*}}, i32 1, <7 x i1> %{{.*}}, <7 x float> %{{.*}})
%b = llvm.intr.masked.load %A, %mask, %a { alignment = 1: i32} : %b = llvm.intr.masked.load %A, %mask, %a { alignment = 1: i32} :
(!llvm.ptr<vector<7xf32>>, vector<7xi1>, vector<7xf32>) -> vector<7xf32> (!llvm.ptr<vector<7xf32>>, vector<7xi1>, vector<7xf32>) -> vector<7xf32>
// CHECK: call void @llvm.masked.store.v7f32.p0v7f32(<7 x float> %{{.*}}, <7 x float>* %0, i32 {{.*}}, <7 x i1> %{{.*}}) // CHECK: call void @llvm.masked.store.v7f32.p0(<7 x float> %{{.*}}, ptr %0, i32 {{.*}}, <7 x i1> %{{.*}})
llvm.intr.masked.store %b, %A, %mask { alignment = 1: i32} : llvm.intr.masked.store %b, %A, %mask { alignment = 1: i32} :
vector<7xf32>, vector<7xi1> into !llvm.ptr<vector<7xf32>> vector<7xf32>, vector<7xi1> into !llvm.ptr<vector<7xf32>>
llvm.return llvm.return
} }
// CHECK-LABEL: @masked_gather_scatter_intrinsics // CHECK-LABEL: @masked_gather_scatter_intrinsics
llvm.func @masked_gather_scatter_intrinsics(%M: !llvm.vec<7 x ptr<f32>>, %mask: vector<7xi1>) { llvm.func @masked_gather_scatter_intrinsics(%M: !llvm.vec<7 x ptr<f32>>, %mask: vector<7xi1>) {
// CHECK: call <7 x float> @llvm.masked.gather.v7f32.v7p0f32(<7 x float*> %{{.*}}, i32 1, <7 x i1> %{{.*}}, <7 x float> undef) // CHECK: call <7 x float> @llvm.masked.gather.v7f32.v7p0(<7 x ptr> %{{.*}}, i32 1, <7 x i1> %{{.*}}, <7 x float> undef)
%a = llvm.intr.masked.gather %M, %mask { alignment = 1: i32} : %a = llvm.intr.masked.gather %M, %mask { alignment = 1: i32} :
(!llvm.vec<7 x ptr<f32>>, vector<7xi1>) -> vector<7xf32> (!llvm.vec<7 x ptr<f32>>, vector<7xi1>) -> vector<7xf32>
// CHECK: call <7 x float> @llvm.masked.gather.v7f32.v7p0f32(<7 x float*> %{{.*}}, i32 1, <7 x i1> %{{.*}}, <7 x float> %{{.*}}) // CHECK: call <7 x float> @llvm.masked.gather.v7f32.v7p0(<7 x ptr> %{{.*}}, i32 1, <7 x i1> %{{.*}}, <7 x float> %{{.*}})
%b = llvm.intr.masked.gather %M, %mask, %a { alignment = 1: i32} : %b = llvm.intr.masked.gather %M, %mask, %a { alignment = 1: i32} :
(!llvm.vec<7 x ptr<f32>>, vector<7xi1>, vector<7xf32>) -> vector<7xf32> (!llvm.vec<7 x ptr<f32>>, vector<7xi1>, vector<7xf32>) -> vector<7xf32>
// CHECK: call void @llvm.masked.scatter.v7f32.v7p0f32(<7 x float> %{{.*}}, <7 x float*> %{{.*}}, i32 1, <7 x i1> %{{.*}}) // CHECK: call void @llvm.masked.scatter.v7f32.v7p0(<7 x float> %{{.*}}, <7 x ptr> %{{.*}}, i32 1, <7 x i1> %{{.*}})
llvm.intr.masked.scatter %b, %M, %mask { alignment = 1: i32} : llvm.intr.masked.scatter %b, %M, %mask { alignment = 1: i32} :
vector<7xf32>, vector<7xi1> into !llvm.vec<7 x ptr<f32>> vector<7xf32>, vector<7xi1> into !llvm.vec<7 x ptr<f32>>
llvm.return llvm.return
} }
// CHECK-LABEL: @masked_expand_compress_intrinsics // CHECK-LABEL: @masked_expand_compress_intrinsics
llvm.func @masked_expand_compress_intrinsics(%ptr: !llvm.ptr<f32>, %mask: vector<7xi1>, %passthru: vector<7xf32>) { llvm.func @masked_expand_compress_intrinsics(%ptr: !llvm.ptr<f32>, %mask: vector<7xi1>, %passthru: vector<7xf32>) {
// CHECK: call <7 x float> @llvm.masked.expandload.v7f32(float* %{{.*}}, <7 x i1> %{{.*}}, <7 x float> %{{.*}}) // CHECK: call <7 x float> @llvm.masked.expandload.v7f32(ptr %{{.*}}, <7 x i1> %{{.*}}, <7 x float> %{{.*}})
%0 = "llvm.intr.masked.expandload"(%ptr, %mask, %passthru) %0 = "llvm.intr.masked.expandload"(%ptr, %mask, %passthru)
: (!llvm.ptr<f32>, vector<7xi1>, vector<7xf32>) -> (vector<7xf32>) : (!llvm.ptr<f32>, vector<7xi1>, vector<7xf32>) -> (vector<7xf32>)
// CHECK: call void @llvm.masked.compressstore.v7f32(<7 x float> %{{.*}}, float* %{{.*}}, <7 x i1> %{{.*}}) // CHECK: call void @llvm.masked.compressstore.v7f32(<7 x float> %{{.*}}, ptr %{{.*}}, <7 x i1> %{{.*}})
"llvm.intr.masked.compressstore"(%0, %ptr, %mask) "llvm.intr.masked.compressstore"(%0, %ptr, %mask)
: (vector<7xf32>, !llvm.ptr<f32>, vector<7xi1>) -> () : (vector<7xf32>, !llvm.ptr<f32>, vector<7xi1>) -> ()
llvm.return llvm.return
} }
// CHECK-LABEL: @memcpy_test // CHECK-LABEL: @memcpy_test
llvm.func @memcpy_test(%arg0: i32, %arg2: !llvm.ptr<i8>, %arg3: !llvm.ptr<i8>) { llvm.func @memcpy_test(%arg0: i32, %arg2: !llvm.ptr<i8>, %arg3: !llvm.ptr<i8>) {
%i1 = llvm.mlir.constant(false) : i1 %i1 = llvm.mlir.constant(false) : i1
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %{{.*}}, i8* %{{.*}}, i32 %{{.*}}, i1 {{.*}}) // CHECK: call void @llvm.memcpy.p0.p0.i32(ptr %{{.*}}, ptr %{{.*}}, i32 %{{.*}}, i1 {{.*}})
"llvm.intr.memcpy"(%arg2, %arg3, %arg0, %i1) : (!llvm.ptr<i8>, !llvm.ptr<i8>, i32, i1) -> () "llvm.intr.memcpy"(%arg2, %arg3, %arg0, %i1) : (!llvm.ptr<i8>, !llvm.ptr<i8>, i32, i1) -> ()
%sz = llvm.mlir.constant(10: i64) : i64 %sz = llvm.mlir.constant(10: i64) : i64
// CHECK: call void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 10, i1 {{.*}}) // CHECK: call void @llvm.memcpy.inline.p0.p0.i64(ptr %{{.*}}, ptr %{{.*}}, i64 10, i1 {{.*}})
"llvm.intr.memcpy.inline"(%arg2, %arg3, %sz, %i1) : (!llvm.ptr<i8>, !llvm.ptr<i8>, i64, i1) -> () "llvm.intr.memcpy.inline"(%arg2, %arg3, %sz, %i1) : (!llvm.ptr<i8>, !llvm.ptr<i8>, i64, i1) -> ()
llvm.return llvm.return
} }
// CHECK-LABEL: @memmove_test // CHECK-LABEL: @memmove_test
llvm.func @memmove_test(%arg0: i32, %arg2: !llvm.ptr<i8>, %arg3: !llvm.ptr<i8>) { llvm.func @memmove_test(%arg0: i32, %arg2: !llvm.ptr<i8>, %arg3: !llvm.ptr<i8>) {
%i1 = llvm.mlir.constant(false) : i1 %i1 = llvm.mlir.constant(false) : i1
// CHECK: call void @llvm.memmove.p0i8.p0i8.i32(i8* %{{.*}}, i8* %{{.*}}, i32 %{{.*}}, i1 {{.*}}) // CHECK: call void @llvm.memmove.p0.p0.i32(ptr %{{.*}}, ptr %{{.*}}, i32 %{{.*}}, i1 {{.*}})
"llvm.intr.memmove"(%arg2, %arg3, %arg0, %i1) : (!llvm.ptr<i8>, !llvm.ptr<i8>, i32, i1) -> () "llvm.intr.memmove"(%arg2, %arg3, %arg0, %i1) : (!llvm.ptr<i8>, !llvm.ptr<i8>, i32, i1) -> ()
llvm.return llvm.return
} }
// CHECK-LABEL: @memset_test // CHECK-LABEL: @memset_test
llvm.func @memset_test(%arg0: i32, %arg2: !llvm.ptr<i8>, %arg3: i8) { llvm.func @memset_test(%arg0: i32, %arg2: !llvm.ptr<i8>, %arg3: i8) {
%i1 = llvm.mlir.constant(false) : i1 %i1 = llvm.mlir.constant(false) : i1
// CHECK: call void @llvm.memset.p0i8.i32(i8* %{{.*}}, i8 %{{.*}}, i32 %{{.*}}, i1 {{.*}}) // CHECK: call void @llvm.memset.p0.i32(ptr %{{.*}}, i8 %{{.*}}, i32 %{{.*}}, i1 {{.*}})
"llvm.intr.memset"(%arg2, %arg3, %arg0, %i1) : (!llvm.ptr<i8>, i8, i32, i1) -> () "llvm.intr.memset"(%arg2, %arg3, %arg0, %i1) : (!llvm.ptr<i8>, i8, i32, i1) -> ()
llvm.return llvm.return
} }
// CHECK-LABEL: @sadd_with_overflow_test // CHECK-LABEL: @sadd_with_overflow_test
llvm.func @sadd_with_overflow_test(%arg0: i32, %arg1: i32, %arg2: vector<8xi32>, %arg3: vector<8xi32>) { llvm.func @sadd_with_overflow_test(%arg0: i32, %arg1: i32, %arg2: vector<8xi32>, %arg3: vector<8xi32>) {
// CHECK: call { i32, i1 } @llvm.sadd.with.overflow.i32 // CHECK: call { i32, i1 } @llvm.sadd.with.overflow.i32
"llvm.intr.sadd.with.overflow"(%arg0, %arg1) : (i32, i32) -> !llvm.struct<(i32, i1)> "llvm.intr.sadd.with.overflow"(%arg0, %arg1) : (i32, i32) -> !llvm.struct<(i32, i1)>
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Linesllvm.func @coro_id(%arg0: i32, %arg1: !llvm.ptr<i8>) {
llvm.intr.coro.id %arg0, %arg1, %arg1, %null : !llvm.token llvm.intr.coro.id %arg0, %arg1, %arg1, %null : !llvm.token
llvm.return llvm.return
} }
// CHECK-LABEL: @coro_begin // CHECK-LABEL: @coro_begin
llvm.func @coro_begin(%arg0: i32, %arg1: !llvm.ptr<i8>) { llvm.func @coro_begin(%arg0: i32, %arg1: !llvm.ptr<i8>) {
%null = llvm.mlir.null : !llvm.ptr<i8> %null = llvm.mlir.null : !llvm.ptr<i8>
%token = llvm.intr.coro.id %arg0, %arg1, %arg1, %null : !llvm.token %token = llvm.intr.coro.id %arg0, %arg1, %arg1, %null : !llvm.token
// CHECK: call i8* @llvm.coro.begin // CHECK: call ptr @llvm.coro.begin
llvm.intr.coro.begin %token, %arg1 : !llvm.ptr<i8> llvm.intr.coro.begin %token, %arg1 : !llvm.ptr<i8>
llvm.return llvm.return
} }
// CHECK-LABEL: @coro_size // CHECK-LABEL: @coro_size
llvm.func @coro_size() { llvm.func @coro_size() {
// CHECK: call i64 @llvm.coro.size.i64 // CHECK: call i64 @llvm.coro.size.i64
%0 = llvm.intr.coro.size : i64 %0 = llvm.intr.coro.size : i64
Show All 33 Linesllvm.func @coro_end(%arg0: !llvm.ptr<i8>, %arg1 : i1) {
%0 = llvm.intr.coro.end %arg0, %arg1 : i1 %0 = llvm.intr.coro.end %arg0, %arg1 : i1
llvm.return llvm.return
} }
// CHECK-LABEL: @coro_free // CHECK-LABEL: @coro_free
llvm.func @coro_free(%arg0: i32, %arg1 : !llvm.ptr<i8>) { llvm.func @coro_free(%arg0: i32, %arg1 : !llvm.ptr<i8>) {
%null = llvm.mlir.null : !llvm.ptr<i8> %null = llvm.mlir.null : !llvm.ptr<i8>
%token = llvm.intr.coro.id %arg0, %arg1, %arg1, %null : !llvm.token %token = llvm.intr.coro.id %arg0, %arg1, %arg1, %null : !llvm.token
// CHECK: call i8* @llvm.coro.free // CHECK: call ptr @llvm.coro.free
%0 = llvm.intr.coro.free %token, %arg1 : !llvm.ptr<i8> %0 = llvm.intr.coro.free %token, %arg1 : !llvm.ptr<i8>
llvm.return llvm.return
} }
// CHECK-LABEL: @coro_resume // CHECK-LABEL: @coro_resume
llvm.func @coro_resume(%arg0: !llvm.ptr<i8>) { llvm.func @coro_resume(%arg0: !llvm.ptr<i8>) {
// CHECK: call void @llvm.coro.resume // CHECK: call void @llvm.coro.resume
llvm.intr.coro.resume %arg0 llvm.intr.coro.resume %arg0
llvm.return llvm.return
} }
// CHECK-LABEL: @eh_typeid_for // CHECK-LABEL: @eh_typeid_for
llvm.func @eh_typeid_for(%arg0 : !llvm.ptr<i8>) { llvm.func @eh_typeid_for(%arg0 : !llvm.ptr<i8>) {
// CHECK: call i32 @llvm.eh.typeid.for // CHECK: call i32 @llvm.eh.typeid.for
%0 = llvm.intr.eh.typeid.for %arg0 : i32 %0 = llvm.intr.eh.typeid.for %arg0 : i32
llvm.return llvm.return
} }
// CHECK-LABEL: @stack_save // CHECK-LABEL: @stack_save
llvm.func @stack_save() { llvm.func @stack_save() {
// CHECK: call i8* @llvm.stacksave // CHECK: call ptr @llvm.stacksave
%0 = llvm.intr.stacksave : !llvm.ptr<i8> %0 = llvm.intr.stacksave : !llvm.ptr<i8>
llvm.return llvm.return
} }
// CHECK-LABEL: @stack_restore // CHECK-LABEL: @stack_restore
llvm.func @stack_restore(%arg0: !llvm.ptr<i8>) { llvm.func @stack_restore(%arg0: !llvm.ptr<i8>) {
// CHECK: call void @llvm.stackrestore // CHECK: call void @llvm.stackrestore
llvm.intr.stackrestore %arg0 llvm.intr.stackrestore %arg0
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Linesllvm.func @vector_predication_intrinsics(%A: vector<8xi32>, %B: vector<8xi32>,
// CHECK: call <8 x i32> @llvm.vp.select.v8i32 // CHECK: call <8 x i32> @llvm.vp.select.v8i32
"llvm.intr.vp.select" (%mask, %A, %B, %evl) : "llvm.intr.vp.select" (%mask, %A, %B, %evl) :
(vector<8xi1>, vector<8xi32>, vector<8xi32>, i32) -> vector<8xi32> (vector<8xi1>, vector<8xi32>, vector<8xi32>, i32) -> vector<8xi32>
// CHECK: call <8 x i32> @llvm.vp.merge.v8i32 // CHECK: call <8 x i32> @llvm.vp.merge.v8i32
"llvm.intr.vp.merge" (%mask, %A, %B, %evl) : "llvm.intr.vp.merge" (%mask, %A, %B, %evl) :
(vector<8xi1>, vector<8xi32>, vector<8xi32>, i32) -> vector<8xi32> (vector<8xi1>, vector<8xi32>, vector<8xi32>, i32) -> vector<8xi32>
// CHECK: call void @llvm.vp.store.v8i32.p0i32 // CHECK: call void @llvm.vp.store.v8i32.p0
"llvm.intr.vp.store" (%A, %iptr, %mask, %evl) : "llvm.intr.vp.store" (%A, %iptr, %mask, %evl) :
(vector<8xi32>, !llvm.ptr<i32>, vector<8xi1>, i32) -> () (vector<8xi32>, !llvm.ptr<i32>, vector<8xi1>, i32) -> ()
// CHECK: call <8 x i32> @llvm.vp.load.v8i32.p0i32 // CHECK: call <8 x i32> @llvm.vp.load.v8i32.p0
"llvm.intr.vp.load" (%iptr, %mask, %evl) : "llvm.intr.vp.load" (%iptr, %mask, %evl) :
(!llvm.ptr<i32>, vector<8xi1>, i32) -> vector<8xi32> (!llvm.ptr<i32>, vector<8xi1>, i32) -> vector<8xi32>
// CHECK: call void @llvm.experimental.vp.strided.store.v8i32.p0i32.i32 // CHECK: call void @llvm.experimental.vp.strided.store.v8i32.p0.i32
"llvm.intr.experimental.vp.strided.store" (%A, %iptr, %i, %mask, %evl) : "llvm.intr.experimental.vp.strided.store" (%A, %iptr, %i, %mask, %evl) :
(vector<8xi32>, !llvm.ptr<i32>, i32, vector<8xi1>, i32) -> () (vector<8xi32>, !llvm.ptr<i32>, i32, vector<8xi1>, i32) -> ()
// CHECK: call <8 x i32> @llvm.experimental.vp.strided.load.v8i32.p0i32.i32 // CHECK: call <8 x i32> @llvm.experimental.vp.strided.load.v8i32.p0.i32
"llvm.intr.experimental.vp.strided.load" (%iptr, %i, %mask, %evl) : "llvm.intr.experimental.vp.strided.load" (%iptr, %i, %mask, %evl) :
(!llvm.ptr<i32>, i32, vector<8xi1>, i32) -> vector<8xi32> (!llvm.ptr<i32>, i32, vector<8xi1>, i32) -> vector<8xi32>
// CHECK: call <8 x i32> @llvm.vp.trunc.v8i32.v8i64 // CHECK: call <8 x i32> @llvm.vp.trunc.v8i32.v8i64
"llvm.intr.vp.trunc" (%E, %mask, %evl) : "llvm.intr.vp.trunc" (%E, %mask, %evl) :
(vector<8xi64>, vector<8xi1>, i32) -> vector<8xi32> (vector<8xi64>, vector<8xi1>, i32) -> vector<8xi32>
// CHECK: call <8 x i64> @llvm.vp.zext.v8i64.v8i32 // CHECK: call <8 x i64> @llvm.vp.zext.v8i64.v8i32
"llvm.intr.vp.zext" (%A, %mask, %evl) : "llvm.intr.vp.zext" (%A, %mask, %evl) :
Show All 11 Linesllvm.func @vector_predication_intrinsics(%A: vector<8xi32>, %B: vector<8xi32>,
// CHECK: call <8 x i64> @llvm.vp.fptoui.v8i64.v8f64 // CHECK: call <8 x i64> @llvm.vp.fptoui.v8i64.v8f64
"llvm.intr.vp.fptoui" (%F, %mask, %evl) : "llvm.intr.vp.fptoui" (%F, %mask, %evl) :
(vector<8xf64>, vector<8xi1>, i32) -> vector<8xi64> (vector<8xf64>, vector<8xi1>, i32) -> vector<8xi64>
// CHECK: call <8 x i64> @llvm.vp.fptosi.v8i64.v8f64 // CHECK: call <8 x i64> @llvm.vp.fptosi.v8i64.v8f64
"llvm.intr.vp.fptosi" (%F, %mask, %evl) : "llvm.intr.vp.fptosi" (%F, %mask, %evl) :
(vector<8xf64>, vector<8xi1>, i32) -> vector<8xi64> (vector<8xf64>, vector<8xi1>, i32) -> vector<8xi64>
// CHECK: call <8 x i64> @llvm.vp.ptrtoint.v8i64.v8p0i32 // CHECK: call <8 x i64> @llvm.vp.ptrtoint.v8i64.v8p0
"llvm.intr.vp.ptrtoint" (%G, %mask, %evl) : "llvm.intr.vp.ptrtoint" (%G, %mask, %evl) :
(!llvm.vec<8 x !llvm.ptr<i32>>, vector<8xi1>, i32) -> vector<8xi64> (!llvm.vec<8 x !llvm.ptr<i32>>, vector<8xi1>, i32) -> vector<8xi64>
// CHECK: call <8 x i32*> @llvm.vp.inttoptr.v8p0i32.v8i64 // CHECK: call <8 x ptr> @llvm.vp.inttoptr.v8p0.v8i64
"llvm.intr.vp.inttoptr" (%E, %mask, %evl) : "llvm.intr.vp.inttoptr" (%E, %mask, %evl) :
(vector<8xi64>, vector<8xi1>, i32) -> !llvm.vec<8 x !llvm.ptr<i32>> (vector<8xi64>, vector<8xi1>, i32) -> !llvm.vec<8 x !llvm.ptr<i32>>
llvm.return llvm.return
} }
// Check that intrinsics are declared with appropriate types. // Check that intrinsics are declared with appropriate types.
// CHECK-DAG: declare float @llvm.fma.f32(float, float, float) // CHECK-DAG: declare float @llvm.fma.f32(float, float, float)
// CHECK-DAG: declare <8 x float> @llvm.fma.v8f32(<8 x float>, <8 x float>, <8 x float>) #0 // CHECK-DAG: declare <8 x float> @llvm.fma.v8f32(<8 x float>, <8 x float>, <8 x float>) #0
// CHECK-DAG: declare float @llvm.fmuladd.f32(float, float, float) // CHECK-DAG: declare float @llvm.fmuladd.f32(float, float, float)
// CHECK-DAG: declare <8 x float> @llvm.fmuladd.v8f32(<8 x float>, <8 x float>, <8 x float>) #0 // CHECK-DAG: declare <8 x float> @llvm.fmuladd.v8f32(<8 x float>, <8 x float>, <8 x float>) #0
// CHECK-DAG: declare void @llvm.prefetch.p0i8(i8* nocapture readonly, i32 immarg, i32 immarg, i32) // CHECK-DAG: declare void @llvm.prefetch.p0(ptr nocapture readonly, i32 immarg, i32 immarg, i32)
// CHECK-DAG: declare float @llvm.exp.f32(float) // CHECK-DAG: declare float @llvm.exp.f32(float)
// CHECK-DAG: declare <8 x float> @llvm.exp.v8f32(<8 x float>) #0 // CHECK-DAG: declare <8 x float> @llvm.exp.v8f32(<8 x float>) #0
// CHECK-DAG: declare float @llvm.log.f32(float) // CHECK-DAG: declare float @llvm.log.f32(float)
// CHECK-DAG: declare <8 x float> @llvm.log.v8f32(<8 x float>) #0 // CHECK-DAG: declare <8 x float> @llvm.log.v8f32(<8 x float>) #0
// CHECK-DAG: declare float @llvm.log10.f32(float) // CHECK-DAG: declare float @llvm.log10.f32(float)
// CHECK-DAG: declare <8 x float> @llvm.log10.v8f32(<8 x float>) #0 // CHECK-DAG: declare <8 x float> @llvm.log10.v8f32(<8 x float>) #0
// CHECK-DAG: declare float @llvm.log2.f32(float) // CHECK-DAG: declare float @llvm.log2.f32(float)
// CHECK-DAG: declare <8 x float> @llvm.log2.v8f32(<8 x float>) #0 // CHECK-DAG: declare <8 x float> @llvm.log2.v8f32(<8 x float>) #0
// CHECK-DAG: declare float @llvm.fabs.f32(float) // CHECK-DAG: declare float @llvm.fabs.f32(float)
// CHECK-DAG: declare <8 x float> @llvm.fabs.v8f32(<8 x float>) #0 // CHECK-DAG: declare <8 x float> @llvm.fabs.v8f32(<8 x float>) #0
// CHECK-DAG: declare float @llvm.sqrt.f32(float) // CHECK-DAG: declare float @llvm.sqrt.f32(float)
// CHECK-DAG: declare <8 x float> @llvm.sqrt.v8f32(<8 x float>) #0 // CHECK-DAG: declare <8 x float> @llvm.sqrt.v8f32(<8 x float>) #0
// CHECK-DAG: declare float @llvm.ceil.f32(float) // CHECK-DAG: declare float @llvm.ceil.f32(float)
// CHECK-DAG: declare <8 x float> @llvm.ceil.v8f32(<8 x float>) #0 // CHECK-DAG: declare <8 x float> @llvm.ceil.v8f32(<8 x float>) #0
// CHECK-DAG: declare float @llvm.cos.f32(float) // CHECK-DAG: declare float @llvm.cos.f32(float)
// CHECK-DAG: declare <8 x float> @llvm.cos.v8f32(<8 x float>) #0 // CHECK-DAG: declare <8 x float> @llvm.cos.v8f32(<8 x float>) #0
// CHECK-DAG: declare float @llvm.copysign.f32(float, float) // CHECK-DAG: declare float @llvm.copysign.f32(float, float)
// CHECK-DAG: declare <12 x float> @llvm.matrix.multiply.v12f32.v64f32.v48f32(<64 x float>, <48 x float>, i32 immarg, i32 immarg, i32 immarg) // CHECK-DAG: declare <12 x float> @llvm.matrix.multiply.v12f32.v64f32.v48f32(<64 x float>, <48 x float>, i32 immarg, i32 immarg, i32 immarg)
// CHECK-DAG: declare <48 x float> @llvm.matrix.transpose.v48f32(<48 x float>, i32 immarg, i32 immarg) // CHECK-DAG: declare <48 x float> @llvm.matrix.transpose.v48f32(<48 x float>, i32 immarg, i32 immarg)
// CHECK-DAG: declare <48 x float> @llvm.matrix.column.major.load.v48f32.i64(float* nocapture, i64, i1 immarg, i32 immarg, i32 immarg) // CHECK-DAG: declare <48 x float> @llvm.matrix.column.major.load.v48f32.i64(ptr nocapture, i64, i1 immarg, i32 immarg, i32 immarg)
// CHECK-DAG: declare void @llvm.matrix.column.major.store.v48f32.i64(<48 x float>, float* nocapture writeonly, i64, i1 immarg, i32 immarg, i32 immarg) // CHECK-DAG: declare void @llvm.matrix.column.major.store.v48f32.i64(<48 x float>, ptr nocapture writeonly, i64, i1 immarg, i32 immarg, i32 immarg)
// CHECK-DAG: declare <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64, i64) // CHECK-DAG: declare <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64, i64)
// CHECK-DAG: declare <7 x float> @llvm.masked.load.v7f32.p0v7f32(<7 x float>*, i32 immarg, <7 x i1>, <7 x float>) // CHECK-DAG: declare <7 x float> @llvm.masked.load.v7f32.p0(ptr, i32 immarg, <7 x i1>, <7 x float>)
// CHECK-DAG: declare void @llvm.masked.store.v7f32.p0v7f32(<7 x float>, <7 x float>*, i32 immarg, <7 x i1>) // CHECK-DAG: declare void @llvm.masked.store.v7f32.p0(<7 x float>, ptr, i32 immarg, <7 x i1>)
// CHECK-DAG: declare <7 x float> @llvm.masked.gather.v7f32.v7p0f32(<7 x float*>, i32 immarg, <7 x i1>, <7 x float>) // CHECK-DAG: declare <7 x float> @llvm.masked.gather.v7f32.v7p0(<7 x ptr>, i32 immarg, <7 x i1>, <7 x float>)
// CHECK-DAG: declare void @llvm.masked.scatter.v7f32.v7p0f32(<7 x float>, <7 x float*>, i32 immarg, <7 x i1>) // CHECK-DAG: declare void @llvm.masked.scatter.v7f32.v7p0(<7 x float>, <7 x ptr>, i32 immarg, <7 x i1>)
// CHECK-DAG: declare <7 x float> @llvm.masked.expandload.v7f32(float*, <7 x i1>, <7 x float>) // CHECK-DAG: declare <7 x float> @llvm.masked.expandload.v7f32(ptr, <7 x i1>, <7 x float>)
// CHECK-DAG: declare void @llvm.masked.compressstore.v7f32(<7 x float>, float*, <7 x i1>) // CHECK-DAG: declare void @llvm.masked.compressstore.v7f32(<7 x float>, ptr, <7 x i1>)
// CHECK-DAG: declare void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i32, i1 immarg) // CHECK-DAG: declare void @llvm.memcpy.p0.p0.i32(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i32, i1 immarg)
// CHECK-DAG: declare void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64 immarg, i1 immarg) // CHECK-DAG: declare void @llvm.memcpy.inline.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64 immarg, i1 immarg)
// CHECK-DAG: declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) // CHECK-DAG: declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32)
// CHECK-DAG: declare { <8 x i32>, <8 x i1> } @llvm.sadd.with.overflow.v8i32(<8 x i32>, <8 x i32>) #0 // CHECK-DAG: declare { <8 x i32>, <8 x i1> } @llvm.sadd.with.overflow.v8i32(<8 x i32>, <8 x i32>) #0
// CHECK-DAG: declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) // CHECK-DAG: declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
// CHECK-DAG: declare { <8 x i32>, <8 x i1> } @llvm.uadd.with.overflow.v8i32(<8 x i32>, <8 x i32>) #0 // CHECK-DAG: declare { <8 x i32>, <8 x i1> } @llvm.uadd.with.overflow.v8i32(<8 x i32>, <8 x i32>) #0
// CHECK-DAG: declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) // CHECK-DAG: declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32)
// CHECK-DAG: declare { <8 x i32>, <8 x i1> } @llvm.ssub.with.overflow.v8i32(<8 x i32>, <8 x i32>) #0 // CHECK-DAG: declare { <8 x i32>, <8 x i1> } @llvm.ssub.with.overflow.v8i32(<8 x i32>, <8 x i32>) #0
// CHECK-DAG: declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) // CHECK-DAG: declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32)
// CHECK-DAG: declare { <8 x i32>, <8 x i1> } @llvm.usub.with.overflow.v8i32(<8 x i32>, <8 x i32>) #0 // CHECK-DAG: declare { <8 x i32>, <8 x i1> } @llvm.usub.with.overflow.v8i32(<8 x i32>, <8 x i32>) #0
// CHECK-DAG: declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32) // CHECK-DAG: declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
// CHECK-DAG: declare { <8 x i32>, <8 x i1> } @llvm.umul.with.overflow.v8i32(<8 x i32>, <8 x i32>) #0 // CHECK-DAG: declare { <8 x i32>, <8 x i1> } @llvm.umul.with.overflow.v8i32(<8 x i32>, <8 x i32>) #0
// CHECK-DAG: declare token @llvm.coro.id(i32, i8* readnone, i8* nocapture readonly, i8*) // CHECK-DAG: declare token @llvm.coro.id(i32, ptr readnone, ptr nocapture readonly, ptr)
// CHECK-DAG: declare i8* @llvm.coro.begin(token, i8* writeonly) // CHECK-DAG: declare ptr @llvm.coro.begin(token, ptr writeonly)
// CHECK-DAG: declare i64 @llvm.coro.size.i64() // CHECK-DAG: declare i64 @llvm.coro.size.i64()
// CHECK-DAG: declare i32 @llvm.coro.size.i32() // CHECK-DAG: declare i32 @llvm.coro.size.i32()
// CHECK-DAG: declare token @llvm.coro.save(i8*) // CHECK-DAG: declare token @llvm.coro.save(ptr)
// CHECK-DAG: declare i8 @llvm.coro.suspend(token, i1) // CHECK-DAG: declare i8 @llvm.coro.suspend(token, i1)
// CHECK-DAG: declare i1 @llvm.coro.end(i8*, i1) // CHECK-DAG: declare i1 @llvm.coro.end(ptr, i1)
// CHECK-DAG: declare i8* @llvm.coro.free(token, i8* nocapture readonly) // CHECK-DAG: declare ptr @llvm.coro.free(token, ptr nocapture readonly)
// CHECK-DAG: declare void @llvm.coro.resume(i8*) // CHECK-DAG: declare void @llvm.coro.resume(ptr)
// CHECK-DAG: declare <8 x i32> @llvm.vp.add.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x i32> @llvm.vp.add.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x i32> @llvm.vp.sub.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x i32> @llvm.vp.sub.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x i32> @llvm.vp.mul.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x i32> @llvm.vp.mul.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x i32> @llvm.vp.srem.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x i32> @llvm.vp.srem.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x i32> @llvm.vp.urem.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x i32> @llvm.vp.urem.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) #2
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// CHECK-DAG: declare i32 @llvm.vp.reduce.umax.v8i32(i32, <8 x i32>, <8 x i1>, i32) #2 // CHECK-DAG: declare i32 @llvm.vp.reduce.umax.v8i32(i32, <8 x i32>, <8 x i1>, i32) #2
// CHECK-DAG: declare i32 @llvm.vp.reduce.umin.v8i32(i32, <8 x i32>, <8 x i1>, i32) #2 // CHECK-DAG: declare i32 @llvm.vp.reduce.umin.v8i32(i32, <8 x i32>, <8 x i1>, i32) #2
// CHECK-DAG: declare float @llvm.vp.reduce.fadd.v8f32(float, <8 x float>, <8 x i1>, i32) #2 // CHECK-DAG: declare float @llvm.vp.reduce.fadd.v8f32(float, <8 x float>, <8 x i1>, i32) #2
// CHECK-DAG: declare float @llvm.vp.reduce.fmul.v8f32(float, <8 x float>, <8 x i1>, i32) #2 // CHECK-DAG: declare float @llvm.vp.reduce.fmul.v8f32(float, <8 x float>, <8 x i1>, i32) #2
// CHECK-DAG: declare float @llvm.vp.reduce.fmax.v8f32(float, <8 x float>, <8 x i1>, i32) #2 // CHECK-DAG: declare float @llvm.vp.reduce.fmax.v8f32(float, <8 x float>, <8 x i1>, i32) #2
// CHECK-DAG: declare float @llvm.vp.reduce.fmin.v8f32(float, <8 x float>, <8 x i1>, i32) #2 // CHECK-DAG: declare float @llvm.vp.reduce.fmin.v8f32(float, <8 x float>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x i32> @llvm.vp.select.v8i32(<8 x i1>, <8 x i32>, <8 x i32>, i32) #2 // CHECK-DAG: declare <8 x i32> @llvm.vp.select.v8i32(<8 x i1>, <8 x i32>, <8 x i32>, i32) #2
// CHECK-DAG: declare <8 x i32> @llvm.vp.merge.v8i32(<8 x i1>, <8 x i32>, <8 x i32>, i32) #2 // CHECK-DAG: declare <8 x i32> @llvm.vp.merge.v8i32(<8 x i1>, <8 x i32>, <8 x i32>, i32) #2
// CHECK-DAG: declare void @llvm.experimental.vp.strided.store.v8i32.p0i32.i32(<8 x i32>, i32* nocapture, i32, <8 x i1>, i32) #4 // CHECK-DAG: declare void @llvm.experimental.vp.strided.store.v8i32.p0.i32(<8 x i32>, ptr nocapture, i32, <8 x i1>, i32) #4
// CHECK-DAG: declare <8 x i32> @llvm.experimental.vp.strided.load.v8i32.p0i32.i32(i32* nocapture, i32, <8 x i1>, i32) #3 // CHECK-DAG: declare <8 x i32> @llvm.experimental.vp.strided.load.v8i32.p0.i32(ptr nocapture, i32, <8 x i1>, i32) #3
// CHECK-DAG: declare <8 x i32> @llvm.vp.trunc.v8i32.v8i64(<8 x i64>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x i32> @llvm.vp.trunc.v8i32.v8i64(<8 x i64>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x i64> @llvm.vp.zext.v8i64.v8i32(<8 x i32>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x i64> @llvm.vp.zext.v8i64.v8i32(<8 x i32>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x i64> @llvm.vp.sext.v8i64.v8i32(<8 x i32>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x i64> @llvm.vp.sext.v8i64.v8i32(<8 x i32>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x float> @llvm.vp.fptrunc.v8f32.v8f64(<8 x double>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x float> @llvm.vp.fptrunc.v8f32.v8f64(<8 x double>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x double> @llvm.vp.fpext.v8f64.v8f32(<8 x float>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x double> @llvm.vp.fpext.v8f64.v8f32(<8 x float>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x i64> @llvm.vp.fptoui.v8i64.v8f64(<8 x double>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x i64> @llvm.vp.fptoui.v8i64.v8f64(<8 x double>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x i64> @llvm.vp.fptosi.v8i64.v8f64(<8 x double>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x i64> @llvm.vp.fptosi.v8i64.v8f64(<8 x double>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x i64> @llvm.vp.ptrtoint.v8i64.v8p0i32(<8 x i32*>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x i64> @llvm.vp.ptrtoint.v8i64.v8p0(<8 x ptr>, <8 x i1>, i32) #2
// CHECK-DAG: declare <8 x i32*> @llvm.vp.inttoptr.v8p0i32.v8i64(<8 x i64>, <8 x i1>, i32) #2 // CHECK-DAG: declare <8 x ptr> @llvm.vp.inttoptr.v8p0.v8i64(<8 x i64>, <8 x i1>, i32) #2

mlir/test/Target/LLVMIR/llvmir-types.mlir

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// CHECK: declare i32 @f_i32_half_bfloat_float_double(half, bfloat, float, double) // CHECK: declare i32 @f_i32_half_bfloat_float_double(half, bfloat, float, double)
llvm.func @f_i32_half_bfloat_float_double(f16, bf16, f32, f64) -> i32 llvm.func @f_i32_half_bfloat_float_double(f16, bf16, f32, f64) -> i32
// CHECK: declare i32 @f_i32_i32_i32(i32, i32) // CHECK: declare i32 @f_i32_i32_i32(i32, i32)
llvm.func @f_i32_i32_i32(i32, i32) -> i32 llvm.func @f_i32_i32_i32(i32, i32) -> i32
// CHECK: declare void @f_void_variadic(...) // CHECK: declare void @f_void_variadic(...)
llvm.func @f_void_variadic(...) llvm.func @f_void_variadic(...)
// CHECK: declare void @f_void_i32_i32_variadic(i32, i32, ...) // CHECK: declare void @f_void_i32_i32_variadic(i32, i32, ...)
llvm.func @f_void_i32_i32_variadic(i32, i32, ...) llvm.func @f_void_i32_i32_variadic(i32, i32, ...)
// CHECK: declare i32 (i32)* @f_f_i32_i32() // CHECK: declare ptr @f_f_i32_i32()
llvm.func @f_f_i32_i32() -> !llvm.ptr<func<i32 (i32)>> llvm.func @f_f_i32_i32() -> !llvm.ptr<func<i32 (i32)>>
// //
// Integers. // Integers.
// //
// CHECK: declare i1 @return_i1() // CHECK: declare i1 @return_i1()
llvm.func @return_i1() -> i1 llvm.func @return_i1() -> i1
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llvm.func @return_i57() -> i57 llvm.func @return_i57() -> i57
// CHECK: declare i129 @return_i129() // CHECK: declare i129 @return_i129()
llvm.func @return_i129() -> i129 llvm.func @return_i129() -> i129
// //
// Pointers. // Pointers.
// //
// CHECK: declare i8* @return_pi8() // CHECK: declare ptr @return_pi8()
llvm.func @return_pi8() -> !llvm.ptr<i8> llvm.func @return_pi8() -> !llvm.ptr<i8>
// CHECK: declare float* @return_pfloat() // CHECK: declare ptr @return_pfloat()
llvm.func @return_pfloat() -> !llvm.ptr<f32> llvm.func @return_pfloat() -> !llvm.ptr<f32>
// CHECK: declare i8** @return_ppi8() // CHECK: declare ptr @return_ppi8()
llvm.func @return_ppi8() -> !llvm.ptr<ptr<i8>> llvm.func @return_ppi8() -> !llvm.ptr<ptr<i8>>
// CHECK: declare i8***** @return_pppppi8() // CHECK: declare ptr @return_pppppi8()
llvm.func @return_pppppi8() -> !llvm.ptr<ptr<ptr<ptr<ptr<i8>>>>> llvm.func @return_pppppi8() -> !llvm.ptr<ptr<ptr<ptr<ptr<i8>>>>>
// CHECK: declare i8* @return_pi8_0() // CHECK: declare ptr @return_pi8_0()
llvm.func @return_pi8_0() -> !llvm.ptr<i8, 0> llvm.func @return_pi8_0() -> !llvm.ptr<i8, 0>
// CHECK: declare i8 addrspace(1)* @return_pi8_1() // CHECK: declare ptr addrspace(1) @return_pi8_1()
llvm.func @return_pi8_1() -> !llvm.ptr<i8, 1> llvm.func @return_pi8_1() -> !llvm.ptr<i8, 1>
// CHECK: declare i8 addrspace(42)* @return_pi8_42() // CHECK: declare ptr addrspace(42) @return_pi8_42()
llvm.func @return_pi8_42() -> !llvm.ptr<i8, 42> llvm.func @return_pi8_42() -> !llvm.ptr<i8, 42>
// CHECK: declare i8 addrspace(42)* addrspace(9)* @return_ppi8_42_9() // CHECK: declare ptr addrspace(9) @return_ppi8_42_9()
llvm.func @return_ppi8_42_9() -> !llvm.ptr<ptr<i8, 42>, 9> llvm.func @return_ppi8_42_9() -> !llvm.ptr<ptr<i8, 42>, 9>
// //
// Vectors. // Vectors.
// //
// CHECK: declare <4 x i32> @return_v4_i32() // CHECK: declare <4 x i32> @return_v4_i32()
llvm.func @return_v4_i32() -> vector<4xi32> llvm.func @return_v4_i32() -> vector<4xi32>
// CHECK: declare <4 x float> @return_v4_float() // CHECK: declare <4 x float> @return_v4_float()
llvm.func @return_v4_float() -> vector<4xf32> llvm.func @return_v4_float() -> vector<4xf32>
// CHECK: declare <vscale x 4 x float> @return_vs_4_float() // CHECK: declare <vscale x 4 x float> @return_vs_4_float()
llvm.func @return_vs_4_float() -> vector<[4]xf32> llvm.func @return_vs_4_float() -> vector<[4]xf32>
// CHECK: declare <vscale x 4 x i32> @return_vs_4_i32() // CHECK: declare <vscale x 4 x i32> @return_vs_4_i32()
llvm.func @return_vs_4_i32() -> !llvm.vec<?x4 x i32> llvm.func @return_vs_4_i32() -> !llvm.vec<?x4 x i32>
// CHECK: declare <vscale x 8 x half> @return_vs_8_half() // CHECK: declare <vscale x 8 x half> @return_vs_8_half()
llvm.func @return_vs_8_half() -> !llvm.vec<?x8 x f16> llvm.func @return_vs_8_half() -> !llvm.vec<?x8 x f16>
// CHECK: declare <4 x i8*> @return_v_4_pi8() // CHECK: declare <4 x ptr> @return_v_4_pi8()
llvm.func @return_v_4_pi8() -> !llvm.vec<4xptr<i8>> llvm.func @return_v_4_pi8() -> !llvm.vec<4xptr<i8>>
// //
// Arrays. // Arrays.
// //
// CHECK: declare [10 x i32] @return_a10_i32() // CHECK: declare [10 x i32] @return_a10_i32()
llvm.func @return_a10_i32() -> !llvm.array<10 x i32> llvm.func @return_a10_i32() -> !llvm.array<10 x i32>
// CHECK: declare [8 x float] @return_a8_float() // CHECK: declare [8 x float] @return_a8_float()
llvm.func @return_a8_float() -> !llvm.array<8 x f32> llvm.func @return_a8_float() -> !llvm.array<8 x f32>
// CHECK: declare [10 x i32 addrspace(4)*] @return_a10_pi32_4() // CHECK: declare [10 x ptr addrspace(4)] @return_a10_pi32_4()
llvm.func @return_a10_pi32_4() -> !llvm.array<10 x ptr<i32, 4>> llvm.func @return_a10_pi32_4() -> !llvm.array<10 x ptr<i32, 4>>
// CHECK: declare [10 x [4 x float]] @return_a10_a4_float() // CHECK: declare [10 x [4 x float]] @return_a10_a4_float()
llvm.func @return_a10_a4_float() -> !llvm.array<10 x array<4 x f32>> llvm.func @return_a10_a4_float() -> !llvm.array<10 x array<4 x f32>>
// //
// Literal structures. // Literal structures.
// //
Show All 23 Lines
llvm.func @return_sp_s_i32() -> !llvm.struct<packed (struct<(i32)>)> llvm.func @return_sp_s_i32() -> !llvm.struct<packed (struct<(i32)>)>
// ----- // -----
// Put structs into a separate split so that we can match their declarations // Put structs into a separate split so that we can match their declarations
// locally. // locally.
// CHECK: %empty = type {} // CHECK: %empty = type {}
// CHECK: %opaque = type opaque // CHECK: %opaque = type opaque
// CHECK: %long = type { i32, { i32, i1 }, float, void ()* } // CHECK: %long = type { i32, { i32, i1 }, float, ptr }
// CHECK: %self-recursive = type { %self-recursive* } // CHECK: %self-recursive = type { ptr }
// CHECK: %unpacked = type { i32 } // CHECK: %unpacked = type { i32 }
// CHECK: %packed = type <{ i32 }> // CHECK: %packed = type <{ i32 }>
// CHECK: %"name with spaces and !^$@$#" = type <{ i32 }> // CHECK: %"name with spaces and !^$@$#" = type <{ i32 }>
// CHECK: %mutually-a = type { %mutually-b* } // CHECK: %mutually-a = type { ptr }
// CHECK: %mutually-b = type { %mutually-a addrspace(3)* } // CHECK: %mutually-b = type { ptr addrspace(3) }
// CHECK: %struct-of-arrays = type { [10 x i32] } // CHECK: %struct-of-arrays = type { [10 x i32] }
// CHECK: %array-of-structs = type { i32 } // CHECK: %array-of-structs = type { i32 }
// CHECK: %ptr-to-struct = type { i8 }
// CHECK: declare %empty // CHECK: declare %empty
llvm.func @return_s_empty() -> !llvm.struct<"empty", ()> llvm.func @return_s_empty() -> !llvm.struct<"empty", ()>
// CHECK: declare %opaque // CHECK: declare %opaque
llvm.func @return_s_opaque() -> !llvm.struct<"opaque", opaque> llvm.func @return_s_opaque() -> !llvm.struct<"opaque", opaque>
// CHECK: declare %long // CHECK: declare %long
llvm.func @return_s_long() -> !llvm.struct<"long", (i32, struct<(i32, i1)>, f32, ptr<func<void ()>>)> llvm.func @return_s_long() -> !llvm.struct<"long", (i32, struct<(i32, i1)>, f32, ptr<func<void ()>>)>
// CHECK: declare %self-recursive // CHECK: declare %self-recursive
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llvm.func @return_s_mutually_a() -> !llvm.struct<"mutually-a", (ptr<struct<"mutually-b", (ptr<struct<"mutually-a">, 3>)>>)> llvm.func @return_s_mutually_a() -> !llvm.struct<"mutually-a", (ptr<struct<"mutually-b", (ptr<struct<"mutually-a">, 3>)>>)>
// CHECK: declare %mutually-b // CHECK: declare %mutually-b
llvm.func @return_s_mutually_b() -> !llvm.struct<"mutually-b", (ptr<struct<"mutually-a", (ptr<struct<"mutually-b">>)>, 3>)> llvm.func @return_s_mutually_b() -> !llvm.struct<"mutually-b", (ptr<struct<"mutually-a", (ptr<struct<"mutually-b">>)>, 3>)>
// CHECK: declare %struct-of-arrays // CHECK: declare %struct-of-arrays
llvm.func @return_s_struct_of_arrays() -> !llvm.struct<"struct-of-arrays", (array<10 x i32>)> llvm.func @return_s_struct_of_arrays() -> !llvm.struct<"struct-of-arrays", (array<10 x i32>)>
// CHECK: declare [10 x %array-of-structs] // CHECK: declare [10 x %array-of-structs]
llvm.func @return_s_array_of_structs() -> !llvm.array<10 x struct<"array-of-structs", (i32)>> llvm.func @return_s_array_of_structs() -> !llvm.array<10 x struct<"array-of-structs", (i32)>>
// CHECK: declare %ptr-to-struct* // CHECK: declare ptr
llvm.func @return_s_ptr_to_struct() -> !llvm.ptr<struct<"ptr-to-struct", (i8)>> llvm.func @return_s_ptr_to_struct() -> !llvm.ptr<struct<"ptr-to-struct", (i8)>>

mlir/test/Target/LLVMIR/llvmir.mlir

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llvm.mlir.global internal @int_global_undef() : i64 llvm.mlir.global internal @int_global_undef() : i64
// CHECK: @explicit_undef = global i32 undef // CHECK: @explicit_undef = global i32 undef
llvm.mlir.global external @explicit_undef() : i32 { llvm.mlir.global external @explicit_undef() : i32 {
%0 = llvm.mlir.undef : i32 %0 = llvm.mlir.undef : i32
llvm.return %0 : i32 llvm.return %0 : i32
} }
// CHECK: @int_gep = internal constant i32* getelementptr (i32, i32* @i32_global, i32 2) // CHECK: @int_gep = internal constant ptr getelementptr (i32, ptr @i32_global, i32 2)
llvm.mlir.global internal constant @int_gep() : !llvm.ptr<i32> { llvm.mlir.global internal constant @int_gep() : !llvm.ptr<i32> {
%addr = llvm.mlir.addressof @i32_global : !llvm.ptr<i32> %addr = llvm.mlir.addressof @i32_global : !llvm.ptr<i32>
%_c0 = llvm.mlir.constant(2: i32) :i32 %_c0 = llvm.mlir.constant(2: i32) :i32
%gepinit = llvm.getelementptr %addr[%_c0] : (!llvm.ptr<i32>, i32) -> !llvm.ptr<i32> %gepinit = llvm.getelementptr %addr[%_c0] : (!llvm.ptr<i32>, i32) -> !llvm.ptr<i32>
llvm.return %gepinit : !llvm.ptr<i32> llvm.return %gepinit : !llvm.ptr<i32>
} }
// CHECK{LITERAL}: @dense_float_vector = internal global <3 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00> // CHECK{LITERAL}: @dense_float_vector = internal global <3 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>
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// CHECK: @sectionvar = internal constant [10 x i8] c"teststring", section ".mysection" // CHECK: @sectionvar = internal constant [10 x i8] c"teststring", section ".mysection"
llvm.mlir.global internal constant @sectionvar("teststring") {section = ".mysection"}: !llvm.array<10 x i8> llvm.mlir.global internal constant @sectionvar("teststring") {section = ".mysection"}: !llvm.array<10 x i8>
// //
// Declarations of the allocation functions to be linked against. These are // Declarations of the allocation functions to be linked against. These are
// inserted before other functions in the module. // inserted before other functions in the module.
// //
// CHECK: declare i8* @malloc(i64) // CHECK: declare ptr @malloc(i64)
llvm.func @malloc(i64) -> !llvm.ptr<i8> llvm.func @malloc(i64) -> !llvm.ptr<i8>
// CHECK: declare void @free(i8*) // CHECK: declare void @free(ptr)
// //
// Basic functionality: function and block conversion, function calls, // Basic functionality: function and block conversion, function calls,
// phi nodes, scalar type conversion, arithmetic operations. // phi nodes, scalar type conversion, arithmetic operations.
// //
// CHECK-LABEL: define void @empty() // CHECK-LABEL: define void @empty()
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// CHECK-NEXT: } // CHECK-NEXT: }
llvm.func @empty() { llvm.func @empty() {
llvm.return llvm.return
} }
// CHECK-LABEL: @global_refs // CHECK-LABEL: @global_refs
llvm.func @global_refs() { llvm.func @global_refs() {
// Check load from globals. // Check load from globals.
// CHECK: load i32, i32* @i32_global // CHECK: load i32, ptr @i32_global
%0 = llvm.mlir.addressof @i32_global : !llvm.ptr<i32> %0 = llvm.mlir.addressof @i32_global : !llvm.ptr<i32>
%1 = llvm.load %0 : !llvm.ptr<i32> %1 = llvm.load %0 : !llvm.ptr<i32>
// Check the contracted form of load from array constants. // Check the contracted form of load from array constants.
// CHECK: load i8, i8* getelementptr inbounds ([6 x i8], [6 x i8]* @string_const, i64 0, i64 0) // CHECK: load i8, ptr @string_const
%2 = llvm.mlir.addressof @string_const : !llvm.ptr<array<6 x i8>> %2 = llvm.mlir.addressof @string_const : !llvm.ptr<array<6 x i8>>
%c0 = llvm.mlir.constant(0 : index) : i64 %c0 = llvm.mlir.constant(0 : index) : i64
%3 = llvm.getelementptr %2[%c0, %c0] : (!llvm.ptr<array<6 x i8>>, i64, i64) -> !llvm.ptr<i8> %3 = llvm.getelementptr %2[%c0, %c0] : (!llvm.ptr<array<6 x i8>>, i64, i64) -> !llvm.ptr<i8>
%4 = llvm.load %3 : !llvm.ptr<i8> %4 = llvm.load %3 : !llvm.ptr<i8>
llvm.return llvm.return
} }
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} }
// //
// MemRef type conversion, allocation and communication with functions. // MemRef type conversion, allocation and communication with functions.
// //
// CHECK-LABEL: define void @memref_alloc() // CHECK-LABEL: define void @memref_alloc()
llvm.func @memref_alloc() { llvm.func @memref_alloc() {
// CHECK-NEXT: %{{[0-9]+}} = call i8* @malloc(i64 400) // CHECK-NEXT: %{{[0-9]+}} = call ptr @malloc(i64 400)
// CHECK-NEXT: %{{[0-9]+}} = bitcast i8* %{{[0-9]+}} to float* // CHECK-NEXT: %{{[0-9]+}} = insertvalue { ptr } undef, ptr %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = insertvalue { float* } undef, float* %{{[0-9]+}}, 0
%0 = llvm.mlir.constant(10 : index) : i64 %0 = llvm.mlir.constant(10 : index) : i64
%1 = llvm.mlir.constant(10 : index) : i64 %1 = llvm.mlir.constant(10 : index) : i64
%2 = llvm.mul %0, %1 : i64 %2 = llvm.mul %0, %1 : i64
%3 = llvm.mlir.undef : !llvm.struct<(ptr<f32>)> %3 = llvm.mlir.undef : !llvm.struct<(ptr<f32>)>
%4 = llvm.mlir.constant(4 : index) : i64 %4 = llvm.mlir.constant(4 : index) : i64
%5 = llvm.mul %2, %4 : i64 %5 = llvm.mul %2, %4 : i64
%6 = llvm.call @malloc(%5) : (i64) -> !llvm.ptr<i8> %6 = llvm.call @malloc(%5) : (i64) -> !llvm.ptr<i8>
%7 = llvm.bitcast %6 : !llvm.ptr<i8> to !llvm.ptr<f32> %7 = llvm.bitcast %6 : !llvm.ptr<i8> to !llvm.ptr<f32>
%8 = llvm.insertvalue %7, %3[0] : !llvm.struct<(ptr<f32>)> %8 = llvm.insertvalue %7, %3[0] : !llvm.struct<(ptr<f32>)>
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
llvm.return llvm.return
} }
// CHECK-LABEL: declare i64 @get_index() // CHECK-LABEL: declare i64 @get_index()
llvm.func @get_index() -> i64 llvm.func @get_index() -> i64
// CHECK-LABEL: define void @store_load_static() // CHECK-LABEL: define void @store_load_static()
llvm.func @store_load_static() { llvm.func @store_load_static() {
^bb0: ^bb0:
// CHECK-NEXT: %{{[0-9]+}} = call i8* @malloc(i64 40) // CHECK-NEXT: %{{[0-9]+}} = call ptr @malloc(i64 40)
// CHECK-NEXT: %{{[0-9]+}} = bitcast i8* %{{[0-9]+}} to float* // CHECK-NEXT: %{{[0-9]+}} = insertvalue { ptr } undef, ptr %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = insertvalue { float* } undef, float* %{{[0-9]+}}, 0
%0 = llvm.mlir.constant(10 : index) : i64 %0 = llvm.mlir.constant(10 : index) : i64
%1 = llvm.mlir.undef : !llvm.struct<(ptr<f32>)> %1 = llvm.mlir.undef : !llvm.struct<(ptr<f32>)>
%2 = llvm.mlir.constant(4 : index) : i64 %2 = llvm.mlir.constant(4 : index) : i64
%3 = llvm.mul %0, %2 : i64 %3 = llvm.mul %0, %2 : i64
%4 = llvm.call @malloc(%3) : (i64) -> !llvm.ptr<i8> %4 = llvm.call @malloc(%3) : (i64) -> !llvm.ptr<i8>
%5 = llvm.bitcast %4 : !llvm.ptr<i8> to !llvm.ptr<f32> %5 = llvm.bitcast %4 : !llvm.ptr<i8> to !llvm.ptr<f32>
%6 = llvm.insertvalue %5, %1[0] : !llvm.struct<(ptr<f32>)> %6 = llvm.insertvalue %5, %1[0] : !llvm.struct<(ptr<f32>)>
%7 = llvm.mlir.constant(1.000000e+00 : f32) : f32 %7 = llvm.mlir.constant(1.000000e+00 : f32) : f32
llvm.br ^bb1 llvm.br ^bb1
^bb1: // pred: ^bb0 ^bb1: // pred: ^bb0
%8 = llvm.mlir.constant(0 : index) : i64 %8 = llvm.mlir.constant(0 : index) : i64
%9 = llvm.mlir.constant(10 : index) : i64 %9 = llvm.mlir.constant(10 : index) : i64
llvm.br ^bb2(%8 : i64) llvm.br ^bb2(%8 : i64)
// CHECK: %{{[0-9]+}} = phi i64 [ %{{[0-9]+}}, %{{[0-9]+}} ], [ 0, %{{[0-9]+}} ] // CHECK: %{{[0-9]+}} = phi i64 [ %{{[0-9]+}}, %{{[0-9]+}} ], [ 0, %{{[0-9]+}} ]
^bb2(%10: i64): // 2 preds: ^bb1, ^bb3 ^bb2(%10: i64): // 2 preds: ^bb1, ^bb3
// CHECK-NEXT: %{{[0-9]+}} = icmp slt i64 %{{[0-9]+}}, 10 // CHECK-NEXT: %{{[0-9]+}} = icmp slt i64 %{{[0-9]+}}, 10
%11 = llvm.icmp "slt" %10, %9 : i64 %11 = llvm.icmp "slt" %10, %9 : i64
// CHECK-NEXT: br i1 %{{[0-9]+}}, label %{{[0-9]+}}, label %{{[0-9]+}} // CHECK-NEXT: br i1 %{{[0-9]+}}, label %{{[0-9]+}}, label %{{[0-9]+}}
llvm.cond_br %11, ^bb3, ^bb4 llvm.cond_br %11, ^bb3, ^bb4
^bb3: // pred: ^bb2 ^bb3: // pred: ^bb2
// CHECK: %{{[0-9]+}} = extractvalue { float* } %{{[0-9]+}}, 0 // CHECK: %{{[0-9]+}} = extractvalue { ptr } %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = getelementptr float, float* %{{[0-9]+}}, i64 %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = getelementptr float, ptr %{{[0-9]+}}, i64 %{{[0-9]+}}
// CHECK-NEXT: store float 1.000000e+00, float* %{{[0-9]+}} // CHECK-NEXT: store float 1.000000e+00, ptr %{{[0-9]+}}
%12 = llvm.mlir.constant(10 : index) : i64 %12 = llvm.mlir.constant(10 : index) : i64
%13 = llvm.extractvalue %6[0] : !llvm.struct<(ptr<f32>)> %13 = llvm.extractvalue %6[0] : !llvm.struct<(ptr<f32>)>
%14 = llvm.getelementptr %13[%10] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %14 = llvm.getelementptr %13[%10] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
llvm.store %7, %14 : !llvm.ptr<f32> llvm.store %7, %14 : !llvm.ptr<f32>
%15 = llvm.mlir.constant(1 : index) : i64 %15 = llvm.mlir.constant(1 : index) : i64
// CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, 1 // CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, 1
%16 = llvm.add %10, %15 : i64 %16 = llvm.add %10, %15 : i64
// CHECK-NEXT: br label %{{[0-9]+}} // CHECK-NEXT: br label %{{[0-9]+}}
llvm.br ^bb2(%16 : i64) llvm.br ^bb2(%16 : i64)
^bb4: // pred: ^bb2 ^bb4: // pred: ^bb2
llvm.br ^bb5 llvm.br ^bb5
^bb5: // pred: ^bb4 ^bb5: // pred: ^bb4
%17 = llvm.mlir.constant(0 : index) : i64 %17 = llvm.mlir.constant(0 : index) : i64
%18 = llvm.mlir.constant(10 : index) : i64 %18 = llvm.mlir.constant(10 : index) : i64
llvm.br ^bb6(%17 : i64) llvm.br ^bb6(%17 : i64)
// CHECK: %{{[0-9]+}} = phi i64 [ %{{[0-9]+}}, %{{[0-9]+}} ], [ 0, %{{[0-9]+}} ] // CHECK: %{{[0-9]+}} = phi i64 [ %{{[0-9]+}}, %{{[0-9]+}} ], [ 0, %{{[0-9]+}} ]
^bb6(%19: i64): // 2 preds: ^bb5, ^bb7 ^bb6(%19: i64): // 2 preds: ^bb5, ^bb7
// CHECK-NEXT: %{{[0-9]+}} = icmp slt i64 %{{[0-9]+}}, 10 // CHECK-NEXT: %{{[0-9]+}} = icmp slt i64 %{{[0-9]+}}, 10
%20 = llvm.icmp "slt" %19, %18 : i64 %20 = llvm.icmp "slt" %19, %18 : i64
// CHECK-NEXT: br i1 %{{[0-9]+}}, label %{{[0-9]+}}, label %{{[0-9]+}} // CHECK-NEXT: br i1 %{{[0-9]+}}, label %{{[0-9]+}}, label %{{[0-9]+}}
llvm.cond_br %20, ^bb7, ^bb8 llvm.cond_br %20, ^bb7, ^bb8
^bb7: // pred: ^bb6 ^bb7: // pred: ^bb6
// CHECK: %{{[0-9]+}} = extractvalue { float* } %{{[0-9]+}}, 0 // CHECK: %{{[0-9]+}} = extractvalue { ptr } %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = getelementptr float, float* %{{[0-9]+}}, i64 %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = getelementptr float, ptr %{{[0-9]+}}, i64 %{{[0-9]+}}
// CHECK-NEXT: %{{[0-9]+}} = load float, float* %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = load float, ptr %{{[0-9]+}}
%21 = llvm.mlir.constant(10 : index) : i64 %21 = llvm.mlir.constant(10 : index) : i64
%22 = llvm.extractvalue %6[0] : !llvm.struct<(ptr<f32>)> %22 = llvm.extractvalue %6[0] : !llvm.struct<(ptr<f32>)>
%23 = llvm.getelementptr %22[%19] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %23 = llvm.getelementptr %22[%19] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
%24 = llvm.load %23 : !llvm.ptr<f32> %24 = llvm.load %23 : !llvm.ptr<f32>
%25 = llvm.mlir.constant(1 : index) : i64 %25 = llvm.mlir.constant(1 : index) : i64
// CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, 1 // CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, 1
%26 = llvm.add %19, %25 : i64 %26 = llvm.add %19, %25 : i64
// CHECK-NEXT: br label %{{[0-9]+}} // CHECK-NEXT: br label %{{[0-9]+}}
llvm.br ^bb6(%26 : i64) llvm.br ^bb6(%26 : i64)
^bb8: // pred: ^bb6 ^bb8: // pred: ^bb6
// CHECK: ret void // CHECK: ret void
llvm.return llvm.return
} }
// CHECK-LABEL: define void @store_load_dynamic(i64 {{%.*}}) // CHECK-LABEL: define void @store_load_dynamic(i64 {{%.*}})
llvm.func @store_load_dynamic(%arg0: i64) { llvm.func @store_load_dynamic(%arg0: i64) {
// CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, 4 // CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, 4
// CHECK-NEXT: %{{[0-9]+}} = call i8* @malloc(i64 %{{[0-9]+}}) // CHECK-NEXT: %{{[0-9]+}} = call ptr @malloc(i64 %{{[0-9]+}})
// CHECK-NEXT: %{{[0-9]+}} = bitcast i8* %{{[0-9]+}} to float* // CHECK-NEXT: %{{[0-9]+}} = insertvalue { ptr, i64 } undef, ptr %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = insertvalue { float*, i64 } undef, float* %{{[0-9]+}}, 0 // CHECK-NEXT: %{{[0-9]+}} = insertvalue { ptr, i64 } %{{[0-9]+}}, i64 %{{[0-9]+}}, 1
// CHECK-NEXT: %{{[0-9]+}} = insertvalue { float*, i64 } %{{[0-9]+}}, i64 %{{[0-9]+}}, 1
%0 = llvm.mlir.undef : !llvm.struct<(ptr<f32>, i64)> %0 = llvm.mlir.undef : !llvm.struct<(ptr<f32>, i64)>
%1 = llvm.mlir.constant(4 : index) : i64 %1 = llvm.mlir.constant(4 : index) : i64
%2 = llvm.mul %arg0, %1 : i64 %2 = llvm.mul %arg0, %1 : i64
%3 = llvm.call @malloc(%2) : (i64) -> !llvm.ptr<i8> %3 = llvm.call @malloc(%2) : (i64) -> !llvm.ptr<i8>
%4 = llvm.bitcast %3 : !llvm.ptr<i8> to !llvm.ptr<f32> %4 = llvm.bitcast %3 : !llvm.ptr<i8> to !llvm.ptr<f32>
%5 = llvm.insertvalue %4, %0[0] : !llvm.struct<(ptr<f32>, i64)> %5 = llvm.insertvalue %4, %0[0] : !llvm.struct<(ptr<f32>, i64)>
%6 = llvm.insertvalue %arg0, %5[1] : !llvm.struct<(ptr<f32>, i64)> %6 = llvm.insertvalue %arg0, %5[1] : !llvm.struct<(ptr<f32>, i64)>
%7 = llvm.mlir.constant(1.000000e+00 : f32) : f32 %7 = llvm.mlir.constant(1.000000e+00 : f32) : f32
// CHECK-NEXT: br label %{{[0-9]+}} // CHECK-NEXT: br label %{{[0-9]+}}
llvm.br ^bb1 llvm.br ^bb1
^bb1: // pred: ^bb0 ^bb1: // pred: ^bb0
%8 = llvm.mlir.constant(0 : index) : i64 %8 = llvm.mlir.constant(0 : index) : i64
llvm.br ^bb2(%8 : i64) llvm.br ^bb2(%8 : i64)
// CHECK: %{{[0-9]+}} = phi i64 [ %{{[0-9]+}}, %{{[0-9]+}} ], [ 0, %{{[0-9]+}} ] // CHECK: %{{[0-9]+}} = phi i64 [ %{{[0-9]+}}, %{{[0-9]+}} ], [ 0, %{{[0-9]+}} ]
^bb2(%9: i64): // 2 preds: ^bb1, ^bb3 ^bb2(%9: i64): // 2 preds: ^bb1, ^bb3
// CHECK-NEXT: %{{[0-9]+}} = icmp slt i64 %{{[0-9]+}}, %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = icmp slt i64 %{{[0-9]+}}, %{{[0-9]+}}
%10 = llvm.icmp "slt" %9, %arg0 : i64 %10 = llvm.icmp "slt" %9, %arg0 : i64
// CHECK-NEXT: br i1 %{{[0-9]+}}, label %{{[0-9]+}}, label %{{[0-9]+}} // CHECK-NEXT: br i1 %{{[0-9]+}}, label %{{[0-9]+}}, label %{{[0-9]+}}
llvm.cond_br %10, ^bb3, ^bb4 llvm.cond_br %10, ^bb3, ^bb4
^bb3: // pred: ^bb2 ^bb3: // pred: ^bb2
// CHECK: %{{[0-9]+}} = extractvalue { float*, i64 } %{{[0-9]+}}, 1 // CHECK: %{{[0-9]+}} = extractvalue { ptr, i64 } %{{[0-9]+}}, 1
// CHECK-NEXT: %{{[0-9]+}} = extractvalue { float*, i64 } %{{[0-9]+}}, 0 // CHECK-NEXT: %{{[0-9]+}} = extractvalue { ptr, i64 } %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = getelementptr float, float* %{{[0-9]+}}, i64 %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = getelementptr float, ptr %{{[0-9]+}}, i64 %{{[0-9]+}}
// CHECK-NEXT: store float 1.000000e+00, float* %{{[0-9]+}} // CHECK-NEXT: store float 1.000000e+00, ptr %{{[0-9]+}}
%11 = llvm.extractvalue %6[1] : !llvm.struct<(ptr<f32>, i64)> %11 = llvm.extractvalue %6[1] : !llvm.struct<(ptr<f32>, i64)>
%12 = llvm.extractvalue %6[0] : !llvm.struct<(ptr<f32>, i64)> %12 = llvm.extractvalue %6[0] : !llvm.struct<(ptr<f32>, i64)>
%13 = llvm.getelementptr %12[%9] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %13 = llvm.getelementptr %12[%9] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
llvm.store %7, %13 : !llvm.ptr<f32> llvm.store %7, %13 : !llvm.ptr<f32>
%14 = llvm.mlir.constant(1 : index) : i64 %14 = llvm.mlir.constant(1 : index) : i64
// CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, 1 // CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, 1
%15 = llvm.add %9, %14 : i64 %15 = llvm.add %9, %14 : i64
// CHECK-NEXT: br label %{{[0-9]+}} // CHECK-NEXT: br label %{{[0-9]+}}
llvm.br ^bb2(%15 : i64) llvm.br ^bb2(%15 : i64)
^bb4: // pred: ^bb3 ^bb4: // pred: ^bb3
llvm.br ^bb5 llvm.br ^bb5
^bb5: // pred: ^bb4 ^bb5: // pred: ^bb4
%16 = llvm.mlir.constant(0 : index) : i64 %16 = llvm.mlir.constant(0 : index) : i64
llvm.br ^bb6(%16 : i64) llvm.br ^bb6(%16 : i64)
// CHECK: %{{[0-9]+}} = phi i64 [ %{{[0-9]+}}, %{{[0-9]+}} ], [ 0, %{{[0-9]+}} ] // CHECK: %{{[0-9]+}} = phi i64 [ %{{[0-9]+}}, %{{[0-9]+}} ], [ 0, %{{[0-9]+}} ]
^bb6(%17: i64): // 2 preds: ^bb5, ^bb7 ^bb6(%17: i64): // 2 preds: ^bb5, ^bb7
// CHECK-NEXT: %{{[0-9]+}} = icmp slt i64 %{{[0-9]+}}, %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = icmp slt i64 %{{[0-9]+}}, %{{[0-9]+}}
%18 = llvm.icmp "slt" %17, %arg0 : i64 %18 = llvm.icmp "slt" %17, %arg0 : i64
// CHECK-NEXT: br i1 %{{[0-9]+}}, label %{{[0-9]+}}, label %{{[0-9]+}} // CHECK-NEXT: br i1 %{{[0-9]+}}, label %{{[0-9]+}}, label %{{[0-9]+}}
llvm.cond_br %18, ^bb7, ^bb8 llvm.cond_br %18, ^bb7, ^bb8
^bb7: // pred: ^bb6 ^bb7: // pred: ^bb6
// CHECK: %{{[0-9]+}} = extractvalue { float*, i64 } %{{[0-9]+}}, 1 // CHECK: %{{[0-9]+}} = extractvalue { ptr, i64 } %{{[0-9]+}}, 1
// CHECK-NEXT: %{{[0-9]+}} = extractvalue { float*, i64 } %{{[0-9]+}}, 0 // CHECK-NEXT: %{{[0-9]+}} = extractvalue { ptr, i64 } %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = getelementptr float, float* %{{[0-9]+}}, i64 %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = getelementptr float, ptr %{{[0-9]+}}, i64 %{{[0-9]+}}
// CHECK-NEXT: %{{[0-9]+}} = load float, float* %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = load float, ptr %{{[0-9]+}}
%19 = llvm.extractvalue %6[1] : !llvm.struct<(ptr<f32>, i64)> %19 = llvm.extractvalue %6[1] : !llvm.struct<(ptr<f32>, i64)>
%20 = llvm.extractvalue %6[0] : !llvm.struct<(ptr<f32>, i64)> %20 = llvm.extractvalue %6[0] : !llvm.struct<(ptr<f32>, i64)>
%21 = llvm.getelementptr %20[%17] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %21 = llvm.getelementptr %20[%17] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
%22 = llvm.load %21 : !llvm.ptr<f32> %22 = llvm.load %21 : !llvm.ptr<f32>
%23 = llvm.mlir.constant(1 : index) : i64 %23 = llvm.mlir.constant(1 : index) : i64
// CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, 1 // CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, 1
%24 = llvm.add %17, %23 : i64 %24 = llvm.add %17, %23 : i64
// CHECK-NEXT: br label %{{[0-9]+}} // CHECK-NEXT: br label %{{[0-9]+}}
llvm.br ^bb6(%24 : i64) llvm.br ^bb6(%24 : i64)
^bb8: // pred: ^bb6 ^bb8: // pred: ^bb6
// CHECK: ret void // CHECK: ret void
llvm.return llvm.return
} }
// CHECK-LABEL: define void @store_load_mixed(i64 {{%.*}}) // CHECK-LABEL: define void @store_load_mixed(i64 {{%.*}})
llvm.func @store_load_mixed(%arg0: i64) { llvm.func @store_load_mixed(%arg0: i64) {
%0 = llvm.mlir.constant(10 : index) : i64 %0 = llvm.mlir.constant(10 : index) : i64
// CHECK-NEXT: %{{[0-9]+}} = mul i64 2, %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = mul i64 2, %{{[0-9]+}}
// CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, 4 // CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, 4
// CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, 10 // CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, 10
// CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, 4 // CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, 4
// CHECK-NEXT: %{{[0-9]+}} = call i8* @malloc(i64 %{{[0-9]+}}) // CHECK-NEXT: %{{[0-9]+}} = call ptr @malloc(i64 %{{[0-9]+}})
// CHECK-NEXT: %{{[0-9]+}} = bitcast i8* %{{[0-9]+}} to float* // CHECK-NEXT: %{{[0-9]+}} = insertvalue { ptr, i64, i64 } undef, ptr %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = insertvalue { float*, i64, i64 } undef, float* %{{[0-9]+}}, 0 // CHECK-NEXT: %{{[0-9]+}} = insertvalue { ptr, i64, i64 } %{{[0-9]+}}, i64 %{{[0-9]+}}, 1
// CHECK-NEXT: %{{[0-9]+}} = insertvalue { float*, i64, i64 } %{{[0-9]+}}, i64 %{{[0-9]+}}, 1 // CHECK-NEXT: %{{[0-9]+}} = insertvalue { ptr, i64, i64 } %{{[0-9]+}}, i64 10, 2
// CHECK-NEXT: %{{[0-9]+}} = insertvalue { float*, i64, i64 } %{{[0-9]+}}, i64 10, 2
%1 = llvm.mlir.constant(2 : index) : i64 %1 = llvm.mlir.constant(2 : index) : i64
%2 = llvm.mlir.constant(4 : index) : i64 %2 = llvm.mlir.constant(4 : index) : i64
%3 = llvm.mul %1, %arg0 : i64 %3 = llvm.mul %1, %arg0 : i64
%4 = llvm.mul %3, %2 : i64 %4 = llvm.mul %3, %2 : i64
%5 = llvm.mul %4, %0 : i64 %5 = llvm.mul %4, %0 : i64
%6 = llvm.mlir.undef : !llvm.struct<(ptr<f32>, i64, i64)> %6 = llvm.mlir.undef : !llvm.struct<(ptr<f32>, i64, i64)>
%7 = llvm.mlir.constant(4 : index) : i64 %7 = llvm.mlir.constant(4 : index) : i64
%8 = llvm.mul %5, %7 : i64 %8 = llvm.mul %5, %7 : i64
%9 = llvm.call @malloc(%8) : (i64) -> !llvm.ptr<i8> %9 = llvm.call @malloc(%8) : (i64) -> !llvm.ptr<i8>
%10 = llvm.bitcast %9 : !llvm.ptr<i8> to !llvm.ptr<f32> %10 = llvm.bitcast %9 : !llvm.ptr<i8> to !llvm.ptr<f32>
%11 = llvm.insertvalue %10, %6[0] : !llvm.struct<(ptr<f32>, i64, i64)> %11 = llvm.insertvalue %10, %6[0] : !llvm.struct<(ptr<f32>, i64, i64)>
%12 = llvm.insertvalue %arg0, %11[1] : !llvm.struct<(ptr<f32>, i64, i64)> %12 = llvm.insertvalue %arg0, %11[1] : !llvm.struct<(ptr<f32>, i64, i64)>
%13 = llvm.insertvalue %0, %12[2] : !llvm.struct<(ptr<f32>, i64, i64)> %13 = llvm.insertvalue %0, %12[2] : !llvm.struct<(ptr<f32>, i64, i64)>
// CHECK-NEXT: %{{[0-9]+}} = call i64 @get_index() // CHECK-NEXT: %{{[0-9]+}} = call i64 @get_index()
// CHECK-NEXT: %{{[0-9]+}} = call i64 @get_index() // CHECK-NEXT: %{{[0-9]+}} = call i64 @get_index()
%14 = llvm.mlir.constant(1 : index) : i64 %14 = llvm.mlir.constant(1 : index) : i64
%15 = llvm.mlir.constant(2 : index) : i64 %15 = llvm.mlir.constant(2 : index) : i64
%16 = llvm.call @get_index() : () -> i64 %16 = llvm.call @get_index() : () -> i64
%17 = llvm.call @get_index() : () -> i64 %17 = llvm.call @get_index() : () -> i64
%18 = llvm.mlir.constant(4.200000e+01 : f32) : f32 %18 = llvm.mlir.constant(4.200000e+01 : f32) : f32
%19 = llvm.mlir.constant(2 : index) : i64 %19 = llvm.mlir.constant(2 : index) : i64
// CHECK-NEXT: %{{[0-9]+}} = extractvalue { float*, i64, i64 } %{{[0-9]+}}, 1 // CHECK-NEXT: %{{[0-9]+}} = extractvalue { ptr, i64, i64 } %{{[0-9]+}}, 1
// CHECK-NEXT: %{{[0-9]+}} = extractvalue { float*, i64, i64 } %{{[0-9]+}}, 2 // CHECK-NEXT: %{{[0-9]+}} = extractvalue { ptr, i64, i64 } %{{[0-9]+}}, 2
// CHECK-NEXT: %{{[0-9]+}} = mul i64 1, %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = mul i64 1, %{{[0-9]+}}
// CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, 2 // CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, 2
// CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, 4 // CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, 4
// CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-NEXT: %{{[0-9]+}} = extractvalue { float*, i64, i64 } %{{[0-9]+}}, 0 // CHECK-NEXT: %{{[0-9]+}} = extractvalue { ptr, i64, i64 } %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = getelementptr float, float* %{{[0-9]+}}, i64 %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = getelementptr float, ptr %{{[0-9]+}}, i64 %{{[0-9]+}}
// CHECK-NEXT: store float 4.200000e+01, float* %{{[0-9]+}} // CHECK-NEXT: store float 4.200000e+01, ptr %{{[0-9]+}}
%20 = llvm.extractvalue %13[1] : !llvm.struct<(ptr<f32>, i64, i64)> %20 = llvm.extractvalue %13[1] : !llvm.struct<(ptr<f32>, i64, i64)>
%21 = llvm.mlir.constant(4 : index) : i64 %21 = llvm.mlir.constant(4 : index) : i64
%22 = llvm.extractvalue %13[2] : !llvm.struct<(ptr<f32>, i64, i64)> %22 = llvm.extractvalue %13[2] : !llvm.struct<(ptr<f32>, i64, i64)>
%23 = llvm.mul %14, %20 : i64 %23 = llvm.mul %14, %20 : i64
%24 = llvm.add %23, %15 : i64 %24 = llvm.add %23, %15 : i64
%25 = llvm.mul %24, %21 : i64 %25 = llvm.mul %24, %21 : i64
%26 = llvm.add %25, %16 : i64 %26 = llvm.add %25, %16 : i64
%27 = llvm.mul %26, %22 : i64 %27 = llvm.mul %26, %22 : i64
%28 = llvm.add %27, %17 : i64 %28 = llvm.add %27, %17 : i64
%29 = llvm.extractvalue %13[0] : !llvm.struct<(ptr<f32>, i64, i64)> %29 = llvm.extractvalue %13[0] : !llvm.struct<(ptr<f32>, i64, i64)>
%30 = llvm.getelementptr %29[%28] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %30 = llvm.getelementptr %29[%28] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
llvm.store %18, %30 : !llvm.ptr<f32> llvm.store %18, %30 : !llvm.ptr<f32>
// CHECK-NEXT: %{{[0-9]+}} = extractvalue { float*, i64, i64 } %{{[0-9]+}}, 1 // CHECK-NEXT: %{{[0-9]+}} = extractvalue { ptr, i64, i64 } %{{[0-9]+}}, 1
// CHECK-NEXT: %{{[0-9]+}} = extractvalue { float*, i64, i64 } %{{[0-9]+}}, 2 // CHECK-NEXT: %{{[0-9]+}} = extractvalue { ptr, i64, i64 } %{{[0-9]+}}, 2
// CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, 4 // CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, 4
// CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, 2 // CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, 2
// CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, 1 // CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, 1
// CHECK-NEXT: %{{[0-9]+}} = extractvalue { float*, i64, i64 } %{{[0-9]+}}, 0 // CHECK-NEXT: %{{[0-9]+}} = extractvalue { ptr, i64, i64 } %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = getelementptr float, float* %{{[0-9]+}}, i64 %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = getelementptr float, ptr %{{[0-9]+}}, i64 %{{[0-9]+}}
// CHECK-NEXT: %{{[0-9]+}} = load float, float* %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = load float, ptr %{{[0-9]+}}
%31 = llvm.mlir.constant(2 : index) : i64 %31 = llvm.mlir.constant(2 : index) : i64
%32 = llvm.extractvalue %13[1] : !llvm.struct<(ptr<f32>, i64, i64)> %32 = llvm.extractvalue %13[1] : !llvm.struct<(ptr<f32>, i64, i64)>
%33 = llvm.mlir.constant(4 : index) : i64 %33 = llvm.mlir.constant(4 : index) : i64
%34 = llvm.extractvalue %13[2] : !llvm.struct<(ptr<f32>, i64, i64)> %34 = llvm.extractvalue %13[2] : !llvm.struct<(ptr<f32>, i64, i64)>
%35 = llvm.mul %17, %32 : i64 %35 = llvm.mul %17, %32 : i64
%36 = llvm.add %35, %16 : i64 %36 = llvm.add %35, %16 : i64
%37 = llvm.mul %36, %33 : i64 %37 = llvm.mul %36, %33 : i64
%38 = llvm.add %37, %15 : i64 %38 = llvm.add %37, %15 : i64
%39 = llvm.mul %38, %34 : i64 %39 = llvm.mul %38, %34 : i64
%40 = llvm.add %39, %14 : i64 %40 = llvm.add %39, %14 : i64
%41 = llvm.extractvalue %13[0] : !llvm.struct<(ptr<f32>, i64, i64)> %41 = llvm.extractvalue %13[0] : !llvm.struct<(ptr<f32>, i64, i64)>
%42 = llvm.getelementptr %41[%40] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %42 = llvm.getelementptr %41[%40] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
%43 = llvm.load %42 : !llvm.ptr<f32> %43 = llvm.load %42 : !llvm.ptr<f32>
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
llvm.return llvm.return
} }
// CHECK-LABEL: define { float*, i64 } @memref_args_rets({ float* } {{%.*}}, { float*, i64 } {{%.*}}, { float*, i64 } {{%.*}}) // CHECK-LABEL: define { ptr, i64 } @memref_args_rets({ ptr } {{%.*}}, { ptr, i64 } {{%.*}}, { ptr, i64 } {{%.*}})
llvm.func @memref_args_rets(%arg0: !llvm.struct<(ptr<f32>)>, %arg1: !llvm.struct<(ptr<f32>, i64)>, %arg2: !llvm.struct<(ptr<f32>, i64)>) -> !llvm.struct<(ptr<f32>, i64)> { llvm.func @memref_args_rets(%arg0: !llvm.struct<(ptr<f32>)>, %arg1: !llvm.struct<(ptr<f32>, i64)>, %arg2: !llvm.struct<(ptr<f32>, i64)>) -> !llvm.struct<(ptr<f32>, i64)> {
%0 = llvm.mlir.constant(7 : index) : i64 %0 = llvm.mlir.constant(7 : index) : i64
// CHECK-NEXT: %{{[0-9]+}} = call i64 @get_index() // CHECK-NEXT: %{{[0-9]+}} = call i64 @get_index()
%1 = llvm.call @get_index() : () -> i64 %1 = llvm.call @get_index() : () -> i64
%2 = llvm.mlir.constant(4.200000e+01 : f32) : f32 %2 = llvm.mlir.constant(4.200000e+01 : f32) : f32
// CHECK-NEXT: %{{[0-9]+}} = extractvalue { float* } %{{[0-9]+}}, 0 // CHECK-NEXT: %{{[0-9]+}} = extractvalue { ptr } %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = getelementptr float, float* %{{[0-9]+}}, i64 7 // CHECK-NEXT: %{{[0-9]+}} = getelementptr float, ptr %{{[0-9]+}}, i64 7
// CHECK-NEXT: store float 4.200000e+01, float* %{{[0-9]+}} // CHECK-NEXT: store float 4.200000e+01, ptr %{{[0-9]+}}
%3 = llvm.mlir.constant(10 : index) : i64 %3 = llvm.mlir.constant(10 : index) : i64
%4 = llvm.extractvalue %arg0[0] : !llvm.struct<(ptr<f32>)> %4 = llvm.extractvalue %arg0[0] : !llvm.struct<(ptr<f32>)>
%5 = llvm.getelementptr %4[%0] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %5 = llvm.getelementptr %4[%0] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
llvm.store %2, %5 : !llvm.ptr<f32> llvm.store %2, %5 : !llvm.ptr<f32>
// CHECK-NEXT: %{{[0-9]+}} = extractvalue { float*, i64 } %{{[0-9]+}}, 1 // CHECK-NEXT: %{{[0-9]+}} = extractvalue { ptr, i64 } %{{[0-9]+}}, 1
// CHECK-NEXT: %{{[0-9]+}} = extractvalue { float*, i64 } %{{[0-9]+}}, 0 // CHECK-NEXT: %{{[0-9]+}} = extractvalue { ptr, i64 } %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = getelementptr float, float* %{{[0-9]+}}, i64 7 // CHECK-NEXT: %{{[0-9]+}} = getelementptr float, ptr %{{[0-9]+}}, i64 7
// CHECK-NEXT: store float 4.200000e+01, float* %{{[0-9]+}} // CHECK-NEXT: store float 4.200000e+01, ptr %{{[0-9]+}}
%6 = llvm.extractvalue %arg1[1] : !llvm.struct<(ptr<f32>, i64)> %6 = llvm.extractvalue %arg1[1] : !llvm.struct<(ptr<f32>, i64)>
%7 = llvm.extractvalue %arg1[0] : !llvm.struct<(ptr<f32>, i64)> %7 = llvm.extractvalue %arg1[0] : !llvm.struct<(ptr<f32>, i64)>
%8 = llvm.getelementptr %7[%0] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %8 = llvm.getelementptr %7[%0] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
llvm.store %2, %8 : !llvm.ptr<f32> llvm.store %2, %8 : !llvm.ptr<f32>
// CHECK-NEXT: %{{[0-9]+}} = extractvalue { float*, i64 } %{{[0-9]+}}, 1 // CHECK-NEXT: %{{[0-9]+}} = extractvalue { ptr, i64 } %{{[0-9]+}}, 1
// CHECK-NEXT: %{{[0-9]+}} = mul i64 7, %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = mul i64 7, %{{[0-9]+}}
// CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = add i64 %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-NEXT: %{{[0-9]+}} = extractvalue { float*, i64 } %{{[0-9]+}}, 0 // CHECK-NEXT: %{{[0-9]+}} = extractvalue { ptr, i64 } %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = getelementptr float, float* %{{[0-9]+}}, i64 %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = getelementptr float, ptr %{{[0-9]+}}, i64 %{{[0-9]+}}
// CHECK-NEXT: store float 4.200000e+01, float* %{{[0-9]+}} // CHECK-NEXT: store float 4.200000e+01, ptr %{{[0-9]+}}
%9 = llvm.mlir.constant(10 : index) : i64 %9 = llvm.mlir.constant(10 : index) : i64
%10 = llvm.extractvalue %arg2[1] : !llvm.struct<(ptr<f32>, i64)> %10 = llvm.extractvalue %arg2[1] : !llvm.struct<(ptr<f32>, i64)>
%11 = llvm.mul %0, %10 : i64 %11 = llvm.mul %0, %10 : i64
%12 = llvm.add %11, %1 : i64 %12 = llvm.add %11, %1 : i64
%13 = llvm.extractvalue %arg2[0] : !llvm.struct<(ptr<f32>, i64)> %13 = llvm.extractvalue %arg2[0] : !llvm.struct<(ptr<f32>, i64)>
%14 = llvm.getelementptr %13[%12] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %14 = llvm.getelementptr %13[%12] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
llvm.store %2, %14 : !llvm.ptr<f32> llvm.store %2, %14 : !llvm.ptr<f32>
// CHECK-NEXT: %{{[0-9]+}} = mul i64 10, %{{[0-9]+}} // CHECK-NEXT: %{{[0-9]+}} = mul i64 10, %{{[0-9]+}}
// CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, 4 // CHECK-NEXT: %{{[0-9]+}} = mul i64 %{{[0-9]+}}, 4
// CHECK-NEXT: %{{[0-9]+}} = call i8* @malloc(i64 %{{[0-9]+}}) // CHECK-NEXT: %{{[0-9]+}} = call ptr @malloc(i64 %{{[0-9]+}})
// CHECK-NEXT: %{{[0-9]+}} = bitcast i8* %{{[0-9]+}} to float* // CHECK-NEXT: %{{[0-9]+}} = insertvalue { ptr, i64 } undef, ptr %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = insertvalue { float*, i64 } undef, float* %{{[0-9]+}}, 0 // CHECK-NEXT: %{{[0-9]+}} = insertvalue { ptr, i64 } %{{[0-9]+}}, i64 %{{[0-9]+}}, 1
// CHECK-NEXT: %{{[0-9]+}} = insertvalue { float*, i64 } %{{[0-9]+}}, i64 %{{[0-9]+}}, 1
%15 = llvm.mlir.constant(10 : index) : i64 %15 = llvm.mlir.constant(10 : index) : i64
%16 = llvm.mul %15, %1 : i64 %16 = llvm.mul %15, %1 : i64
%17 = llvm.mlir.undef : !llvm.struct<(ptr<f32>, i64)> %17 = llvm.mlir.undef : !llvm.struct<(ptr<f32>, i64)>
%18 = llvm.mlir.constant(4 : index) : i64 %18 = llvm.mlir.constant(4 : index) : i64
%19 = llvm.mul %16, %18 : i64 %19 = llvm.mul %16, %18 : i64
%20 = llvm.call @malloc(%19) : (i64) -> !llvm.ptr<i8> %20 = llvm.call @malloc(%19) : (i64) -> !llvm.ptr<i8>
%21 = llvm.bitcast %20 : !llvm.ptr<i8> to !llvm.ptr<f32> %21 = llvm.bitcast %20 : !llvm.ptr<i8> to !llvm.ptr<f32>
%22 = llvm.insertvalue %21, %17[0] : !llvm.struct<(ptr<f32>, i64)> %22 = llvm.insertvalue %21, %17[0] : !llvm.struct<(ptr<f32>, i64)>
%23 = llvm.insertvalue %1, %22[1] : !llvm.struct<(ptr<f32>, i64)> %23 = llvm.insertvalue %1, %22[1] : !llvm.struct<(ptr<f32>, i64)>
// CHECK-NEXT: ret { float*, i64 } %{{[0-9]+}} // CHECK-NEXT: ret { ptr, i64 } %{{[0-9]+}}
llvm.return %23 : !llvm.struct<(ptr<f32>, i64)> llvm.return %23 : !llvm.struct<(ptr<f32>, i64)>
} }
// CHECK-LABEL: define i64 @memref_dim({ float*, i64, i64 } {{%.*}}) // CHECK-LABEL: define i64 @memref_dim({ ptr, i64, i64 } {{%.*}})
llvm.func @memref_dim(%arg0: !llvm.struct<(ptr<f32>, i64, i64)>) -> i64 { llvm.func @memref_dim(%arg0: !llvm.struct<(ptr<f32>, i64, i64)>) -> i64 {
// Expecting this to create an LLVM constant. // Expecting this to create an LLVM constant.
%0 = llvm.mlir.constant(42 : index) : i64 %0 = llvm.mlir.constant(42 : index) : i64
// CHECK-NEXT: %2 = extractvalue { float*, i64, i64 } %0, 1 // CHECK-NEXT: %2 = extractvalue { ptr, i64, i64 } %0, 1
%1 = llvm.extractvalue %arg0[1] : !llvm.struct<(ptr<f32>, i64, i64)> %1 = llvm.extractvalue %arg0[1] : !llvm.struct<(ptr<f32>, i64, i64)>
// Expecting this to create an LLVM constant. // Expecting this to create an LLVM constant.
%2 = llvm.mlir.constant(10 : index) : i64 %2 = llvm.mlir.constant(10 : index) : i64
// CHECK-NEXT: %3 = extractvalue { float*, i64, i64 } %0, 2 // CHECK-NEXT: %3 = extractvalue { ptr, i64, i64 } %0, 2
%3 = llvm.extractvalue %arg0[2] : !llvm.struct<(ptr<f32>, i64, i64)> %3 = llvm.extractvalue %arg0[2] : !llvm.struct<(ptr<f32>, i64, i64)>
// Checking that the constant for d0 has been created. // Checking that the constant for d0 has been created.
// CHECK-NEXT: %4 = add i64 42, %2 // CHECK-NEXT: %4 = add i64 42, %2
%4 = llvm.add %0, %1 : i64 %4 = llvm.add %0, %1 : i64
// Checking that the constant for d2 has been created. // Checking that the constant for d2 has been created.
// CHECK-NEXT: %5 = add i64 10, %3 // CHECK-NEXT: %5 = add i64 10, %3
%5 = llvm.add %2, %3 : i64 %5 = llvm.add %2, %3 : i64
// CHECK-NEXT: %6 = add i64 %4, %5 // CHECK-NEXT: %6 = add i64 %4, %5
%6 = llvm.add %4, %5 : i64 %6 = llvm.add %4, %5 : i64
// CHECK-NEXT: ret i64 %6 // CHECK-NEXT: ret i64 %6
llvm.return %6 : i64 llvm.return %6 : i64
} }
llvm.func @get_i64() -> i64 llvm.func @get_i64() -> i64
llvm.func @get_f32() -> f32 llvm.func @get_f32() -> f32
llvm.func @get_memref() -> !llvm.struct<(ptr<f32>, i64, i64)> llvm.func @get_memref() -> !llvm.struct<(ptr<f32>, i64, i64)>
// CHECK-LABEL: define { i64, float, { float*, i64, i64 } } @multireturn() // CHECK-LABEL: define { i64, float, { ptr, i64, i64 } } @multireturn()
llvm.func @multireturn() -> !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)> { llvm.func @multireturn() -> !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)> {
%0 = llvm.call @get_i64() : () -> i64 %0 = llvm.call @get_i64() : () -> i64
%1 = llvm.call @get_f32() : () -> f32 %1 = llvm.call @get_f32() : () -> f32
%2 = llvm.call @get_memref() : () -> !llvm.struct<(ptr<f32>, i64, i64)> %2 = llvm.call @get_memref() : () -> !llvm.struct<(ptr<f32>, i64, i64)>
// CHECK: %{{[0-9]+}} = insertvalue { i64, float, { float*, i64, i64 } } undef, i64 %{{[0-9]+}}, 0 // CHECK: %{{[0-9]+}} = insertvalue { i64, float, { ptr, i64, i64 } } undef, i64 %{{[0-9]+}}, 0
// CHECK-NEXT: %{{[0-9]+}} = insertvalue { i64, float, { float*, i64, i64 } } %{{[0-9]+}}, float %{{[0-9]+}}, 1 // CHECK-NEXT: %{{[0-9]+}} = insertvalue { i64, float, { ptr, i64, i64 } } %{{[0-9]+}}, float %{{[0-9]+}}, 1
// CHECK-NEXT: %{{[0-9]+}} = insertvalue { i64, float, { float*, i64, i64 } } %{{[0-9]+}}, { float*, i64, i64 } %{{[0-9]+}}, 2 // CHECK-NEXT: %{{[0-9]+}} = insertvalue { i64, float, { ptr, i64, i64 } } %{{[0-9]+}}, { ptr, i64, i64 } %{{[0-9]+}}, 2
// CHECK-NEXT: ret { i64, float, { float*, i64, i64 } } %{{[0-9]+}} // CHECK-NEXT: ret { i64, float, { ptr, i64, i64 } } %{{[0-9]+}}
%3 = llvm.mlir.undef : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)> %3 = llvm.mlir.undef : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)>
%4 = llvm.insertvalue %0, %3[0] : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)> %4 = llvm.insertvalue %0, %3[0] : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)>
%5 = llvm.insertvalue %1, %4[1] : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)> %5 = llvm.insertvalue %1, %4[1] : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)>
%6 = llvm.insertvalue %2, %5[2] : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)> %6 = llvm.insertvalue %2, %5[2] : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)>
llvm.return %6 : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)> llvm.return %6 : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)>
} }
// CHECK-LABEL: define void @multireturn_caller() // CHECK-LABEL: define void @multireturn_caller()
llvm.func @multireturn_caller() { llvm.func @multireturn_caller() {
// CHECK-NEXT: %1 = call { i64, float, { float*, i64, i64 } } @multireturn() // CHECK-NEXT: %1 = call { i64, float, { ptr, i64, i64 } } @multireturn()
// CHECK-NEXT: [[ret0:%[0-9]+]] = extractvalue { i64, float, { float*, i64, i64 } } %1, 0 // CHECK-NEXT: [[ret0:%[0-9]+]] = extractvalue { i64, float, { ptr, i64, i64 } } %1, 0
// CHECK-NEXT: [[ret1:%[0-9]+]] = extractvalue { i64, float, { float*, i64, i64 } } %1, 1 // CHECK-NEXT: [[ret1:%[0-9]+]] = extractvalue { i64, float, { ptr, i64, i64 } } %1, 1
// CHECK-NEXT: [[ret2:%[0-9]+]] = extractvalue { i64, float, { float*, i64, i64 } } %1, 2 // CHECK-NEXT: [[ret2:%[0-9]+]] = extractvalue { i64, float, { ptr, i64, i64 } } %1, 2
%0 = llvm.call @multireturn() : () -> !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)> %0 = llvm.call @multireturn() : () -> !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)>
%1 = llvm.extractvalue %0[0] : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)> %1 = llvm.extractvalue %0[0] : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)>
%2 = llvm.extractvalue %0[1] : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)> %2 = llvm.extractvalue %0[1] : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)>
%3 = llvm.extractvalue %0[2] : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)> %3 = llvm.extractvalue %0[2] : !llvm.struct<(i64, f32, struct<(ptr<f32>, i64, i64)>)>
%4 = llvm.mlir.constant(42) : i64 %4 = llvm.mlir.constant(42) : i64
// CHECK: add i64 [[ret0]], 42 // CHECK: add i64 [[ret0]], 42
%5 = llvm.add %1, %4 : i64 %5 = llvm.add %1, %4 : i64
%6 = llvm.mlir.constant(4.200000e+01 : f32) : f32 %6 = llvm.mlir.constant(4.200000e+01 : f32) : f32
// CHECK: fadd float [[ret1]], 4.200000e+01 // CHECK: fadd float [[ret1]], 4.200000e+01
%7 = llvm.fadd %2, %6 : f32 %7 = llvm.fadd %2, %6 : f32
%8 = llvm.mlir.constant(0 : index) : i64 %8 = llvm.mlir.constant(0 : index) : i64
%9 = llvm.mlir.constant(42 : index) : i64 %9 = llvm.mlir.constant(42 : index) : i64
// CHECK: extractvalue { float*, i64, i64 } [[ret2]], 0 // CHECK: extractvalue { ptr, i64, i64 } [[ret2]], 0
%10 = llvm.extractvalue %3[1] : !llvm.struct<(ptr<f32>, i64, i64)> %10 = llvm.extractvalue %3[1] : !llvm.struct<(ptr<f32>, i64, i64)>
%11 = llvm.mlir.constant(10 : index) : i64 %11 = llvm.mlir.constant(10 : index) : i64
%12 = llvm.extractvalue %3[2] : !llvm.struct<(ptr<f32>, i64, i64)> %12 = llvm.extractvalue %3[2] : !llvm.struct<(ptr<f32>, i64, i64)>
%13 = llvm.mul %8, %10 : i64 %13 = llvm.mul %8, %10 : i64
%14 = llvm.add %13, %8 : i64 %14 = llvm.add %13, %8 : i64
%15 = llvm.mul %14, %11 : i64 %15 = llvm.mul %14, %11 : i64
%16 = llvm.add %15, %8 : i64 %16 = llvm.add %15, %8 : i64
%17 = llvm.mul %16, %12 : i64 %17 = llvm.mul %16, %12 : i64
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines// CHECK-NEXT: fneg float %0
%19 = llvm.fneg %arg0 : f32 %19 = llvm.fneg %arg0 : f32
llvm.return %10 : !llvm.struct<(f32, i32)> llvm.return %10 : !llvm.struct<(f32, i32)>
} }
// CHECK-LABEL: @gep // CHECK-LABEL: @gep
llvm.func @gep(%ptr: !llvm.ptr<struct<(i32, struct<(i32, f32)>)>>, %idx: i64, llvm.func @gep(%ptr: !llvm.ptr<struct<(i32, struct<(i32, f32)>)>>, %idx: i64,
%ptr2: !llvm.ptr<struct<(array<10xf32>)>>) { %ptr2: !llvm.ptr<struct<(array<10xf32>)>>) {
// CHECK: = getelementptr { i32, { i32, float } }, { i32, { i32, float } }* %{{.*}}, i64 %{{.*}}, i32 1, i32 0 // CHECK: = getelementptr { i32, { i32, float } }, ptr %{{.*}}, i64 %{{.*}}, i32 1, i32 0
llvm.getelementptr %ptr[%idx, 1, 0] : (!llvm.ptr<struct<(i32, struct<(i32, f32)>)>>, i64) -> !llvm.ptr<i32> llvm.getelementptr %ptr[%idx, 1, 0] : (!llvm.ptr<struct<(i32, struct<(i32, f32)>)>>, i64) -> !llvm.ptr<i32>
// CHECK: = getelementptr { [10 x float] }, { [10 x float] }* %{{.*}}, i64 %{{.*}}, i32 0, i64 %{{.*}} // CHECK: = getelementptr { [10 x float] }, ptr %{{.*}}, i64 %{{.*}}, i32 0, i64 %{{.*}}
llvm.getelementptr %ptr2[%idx, 0, %idx] : (!llvm.ptr<struct<(array<10xf32>)>>, i64, i64) -> !llvm.ptr<f32> llvm.getelementptr %ptr2[%idx, 0, %idx] : (!llvm.ptr<struct<(array<10xf32>)>>, i64, i64) -> !llvm.ptr<f32>
llvm.return llvm.return
} }
// //
// Indirect function calls // Indirect function calls
// //
// CHECK-LABEL: define void @indirect_const_call(i64 {{%.*}}) // CHECK-LABEL: define void @indirect_const_call(i64 {{%.*}})
llvm.func @indirect_const_call(%arg0: i64) { llvm.func @indirect_const_call(%arg0: i64) {
// CHECK-NEXT: call void @body(i64 %0) // CHECK-NEXT: call void @body(i64 %0)
%0 = llvm.mlir.addressof @body : !llvm.ptr<func<void (i64)>> %0 = llvm.mlir.addressof @body : !llvm.ptr<func<void (i64)>>
llvm.call %0(%arg0) : (i64) -> () llvm.call %0(%arg0) : (i64) -> ()
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
llvm.return llvm.return
} }
// CHECK-LABEL: define i32 @indirect_call(i32 (float)* {{%.*}}, float {{%.*}}) // CHECK-LABEL: define i32 @indirect_call(ptr {{%.*}}, float {{%.*}})
llvm.func @indirect_call(%arg0: !llvm.ptr<func<i32 (f32)>>, %arg1: f32) -> i32 { llvm.func @indirect_call(%arg0: !llvm.ptr<func<i32 (f32)>>, %arg1: f32) -> i32 {
// CHECK-NEXT: %3 = call i32 %0(float %1) // CHECK-NEXT: %3 = call i32 %0(float %1)
%0 = llvm.call %arg0(%arg1) : (f32) -> i32 %0 = llvm.call %arg0(%arg1) : (f32) -> i32
// CHECK-NEXT: ret i32 %3 // CHECK-NEXT: ret i32 %3
llvm.return %0 : i32 llvm.return %0 : i32
} }
// //
Show All 13 Lines// CHECK-NEXT: ret void
llvm.return llvm.return
// CHECK: 5: // CHECK: 5:
^bb2: ^bb2:
// CHECK-NEXT: br label %3 // CHECK-NEXT: br label %3
llvm.br ^bb1(%arg1 : i1) llvm.br ^bb1(%arg1 : i1)
} }
// CHECK-LABEL: define void @llvm_noalias(float* noalias {{%*.}}) // CHECK-LABEL: define void @llvm_noalias(ptr noalias {{%*.}})
llvm.func @llvm_noalias(%arg0: !llvm.ptr<f32> {llvm.noalias}) { llvm.func @llvm_noalias(%arg0: !llvm.ptr<f32> {llvm.noalias}) {
llvm.return llvm.return
} }
// CHECK-LABEL: define void @byvalattr(i32* byval(i32) % // CHECK-LABEL: define void @byvalattr(ptr byval(i32) %
llvm.func @byvalattr(%arg0: !llvm.ptr<i32> {llvm.byval}) { llvm.func @byvalattr(%arg0: !llvm.ptr<i32> {llvm.byval}) {
llvm.return llvm.return
} }
// CHECK-LABEL: define void @sretattr(i32* sret(i32) % // CHECK-LABEL: define void @sretattr(ptr sret(i32) %
llvm.func @sretattr(%arg0: !llvm.ptr<i32> {llvm.sret}) { llvm.func @sretattr(%arg0: !llvm.ptr<i32> {llvm.sret}) {
llvm.return llvm.return
} }
// CHECK-LABEL: define void @nestattr(i32* nest % // CHECK-LABEL: define void @nestattr(ptr nest %
llvm.func @nestattr(%arg0: !llvm.ptr<i32> {llvm.nest}) { llvm.func @nestattr(%arg0: !llvm.ptr<i32> {llvm.nest}) {
llvm.return llvm.return
} }
// CHECK-LABEL: define void @llvm_align(float* align 4 {{%*.}}) // CHECK-LABEL: define void @llvm_align(ptr align 4 {{%*.}})
llvm.func @llvm_align(%arg0: !llvm.ptr<f32> {llvm.align = 4}) { llvm.func @llvm_align(%arg0: !llvm.ptr<f32> {llvm.align = 4}) {
llvm.return llvm.return
} }
// CHECK-LABEL: @llvm_varargs(...) // CHECK-LABEL: @llvm_varargs(...)
llvm.func @llvm_varargs(...) llvm.func @llvm_varargs(...)
llvm.func @intpointerconversion(%arg0 : i32) -> i32 { llvm.func @intpointerconversion(%arg0 : i32) -> i32 {
// CHECK: %2 = inttoptr i32 %0 to i32* // CHECK: %2 = inttoptr i32 %0 to ptr
// CHECK-NEXT: %3 = ptrtoint i32* %2 to i32 // CHECK-NEXT: %3 = ptrtoint ptr %2 to i32
%1 = llvm.inttoptr %arg0 : i32 to !llvm.ptr<i32> %1 = llvm.inttoptr %arg0 : i32 to !llvm.ptr<i32>
%2 = llvm.ptrtoint %1 : !llvm.ptr<i32> to i32 %2 = llvm.ptrtoint %1 : !llvm.ptr<i32> to i32
llvm.return %2 : i32 llvm.return %2 : i32
} }
llvm.func @fpconversion(%arg0 : i32) -> i32 { llvm.func @fpconversion(%arg0 : i32) -> i32 {
// CHECK: %2 = sitofp i32 %0 to float // CHECK: %2 = sitofp i32 %0 to float
// CHECK-NEXT: %3 = fptosi float %2 to i32 // CHECK-NEXT: %3 = fptosi float %2 to i32
// CHECK-NEXT: %4 = uitofp i32 %3 to float // CHECK-NEXT: %4 = uitofp i32 %3 to float
// CHECK-NEXT: %5 = fptoui float %4 to i32 // CHECK-NEXT: %5 = fptoui float %4 to i32
%1 = llvm.sitofp %arg0 : i32 to f32 %1 = llvm.sitofp %arg0 : i32 to f32
%2 = llvm.fptosi %1 : f32 to i32 %2 = llvm.fptosi %1 : f32 to i32
%3 = llvm.uitofp %2 : i32 to f32 %3 = llvm.uitofp %2 : i32 to f32
%4 = llvm.fptoui %3 : f32 to i32 %4 = llvm.fptoui %3 : f32 to i32
llvm.return %4 : i32 llvm.return %4 : i32
} }
// CHECK-LABEL: @addrspace // CHECK-LABEL: @addrspace
llvm.func @addrspace(%arg0 : !llvm.ptr<i32>) -> !llvm.ptr<i32, 2> { llvm.func @addrspace(%arg0 : !llvm.ptr<i32>) -> !llvm.ptr<i32, 2> {
// CHECK: %2 = addrspacecast i32* %0 to i32 addrspace(2)* // CHECK: %2 = addrspacecast ptr %0 to ptr addrspace(2)
%1 = llvm.addrspacecast %arg0 : !llvm.ptr<i32> to !llvm.ptr<i32, 2> %1 = llvm.addrspacecast %arg0 : !llvm.ptr<i32> to !llvm.ptr<i32, 2>
llvm.return %1 : !llvm.ptr<i32, 2> llvm.return %1 : !llvm.ptr<i32, 2>
} }
llvm.func @stringconstant() -> !llvm.array<12 x i8> { llvm.func @stringconstant() -> !llvm.array<12 x i8> {
%1 = llvm.mlir.constant("Hello world!") : !llvm.array<12 x i8> %1 = llvm.mlir.constant("Hello world!") : !llvm.array<12 x i8>
// CHECK: ret [12 x i8] c"Hello world!" // CHECK: ret [12 x i8] c"Hello world!"
llvm.return %1 : !llvm.array<12 x i8> llvm.return %1 : !llvm.array<12 x i8>
▲ Show 20 Lines • Show All 142 Lines • ▼ Show 20 Lines// CHECK: trunc i32 {{.*}} to i16
%2 = llvm.trunc %a : i32 to i16 %2 = llvm.trunc %a : i32 to i16
llvm.return llvm.return
} }
// Check that the auxiliary `null` operation is converted into a `null` value. // Check that the auxiliary `null` operation is converted into a `null` value.
// CHECK-LABEL: @null // CHECK-LABEL: @null
llvm.func @null() -> !llvm.ptr<i32> { llvm.func @null() -> !llvm.ptr<i32> {
%0 = llvm.mlir.null : !llvm.ptr<i32> %0 = llvm.mlir.null : !llvm.ptr<i32>
// CHECK: ret i32* null // CHECK: ret ptr null
llvm.return %0 : !llvm.ptr<i32> llvm.return %0 : !llvm.ptr<i32>
} }
// Check that dense elements attributes are exported properly in constants. // Check that dense elements attributes are exported properly in constants.
// CHECK-LABEL: @elements_constant_3d_vector // CHECK-LABEL: @elements_constant_3d_vector
llvm.func @elements_constant_3d_vector() -> !llvm.array<2 x array<2 x vector<2 x i32>>> { llvm.func @elements_constant_3d_vector() -> !llvm.array<2 x array<2 x vector<2 x i32>>> {
// CHECK: ret [2 x [2 x <2 x i32>]] // CHECK: ret [2 x [2 x <2 x i32>]]
// CHECK-SAME: {{\[}}[2 x <2 x i32>] [<2 x i32> <i32 1, i32 2>, <2 x i32> <i32 3, i32 4>], // CHECK-SAME: {{\[}}[2 x <2 x i32>] [<2 x i32> <i32 1, i32 2>, <2 x i32> <i32 3, i32 4>],
Show All 10 Linesllvm.func @elements_constant_3d_array() -> !llvm.array<2 x array<2 x array<2 x i32>>> {
%0 = llvm.mlir.constant(dense<[[[1, 2], [3, 4]], [[42, 43], [44, 45]]]> : tensor<2x2x2xi32>) : !llvm.array<2 x array<2 x array<2 x i32>>> %0 = llvm.mlir.constant(dense<[[[1, 2], [3, 4]], [[42, 43], [44, 45]]]> : tensor<2x2x2xi32>) : !llvm.array<2 x array<2 x array<2 x i32>>>
llvm.return %0 : !llvm.array<2 x array<2 x array<2 x i32>>> llvm.return %0 : !llvm.array<2 x array<2 x array<2 x i32>>>
} }
// CHECK-LABEL: @atomicrmw // CHECK-LABEL: @atomicrmw
llvm.func @atomicrmw( llvm.func @atomicrmw(
%f32_ptr : !llvm.ptr<f32>, %f32 : f32, %f32_ptr : !llvm.ptr<f32>, %f32 : f32,
%i32_ptr : !llvm.ptr<i32>, %i32 : i32) { %i32_ptr : !llvm.ptr<i32>, %i32 : i32) {
// CHECK: atomicrmw fadd float* %{{.*}}, float %{{.*}} monotonic // CHECK: atomicrmw fadd ptr %{{.*}}, float %{{.*}} monotonic
%0 = llvm.atomicrmw fadd %f32_ptr, %f32 monotonic : f32 %0 = llvm.atomicrmw fadd %f32_ptr, %f32 monotonic : f32
// CHECK: atomicrmw fsub float* %{{.*}}, float %{{.*}} monotonic // CHECK: atomicrmw fsub ptr %{{.*}}, float %{{.*}} monotonic
%1 = llvm.atomicrmw fsub %f32_ptr, %f32 monotonic : f32 %1 = llvm.atomicrmw fsub %f32_ptr, %f32 monotonic : f32
// CHECK: atomicrmw xchg float* %{{.*}}, float %{{.*}} monotonic // CHECK: atomicrmw xchg ptr %{{.*}}, float %{{.*}} monotonic
%2 = llvm.atomicrmw xchg %f32_ptr, %f32 monotonic : f32 %2 = llvm.atomicrmw xchg %f32_ptr, %f32 monotonic : f32
// CHECK: atomicrmw add i32* %{{.*}}, i32 %{{.*}} acquire // CHECK: atomicrmw add ptr %{{.*}}, i32 %{{.*}} acquire
%3 = llvm.atomicrmw add %i32_ptr, %i32 acquire : i32 %3 = llvm.atomicrmw add %i32_ptr, %i32 acquire : i32
// CHECK: atomicrmw sub i32* %{{.*}}, i32 %{{.*}} release // CHECK: atomicrmw sub ptr %{{.*}}, i32 %{{.*}} release
%4 = llvm.atomicrmw sub %i32_ptr, %i32 release : i32 %4 = llvm.atomicrmw sub %i32_ptr, %i32 release : i32
// CHECK: atomicrmw and i32* %{{.*}}, i32 %{{.*}} acq_rel // CHECK: atomicrmw and ptr %{{.*}}, i32 %{{.*}} acq_rel
%5 = llvm.atomicrmw _and %i32_ptr, %i32 acq_rel : i32 %5 = llvm.atomicrmw _and %i32_ptr, %i32 acq_rel : i32
// CHECK: atomicrmw nand i32* %{{.*}}, i32 %{{.*}} seq_cst // CHECK: atomicrmw nand ptr %{{.*}}, i32 %{{.*}} seq_cst
%6 = llvm.atomicrmw nand %i32_ptr, %i32 seq_cst : i32 %6 = llvm.atomicrmw nand %i32_ptr, %i32 seq_cst : i32
// CHECK: atomicrmw or i32* %{{.*}}, i32 %{{.*}} monotonic // CHECK: atomicrmw or ptr %{{.*}}, i32 %{{.*}} monotonic
%7 = llvm.atomicrmw _or %i32_ptr, %i32 monotonic : i32 %7 = llvm.atomicrmw _or %i32_ptr, %i32 monotonic : i32
// CHECK: atomicrmw xor i32* %{{.*}}, i32 %{{.*}} monotonic // CHECK: atomicrmw xor ptr %{{.*}}, i32 %{{.*}} monotonic
%8 = llvm.atomicrmw _xor %i32_ptr, %i32 monotonic : i32 %8 = llvm.atomicrmw _xor %i32_ptr, %i32 monotonic : i32
// CHECK: atomicrmw max i32* %{{.*}}, i32 %{{.*}} monotonic // CHECK: atomicrmw max ptr %{{.*}}, i32 %{{.*}} monotonic
%9 = llvm.atomicrmw max %i32_ptr, %i32 monotonic : i32 %9 = llvm.atomicrmw max %i32_ptr, %i32 monotonic : i32
// CHECK: atomicrmw min i32* %{{.*}}, i32 %{{.*}} monotonic // CHECK: atomicrmw min ptr %{{.*}}, i32 %{{.*}} monotonic
%10 = llvm.atomicrmw min %i32_ptr, %i32 monotonic : i32 %10 = llvm.atomicrmw min %i32_ptr, %i32 monotonic : i32
// CHECK: atomicrmw umax i32* %{{.*}}, i32 %{{.*}} monotonic // CHECK: atomicrmw umax ptr %{{.*}}, i32 %{{.*}} monotonic
%11 = llvm.atomicrmw umax %i32_ptr, %i32 monotonic : i32 %11 = llvm.atomicrmw umax %i32_ptr, %i32 monotonic : i32
// CHECK: atomicrmw umin i32* %{{.*}}, i32 %{{.*}} monotonic // CHECK: atomicrmw umin ptr %{{.*}}, i32 %{{.*}} monotonic
%12 = llvm.atomicrmw umin %i32_ptr, %i32 monotonic : i32 %12 = llvm.atomicrmw umin %i32_ptr, %i32 monotonic : i32
llvm.return llvm.return
} }
// CHECK-LABEL: @cmpxchg // CHECK-LABEL: @cmpxchg
llvm.func @cmpxchg(%ptr : !llvm.ptr<i32>, %cmp : i32, %val: i32) { llvm.func @cmpxchg(%ptr : !llvm.ptr<i32>, %cmp : i32, %val: i32) {
// CHECK: cmpxchg i32* %{{.*}}, i32 %{{.*}}, i32 %{{.*}} acq_rel monotonic // CHECK: cmpxchg ptr %{{.*}}, i32 %{{.*}}, i32 %{{.*}} acq_rel monotonic
%0 = llvm.cmpxchg %ptr, %cmp, %val acq_rel monotonic : i32 %0 = llvm.cmpxchg %ptr, %cmp, %val acq_rel monotonic : i32
// CHECK: %{{[0-9]+}} = extractvalue { i32, i1 } %{{[0-9]+}}, 0 // CHECK: %{{[0-9]+}} = extractvalue { i32, i1 } %{{[0-9]+}}, 0
%1 = llvm.extractvalue %0[0] : !llvm.struct<(i32, i1)> %1 = llvm.extractvalue %0[0] : !llvm.struct<(i32, i1)>
// CHECK: %{{[0-9]+}} = extractvalue { i32, i1 } %{{[0-9]+}}, 1 // CHECK: %{{[0-9]+}} = extractvalue { i32, i1 } %{{[0-9]+}}, 1
%2 = llvm.extractvalue %0[1] : !llvm.struct<(i32, i1)> %2 = llvm.extractvalue %0[1] : !llvm.struct<(i32, i1)>
llvm.return llvm.return
} }
llvm.mlir.global external constant @_ZTIi() : !llvm.ptr<i8> llvm.mlir.global external constant @_ZTIi() : !llvm.ptr<i8>
llvm.func @foo(!llvm.ptr<i8>) llvm.func @foo(!llvm.ptr<i8>)
llvm.func @bar(!llvm.ptr<i8>) -> !llvm.ptr<i8> llvm.func @bar(!llvm.ptr<i8>) -> !llvm.ptr<i8>
llvm.func @__gxx_personality_v0(...) -> i32 llvm.func @__gxx_personality_v0(...) -> i32
// CHECK-LABEL: @invokeLandingpad // CHECK-LABEL: @invokeLandingpad
llvm.func @invokeLandingpad() -> i32 attributes { personality = @__gxx_personality_v0 } { llvm.func @invokeLandingpad() -> i32 attributes { personality = @__gxx_personality_v0 } {
// CHECK: %[[a1:[0-9]+]] = alloca i8 // CHECK: %[[a1:[0-9]+]] = alloca i8
%0 = llvm.mlir.constant(0 : i32) : i32 %0 = llvm.mlir.constant(0 : i32) : i32
%1 = llvm.mlir.constant(dense<0> : vector<1xi8>) : !llvm.array<1 x i8> %1 = llvm.mlir.constant(dense<0> : vector<1xi8>) : !llvm.array<1 x i8>
%2 = llvm.mlir.addressof @_ZTIi : !llvm.ptr<ptr<i8>> %2 = llvm.mlir.addressof @_ZTIi : !llvm.ptr<ptr<i8>>
%3 = llvm.bitcast %2 : !llvm.ptr<ptr<i8>> to !llvm.ptr<i8> %3 = llvm.bitcast %2 : !llvm.ptr<ptr<i8>> to !llvm.ptr<i8>
%4 = llvm.mlir.null : !llvm.ptr<ptr<i8>> %4 = llvm.mlir.null : !llvm.ptr<ptr<i8>>
%5 = llvm.mlir.constant(1 : i32) : i32 %5 = llvm.mlir.constant(1 : i32) : i32
%6 = llvm.alloca %5 x i8 : (i32) -> !llvm.ptr<i8> %6 = llvm.alloca %5 x i8 : (i32) -> !llvm.ptr<i8>
// CHECK: invoke void @foo(i8* %[[a1]]) // CHECK: invoke void @foo(ptr %[[a1]])
// CHECK-NEXT: to label %[[normal:[0-9]+]] unwind label %[[unwind:[0-9]+]] // CHECK-NEXT: to label %[[normal:[0-9]+]] unwind label %[[unwind:[0-9]+]]
llvm.invoke @foo(%6) to ^bb2 unwind ^bb1 : (!llvm.ptr<i8>) -> () llvm.invoke @foo(%6) to ^bb2 unwind ^bb1 : (!llvm.ptr<i8>) -> ()
// CHECK: [[unwind]]: // CHECK: [[unwind]]:
^bb1: ^bb1:
// CHECK: %{{[0-9]+}} = landingpad { i8*, i32 } // CHECK: %{{[0-9]+}} = landingpad { ptr, i32 }
// CHECK-NEXT: catch i8** null // CHECK-NEXT: catch ptr null
// CHECK-NEXT: catch i8* bitcast (i8** @_ZTIi to i8*) // CHECK-NEXT: catch ptr @_ZTIi
// CHECK-NEXT: filter [1 x i8] zeroinitializer // CHECK-NEXT: filter [1 x i8] zeroinitializer
%7 = llvm.landingpad (catch %4 : !llvm.ptr<ptr<i8>>) (catch %3 : !llvm.ptr<i8>) (filter %1 : !llvm.array<1 x i8>) : !llvm.struct<(ptr<i8>, i32)> %7 = llvm.landingpad (catch %4 : !llvm.ptr<ptr<i8>>) (catch %3 : !llvm.ptr<i8>) (filter %1 : !llvm.array<1 x i8>) : !llvm.struct<(ptr<i8>, i32)>
// CHECK: br label %[[final:[0-9]+]] // CHECK: br label %[[final:[0-9]+]]
llvm.br ^bb3 llvm.br ^bb3
// CHECK: [[normal]]: // CHECK: [[normal]]:
// CHECK-NEXT: ret i32 1 // CHECK-NEXT: ret i32 1
^bb2: // 2 preds: ^bb0, ^bb3 ^bb2: // 2 preds: ^bb0, ^bb3
llvm.return %5 : i32 llvm.return %5 : i32
// CHECK: [[final]]: // CHECK: [[final]]:
// CHECK-NEXT: %{{[0-9]+}} = invoke i8* @bar(i8* %[[a1]]) // CHECK-NEXT: %{{[0-9]+}} = invoke ptr @bar(ptr %[[a1]])
// CHECK-NEXT: to label %[[normal]] unwind label %[[unwind]] // CHECK-NEXT: to label %[[normal]] unwind label %[[unwind]]
^bb3: // pred: ^bb1 ^bb3: // pred: ^bb1
%8 = llvm.invoke @bar(%6) to ^bb2 unwind ^bb1 : (!llvm.ptr<i8>) -> !llvm.ptr<i8> %8 = llvm.invoke @bar(%6) to ^bb2 unwind ^bb1 : (!llvm.ptr<i8>) -> !llvm.ptr<i8>
} }
// ----- // -----
llvm.func @foo() -> i8 llvm.func @foo() -> i8
llvm.func @__gxx_personality_v0(...) -> i32 llvm.func @__gxx_personality_v0(...) -> i32
// CHECK-LABEL: @invoke_result // CHECK-LABEL: @invoke_result
// CHECK-SAME: %[[a0:[0-9]+]] // CHECK-SAME: %[[a0:[0-9]+]]
llvm.func @invoke_result(%arg0 : !llvm.ptr<i8>) attributes { personality = @__gxx_personality_v0 } { llvm.func @invoke_result(%arg0 : !llvm.ptr<i8>) attributes { personality = @__gxx_personality_v0 } {
// CHECK: %[[a1:[0-9]+]] = invoke i8 @foo() // CHECK: %[[a1:[0-9]+]] = invoke i8 @foo()
// CHECK-NEXT: to label %[[normal:[0-9]+]] unwind label %[[unwind:[0-9]+]] // CHECK-NEXT: to label %[[normal:[0-9]+]] unwind label %[[unwind:[0-9]+]]
%0 = llvm.invoke @foo() to ^bb1 unwind ^bb2 : () -> i8 %0 = llvm.invoke @foo() to ^bb1 unwind ^bb2 : () -> i8
// CHECK: [[normal]]: // CHECK: [[normal]]:
// CHECK-NEXT: store i8 %[[a1]], i8* %[[a0]] // CHECK-NEXT: store i8 %[[a1]], ptr %[[a0]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
^bb1: ^bb1:
llvm.store %0, %arg0 : !llvm.ptr<i8> llvm.store %0, %arg0 : !llvm.ptr<i8>
llvm.return llvm.return
// CHECK: [[unwind]]: // CHECK: [[unwind]]:
// CHECK-NEXT: landingpad { i8*, i32 } // CHECK-NEXT: landingpad { ptr, i32 }
// CHECK-NEXT: cleanup // CHECK-NEXT: cleanup
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
^bb2: ^bb2:
%7 = llvm.landingpad cleanup : !llvm.struct<(ptr<i8>, i32)> %7 = llvm.landingpad cleanup : !llvm.struct<(ptr<i8>, i32)>
llvm.return llvm.return
} }
// ----- // -----
Show All 10 Lines
// CHECK: [[normal]]: // CHECK: [[normal]]:
// CHECK-NEXT: %[[a1:[0-9]+]] = phi i32 [ 1, %[[unwind]] ], [ 0, %0 ] // CHECK-NEXT: %[[a1:[0-9]+]] = phi i32 [ 1, %[[unwind]] ], [ 0, %0 ]
// CHECK-NEXT: ret i32 %[[a1]] // CHECK-NEXT: ret i32 %[[a1]]
^bb1(%1 : i32): ^bb1(%1 : i32):
llvm.return %1 : i32 llvm.return %1 : i32
// CHECK: [[unwind]]: // CHECK: [[unwind]]:
// CHECK-NEXT: landingpad { i8*, i32 } // CHECK-NEXT: landingpad { ptr, i32 }
// CHECK-NEXT: cleanup // CHECK-NEXT: cleanup
// CHECK-NEXT: br label %[[normal]] // CHECK-NEXT: br label %[[normal]]
^bb2: ^bb2:
%2 = llvm.landingpad cleanup : !llvm.struct<(ptr<i8>, i32)> %2 = llvm.landingpad cleanup : !llvm.struct<(ptr<i8>, i32)>
%3 = llvm.mlir.constant(1 : i32) : i32 %3 = llvm.mlir.constant(1 : i32) : i32
llvm.br ^bb1(%3 : i32) llvm.br ^bb1(%3 : i32)
} }
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
llvm.mlir.global internal constant @taker_of_address() : !llvm.ptr<func<void ()>> { llvm.mlir.global internal constant @taker_of_address() : !llvm.ptr<func<void ()>> {
%0 = llvm.mlir.addressof @address_taken : !llvm.ptr<func<void ()>> %0 = llvm.mlir.addressof @address_taken : !llvm.ptr<func<void ()>>
llvm.return %0 : !llvm.ptr<func<void ()>> llvm.return %0 : !llvm.ptr<func<void ()>>
} }
// ----- // -----
// CHECK: @forward_use_of_address = linkonce global float* @address_declared_after_use // CHECK: @forward_use_of_address = linkonce global ptr @address_declared_after_use
llvm.mlir.global linkonce @forward_use_of_address() : !llvm.ptr<f32> { llvm.mlir.global linkonce @forward_use_of_address() : !llvm.ptr<f32> {
%0 = llvm.mlir.addressof @address_declared_after_use : !llvm.ptr<f32> %0 = llvm.mlir.addressof @address_declared_after_use : !llvm.ptr<f32>
llvm.return %0 : !llvm.ptr<f32> llvm.return %0 : !llvm.ptr<f32>
} }
llvm.mlir.global linkonce @address_declared_after_use() : f32 llvm.mlir.global linkonce @address_declared_after_use() : f32
// ----- // -----
// CHECK: @take_self_address = linkonce global { i32, i32* } {{.*}} { i32, i32* }* @take_self_address // CHECK: @take_self_address = linkonce global { i32, ptr } {{.*}} ptr @take_self_address
llvm.mlir.global linkonce @take_self_address() : !llvm.struct<(i32, !llvm.ptr<i32>)> { llvm.mlir.global linkonce @take_self_address() : !llvm.struct<(i32, !llvm.ptr<i32>)> {
%z32 = llvm.mlir.constant(0 : i32) : i32 %z32 = llvm.mlir.constant(0 : i32) : i32
%0 = llvm.mlir.undef : !llvm.struct<(i32, !llvm.ptr<i32>)> %0 = llvm.mlir.undef : !llvm.struct<(i32, !llvm.ptr<i32>)>
%1 = llvm.mlir.addressof @take_self_address : !llvm.ptr<!llvm.struct<(i32, !llvm.ptr<i32>)>> %1 = llvm.mlir.addressof @take_self_address : !llvm.ptr<!llvm.struct<(i32, !llvm.ptr<i32>)>>
%2 = llvm.getelementptr %1[%z32, 0] : (!llvm.ptr<!llvm.struct<(i32, !llvm.ptr<i32>)>>, i32) -> !llvm.ptr<i32> %2 = llvm.getelementptr %1[%z32, 0] : (!llvm.ptr<!llvm.struct<(i32, !llvm.ptr<i32>)>>, i32) -> !llvm.ptr<i32>
%3 = llvm.insertvalue %z32, %0[0 : i32] : !llvm.struct<(i32, !llvm.ptr<i32>)> %3 = llvm.insertvalue %z32, %0[0 : i32] : !llvm.struct<(i32, !llvm.ptr<i32>)>
%4 = llvm.insertvalue %2, %3[1 : i32] : !llvm.struct<(i32, !llvm.ptr<i32>)> %4 = llvm.insertvalue %2, %3[1 : i32] : !llvm.struct<(i32, !llvm.ptr<i32>)>
llvm.return %4 : !llvm.struct<(i32, !llvm.ptr<i32>)> llvm.return %4 : !llvm.struct<(i32, !llvm.ptr<i32>)>
} }
// ----- // -----
// CHECK: @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 0, void ()* @foo, i8* null }] // CHECK: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 0, ptr @foo, ptr null }]
llvm.mlir.global_ctors { ctors = [@foo], priorities = [0 : i32]} llvm.mlir.global_ctors { ctors = [@foo], priorities = [0 : i32]}
llvm.func @foo() { llvm.func @foo() {
llvm.return llvm.return
} }
// ----- // -----
// CHECK: @llvm.global_dtors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 0, void ()* @foo, i8* null }] // CHECK: @llvm.global_dtors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 0, ptr @foo, ptr null }]
llvm.mlir.global_dtors { dtors = [@foo], priorities = [0 : i32]} llvm.mlir.global_dtors { dtors = [@foo], priorities = [0 : i32]}
llvm.func @foo() { llvm.func @foo() {
llvm.return llvm.return
} }
// ----- // -----
Show All 10 Lines
// CHECK: ![[NODE]] = !{!"branch_weights", i32 5, i32 10} // CHECK: ![[NODE]] = !{!"branch_weights", i32 5, i32 10}
// ----- // -----
llvm.func @volatile_store_and_load() { llvm.func @volatile_store_and_load() {
%val = llvm.mlir.constant(5 : i32) : i32 %val = llvm.mlir.constant(5 : i32) : i32
%size = llvm.mlir.constant(1 : i64) : i64 %size = llvm.mlir.constant(1 : i64) : i64
%0 = llvm.alloca %size x i32 : (i64) -> (!llvm.ptr<i32>) %0 = llvm.alloca %size x i32 : (i64) -> (!llvm.ptr<i32>)
// CHECK: store volatile i32 5, i32* %{{.*}} // CHECK: store volatile i32 5, ptr %{{.*}}
llvm.store volatile %val, %0 : !llvm.ptr<i32> llvm.store volatile %val, %0 : !llvm.ptr<i32>
// CHECK: %{{.*}} = load volatile i32, i32* %{{.*}} // CHECK: %{{.*}} = load volatile i32, ptr %{{.*}}
%1 = llvm.load volatile %0: !llvm.ptr<i32> %1 = llvm.load volatile %0: !llvm.ptr<i32>
llvm.return llvm.return
} }
// ----- // -----
// Check that nontemporal attribute is exported as metadata node. // Check that nontemporal attribute is exported as metadata node.
llvm.func @nontemporal_store_and_load() { llvm.func @nontemporal_store_and_load() {
▲ Show 20 Lines • Show All 181 Lines • ▼ Show 20 Lines llvm.func @loopOptions(%arg1 : i32, %arg2 : i32) {
%4 = llvm.alloca %arg1 x i32 : (i32) -> (!llvm.ptr<i32>) %4 = llvm.alloca %arg1 x i32 : (i32) -> (!llvm.ptr<i32>)
llvm.br ^bb3(%0 : i32) llvm.br ^bb3(%0 : i32)
^bb3(%1: i32): ^bb3(%1: i32):
%2 = llvm.icmp "slt" %1, %arg1 : i32 %2 = llvm.icmp "slt" %1, %arg1 : i32
// CHECK: br i1 {{.*}} !llvm.loop ![[LOOP_NODE:[0-9]+]] // CHECK: br i1 {{.*}} !llvm.loop ![[LOOP_NODE:[0-9]+]]
llvm.cond_br %2, ^bb4, ^bb5 {llvm.loop = {parallel_access = [@metadata::@group1, @metadata::@group2], options = #llvm.loopopts<disable_licm = true, disable_unroll = true, interleave_count = 1, disable_pipeline = true, pipeline_initiation_interval = 2>}} llvm.cond_br %2, ^bb4, ^bb5 {llvm.loop = {parallel_access = [@metadata::@group1, @metadata::@group2], options = #llvm.loopopts<disable_licm = true, disable_unroll = true, interleave_count = 1, disable_pipeline = true, pipeline_initiation_interval = 2>}}
^bb4: ^bb4:
%3 = llvm.add %1, %arg2 : i32 %3 = llvm.add %1, %arg2 : i32
// CHECK: = load i32, i32* %{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE:[0-9]+]] // CHECK: = load i32, ptr %{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE:[0-9]+]]
%5 = llvm.load %4 { access_groups = [@metadata::@group1, @metadata::@group2] } : !llvm.ptr<i32> %5 = llvm.load %4 { access_groups = [@metadata::@group1, @metadata::@group2] } : !llvm.ptr<i32>
// CHECK: br label {{.*}} !llvm.loop ![[LOOP_NODE]] // CHECK: br label {{.*}} !llvm.loop ![[LOOP_NODE]]
llvm.br ^bb3(%3 : i32) {llvm.loop = {parallel_access = [@metadata::@group1, @metadata::@group2], options = #llvm.loopopts<disable_unroll = true, disable_licm = true, interleave_count = 1, disable_pipeline = true, pipeline_initiation_interval = 2>}} llvm.br ^bb3(%3 : i32) {llvm.loop = {parallel_access = [@metadata::@group1, @metadata::@group2], options = #llvm.loopopts<disable_unroll = true, disable_licm = true, interleave_count = 1, disable_pipeline = true, pipeline_initiation_interval = 2>}}
^bb5: ^bb5:
llvm.return llvm.return
} }
llvm.metadata @metadata { llvm.metadata @metadata {
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mlir/test/Target/LLVMIR/nvvmir.mlir

Show First 20 Lines • Show All 227 Lines • ▼ Show 20 Lines %0 = nvvm.mma.sync A[%a0, %a1] B[%b0] C[%c0, %c1, %c2, %c3]
shape = {m = 16 : i32, n = 8 : i32, k = 4 : i32}} : (i32, i32, f32) -> !llvm.struct<(f32, f32, f32, f32)> shape = {m = 16 : i32, n = 8 : i32, k = 4 : i32}} : (i32, i32, f32) -> !llvm.struct<(f32, f32, f32, f32)>
llvm.return %0 : !llvm.struct<(f32, f32, f32, f32)> llvm.return %0 : !llvm.struct<(f32, f32, f32, f32)>
} }
// The test below checks the correct mapping of the nvvm.wmma.*.load.* op to the correct intrinsic // The test below checks the correct mapping of the nvvm.wmma.*.load.* op to the correct intrinsic
// in the LLVM NVPTX backend. // in the LLVM NVPTX backend.
// CHECK-LABEL: @gpu_wmma_load_op // CHECK-LABEL: @gpu_wmma_load_op
llvm.func @gpu_wmma_load_op(%arg0: !llvm.ptr<i32, 3>, %arg1: i32) { llvm.func @gpu_wmma_load_op(%arg0: !llvm.ptr<i32, 3>, %arg1: i32) {
// CHECK: call { <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half> } @llvm.nvvm.wmma.m16n16k16.load.a.row.stride.f16.p3i32(i32 addrspace(3)* %{{.*}}, i32 %{{.*}}) // CHECK: call { <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half> } @llvm.nvvm.wmma.m16n16k16.load.a.row.stride.f16.p3(ptr addrspace(3) %{{.*}}, i32 %{{.*}})
%0 = nvvm.wmma.load %arg0, %arg1 %0 = nvvm.wmma.load %arg0, %arg1
{eltype = #nvvm.mma_type<f16>, frag = #nvvm.mma_frag<a>, k = 16 : i32, layout = #nvvm.mma_layout<row>, m = 16 : i32, n = 16 : i32} {eltype = #nvvm.mma_type<f16>, frag = #nvvm.mma_frag<a>, k = 16 : i32, layout = #nvvm.mma_layout<row>, m = 16 : i32, n = 16 : i32}
: (!llvm.ptr<i32, 3>) -> !llvm.struct<(vector<2xf16>, vector<2xf16>, vector<2xf16>, vector<2xf16>, vector<2xf16>, vector<2xf16>, vector<2xf16>, vector<2xf16>)> : (!llvm.ptr<i32, 3>) -> !llvm.struct<(vector<2xf16>, vector<2xf16>, vector<2xf16>, vector<2xf16>, vector<2xf16>, vector<2xf16>, vector<2xf16>, vector<2xf16>)>
llvm.return llvm.return
} }
// The test below checks the correct mapping of the nvvm.wmma.*.store.* op to the correct intrinsic // The test below checks the correct mapping of the nvvm.wmma.*.store.* op to the correct intrinsic
// in the LLVM NVPTX backend. // in the LLVM NVPTX backend.
// CHECK-LABEL: @gpu_wmma_store_op // CHECK-LABEL: @gpu_wmma_store_op
llvm.func @gpu_wmma_store_op(%arg0: !llvm.ptr<i32, 3>, %arg1: i32, llvm.func @gpu_wmma_store_op(%arg0: !llvm.ptr<i32, 3>, %arg1: i32,
%arg2: vector<2 x f16>, %arg3: vector<2 x f16>, %arg2: vector<2 x f16>, %arg3: vector<2 x f16>,
%arg4: vector<2 xf16>, %arg5: vector<2 x f16>) { %arg4: vector<2 xf16>, %arg5: vector<2 x f16>) {
// CHECK: call void @llvm.nvvm.wmma.m16n16k16.store.d.row.stride.f16.p3i32(i32 addrspace(3)* %{{.*}}, <2 x half> {{.*}}, <2 x half> %{{.*}}, <2 x half> %{{.*}}, <2 x half> %{{.*}}, i32 %{{.*}}) // CHECK: call void @llvm.nvvm.wmma.m16n16k16.store.d.row.stride.f16.p3(ptr addrspace(3) %{{.*}}, <2 x half> {{.*}}, <2 x half> %{{.*}}, <2 x half> %{{.*}}, <2 x half> %{{.*}}, i32 %{{.*}})
nvvm.wmma.store %arg0, %arg1, %arg2, %arg3, %arg4, %arg5 nvvm.wmma.store %arg0, %arg1, %arg2, %arg3, %arg4, %arg5
{eltype = #nvvm.mma_type<f16>, k = 16 : i32, layout = #nvvm.mma_layout<row>, m = 16 : i32, n = 16 : i32} {eltype = #nvvm.mma_type<f16>, k = 16 : i32, layout = #nvvm.mma_layout<row>, m = 16 : i32, n = 16 : i32}
: !llvm.ptr<i32, 3>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16> : !llvm.ptr<i32, 3>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>
llvm.return llvm.return
} }
// The test below checks the correct mapping of the nvvm.wmma.*.mma.* op to the correct intrinsic // The test below checks the correct mapping of the nvvm.wmma.*.mma.* op to the correct intrinsic
// in the LLVM NVPTX backend. // in the LLVM NVPTX backend.
Show All 16 Lines : (vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>,
vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>,
vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>) vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>)
-> !llvm.struct<(vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>)> -> !llvm.struct<(vector<2 x f16>, vector<2 x f16>, vector<2 x f16>, vector<2 x f16>)>
llvm.return llvm.return
} }
// CHECK-LABEL: @nvvm_wmma_load_tf32 // CHECK-LABEL: @nvvm_wmma_load_tf32
llvm.func @nvvm_wmma_load_tf32(%arg0: !llvm.ptr<i32>, %arg1 : i32) { llvm.func @nvvm_wmma_load_tf32(%arg0: !llvm.ptr<i32>, %arg1 : i32) {
// CHECK: call { i32, i32, i32, i32 } @llvm.nvvm.wmma.m16n16k8.load.a.row.stride.tf32.p0i32(i32* %{{.*}}, i32 %{{.*}}) // CHECK: call { i32, i32, i32, i32 } @llvm.nvvm.wmma.m16n16k8.load.a.row.stride.tf32.p0(ptr %{{.*}}, i32 %{{.*}})
%0 = nvvm.wmma.load %arg0, %arg1 %0 = nvvm.wmma.load %arg0, %arg1
{eltype = #nvvm.mma_type<tf32>, frag = #nvvm.mma_frag<a>, k = 8 : i32, layout = #nvvm.mma_layout<row>, m = 16 : i32, n = 16 : i32} {eltype = #nvvm.mma_type<tf32>, frag = #nvvm.mma_frag<a>, k = 8 : i32, layout = #nvvm.mma_layout<row>, m = 16 : i32, n = 16 : i32}
: (!llvm.ptr<i32>) -> !llvm.struct<(i32, i32, i32, i32)> : (!llvm.ptr<i32>) -> !llvm.struct<(i32, i32, i32, i32)>
llvm.return llvm.return
} }
// CHECK-LABEL: @nvvm_wmma_mma // CHECK-LABEL: @nvvm_wmma_mma
llvm.func @nvvm_wmma_mma(%0 : i32, %1 : i32, %2 : i32, %3 : i32, %4 : i32, %5 : i32, llvm.func @nvvm_wmma_mma(%0 : i32, %1 : i32, %2 : i32, %3 : i32, %4 : i32, %5 : i32,
%6 : i32, %7 : i32, %8 : f32, %9 : f32, %10 : f32, %6 : i32, %7 : i32, %8 : f32, %9 : f32, %10 : f32,
%11 : f32, %12 : f32, %13 : f32, %14 : f32, %15 : f32) { %11 : f32, %12 : f32, %13 : f32, %14 : f32, %15 : f32) {
// CHECK: { float, float, float, float, float, float, float, float } @llvm.nvvm.wmma.m16n16k8.mma.row.row.tf32(i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}) // CHECK: { float, float, float, float, float, float, float, float } @llvm.nvvm.wmma.m16n16k8.mma.row.row.tf32(i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}})
%r = nvvm.wmma.mma %0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15 %r = nvvm.wmma.mma %0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15
{eltypeA = #nvvm.mma_type<tf32>, eltypeB = #nvvm.mma_type<f32>, k = 8 : i32, layoutA = #nvvm.mma_layout<row>, layoutB = #nvvm.mma_layout<row>, m = 16 : i32, n = 16 : i32} {eltypeA = #nvvm.mma_type<tf32>, eltypeB = #nvvm.mma_type<f32>, k = 8 : i32, layoutA = #nvvm.mma_layout<row>, layoutB = #nvvm.mma_layout<row>, m = 16 : i32, n = 16 : i32}
: (i32, i32, i32, i32, i32, i32, i32, i32, f32, f32, f32, f32, f32, f32, f32, f32) : (i32, i32, i32, i32, i32, i32, i32, i32, f32, f32, f32, f32, f32, f32, f32, f32)
-> !llvm.struct<(f32, f32, f32, f32, f32, f32, f32, f32)> -> !llvm.struct<(f32, f32, f32, f32, f32, f32, f32, f32)>
llvm.return llvm.return
} }
// CHECK-LABEL: @cp_async // CHECK-LABEL: @cp_async
llvm.func @cp_async(%arg0: !llvm.ptr<i8, 3>, %arg1: !llvm.ptr<i8, 1>) { llvm.func @cp_async(%arg0: !llvm.ptr<i8, 3>, %arg1: !llvm.ptr<i8, 1>) {
// CHECK: call void @llvm.nvvm.cp.async.ca.shared.global.4(i8 addrspace(3)* %{{.*}}, i8 addrspace(1)* %{{.*}}) // CHECK: call void @llvm.nvvm.cp.async.ca.shared.global.4(ptr addrspace(3) %{{.*}}, ptr addrspace(1) %{{.*}})
nvvm.cp.async.shared.global %arg0, %arg1, 4 nvvm.cp.async.shared.global %arg0, %arg1, 4
// CHECK: call void @llvm.nvvm.cp.async.ca.shared.global.8(i8 addrspace(3)* %{{.*}}, i8 addrspace(1)* %{{.*}}) // CHECK: call void @llvm.nvvm.cp.async.ca.shared.global.8(ptr addrspace(3) %{{.*}}, ptr addrspace(1) %{{.*}})
nvvm.cp.async.shared.global %arg0, %arg1, 8 nvvm.cp.async.shared.global %arg0, %arg1, 8
// CHECK: call void @llvm.nvvm.cp.async.ca.shared.global.16(i8 addrspace(3)* %{{.*}}, i8 addrspace(1)* %{{.*}}) // CHECK: call void @llvm.nvvm.cp.async.ca.shared.global.16(ptr addrspace(3) %{{.*}}, ptr addrspace(1) %{{.*}})
nvvm.cp.async.shared.global %arg0, %arg1, 16 nvvm.cp.async.shared.global %arg0, %arg1, 16
// CHECK: call void @llvm.nvvm.cp.async.cg.shared.global.16(i8 addrspace(3)* %{{.*}}, i8 addrspace(1)* %{{.*}}) // CHECK: call void @llvm.nvvm.cp.async.cg.shared.global.16(ptr addrspace(3) %{{.*}}, ptr addrspace(1) %{{.*}})
nvvm.cp.async.shared.global %arg0, %arg1, 16 {bypass_l1} nvvm.cp.async.shared.global %arg0, %arg1, 16 {bypass_l1}
// CHECK: call void @llvm.nvvm.cp.async.commit.group() // CHECK: call void @llvm.nvvm.cp.async.commit.group()
nvvm.cp.async.commit.group nvvm.cp.async.commit.group
// CHECK: call void @llvm.nvvm.cp.async.wait.group(i32 0) // CHECK: call void @llvm.nvvm.cp.async.wait.group(i32 0)
nvvm.cp.async.wait.group 0 nvvm.cp.async.wait.group 0
llvm.return llvm.return
} }
// CHECK-LABEL: @ld_matrix // CHECK-LABEL: @ld_matrix
llvm.func @ld_matrix(%arg0: !llvm.ptr<i32, 3>) { llvm.func @ld_matrix(%arg0: !llvm.ptr<i32, 3>) {
// CHECK: call i32 @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.b16.p3i32(i32 addrspace(3)* %{{.*}}) // CHECK: call i32 @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.b16.p3(ptr addrspace(3) %{{.*}})
%l1 = nvvm.ldmatrix %arg0 {num = 1 : i32, layout = #nvvm.mma_layout<row>} : (!llvm.ptr<i32, 3>) -> i32 %l1 = nvvm.ldmatrix %arg0 {num = 1 : i32, layout = #nvvm.mma_layout<row>} : (!llvm.ptr<i32, 3>) -> i32
// CHECK: call { i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x2.b16.p3i32(i32 addrspace(3)* %{{.*}}) // CHECK: call { i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x2.b16.p3(ptr addrspace(3) %{{.*}})
%l2 = nvvm.ldmatrix %arg0 {num = 2 : i32, layout = #nvvm.mma_layout<row>} : (!llvm.ptr<i32, 3>) -> !llvm.struct<(i32, i32)> %l2 = nvvm.ldmatrix %arg0 {num = 2 : i32, layout = #nvvm.mma_layout<row>} : (!llvm.ptr<i32, 3>) -> !llvm.struct<(i32, i32)>
// CHECK: call { i32, i32, i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x4.b16.p3i32(i32 addrspace(3)* %{{.*}}) // CHECK: call { i32, i32, i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x4.b16.p3(ptr addrspace(3) %{{.*}})
%l4 = nvvm.ldmatrix %arg0 {num = 4 : i32, layout = #nvvm.mma_layout<row>} : (!llvm.ptr<i32, 3>) -> !llvm.struct<(i32, i32, i32, i32)> %l4 = nvvm.ldmatrix %arg0 {num = 4 : i32, layout = #nvvm.mma_layout<row>} : (!llvm.ptr<i32, 3>) -> !llvm.struct<(i32, i32, i32, i32)>
// CHECK: call i32 @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.trans.b16.p3i32(i32 addrspace(3)* %{{.*}}) // CHECK: call i32 @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.trans.b16.p3(ptr addrspace(3) %{{.*}})
%l1t = nvvm.ldmatrix %arg0 {num = 1 : i32, layout = #nvvm.mma_layout<col>} : (!llvm.ptr<i32, 3>) -> i32 %l1t = nvvm.ldmatrix %arg0 {num = 1 : i32, layout = #nvvm.mma_layout<col>} : (!llvm.ptr<i32, 3>) -> i32
// CHECK: call { i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x2.trans.b16.p3i32(i32 addrspace(3)* %{{.*}}) // CHECK: call { i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x2.trans.b16.p3(ptr addrspace(3) %{{.*}})
%l2t = nvvm.ldmatrix %arg0 {num = 2 : i32, layout = #nvvm.mma_layout<col>} : (!llvm.ptr<i32, 3>) -> !llvm.struct<(i32, i32)> %l2t = nvvm.ldmatrix %arg0 {num = 2 : i32, layout = #nvvm.mma_layout<col>} : (!llvm.ptr<i32, 3>) -> !llvm.struct<(i32, i32)>
// CHECK: call { i32, i32, i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x4.trans.b16.p3i32(i32 addrspace(3)* %{{.*}}) // CHECK: call { i32, i32, i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x4.trans.b16.p3(ptr addrspace(3) %{{.*}})
%l4t = nvvm.ldmatrix %arg0 {num = 4 : i32, layout = #nvvm.mma_layout<col>} : (!llvm.ptr<i32, 3>) -> !llvm.struct<(i32, i32, i32, i32)> %l4t = nvvm.ldmatrix %arg0 {num = 4 : i32, layout = #nvvm.mma_layout<col>} : (!llvm.ptr<i32, 3>) -> !llvm.struct<(i32, i32, i32, i32)>
llvm.return llvm.return
} }
// This function has the "kernel" attribute attached and should appear in the // This function has the "kernel" attribute attached and should appear in the
// NVVM annotations after conversion. // NVVM annotations after conversion.
llvm.func @kernel_func() attributes {nvvm.kernel} { llvm.func @kernel_func() attributes {nvvm.kernel} {
llvm.return llvm.return
} }
// CHECK: !nvvm.annotations = // CHECK: !nvvm.annotations =
// CHECK-NOT: {i32 ()* @nvvm_special_regs, !"kernel", i32 1} // CHECK-NOT: {ptr @nvvm_special_regs, !"kernel", i32 1}
// CHECK: {void ()* @kernel_func, !"kernel", i32 1} // CHECK: {ptr @kernel_func, !"kernel", i32 1}

mlir/test/Target/LLVMIR/openacc-llvm.mlir

Show All 15 Linesllvm.func @testenterdataop(%arg0: !llvm.ptr<f32>, %arg1: !llvm.ptr<f32>, %arg2: i64, %arg3: i64, %arg4: i64, %arg5: !llvm.ptr<f32>) {
%12 = llvm.mlir.undef : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %12 = llvm.mlir.undef : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
%13 = llvm.insertvalue %5, %12[0] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %13 = llvm.insertvalue %5, %12[0] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
%14 = llvm.insertvalue %11, %13[1] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %14 = llvm.insertvalue %11, %13[1] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
%15 = llvm.insertvalue %10, %14[2] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %15 = llvm.insertvalue %10, %14[2] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
acc.enter_data copyin(%arg5 : !llvm.ptr<f32>) create(%15 : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>) acc.enter_data copyin(%arg5 : !llvm.ptr<f32>) create(%15 : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>)
llvm.return llvm.return
} }
// CHECK: %struct.ident_t = type { i32, i32, i32, i32, i8* } // CHECK: %struct.ident_t = type { i32, i32, i32, i32, ptr }
// CHECK: [[LOCSTR:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};testenterdataop;{{[0-9]*}};{{[0-9]*}};;\00", align 1 // CHECK: [[LOCSTR:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};testenterdataop;{{[0-9]*}};{{[0-9]*}};;\00", align 1
// CHECK: [[LOCGLOBAL:@.*]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 {{[0-9]*}}, i8* getelementptr inbounds ([{{[0-9]*}} x i8], [{{[0-9]*}} x i8]* [[LOCSTR]], i32 0, i32 0) }, align 8 // CHECK: [[LOCGLOBAL:@.*]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 {{[0-9]*}}, ptr [[LOCSTR]] }, align 8
// CHECK: [[MAPNAME1:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1 // CHECK: [[MAPNAME1:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1
// CHECK: [[MAPNAME2:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1 // CHECK: [[MAPNAME2:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1
// CHECK: [[MAPTYPES:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i64] [i64 0, i64 1] // CHECK: [[MAPTYPES:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i64] [i64 0, i64 1]
// CHECK: [[MAPNAMES:@.*]] = private constant [{{[0-9]*}} x i8*] [i8* getelementptr inbounds ([{{[0-9]*}} x i8], [{{[0-9]*}} x i8]* [[MAPNAME1]], i32 0, i32 0), i8* getelementptr inbounds ([{{[0-9]*}} x i8], [{{[0-9]*}} x i8]* [[MAPNAME2]], i32 0, i32 0)] // CHECK: [[MAPNAMES:@.*]] = private constant [{{[0-9]*}} x ptr] [ptr [[MAPNAME1]], ptr [[MAPNAME2]]]
// CHECK: define void @testenterdataop(float* %{{.*}}, float* %{{.*}}, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}, float* [[SIMPLEPTR:%.*]]) // CHECK: define void @testenterdataop(ptr %{{.*}}, ptr %{{.*}}, i64 %{{.*}}, i64 %{{.*}}, i64 %{{.*}}, ptr [[SIMPLEPTR:%.*]])
// CHECK: [[ARGBASE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i8*], align 8 // CHECK: [[ARGBASE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x ptr], align 8
// CHECK: [[ARG_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i8*], align 8 // CHECK: [[ARG_ALLOCA:%.*]] = alloca [{{[0-9]*}} x ptr], align 8
// CHECK: [[SIZE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i64], align 8 // CHECK: [[SIZE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i64], align 8
// CHECK: [[ARGBASE:%.*]] = extractvalue %openacc_data %{{.*}}, 0 // CHECK: [[ARGBASE:%.*]] = extractvalue %openacc_data %{{.*}}, 0
// CHECK: [[ARG:%.*]] = extractvalue %openacc_data %{{.*}}, 1 // CHECK: [[ARG:%.*]] = extractvalue %openacc_data %{{.*}}, 1
// CHECK: [[ARGSIZE:%.*]] = extractvalue %openacc_data %{{.*}}, 2 // CHECK: [[ARGSIZE:%.*]] = extractvalue %openacc_data %{{.*}}, 2
// CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARGBASE_ALLOCA]], i32 0, i32 0 // CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 0
// CHECK: [[ARGBASEGEPCAST:%.*]] = bitcast i8** [[ARGBASEGEP]] to { float*, float*, i64, [1 x i64], [1 x i64] }* // CHECK: store { ptr, ptr, i64, [1 x i64], [1 x i64] } [[ARGBASE]], ptr [[ARGBASEGEP]], align 8
// CHECK: store { float*, float*, i64, [1 x i64], [1 x i64] } [[ARGBASE]], { float*, float*, i64, [1 x i64], [1 x i64] }* [[ARGBASEGEPCAST]], align 8 // CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 0
// CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARG_ALLOCA]], i32 0, i32 0 // CHECK: store ptr [[ARG]], ptr [[ARGGEP]], align 8
// CHECK: [[ARGGEPCAST:%.*]] = bitcast i8** [[ARGGEP]] to float** // CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: store float* [[ARG]], float** [[ARGGEPCAST]], align 8 // CHECK: store i64 [[ARGSIZE]], ptr [[SIZEGEP]], align 4
// CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: store i64 [[ARGSIZE]], i64* [[SIZEGEP]], align 4 // CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 1
// CHECK: store ptr [[SIMPLEPTR]], ptr [[ARGBASEGEP]], align 8
// CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARGBASE_ALLOCA]], i32 0, i32 1 // CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 1
// CHECK: [[ARGBASEGEPCAST:%.*]] = bitcast i8** [[ARGBASEGEP]] to float** // CHECK: store ptr [[SIMPLEPTR]], ptr [[ARGGEP]], align 8
// CHECK: store float* [[SIMPLEPTR]], float** [[ARGBASEGEPCAST]], align 8 // CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 1
// CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARG_ALLOCA]], i32 0, i32 1 // CHECK: store i64 ptrtoint (ptr getelementptr (ptr, ptr null, i32 1) to i64), ptr [[SIZEGEP]], align 4
// CHECK: [[ARGGEPCAST:%.*]] = bitcast i8** [[ARGGEP]] to float**
// CHECK: store float* [[SIMPLEPTR]], float** [[ARGGEPCAST]], align 8 // CHECK: [[ARGBASE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 0
// CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[SIZE_ALLOCA]], i32 0, i32 1 // CHECK: [[ARG_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 0
// CHECK: store i64 ptrtoint (float** getelementptr (float*, float** null, i32 1) to i64), i64* [[SIZEGEP]], align 4 // CHECK: [[SIZE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: [[ARGBASE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARGBASE_ALLOCA]], i32 0, i32 0
// CHECK: [[ARG_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARG_ALLOCA]], i32 0, i32 0
// CHECK: [[SIZE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: call void @__tgt_target_data_begin_mapper(%struct.ident_t* [[LOCGLOBAL]], i64 -1, i32 2, i8** [[ARGBASE_ALLOCA_GEP]], i8** [[ARG_ALLOCA_GEP]], i64* [[SIZE_ALLOCA_GEP]], i64* getelementptr inbounds ([{{[0-9]*}} x i64], [{{[0-9]*}} x i64]* [[MAPTYPES]], i32 0, i32 0), i8** getelementptr inbounds ([{{[0-9]*}} x i8*], [{{[0-9]*}} x i8*]* [[MAPNAMES]], i32 0, i32 0), i8** null) // CHECK: call void @__tgt_target_data_begin_mapper(ptr [[LOCGLOBAL]], i64 -1, i32 2, ptr [[ARGBASE_ALLOCA_GEP]], ptr [[ARG_ALLOCA_GEP]], ptr [[SIZE_ALLOCA_GEP]], ptr [[MAPTYPES]], ptr [[MAPNAMES]], ptr null)
// CHECK: declare void @__tgt_target_data_begin_mapper(%struct.ident_t*, i64, i32, i8**, i8**, i64*, i64*, i8**, i8**) #0 // CHECK: declare void @__tgt_target_data_begin_mapper(ptr, i64, i32, ptr, ptr, ptr, ptr, ptr, ptr) #0
// ----- // -----
llvm.func @testexitdataop(%arg0: !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, %arg1: !llvm.ptr<f32>) { llvm.func @testexitdataop(%arg0: !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, %arg1: !llvm.ptr<f32>) {
%0 = llvm.mlir.constant(10 : index) : i64 %0 = llvm.mlir.constant(10 : index) : i64
%1 = llvm.mlir.null : !llvm.ptr<f32> %1 = llvm.mlir.null : !llvm.ptr<f32>
%2 = llvm.getelementptr %1[%0] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %2 = llvm.getelementptr %1[%0] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
%3 = llvm.ptrtoint %2 : !llvm.ptr<f32> to i64 %3 = llvm.ptrtoint %2 : !llvm.ptr<f32> to i64
%4 = llvm.extractvalue %arg0[1] : !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)> %4 = llvm.extractvalue %arg0[1] : !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>
%5 = llvm.mlir.undef : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %5 = llvm.mlir.undef : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
%6 = llvm.insertvalue %arg0, %5[0] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %6 = llvm.insertvalue %arg0, %5[0] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
%7 = llvm.insertvalue %4, %6[1] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %7 = llvm.insertvalue %4, %6[1] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
%8 = llvm.insertvalue %3, %7[2] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %8 = llvm.insertvalue %3, %7[2] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
acc.exit_data copyout(%arg1 : !llvm.ptr<f32>) delete(%8 : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>) acc.exit_data copyout(%arg1 : !llvm.ptr<f32>) delete(%8 : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>)
llvm.return llvm.return
} }
// CHECK: %struct.ident_t = type { i32, i32, i32, i32, i8* } // CHECK: %struct.ident_t = type { i32, i32, i32, i32, ptr }
// CHECK: [[LOCSTR:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};testexitdataop;{{[0-9]*}};{{[0-9]*}};;\00", align 1 // CHECK: [[LOCSTR:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};testexitdataop;{{[0-9]*}};{{[0-9]*}};;\00", align 1
// CHECK: [[LOCGLOBAL:@.*]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 {{[0-9]*}}, i8* getelementptr inbounds ([{{[0-9]*}} x i8], [{{[0-9]*}} x i8]* [[LOCSTR]], i32 0, i32 0) }, align 8 // CHECK: [[LOCGLOBAL:@.*]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 {{[0-9]*}}, ptr [[LOCSTR]] }, align 8
// CHECK: [[MAPNAME1:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1 // CHECK: [[MAPNAME1:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1
// CHECK: [[MAPNAME2:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1 // CHECK: [[MAPNAME2:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1
// CHECK: [[MAPTYPES:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i64] [i64 8, i64 2] // CHECK: [[MAPTYPES:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i64] [i64 8, i64 2]
// CHECK: [[MAPNAMES:@.*]] = private constant [{{[0-9]*}} x i8*] [i8* getelementptr inbounds ([{{[0-9]*}} x i8], [{{[0-9]*}} x i8]* [[MAPNAME1]], i32 0, i32 0), i8* getelementptr inbounds ([{{[0-9]*}} x i8], [{{[0-9]*}} x i8]* [[MAPNAME2]], i32 0, i32 0)] // CHECK: [[MAPNAMES:@.*]] = private constant [{{[0-9]*}} x ptr] [ptr [[MAPNAME1]], ptr [[MAPNAME2]]]
// CHECK: define void @testexitdataop({ float*, float*, i64, [1 x i64], [1 x i64] } %{{.*}}, float* [[SIMPLEPTR:%.*]]) // CHECK: define void @testexitdataop({ ptr, ptr, i64, [1 x i64], [1 x i64] } %{{.*}}, ptr [[SIMPLEPTR:%.*]])
// CHECK: [[ARGBASE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i8*], align 8 // CHECK: [[ARGBASE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x ptr], align 8
// CHECK: [[ARG_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i8*], align 8 // CHECK: [[ARG_ALLOCA:%.*]] = alloca [{{[0-9]*}} x ptr], align 8
// CHECK: [[SIZE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i64], align 8 // CHECK: [[SIZE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i64], align 8
// CHECK: [[ARGBASE:%.*]] = extractvalue %openacc_data %{{.*}}, 0 // CHECK: [[ARGBASE:%.*]] = extractvalue %openacc_data %{{.*}}, 0
// CHECK: [[ARG:%.*]] = extractvalue %openacc_data %{{.*}}, 1 // CHECK: [[ARG:%.*]] = extractvalue %openacc_data %{{.*}}, 1
// CHECK: [[ARGSIZE:%.*]] = extractvalue %openacc_data %{{.*}}, 2 // CHECK: [[ARGSIZE:%.*]] = extractvalue %openacc_data %{{.*}}, 2
// CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARGBASE_ALLOCA]], i32 0, i32 0 // CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 0
// CHECK: [[ARGBASEGEPCAST:%.*]] = bitcast i8** [[ARGBASEGEP]] to { float*, float*, i64, [1 x i64], [1 x i64] }* // CHECK: store { ptr, ptr, i64, [1 x i64], [1 x i64] } [[ARGBASE]], ptr [[ARGBASEGEP]], align 8
// CHECK: store { float*, float*, i64, [1 x i64], [1 x i64] } [[ARGBASE]], { float*, float*, i64, [1 x i64], [1 x i64] }* [[ARGBASEGEPCAST]], align 8 // CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 0
// CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARG_ALLOCA]], i32 0, i32 0 // CHECK: store ptr [[ARG]], ptr [[ARGGEP]], align 8
// CHECK: [[ARGGEPCAST:%.*]] = bitcast i8** [[ARGGEP]] to float** // CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: store float* [[ARG]], float** [[ARGGEPCAST]], align 8 // CHECK: store i64 [[ARGSIZE]], ptr [[SIZEGEP]], align 4
// CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: store i64 [[ARGSIZE]], i64* [[SIZEGEP]], align 4 // CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 1
// CHECK: store ptr [[SIMPLEPTR]], ptr [[ARGBASEGEP]], align 8
// CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARGBASE_ALLOCA]], i32 0, i32 1 // CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 1
// CHECK: [[ARGBASEGEPCAST:%.*]] = bitcast i8** [[ARGBASEGEP]] to float** // CHECK: store ptr [[SIMPLEPTR]], ptr [[ARGGEP]], align 8
// CHECK: store float* [[SIMPLEPTR]], float** [[ARGBASEGEPCAST]], align 8 // CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 1
// CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARG_ALLOCA]], i32 0, i32 1 // CHECK: store i64 ptrtoint (ptr getelementptr (ptr, ptr null, i32 1) to i64), ptr [[SIZEGEP]], align 4
// CHECK: [[ARGGEPCAST:%.*]] = bitcast i8** [[ARGGEP]] to float**
// CHECK: store float* [[SIMPLEPTR]], float** [[ARGGEPCAST]], align 8 // CHECK: [[ARGBASE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 0
// CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[SIZE_ALLOCA]], i32 0, i32 1 // CHECK: [[ARG_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 0
// CHECK: store i64 ptrtoint (float** getelementptr (float*, float** null, i32 1) to i64), i64* [[SIZEGEP]], align 4 // CHECK: [[SIZE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: [[ARGBASE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARGBASE_ALLOCA]], i32 0, i32 0
// CHECK: [[ARG_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARG_ALLOCA]], i32 0, i32 0
// CHECK: [[SIZE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: call void @__tgt_target_data_end_mapper(%struct.ident_t* [[LOCGLOBAL]], i64 -1, i32 2, i8** [[ARGBASE_ALLOCA_GEP]], i8** [[ARG_ALLOCA_GEP]], i64* [[SIZE_ALLOCA_GEP]], i64* getelementptr inbounds ([{{[0-9]*}} x i64], [{{[0-9]*}} x i64]* [[MAPTYPES]], i32 0, i32 0), i8** getelementptr inbounds ([{{[0-9]*}} x i8*], [{{[0-9]*}} x i8*]* [[MAPNAMES]], i32 0, i32 0), i8** null) // CHECK: call void @__tgt_target_data_end_mapper(ptr [[LOCGLOBAL]], i64 -1, i32 2, ptr [[ARGBASE_ALLOCA_GEP]], ptr [[ARG_ALLOCA_GEP]], ptr [[SIZE_ALLOCA_GEP]], ptr [[MAPTYPES]], ptr [[MAPNAMES]], ptr null)
// CHECK: declare void @__tgt_target_data_end_mapper(%struct.ident_t*, i64, i32, i8**, i8**, i64*, i64*, i8**, i8**) #0 // CHECK: declare void @__tgt_target_data_end_mapper(ptr, i64, i32, ptr, ptr, ptr, ptr, ptr, ptr) #0
// ----- // -----
llvm.func @testupdateop(%arg0: !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, %arg1: !llvm.ptr<f32>) { llvm.func @testupdateop(%arg0: !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, %arg1: !llvm.ptr<f32>) {
%0 = llvm.mlir.constant(10 : index) : i64 %0 = llvm.mlir.constant(10 : index) : i64
%1 = llvm.mlir.null : !llvm.ptr<f32> %1 = llvm.mlir.null : !llvm.ptr<f32>
%2 = llvm.getelementptr %1[%0] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %2 = llvm.getelementptr %1[%0] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
%3 = llvm.ptrtoint %2 : !llvm.ptr<f32> to i64 %3 = llvm.ptrtoint %2 : !llvm.ptr<f32> to i64
%4 = llvm.extractvalue %arg0[1] : !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)> %4 = llvm.extractvalue %arg0[1] : !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>
%5 = llvm.mlir.undef : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %5 = llvm.mlir.undef : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
%6 = llvm.insertvalue %arg0, %5[0] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %6 = llvm.insertvalue %arg0, %5[0] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
%7 = llvm.insertvalue %4, %6[1] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %7 = llvm.insertvalue %4, %6[1] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
%8 = llvm.insertvalue %3, %7[2] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %8 = llvm.insertvalue %3, %7[2] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
acc.update host(%8 : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>) device(%arg1 : !llvm.ptr<f32>) acc.update host(%8 : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>) device(%arg1 : !llvm.ptr<f32>)
llvm.return llvm.return
} }
// CHECK: %struct.ident_t = type { i32, i32, i32, i32, i8* } // CHECK: %struct.ident_t = type { i32, i32, i32, i32, ptr }
// CHECK: [[LOCSTR:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};testupdateop;{{[0-9]*}};{{[0-9]*}};;\00", align 1 // CHECK: [[LOCSTR:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};testupdateop;{{[0-9]*}};{{[0-9]*}};;\00", align 1
// CHECK: [[LOCGLOBAL:@.*]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 {{[0-9]*}}, i8* getelementptr inbounds ([{{[0-9]*}} x i8], [{{[0-9]*}} x i8]* [[LOCSTR]], i32 0, i32 0) }, align 8 // CHECK: [[LOCGLOBAL:@.*]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 {{[0-9]*}}, ptr [[LOCSTR]] }, align 8
// CHECK: [[MAPNAME1:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1 // CHECK: [[MAPNAME1:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1
// CHECK: [[MAPNAME2:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1 // CHECK: [[MAPNAME2:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1
// CHECK: [[MAPTYPES:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i64] [i64 2, i64 1] // CHECK: [[MAPTYPES:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i64] [i64 2, i64 1]
// CHECK: [[MAPNAMES:@.*]] = private constant [{{[0-9]*}} x i8*] [i8* getelementptr inbounds ([{{[0-9]*}} x i8], [{{[0-9]*}} x i8]* [[MAPNAME1]], i32 0, i32 0), i8* getelementptr inbounds ([{{[0-9]*}} x i8], [{{[0-9]*}} x i8]* [[MAPNAME2]], i32 0, i32 0)] // CHECK: [[MAPNAMES:@.*]] = private constant [{{[0-9]*}} x ptr] [ptr [[MAPNAME1]], ptr [[MAPNAME2]]]
// CHECK: define void @testupdateop({ float*, float*, i64, [1 x i64], [1 x i64] } %{{.*}}, float* [[SIMPLEPTR:%.*]]) // CHECK: define void @testupdateop({ ptr, ptr, i64, [1 x i64], [1 x i64] } %{{.*}}, ptr [[SIMPLEPTR:%.*]])
// CHECK: [[ARGBASE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i8*], align 8 // CHECK: [[ARGBASE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x ptr], align 8
// CHECK: [[ARG_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i8*], align 8 // CHECK: [[ARG_ALLOCA:%.*]] = alloca [{{[0-9]*}} x ptr], align 8
// CHECK: [[SIZE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i64], align 8 // CHECK: [[SIZE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i64], align 8
// CHECK: [[ARGBASE:%.*]] = extractvalue %openacc_data %{{.*}}, 0 // CHECK: [[ARGBASE:%.*]] = extractvalue %openacc_data %{{.*}}, 0
// CHECK: [[ARG:%.*]] = extractvalue %openacc_data %{{.*}}, 1 // CHECK: [[ARG:%.*]] = extractvalue %openacc_data %{{.*}}, 1
// CHECK: [[ARGSIZE:%.*]] = extractvalue %openacc_data %{{.*}}, 2 // CHECK: [[ARGSIZE:%.*]] = extractvalue %openacc_data %{{.*}}, 2
// CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARGBASE_ALLOCA]], i32 0, i32 0 // CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 0
// CHECK: [[ARGBASEGEPCAST:%.*]] = bitcast i8** [[ARGBASEGEP]] to { float*, float*, i64, [1 x i64], [1 x i64] }* // CHECK: store { ptr, ptr, i64, [1 x i64], [1 x i64] } [[ARGBASE]], ptr [[ARGBASEGEP]], align 8
// CHECK: store { float*, float*, i64, [1 x i64], [1 x i64] } [[ARGBASE]], { float*, float*, i64, [1 x i64], [1 x i64] }* [[ARGBASEGEPCAST]], align 8 // CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 0
// CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARG_ALLOCA]], i32 0, i32 0 // CHECK: store ptr [[ARG]], ptr [[ARGGEP]], align 8
// CHECK: [[ARGGEPCAST:%.*]] = bitcast i8** [[ARGGEP]] to float** // CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: store float* [[ARG]], float** [[ARGGEPCAST]], align 8 // CHECK: store i64 [[ARGSIZE]], ptr [[SIZEGEP]], align 4
// CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: store i64 [[ARGSIZE]], i64* [[SIZEGEP]], align 4 // CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 1
// CHECK: store ptr [[SIMPLEPTR]], ptr [[ARGBASEGEP]], align 8
// CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARGBASE_ALLOCA]], i32 0, i32 1 // CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 1
// CHECK: [[ARGBASEGEPCAST:%.*]] = bitcast i8** [[ARGBASEGEP]] to float** // CHECK: store ptr [[SIMPLEPTR]], ptr [[ARGGEP]], align 8
// CHECK: store float* [[SIMPLEPTR]], float** [[ARGBASEGEPCAST]], align 8 // CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 1
// CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARG_ALLOCA]], i32 0, i32 1 // CHECK: store i64 ptrtoint (ptr getelementptr (ptr, ptr null, i32 1) to i64), ptr [[SIZEGEP]], align 4
// CHECK: [[ARGGEPCAST:%.*]] = bitcast i8** [[ARGGEP]] to float**
// CHECK: store float* [[SIMPLEPTR]], float** [[ARGGEPCAST]], align 8 // CHECK: [[ARGBASE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 0
// CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[SIZE_ALLOCA]], i32 0, i32 1 // CHECK: [[ARG_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 0
// CHECK: store i64 ptrtoint (float** getelementptr (float*, float** null, i32 1) to i64), i64* [[SIZEGEP]], align 4 // CHECK: [[SIZE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: [[ARGBASE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARGBASE_ALLOCA]], i32 0, i32 0
// CHECK: [[ARG_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARG_ALLOCA]], i32 0, i32 0
// CHECK: [[SIZE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: call void @__tgt_target_data_update_mapper(%struct.ident_t* [[LOCGLOBAL]], i64 -1, i32 2, i8** [[ARGBASE_ALLOCA_GEP]], i8** [[ARG_ALLOCA_GEP]], i64* [[SIZE_ALLOCA_GEP]], i64* getelementptr inbounds ([{{[0-9]*}} x i64], [{{[0-9]*}} x i64]* [[MAPTYPES]], i32 0, i32 0), i8** getelementptr inbounds ([{{[0-9]*}} x i8*], [{{[0-9]*}} x i8*]* [[MAPNAMES]], i32 0, i32 0), i8** null) // CHECK: call void @__tgt_target_data_update_mapper(ptr [[LOCGLOBAL]], i64 -1, i32 2, ptr [[ARGBASE_ALLOCA_GEP]], ptr [[ARG_ALLOCA_GEP]], ptr [[SIZE_ALLOCA_GEP]], ptr [[MAPTYPES]], ptr [[MAPNAMES]], ptr null)
// CHECK: declare void @__tgt_target_data_update_mapper(%struct.ident_t*, i64, i32, i8**, i8**, i64*, i64*, i8**, i8**) #0 // CHECK: declare void @__tgt_target_data_update_mapper(ptr, i64, i32, ptr, ptr, ptr, ptr, ptr, ptr) #0
// ----- // -----
llvm.func @testdataop(%arg0: !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, %arg1: !llvm.ptr<f32>, %arg2: !llvm.ptr<i32>) { llvm.func @testdataop(%arg0: !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, %arg1: !llvm.ptr<f32>, %arg2: !llvm.ptr<i32>) {
%0 = llvm.mlir.constant(10 : index) : i64 %0 = llvm.mlir.constant(10 : index) : i64
%1 = llvm.mlir.null : !llvm.ptr<f32> %1 = llvm.mlir.null : !llvm.ptr<f32>
%2 = llvm.getelementptr %1[%0] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %2 = llvm.getelementptr %1[%0] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
%3 = llvm.ptrtoint %2 : !llvm.ptr<f32> to i64 %3 = llvm.ptrtoint %2 : !llvm.ptr<f32> to i64
%4 = llvm.extractvalue %arg0[1] : !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)> %4 = llvm.extractvalue %arg0[1] : !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>
%5 = llvm.mlir.undef : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %5 = llvm.mlir.undef : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
%6 = llvm.insertvalue %arg0, %5[0] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %6 = llvm.insertvalue %arg0, %5[0] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
%7 = llvm.insertvalue %4, %6[1] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %7 = llvm.insertvalue %4, %6[1] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
%8 = llvm.insertvalue %3, %7[2] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)> %8 = llvm.insertvalue %3, %7[2] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
acc.data copy(%8 : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>) copyout(%arg1 : !llvm.ptr<f32>) { acc.data copy(%8 : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>) copyout(%arg1 : !llvm.ptr<f32>) {
%9 = llvm.mlir.constant(2 : i32) : i32 %9 = llvm.mlir.constant(2 : i32) : i32
llvm.store %9, %arg2 : !llvm.ptr<i32> llvm.store %9, %arg2 : !llvm.ptr<i32>
acc.terminator acc.terminator
} }
llvm.return llvm.return
} }
// CHECK: %struct.ident_t = type { i32, i32, i32, i32, i8* } // CHECK: %struct.ident_t = type { i32, i32, i32, i32, ptr }
// CHECK: [[LOCSTR:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};testdataop;{{[0-9]*}};{{[0-9]*}};;\00", align 1 // CHECK: [[LOCSTR:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};testdataop;{{[0-9]*}};{{[0-9]*}};;\00", align 1
// CHECK: [[LOCGLOBAL:@.*]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 {{[0-9]*}}, i8* getelementptr inbounds ([{{[0-9]*}} x i8], [{{[0-9]*}} x i8]* [[LOCSTR]], i32 0, i32 0) }, align 8 // CHECK: [[LOCGLOBAL:@.*]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 {{[0-9]*}}, ptr [[LOCSTR]] }, align 8
// CHECK: [[MAPNAME1:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1 // CHECK: [[MAPNAME1:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1
// CHECK: [[MAPNAME2:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1 // CHECK: [[MAPNAME2:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1
// CHECK: [[MAPTYPES:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i64] [i64 8195, i64 8194] // CHECK: [[MAPTYPES:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i64] [i64 8195, i64 8194]
// CHECK: [[MAPNAMES:@.*]] = private constant [{{[0-9]*}} x i8*] [i8* getelementptr inbounds ([{{[0-9]*}} x i8], [{{[0-9]*}} x i8]* [[MAPNAME1]], i32 0, i32 0), i8* getelementptr inbounds ([{{[0-9]*}} x i8], [{{[0-9]*}} x i8]* [[MAPNAME2]], i32 0, i32 0)] // CHECK: [[MAPNAMES:@.*]] = private constant [{{[0-9]*}} x ptr] [ptr [[MAPNAME1]], ptr [[MAPNAME2]]]
// CHECK: define void @testdataop({ float*, float*, i64, [1 x i64], [1 x i64] } %{{.*}}, float* [[SIMPLEPTR:%.*]], i32* %{{.*}}) // CHECK: define void @testdataop({ ptr, ptr, i64, [1 x i64], [1 x i64] } %{{.*}}, ptr [[SIMPLEPTR:%.*]], ptr %{{.*}})
// CHECK: [[ARGBASE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i8*], align 8 // CHECK: [[ARGBASE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x ptr], align 8
// CHECK: [[ARG_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i8*], align 8 // CHECK: [[ARG_ALLOCA:%.*]] = alloca [{{[0-9]*}} x ptr], align 8
// CHECK: [[SIZE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i64], align 8 // CHECK: [[SIZE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i64], align 8
// CHECK: [[ARGBASE:%.*]] = extractvalue %openacc_data %{{.*}}, 0 // CHECK: [[ARGBASE:%.*]] = extractvalue %openacc_data %{{.*}}, 0
// CHECK: [[ARG:%.*]] = extractvalue %openacc_data %{{.*}}, 1 // CHECK: [[ARG:%.*]] = extractvalue %openacc_data %{{.*}}, 1
// CHECK: [[ARGSIZE:%.*]] = extractvalue %openacc_data %{{.*}}, 2 // CHECK: [[ARGSIZE:%.*]] = extractvalue %openacc_data %{{.*}}, 2
// CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARGBASE_ALLOCA]], i32 0, i32 0 // CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 0
// CHECK: [[ARGBASEGEPCAST:%.*]] = bitcast i8** [[ARGBASEGEP]] to { float*, float*, i64, [1 x i64], [1 x i64] }* // CHECK: store { ptr, ptr, i64, [1 x i64], [1 x i64] } [[ARGBASE]], ptr [[ARGBASEGEP]], align 8
// CHECK: store { float*, float*, i64, [1 x i64], [1 x i64] } [[ARGBASE]], { float*, float*, i64, [1 x i64], [1 x i64] }* [[ARGBASEGEPCAST]], align 8 // CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 0
// CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARG_ALLOCA]], i32 0, i32 0 // CHECK: store ptr [[ARG]], ptr [[ARGGEP]], align 8
// CHECK: [[ARGGEPCAST:%.*]] = bitcast i8** [[ARGGEP]] to float** // CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: store float* [[ARG]], float** [[ARGGEPCAST]], align 8 // CHECK: store i64 [[ARGSIZE]], ptr [[SIZEGEP]], align 4
// CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: store i64 [[ARGSIZE]], i64* [[SIZEGEP]], align 4 // CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 1
// CHECK: store ptr [[SIMPLEPTR]], ptr [[ARGBASEGEP]], align 8
// CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARGBASE_ALLOCA]], i32 0, i32 1 // CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 1
// CHECK: [[ARGBASEGEPCAST:%.*]] = bitcast i8** [[ARGBASEGEP]] to float** // CHECK: store ptr [[SIMPLEPTR]], ptr [[ARGGEP]], align 8
// CHECK: store float* [[SIMPLEPTR]], float** [[ARGBASEGEPCAST]], align 8 // CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 1
// CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARG_ALLOCA]], i32 0, i32 1 // CHECK: store i64 ptrtoint (ptr getelementptr (ptr, ptr null, i32 1) to i64), ptr [[SIZEGEP]], align 4
// CHECK: [[ARGGEPCAST:%.*]] = bitcast i8** [[ARGGEP]] to float**
// CHECK: store float* [[SIMPLEPTR]], float** [[ARGGEPCAST]], align 8 // CHECK: [[ARGBASE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 0
// CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[SIZE_ALLOCA]], i32 0, i32 1 // CHECK: [[ARG_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 0
// CHECK: store i64 ptrtoint (float** getelementptr (float*, float** null, i32 1) to i64), i64* [[SIZEGEP]], align 4 // CHECK: [[SIZE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: call void @__tgt_target_data_begin_mapper(ptr [[LOCGLOBAL]], i64 -1, i32 2, ptr [[ARGBASE_ALLOCA_GEP]], ptr [[ARG_ALLOCA_GEP]], ptr [[SIZE_ALLOCA_GEP]], ptr [[MAPTYPES]], ptr [[MAPNAMES]], ptr null)
// CHECK: [[ARGBASE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARGBASE_ALLOCA]], i32 0, i32 0
// CHECK: [[ARG_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARG_ALLOCA]], i32 0, i32 0
// CHECK: [[SIZE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: call void @__tgt_target_data_begin_mapper(%struct.ident_t* [[LOCGLOBAL]], i64 -1, i32 2, i8** [[ARGBASE_ALLOCA_GEP]], i8** [[ARG_ALLOCA_GEP]], i64* [[SIZE_ALLOCA_GEP]], i64* getelementptr inbounds ([{{[0-9]*}} x i64], [{{[0-9]*}} x i64]* [[MAPTYPES]], i32 0, i32 0), i8** getelementptr inbounds ([{{[0-9]*}} x i8*], [{{[0-9]*}} x i8*]* [[MAPNAMES]], i32 0, i32 0), i8** null)
// CHECK: br label %acc.data // CHECK: br label %acc.data
// CHECK: acc.data: // CHECK: acc.data:
// CHECK-NEXT: store i32 2, i32* %{{.*}} // CHECK-NEXT: store i32 2, ptr %{{.*}}
// CHECK-NEXT: br label %acc.end_data // CHECK-NEXT: br label %acc.end_data
// CHECK: acc.end_data: // CHECK: acc.end_data:
// CHECK: [[ARGBASE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARGBASE_ALLOCA]], i32 0, i32 0 // CHECK: [[ARGBASE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 0
// CHECK: [[ARG_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[ARG_ALLOCA]], i32 0, i32 0 // CHECK: [[ARG_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 0
// CHECK: [[SIZE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[SIZE_ALLOCA]], i32 0, i32 0 // CHECK: [[SIZE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 0
// CHECK: call void @__tgt_target_data_end_mapper(%struct.ident_t* [[LOCGLOBAL]], i64 -1, i32 2, i8** [[ARGBASE_ALLOCA_GEP]], i8** [[ARG_ALLOCA_GEP]], i64* [[SIZE_ALLOCA_GEP]], i64* getelementptr inbounds ([{{[0-9]*}} x i64], [{{[0-9]*}} x i64]* [[MAPTYPES]], i32 0, i32 0), i8** getelementptr inbounds ([{{[0-9]*}} x i8*], [{{[0-9]*}} x i8*]* [[MAPNAMES]], i32 0, i32 0), i8** null) // CHECK: call void @__tgt_target_data_end_mapper(ptr [[LOCGLOBAL]], i64 -1, i32 2, ptr [[ARGBASE_ALLOCA_GEP]], ptr [[ARG_ALLOCA_GEP]], ptr [[SIZE_ALLOCA_GEP]], ptr [[MAPTYPES]], ptr [[MAPNAMES]], ptr null)
// CHECK: declare void @__tgt_target_data_begin_mapper(%struct.ident_t*, i64, i32, i8**, i8**, i64*, i64*, i8**, i8**) // CHECK: declare void @__tgt_target_data_begin_mapper(ptr, i64, i32, ptr, ptr, ptr, ptr, ptr, ptr)
// CHECK: declare void @__tgt_target_data_end_mapper(%struct.ident_t*, i64, i32, i8**, i8**, i64*, i64*, i8**, i8**) // CHECK: declare void @__tgt_target_data_end_mapper(ptr, i64, i32, ptr, ptr, ptr, ptr, ptr, ptr)

mlir/test/Target/LLVMIR/openmp-llvm.mlir

// RUN: mlir-translate -mlir-to-llvmir -split-input-file %s | FileCheck %s // RUN: mlir-translate -mlir-to-llvmir -split-input-file %s | FileCheck %s
// CHECK-LABEL: define void @test_stand_alone_directives() // CHECK-LABEL: define void @test_stand_alone_directives()
llvm.func @test_stand_alone_directives() { llvm.func @test_stand_alone_directives() {
// CHECK: [[OMP_THREAD:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @{{[0-9]+}}) // CHECK: [[OMP_THREAD:%.*]] = call i32 @__kmpc_global_thread_num(ptr @{{[0-9]+}})
// CHECK-NEXT: call void @__kmpc_barrier(%struct.ident_t* @{{[0-9]+}}, i32 [[OMP_THREAD]]) // CHECK-NEXT: call void @__kmpc_barrier(ptr @{{[0-9]+}}, i32 [[OMP_THREAD]])
omp.barrier omp.barrier
// CHECK: [[OMP_THREAD1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @{{[0-9]+}}) // CHECK: [[OMP_THREAD1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @{{[0-9]+}})
// CHECK-NEXT: [[RET_VAL:%.*]] = call i32 @__kmpc_omp_taskwait(%struct.ident_t* @{{[0-9]+}}, i32 [[OMP_THREAD1]]) // CHECK-NEXT: [[RET_VAL:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @{{[0-9]+}}, i32 [[OMP_THREAD1]])
omp.taskwait omp.taskwait
// CHECK: [[OMP_THREAD2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @{{[0-9]+}}) // CHECK: [[OMP_THREAD2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @{{[0-9]+}})
// CHECK-NEXT: [[RET_VAL:%.*]] = call i32 @__kmpc_omp_taskyield(%struct.ident_t* @{{[0-9]+}}, i32 [[OMP_THREAD2]], i32 0) // CHECK-NEXT: [[RET_VAL:%.*]] = call i32 @__kmpc_omp_taskyield(ptr @{{[0-9]+}}, i32 [[OMP_THREAD2]], i32 0)
omp.taskyield omp.taskyield
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
llvm.return llvm.return
} }
// CHECK-LABEL: define void @test_flush_construct(i32 %0) // CHECK-LABEL: define void @test_flush_construct(i32 %0)
llvm.func @test_flush_construct(%arg0: i32) { llvm.func @test_flush_construct(%arg0: i32) {
// CHECK: call void @__kmpc_flush(%struct.ident_t* @{{[0-9]+}} // CHECK: call void @__kmpc_flush(ptr @{{[0-9]+}}
omp.flush omp.flush
// CHECK: call void @__kmpc_flush(%struct.ident_t* @{{[0-9]+}} // CHECK: call void @__kmpc_flush(ptr @{{[0-9]+}}
omp.flush (%arg0 : i32) omp.flush (%arg0 : i32)
// CHECK: call void @__kmpc_flush(%struct.ident_t* @{{[0-9]+}} // CHECK: call void @__kmpc_flush(ptr @{{[0-9]+}}
omp.flush (%arg0, %arg0 : i32, i32) omp.flush (%arg0, %arg0 : i32, i32)
%0 = llvm.mlir.constant(1 : i64) : i64 %0 = llvm.mlir.constant(1 : i64) : i64
// CHECK: alloca {{.*}} align 4 // CHECK: alloca {{.*}} align 4
%1 = llvm.alloca %0 x i32 {in_type = i32, name = "a"} : (i64) -> !llvm.ptr<i32> %1 = llvm.alloca %0 x i32 {in_type = i32, name = "a"} : (i64) -> !llvm.ptr<i32>
// CHECK: call void @__kmpc_flush(%struct.ident_t* @{{[0-9]+}} // CHECK: call void @__kmpc_flush(ptr @{{[0-9]+}}
omp.flush omp.flush
// CHECK: load i32, i32* // CHECK: load i32, ptr
%2 = llvm.load %1 : !llvm.ptr<i32> %2 = llvm.load %1 : !llvm.ptr<i32>
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
llvm.return llvm.return
} }
// CHECK-LABEL: define void @test_omp_parallel_1() // CHECK-LABEL: define void @test_omp_parallel_1()
llvm.func @test_omp_parallel_1() -> () { llvm.func @test_omp_parallel_1() -> () {
// CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_1:.*]] to {{.*}} // CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_1:.*]])
omp.parallel { omp.parallel {
omp.barrier omp.barrier
omp.terminator omp.terminator
} }
llvm.return llvm.return
} }
// CHECK: define internal void @[[OMP_OUTLINED_FN_1]] // CHECK: define internal void @[[OMP_OUTLINED_FN_1]]
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
llvm.func @body(i64) llvm.func @body(i64)
// CHECK-LABEL: define void @test_omp_parallel_2() // CHECK-LABEL: define void @test_omp_parallel_2()
llvm.func @test_omp_parallel_2() -> () { llvm.func @test_omp_parallel_2() -> () {
// CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_2:.*]] to {{.*}} // CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_2:.*]])
omp.parallel { omp.parallel {
^bb0: ^bb0:
%0 = llvm.mlir.constant(1 : index) : i64 %0 = llvm.mlir.constant(1 : index) : i64
%1 = llvm.mlir.constant(42 : index) : i64 %1 = llvm.mlir.constant(42 : index) : i64
llvm.call @body(%0) : (i64) -> () llvm.call @body(%0) : (i64) -> ()
llvm.call @body(%1) : (i64) -> () llvm.call @body(%1) : (i64) -> ()
llvm.br ^bb1 llvm.br ^bb1
Show All 13 Lines// CHECK: define internal void @[[OMP_OUTLINED_FN_2]]
// CHECK: call void @body(i64 42) // CHECK: call void @body(i64 42)
// CHECK: br label %omp.par.region2 // CHECK: br label %omp.par.region2
// CHECK-LABEL: omp.par.region2: // CHECK-LABEL: omp.par.region2:
// CHECK: call void @body(i64 43) // CHECK: call void @body(i64 43)
// CHECK: br label %omp.par.pre_finalize // CHECK: br label %omp.par.pre_finalize
// CHECK: define void @test_omp_parallel_num_threads_1(i32 %[[NUM_THREADS_VAR_1:.*]]) // CHECK: define void @test_omp_parallel_num_threads_1(i32 %[[NUM_THREADS_VAR_1:.*]])
llvm.func @test_omp_parallel_num_threads_1(%arg0: i32) -> () { llvm.func @test_omp_parallel_num_threads_1(%arg0: i32) -> () {
// CHECK: %[[GTN_NUM_THREADS_VAR_1:.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GTN_SI_VAR_1:.*]]) // CHECK: %[[GTN_NUM_THREADS_VAR_1:.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GTN_SI_VAR_1:.*]])
// CHECK: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GTN_SI_VAR_1]], i32 %[[GTN_NUM_THREADS_VAR_1]], i32 %[[NUM_THREADS_VAR_1]]) // CHECK: call void @__kmpc_push_num_threads(ptr @[[GTN_SI_VAR_1]], i32 %[[GTN_NUM_THREADS_VAR_1]], i32 %[[NUM_THREADS_VAR_1]])
// CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_NUM_THREADS_1:.*]] to {{.*}} // CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_NUM_THREADS_1:.*]])
omp.parallel num_threads(%arg0: i32) { omp.parallel num_threads(%arg0: i32) {
omp.barrier omp.barrier
omp.terminator omp.terminator
} }
llvm.return llvm.return
} }
// CHECK: define internal void @[[OMP_OUTLINED_FN_NUM_THREADS_1]] // CHECK: define internal void @[[OMP_OUTLINED_FN_NUM_THREADS_1]]
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
// CHECK: define void @test_omp_parallel_num_threads_2() // CHECK: define void @test_omp_parallel_num_threads_2()
llvm.func @test_omp_parallel_num_threads_2() -> () { llvm.func @test_omp_parallel_num_threads_2() -> () {
%0 = llvm.mlir.constant(4 : index) : i32 %0 = llvm.mlir.constant(4 : index) : i32
// CHECK: %[[GTN_NUM_THREADS_VAR_2:.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GTN_SI_VAR_2:.*]]) // CHECK: %[[GTN_NUM_THREADS_VAR_2:.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GTN_SI_VAR_2:.*]])
// CHECK: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GTN_SI_VAR_2]], i32 %[[GTN_NUM_THREADS_VAR_2]], i32 4) // CHECK: call void @__kmpc_push_num_threads(ptr @[[GTN_SI_VAR_2]], i32 %[[GTN_NUM_THREADS_VAR_2]], i32 4)
// CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_NUM_THREADS_2:.*]] to {{.*}} // CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_NUM_THREADS_2:.*]])
omp.parallel num_threads(%0: i32) { omp.parallel num_threads(%0: i32) {
omp.barrier omp.barrier
omp.terminator omp.terminator
} }
llvm.return llvm.return
} }
// CHECK: define internal void @[[OMP_OUTLINED_FN_NUM_THREADS_2]] // CHECK: define internal void @[[OMP_OUTLINED_FN_NUM_THREADS_2]]
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
// CHECK: define void @test_omp_parallel_num_threads_3() // CHECK: define void @test_omp_parallel_num_threads_3()
llvm.func @test_omp_parallel_num_threads_3() -> () { llvm.func @test_omp_parallel_num_threads_3() -> () {
%0 = llvm.mlir.constant(4 : index) : i32 %0 = llvm.mlir.constant(4 : index) : i32
// CHECK: %[[GTN_NUM_THREADS_VAR_3_1:.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GTN_SI_VAR_3_1:.*]]) // CHECK: %[[GTN_NUM_THREADS_VAR_3_1:.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GTN_SI_VAR_3_1:.*]])
// CHECK: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GTN_SI_VAR_3_1]], i32 %[[GTN_NUM_THREADS_VAR_3_1]], i32 4) // CHECK: call void @__kmpc_push_num_threads(ptr @[[GTN_SI_VAR_3_1]], i32 %[[GTN_NUM_THREADS_VAR_3_1]], i32 4)
// CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_NUM_THREADS_3_1:.*]] to {{.*}} // CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_NUM_THREADS_3_1:.*]])
omp.parallel num_threads(%0: i32) { omp.parallel num_threads(%0: i32) {
omp.barrier omp.barrier
omp.terminator omp.terminator
} }
%1 = llvm.mlir.constant(8 : index) : i32 %1 = llvm.mlir.constant(8 : index) : i32
// CHECK: %[[GTN_NUM_THREADS_VAR_3_2:.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GTN_SI_VAR_3_2:.*]]) // CHECK: %[[GTN_NUM_THREADS_VAR_3_2:.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GTN_SI_VAR_3_2:.*]])
// CHECK: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GTN_SI_VAR_3_2]], i32 %[[GTN_NUM_THREADS_VAR_3_2]], i32 8) // CHECK: call void @__kmpc_push_num_threads(ptr @[[GTN_SI_VAR_3_2]], i32 %[[GTN_NUM_THREADS_VAR_3_2]], i32 8)
// CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_NUM_THREADS_3_2:.*]] to {{.*}} // CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_NUM_THREADS_3_2:.*]])
omp.parallel num_threads(%1: i32) { omp.parallel num_threads(%1: i32) {
omp.barrier omp.barrier
omp.terminator omp.terminator
} }
llvm.return llvm.return
} }
Show All 12 Lines
// actually produces those names. // actually produces those names.
// CHECK: %tid.addr{{.*}} = alloca i32 // CHECK: %tid.addr{{.*}} = alloca i32
// CHECK: %zero.addr{{.*}} = alloca i32 // CHECK: %zero.addr{{.*}} = alloca i32
// CHECK: %[[IF_COND_VAR_1:.*]] = icmp slt i32 %[[IF_VAR_1]], 0 // CHECK: %[[IF_COND_VAR_1:.*]] = icmp slt i32 %[[IF_VAR_1]], 0
%0 = llvm.mlir.constant(0 : index) : i32 %0 = llvm.mlir.constant(0 : index) : i32
%1 = llvm.icmp "slt" %arg0, %0 : i32 %1 = llvm.icmp "slt" %arg0, %0 : i32
// CHECK: %[[GTN_IF_1:.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[SI_VAR_IF_1:.*]]) // CHECK: %[[GTN_IF_1:.*]] = call i32 @__kmpc_global_thread_num(ptr @[[SI_VAR_IF_1:.*]])
// CHECK: br i1 %[[IF_COND_VAR_1]], label %[[IF_COND_TRUE_BLOCK_1:.*]], label %[[IF_COND_FALSE_BLOCK_1:.*]] // CHECK: br i1 %[[IF_COND_VAR_1]], label %[[IF_COND_TRUE_BLOCK_1:.*]], label %[[IF_COND_FALSE_BLOCK_1:.*]]
// CHECK: [[IF_COND_TRUE_BLOCK_1]]: // CHECK: [[IF_COND_TRUE_BLOCK_1]]:
// CHECK: br label %[[OUTLINED_CALL_IF_BLOCK_1:.*]] // CHECK: br label %[[OUTLINED_CALL_IF_BLOCK_1:.*]]
// CHECK: [[OUTLINED_CALL_IF_BLOCK_1]]: // CHECK: [[OUTLINED_CALL_IF_BLOCK_1]]:
// CHECK: call void {{.*}} @__kmpc_fork_call(%struct.ident_t* @[[SI_VAR_IF_1]], {{.*}} @[[OMP_OUTLINED_FN_IF_1:.*]] to void // CHECK: call void {{.*}} @__kmpc_fork_call(ptr @[[SI_VAR_IF_1]], {{.*}} @[[OMP_OUTLINED_FN_IF_1:.*]])
// CHECK: br label %[[OUTLINED_EXIT_IF_1:.*]] // CHECK: br label %[[OUTLINED_EXIT_IF_1:.*]]
// CHECK: [[OUTLINED_EXIT_IF_1]]: // CHECK: [[OUTLINED_EXIT_IF_1]]:
// CHECK: br label %[[OUTLINED_EXIT_IF_2:.*]] // CHECK: br label %[[OUTLINED_EXIT_IF_2:.*]]
// CHECK: [[OUTLINED_EXIT_IF_2]]: // CHECK: [[OUTLINED_EXIT_IF_2]]:
// CHECK: br label %[[RETURN_BLOCK_IF_1:.*]] // CHECK: br label %[[RETURN_BLOCK_IF_1:.*]]
// CHECK: [[IF_COND_FALSE_BLOCK_1]]: // CHECK: [[IF_COND_FALSE_BLOCK_1]]:
// CHECK: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[SI_VAR_IF_1]], i32 %[[GTN_IF_1]]) // CHECK: call void @__kmpc_serialized_parallel(ptr @[[SI_VAR_IF_1]], i32 %[[GTN_IF_1]])
// CHECK: call void @[[OMP_OUTLINED_FN_IF_1]] // CHECK: call void @[[OMP_OUTLINED_FN_IF_1]]
// CHECK: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[SI_VAR_IF_1]], i32 %[[GTN_IF_1]]) // CHECK: call void @__kmpc_end_serialized_parallel(ptr @[[SI_VAR_IF_1]], i32 %[[GTN_IF_1]])
// CHECK: br label %[[RETURN_BLOCK_IF_1]] // CHECK: br label %[[RETURN_BLOCK_IF_1]]
omp.parallel if(%1 : i1) { omp.parallel if(%1 : i1) {
omp.barrier omp.barrier
omp.terminator omp.terminator
} }
// CHECK: [[RETURN_BLOCK_IF_1]]: // CHECK: [[RETURN_BLOCK_IF_1]]:
// CHECK: ret void // CHECK: ret void
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Linesllvm.func @test_nested_alloca_ip(%arg0: i32) -> () {
llvm.return llvm.return
} }
// ----- // -----
// CHECK-LABEL: define void @test_omp_parallel_3() // CHECK-LABEL: define void @test_omp_parallel_3()
llvm.func @test_omp_parallel_3() -> () { llvm.func @test_omp_parallel_3() -> () {
// CHECK: [[OMP_THREAD_3_1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @{{[0-9]+}}) // CHECK: [[OMP_THREAD_3_1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @{{[0-9]+}})
// CHECK: call void @__kmpc_push_proc_bind(%struct.ident_t* @{{[0-9]+}}, i32 [[OMP_THREAD_3_1]], i32 2) // CHECK: call void @__kmpc_push_proc_bind(ptr @{{[0-9]+}}, i32 [[OMP_THREAD_3_1]], i32 2)
// CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_3_1:.*]] to {{.*}} // CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_3_1:.*]])
omp.parallel proc_bind(master) { omp.parallel proc_bind(master) {
omp.barrier omp.barrier
omp.terminator omp.terminator
} }
// CHECK: [[OMP_THREAD_3_2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @{{[0-9]+}}) // CHECK: [[OMP_THREAD_3_2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @{{[0-9]+}})
// CHECK: call void @__kmpc_push_proc_bind(%struct.ident_t* @{{[0-9]+}}, i32 [[OMP_THREAD_3_2]], i32 3) // CHECK: call void @__kmpc_push_proc_bind(ptr @{{[0-9]+}}, i32 [[OMP_THREAD_3_2]], i32 3)
// CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_3_2:.*]] to {{.*}} // CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_3_2:.*]])
omp.parallel proc_bind(close) { omp.parallel proc_bind(close) {
omp.barrier omp.barrier
omp.terminator omp.terminator
} }
// CHECK: [[OMP_THREAD_3_3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @{{[0-9]+}}) // CHECK: [[OMP_THREAD_3_3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @{{[0-9]+}})
// CHECK: call void @__kmpc_push_proc_bind(%struct.ident_t* @{{[0-9]+}}, i32 [[OMP_THREAD_3_3]], i32 4) // CHECK: call void @__kmpc_push_proc_bind(ptr @{{[0-9]+}}, i32 [[OMP_THREAD_3_3]], i32 4)
// CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_3_3:.*]] to {{.*}} // CHECK: call void{{.*}}@__kmpc_fork_call{{.*}}@[[OMP_OUTLINED_FN_3_3:.*]])
omp.parallel proc_bind(spread) { omp.parallel proc_bind(spread) {
omp.barrier omp.barrier
omp.terminator omp.terminator
} }
llvm.return llvm.return
} }
// CHECK: define internal void @[[OMP_OUTLINED_FN_3_3]] // CHECK: define internal void @[[OMP_OUTLINED_FN_3_3]]
// CHECK: define internal void @[[OMP_OUTLINED_FN_3_2]] // CHECK: define internal void @[[OMP_OUTLINED_FN_3_2]]
// CHECK: define internal void @[[OMP_OUTLINED_FN_3_1]] // CHECK: define internal void @[[OMP_OUTLINED_FN_3_1]]
// CHECK-LABEL: define void @test_omp_parallel_4() // CHECK-LABEL: define void @test_omp_parallel_4()
llvm.func @test_omp_parallel_4() -> () { llvm.func @test_omp_parallel_4() -> () {
// CHECK: call void {{.*}}@__kmpc_fork_call{{.*}} @[[OMP_OUTLINED_FN_4_1:.*]] to // CHECK: call void {{.*}}@__kmpc_fork_call{{.*}} @[[OMP_OUTLINED_FN_4_1:.*]])
// CHECK: define internal void @[[OMP_OUTLINED_FN_4_1]] // CHECK: define internal void @[[OMP_OUTLINED_FN_4_1]]
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
// CHECK: call void {{.*}}@__kmpc_fork_call{{.*}} @[[OMP_OUTLINED_FN_4_1_1:.*]] to // CHECK: call void {{.*}}@__kmpc_fork_call{{.*}} @[[OMP_OUTLINED_FN_4_1_1:.*]])
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
omp.parallel { omp.parallel {
omp.barrier omp.barrier
// CHECK: define internal void @[[OMP_OUTLINED_FN_4_1_1]] // CHECK: define internal void @[[OMP_OUTLINED_FN_4_1_1]]
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
omp.parallel { omp.parallel {
omp.barrier omp.barrier
omp.terminator omp.terminator
} }
omp.barrier omp.barrier
omp.terminator omp.terminator
} }
llvm.return llvm.return
} }
llvm.func @test_omp_parallel_5() -> () { llvm.func @test_omp_parallel_5() -> () {
// CHECK: call void {{.*}}@__kmpc_fork_call{{.*}} @[[OMP_OUTLINED_FN_5_1:.*]] to // CHECK: call void {{.*}}@__kmpc_fork_call{{.*}} @[[OMP_OUTLINED_FN_5_1:.*]])
// CHECK: define internal void @[[OMP_OUTLINED_FN_5_1]] // CHECK: define internal void @[[OMP_OUTLINED_FN_5_1]]
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
// CHECK: call void {{.*}}@__kmpc_fork_call{{.*}} @[[OMP_OUTLINED_FN_5_1_1:.*]] to // CHECK: call void {{.*}}@__kmpc_fork_call{{.*}} @[[OMP_OUTLINED_FN_5_1_1:.*]])
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
omp.parallel { omp.parallel {
omp.barrier omp.barrier
// CHECK: define internal void @[[OMP_OUTLINED_FN_5_1_1]] // CHECK: define internal void @[[OMP_OUTLINED_FN_5_1_1]]
omp.parallel { omp.parallel {
// CHECK: call void {{.*}}@__kmpc_fork_call{{.*}} @[[OMP_OUTLINED_FN_5_1_1_1:.*]] to // CHECK: call void {{.*}}@__kmpc_fork_call{{.*}} @[[OMP_OUTLINED_FN_5_1_1_1:.*]])
// CHECK: define internal void @[[OMP_OUTLINED_FN_5_1_1_1]] // CHECK: define internal void @[[OMP_OUTLINED_FN_5_1_1_1]]
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
omp.parallel { omp.parallel {
omp.barrier omp.barrier
omp.terminator omp.terminator
} }
omp.terminator omp.terminator
} }
omp.barrier omp.barrier
omp.terminator omp.terminator
} }
llvm.return llvm.return
} }
// CHECK-LABEL: define void @test_omp_master() // CHECK-LABEL: define void @test_omp_master()
llvm.func @test_omp_master() -> () { llvm.func @test_omp_master() -> () {
// CHECK: call void {{.*}}@__kmpc_fork_call{{.*}} @{{.*}} to // CHECK: call void {{.*}}@__kmpc_fork_call{{.*}} @{{.*}})
// CHECK: omp.par.region1: // CHECK: omp.par.region1:
omp.parallel { omp.parallel {
omp.master { omp.master {
// CHECK: [[OMP_THREAD_3_4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @{{[0-9]+}}) // CHECK: [[OMP_THREAD_3_4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @{{[0-9]+}})
// CHECK: {{[0-9]+}} = call i32 @__kmpc_master(%struct.ident_t* @{{[0-9]+}}, i32 [[OMP_THREAD_3_4]]) // CHECK: {{[0-9]+}} = call i32 @__kmpc_master(ptr @{{[0-9]+}}, i32 [[OMP_THREAD_3_4]])
// CHECK: omp.master.region // CHECK: omp.master.region
// CHECK: call void @__kmpc_end_master(%struct.ident_t* @{{[0-9]+}}, i32 [[OMP_THREAD_3_4]]) // CHECK: call void @__kmpc_end_master(ptr @{{[0-9]+}}, i32 [[OMP_THREAD_3_4]])
// CHECK: br label %omp_region.end // CHECK: br label %omp_region.end
omp.terminator omp.terminator
} }
omp.terminator omp.terminator
} }
omp.parallel { omp.parallel {
omp.parallel { omp.parallel {
omp.master { omp.master {
omp.terminator omp.terminator
} }
omp.terminator omp.terminator
} }
omp.terminator omp.terminator
} }
llvm.return llvm.return
} }
// ----- // -----
// CHECK: %struct.ident_t = type // CHECK: %struct.ident_t = type
// CHECK: @[[$parallel_loc:.*]] = private unnamed_addr constant {{.*}} c";LLVMDialectModule;wsloop_simple;{{[0-9]+}};{{[0-9]+}};;\00" // CHECK: @[[$parallel_loc:.*]] = private unnamed_addr constant {{.*}} c";LLVMDialectModule;wsloop_simple;{{[0-9]+}};{{[0-9]+}};;\00"
// CHECK: @[[$parallel_loc_struct:.*]] = private unnamed_addr constant %struct.ident_t {{.*}} @[[$parallel_loc]], {{.*}} // CHECK: @[[$parallel_loc_struct:.*]] = private unnamed_addr constant %struct.ident_t {{.*}} @[[$parallel_loc]] {{.*}}
// CHECK: @[[$wsloop_loc:.*]] = private unnamed_addr constant {{.*}} c";LLVMDialectModule;wsloop_simple;{{[0-9]+}};{{[0-9]+}};;\00" // CHECK: @[[$wsloop_loc:.*]] = private unnamed_addr constant {{.*}} c";LLVMDialectModule;wsloop_simple;{{[0-9]+}};{{[0-9]+}};;\00"
// CHECK: @[[$wsloop_loc_struct:.*]] = private unnamed_addr constant %struct.ident_t {{.*}} @[[$wsloop_loc]], {{.*}} // CHECK: @[[$wsloop_loc_struct:.*]] = private unnamed_addr constant %struct.ident_t {{.*}} @[[$wsloop_loc]] {{.*}}
// CHECK-LABEL: @wsloop_simple // CHECK-LABEL: @wsloop_simple
llvm.func @wsloop_simple(%arg0: !llvm.ptr<f32>) { llvm.func @wsloop_simple(%arg0: !llvm.ptr<f32>) {
%0 = llvm.mlir.constant(42 : index) : i64 %0 = llvm.mlir.constant(42 : index) : i64
%1 = llvm.mlir.constant(10 : index) : i64 %1 = llvm.mlir.constant(10 : index) : i64
%2 = llvm.mlir.constant(1 : index) : i64 %2 = llvm.mlir.constant(1 : index) : i64
omp.parallel { omp.parallel {
"omp.wsloop"(%1, %0, %2) ({ "omp.wsloop"(%1, %0, %2) ({
^bb0(%arg1: i64): ^bb0(%arg1: i64):
// The form of the emitted IR is controlled by OpenMPIRBuilder and // The form of the emitted IR is controlled by OpenMPIRBuilder and
// tested there. Just check that the right functions are called. // tested there. Just check that the right functions are called.
// CHECK: call i32 @__kmpc_global_thread_num // CHECK: call i32 @__kmpc_global_thread_num
// CHECK: call void @__kmpc_for_static_init_{{.*}}(%struct.ident_t* @[[$wsloop_loc_struct]], // CHECK: call void @__kmpc_for_static_init_{{.*}}(ptr @[[$wsloop_loc_struct]],
%3 = llvm.mlir.constant(2.000000e+00 : f32) : f32 %3 = llvm.mlir.constant(2.000000e+00 : f32) : f32
%4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
llvm.store %3, %4 : !llvm.ptr<f32> llvm.store %3, %4 : !llvm.ptr<f32>
omp.yield omp.yield
// CHECK: call void @__kmpc_for_static_fini(%struct.ident_t* @[[$wsloop_loc_struct]], // CHECK: call void @__kmpc_for_static_fini(ptr @[[$wsloop_loc_struct]],
}) {operand_segment_sizes = dense<[1, 1, 1, 0, 0, 0, 0]> : vector<7xi32>} : (i64, i64, i64) -> () }) {operand_segment_sizes = dense<[1, 1, 1, 0, 0, 0, 0]> : vector<7xi32>} : (i64, i64, i64) -> ()
omp.terminator omp.terminator
} }
llvm.return llvm.return
} }
// ----- // -----
// CHECK-LABEL: @wsloop_inclusive_1 // CHECK-LABEL: @wsloop_inclusive_1
llvm.func @wsloop_inclusive_1(%arg0: !llvm.ptr<f32>) { llvm.func @wsloop_inclusive_1(%arg0: !llvm.ptr<f32>) {
%0 = llvm.mlir.constant(42 : index) : i64 %0 = llvm.mlir.constant(42 : index) : i64
%1 = llvm.mlir.constant(10 : index) : i64 %1 = llvm.mlir.constant(10 : index) : i64
%2 = llvm.mlir.constant(1 : index) : i64 %2 = llvm.mlir.constant(1 : index) : i64
// CHECK: store i64 31, i64* %{{.*}}upperbound // CHECK: store i64 31, ptr %{{.*}}upperbound
"omp.wsloop"(%1, %0, %2) ({ "omp.wsloop"(%1, %0, %2) ({
^bb0(%arg1: i64): ^bb0(%arg1: i64):
%3 = llvm.mlir.constant(2.000000e+00 : f32) : f32 %3 = llvm.mlir.constant(2.000000e+00 : f32) : f32
%4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
llvm.store %3, %4 : !llvm.ptr<f32> llvm.store %3, %4 : !llvm.ptr<f32>
omp.yield omp.yield
}) {operand_segment_sizes = dense<[1, 1, 1, 0, 0, 0, 0]> : vector<7xi32>} : (i64, i64, i64) -> () }) {operand_segment_sizes = dense<[1, 1, 1, 0, 0, 0, 0]> : vector<7xi32>} : (i64, i64, i64) -> ()
llvm.return llvm.return
} }
// ----- // -----
// CHECK-LABEL: @wsloop_inclusive_2 // CHECK-LABEL: @wsloop_inclusive_2
llvm.func @wsloop_inclusive_2(%arg0: !llvm.ptr<f32>) { llvm.func @wsloop_inclusive_2(%arg0: !llvm.ptr<f32>) {
%0 = llvm.mlir.constant(42 : index) : i64 %0 = llvm.mlir.constant(42 : index) : i64
%1 = llvm.mlir.constant(10 : index) : i64 %1 = llvm.mlir.constant(10 : index) : i64
%2 = llvm.mlir.constant(1 : index) : i64 %2 = llvm.mlir.constant(1 : index) : i64
// CHECK: store i64 32, i64* %{{.*}}upperbound // CHECK: store i64 32, ptr %{{.*}}upperbound
"omp.wsloop"(%1, %0, %2) ({ "omp.wsloop"(%1, %0, %2) ({
^bb0(%arg1: i64): ^bb0(%arg1: i64):
%3 = llvm.mlir.constant(2.000000e+00 : f32) : f32 %3 = llvm.mlir.constant(2.000000e+00 : f32) : f32
%4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32> %4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
llvm.store %3, %4 : !llvm.ptr<f32> llvm.store %3, %4 : !llvm.ptr<f32>
omp.yield omp.yield
}) {inclusive, operand_segment_sizes = dense<[1, 1, 1, 0, 0, 0, 0]> : vector<7xi32>} : (i64, i64, i64) -> () }) {inclusive, operand_segment_sizes = dense<[1, 1, 1, 0, 0, 0, 0]> : vector<7xi32>} : (i64, i64, i64) -> ()
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i32) llvm.func @body(i32)
// CHECK-LABEL: @test_omp_wsloop_static_defchunk // CHECK-LABEL: @test_omp_wsloop_static_defchunk
llvm.func @test_omp_wsloop_static_defchunk(%lb : i32, %ub : i32, %step : i32) -> () { llvm.func @test_omp_wsloop_static_defchunk(%lb : i32, %ub : i32, %step : i32) -> () {
omp.wsloop schedule(static) omp.wsloop schedule(static)
for (%iv) : i32 = (%lb) to (%ub) step (%step) { for (%iv) : i32 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_for_static_init_4u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 34, i32* %{{.*}}, i32* %{{.*}}, i32* %{{.*}}, i32* %{{.*}}, i32 1, i32 0) // CHECK: call void @__kmpc_for_static_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 34, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, i32 1, i32 0)
// CHECK: call void @__kmpc_for_static_fini // CHECK: call void @__kmpc_for_static_fini
llvm.call @body(%iv) : (i32) -> () llvm.call @body(%iv) : (i32) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i32) llvm.func @body(i32)
// CHECK-LABEL: @test_omp_wsloop_static_1 // CHECK-LABEL: @test_omp_wsloop_static_1
llvm.func @test_omp_wsloop_static_1(%lb : i32, %ub : i32, %step : i32) -> () { llvm.func @test_omp_wsloop_static_1(%lb : i32, %ub : i32, %step : i32) -> () {
%static_chunk_size = llvm.mlir.constant(1 : i32) : i32 %static_chunk_size = llvm.mlir.constant(1 : i32) : i32
omp.wsloop schedule(static = %static_chunk_size : i32) omp.wsloop schedule(static = %static_chunk_size : i32)
for (%iv) : i32 = (%lb) to (%ub) step (%step) { for (%iv) : i32 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_for_static_init_4u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 33, i32* %{{.*}}, i32* %{{.*}}, i32* %{{.*}}, i32* %{{.*}}, i32 1, i32 1) // CHECK: call void @__kmpc_for_static_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 33, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, i32 1, i32 1)
// CHECK: call void @__kmpc_for_static_fini // CHECK: call void @__kmpc_for_static_fini
llvm.call @body(%iv) : (i32) -> () llvm.call @body(%iv) : (i32) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i32) llvm.func @body(i32)
// CHECK-LABEL: @test_omp_wsloop_static_2 // CHECK-LABEL: @test_omp_wsloop_static_2
llvm.func @test_omp_wsloop_static_2(%lb : i32, %ub : i32, %step : i32) -> () { llvm.func @test_omp_wsloop_static_2(%lb : i32, %ub : i32, %step : i32) -> () {
%static_chunk_size = llvm.mlir.constant(2 : i32) : i32 %static_chunk_size = llvm.mlir.constant(2 : i32) : i32
omp.wsloop schedule(static = %static_chunk_size : i32) omp.wsloop schedule(static = %static_chunk_size : i32)
for (%iv) : i32 = (%lb) to (%ub) step (%step) { for (%iv) : i32 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_for_static_init_4u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 33, i32* %{{.*}}, i32* %{{.*}}, i32* %{{.*}}, i32* %{{.*}}, i32 1, i32 2) // CHECK: call void @__kmpc_for_static_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 33, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, i32 1, i32 2)
// CHECK: call void @__kmpc_for_static_fini // CHECK: call void @__kmpc_for_static_fini
llvm.call @body(%iv) : (i32) -> () llvm.call @body(%iv) : (i32) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
Show All 16 Lines
// ----- // -----
llvm.func @body(i64) llvm.func @body(i64)
llvm.func @test_omp_wsloop_dynamic_chunk_const(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @test_omp_wsloop_dynamic_chunk_const(%lb : i64, %ub : i64, %step : i64) -> () {
%chunk_size_const = llvm.mlir.constant(2 : i16) : i16 %chunk_size_const = llvm.mlir.constant(2 : i16) : i16
omp.wsloop schedule(dynamic = %chunk_size_const : i16) omp.wsloop schedule(dynamic = %chunk_size_const : i16)
for (%iv) : i64 = (%lb) to (%ub) step (%step) { for (%iv) : i64 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 1073741859, i64 {{.*}}, i64 %{{.*}}, i64 {{.*}}, i64 2) // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859, i64 {{.*}}, i64 %{{.*}}, i64 {{.*}}, i64 2)
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i64) -> () llvm.call @body(%iv) : (i64) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i32) llvm.func @body(i32)
llvm.func @test_omp_wsloop_dynamic_chunk_var(%lb : i32, %ub : i32, %step : i32) -> () { llvm.func @test_omp_wsloop_dynamic_chunk_var(%lb : i32, %ub : i32, %step : i32) -> () {
%1 = llvm.mlir.constant(1 : i64) : i64 %1 = llvm.mlir.constant(1 : i64) : i64
%chunk_size_alloca = llvm.alloca %1 x i16 {bindc_name = "chunk_size", in_type = i16, uniq_name = "_QFsub1Echunk_size"} : (i64) -> !llvm.ptr<i16> %chunk_size_alloca = llvm.alloca %1 x i16 {bindc_name = "chunk_size", in_type = i16, uniq_name = "_QFsub1Echunk_size"} : (i64) -> !llvm.ptr<i16>
%chunk_size_var = llvm.load %chunk_size_alloca : !llvm.ptr<i16> %chunk_size_var = llvm.load %chunk_size_alloca : !llvm.ptr<i16>
omp.wsloop schedule(dynamic = %chunk_size_var : i16) omp.wsloop schedule(dynamic = %chunk_size_var : i16)
for (%iv) : i32 = (%lb) to (%ub) step (%step) { for (%iv) : i32 = (%lb) to (%ub) step (%step) {
// CHECK: %[[CHUNK_SIZE:.*]] = sext i16 %{{.*}} to i32 // CHECK: %[[CHUNK_SIZE:.*]] = sext i16 %{{.*}} to i32
// CHECK: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 1073741859, i32 {{.*}}, i32 %{{.*}}, i32 {{.*}}, i32 %[[CHUNK_SIZE]]) // CHECK: call void @__kmpc_dispatch_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859, i32 {{.*}}, i32 %{{.*}}, i32 {{.*}}, i32 %[[CHUNK_SIZE]])
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i32) -> () llvm.call @body(%iv) : (i32) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i32) llvm.func @body(i32)
llvm.func @test_omp_wsloop_dynamic_chunk_var2(%lb : i32, %ub : i32, %step : i32) -> () { llvm.func @test_omp_wsloop_dynamic_chunk_var2(%lb : i32, %ub : i32, %step : i32) -> () {
%1 = llvm.mlir.constant(1 : i64) : i64 %1 = llvm.mlir.constant(1 : i64) : i64
%chunk_size_alloca = llvm.alloca %1 x i64 {bindc_name = "chunk_size", in_type = i64, uniq_name = "_QFsub1Echunk_size"} : (i64) -> !llvm.ptr<i64> %chunk_size_alloca = llvm.alloca %1 x i64 {bindc_name = "chunk_size", in_type = i64, uniq_name = "_QFsub1Echunk_size"} : (i64) -> !llvm.ptr<i64>
%chunk_size_var = llvm.load %chunk_size_alloca : !llvm.ptr<i64> %chunk_size_var = llvm.load %chunk_size_alloca : !llvm.ptr<i64>
omp.wsloop schedule(dynamic = %chunk_size_var : i64) omp.wsloop schedule(dynamic = %chunk_size_var : i64)
for (%iv) : i32 = (%lb) to (%ub) step (%step) { for (%iv) : i32 = (%lb) to (%ub) step (%step) {
// CHECK: %[[CHUNK_SIZE:.*]] = trunc i64 %{{.*}} to i32 // CHECK: %[[CHUNK_SIZE:.*]] = trunc i64 %{{.*}} to i32
// CHECK: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 1073741859, i32 {{.*}}, i32 %{{.*}}, i32 {{.*}}, i32 %[[CHUNK_SIZE]]) // CHECK: call void @__kmpc_dispatch_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859, i32 {{.*}}, i32 %{{.*}}, i32 {{.*}}, i32 %[[CHUNK_SIZE]])
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i32) -> () llvm.call @body(%iv) : (i32) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i32) llvm.func @body(i32)
llvm.func @test_omp_wsloop_dynamic_chunk_var3(%lb : i32, %ub : i32, %step : i32, %chunk_size : i32) -> () { llvm.func @test_omp_wsloop_dynamic_chunk_var3(%lb : i32, %ub : i32, %step : i32, %chunk_size : i32) -> () {
omp.wsloop schedule(dynamic = %chunk_size : i32) omp.wsloop schedule(dynamic = %chunk_size : i32)
for (%iv) : i32 = (%lb) to (%ub) step (%step) { for (%iv) : i32 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 1073741859, i32 {{.*}}, i32 %{{.*}}, i32 {{.*}}, i32 %{{.*}}) // CHECK: call void @__kmpc_dispatch_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859, i32 {{.*}}, i32 %{{.*}}, i32 {{.*}}, i32 %{{.*}})
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i32) -> () llvm.call @body(%iv) : (i32) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
// ----- // -----
llvm.func @body(i64) llvm.func @body(i64)
llvm.func @test_omp_wsloop_dynamic_nonmonotonic(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @test_omp_wsloop_dynamic_nonmonotonic(%lb : i64, %ub : i64, %step : i64) -> () {
omp.wsloop schedule(dynamic, nonmonotonic) omp.wsloop schedule(dynamic, nonmonotonic)
for (%iv) : i64 = (%lb) to (%ub) step (%step) { for (%iv) : i64 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 1073741859 // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i64) -> () llvm.call @body(%iv) : (i64) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i64) llvm.func @body(i64)
llvm.func @test_omp_wsloop_dynamic_monotonic(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @test_omp_wsloop_dynamic_monotonic(%lb : i64, %ub : i64, %step : i64) -> () {
omp.wsloop schedule(dynamic, monotonic) omp.wsloop schedule(dynamic, monotonic)
for (%iv) : i64 = (%lb) to (%ub) step (%step) { for (%iv) : i64 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 536870947 // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 536870947
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i64) -> () llvm.call @body(%iv) : (i64) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i64) llvm.func @body(i64)
llvm.func @test_omp_wsloop_runtime_simd(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @test_omp_wsloop_runtime_simd(%lb : i64, %ub : i64, %step : i64) -> () {
omp.wsloop schedule(runtime, simd) omp.wsloop schedule(runtime, simd)
for (%iv) : i64 = (%lb) to (%ub) step (%step) { for (%iv) : i64 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 1073741871 // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741871
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i64) -> () llvm.call @body(%iv) : (i64) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i64) llvm.func @body(i64)
llvm.func @test_omp_wsloop_guided_simd(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @test_omp_wsloop_guided_simd(%lb : i64, %ub : i64, %step : i64) -> () {
omp.wsloop schedule(guided, simd) omp.wsloop schedule(guided, simd)
for (%iv) : i64 = (%lb) to (%ub) step (%step) { for (%iv) : i64 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 1073741870 // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741870
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i64) -> () llvm.call @body(%iv) : (i64) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
// ----- // -----
llvm.func @body(i64) llvm.func @body(i64)
llvm.func @test_omp_wsloop_ordered(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @test_omp_wsloop_ordered(%lb : i64, %ub : i64, %step : i64) -> () {
omp.wsloop ordered(0) omp.wsloop ordered(0)
for (%iv) : i64 = (%lb) to (%ub) step (%step) { for (%iv) : i64 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 66, i64 1, i64 %{{.*}}, i64 1, i64 1) // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 66, i64 1, i64 %{{.*}}, i64 1, i64 1)
// CHECK: call void @__kmpc_dispatch_fini_8u // CHECK: call void @__kmpc_dispatch_fini_8u
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i64) -> () llvm.call @body(%iv) : (i64) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i64) llvm.func @body(i64)
llvm.func @test_omp_wsloop_static_ordered(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @test_omp_wsloop_static_ordered(%lb : i64, %ub : i64, %step : i64) -> () {
omp.wsloop schedule(static) ordered(0) omp.wsloop schedule(static) ordered(0)
for (%iv) : i64 = (%lb) to (%ub) step (%step) { for (%iv) : i64 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 66, i64 1, i64 %{{.*}}, i64 1, i64 1) // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 66, i64 1, i64 %{{.*}}, i64 1, i64 1)
// CHECK: call void @__kmpc_dispatch_fini_8u // CHECK: call void @__kmpc_dispatch_fini_8u
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i64) -> () llvm.call @body(%iv) : (i64) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i32) llvm.func @body(i32)
llvm.func @test_omp_wsloop_static_chunk_ordered(%lb : i32, %ub : i32, %step : i32) -> () { llvm.func @test_omp_wsloop_static_chunk_ordered(%lb : i32, %ub : i32, %step : i32) -> () {
%static_chunk_size = llvm.mlir.constant(1 : i32) : i32 %static_chunk_size = llvm.mlir.constant(1 : i32) : i32
omp.wsloop schedule(static = %static_chunk_size : i32) ordered(0) omp.wsloop schedule(static = %static_chunk_size : i32) ordered(0)
for (%iv) : i32 = (%lb) to (%ub) step (%step) { for (%iv) : i32 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 65, i32 1, i32 %{{.*}}, i32 1, i32 1) // CHECK: call void @__kmpc_dispatch_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 65, i32 1, i32 %{{.*}}, i32 1, i32 1)
// CHECK: call void @__kmpc_dispatch_fini_4u // CHECK: call void @__kmpc_dispatch_fini_4u
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i32) -> () llvm.call @body(%iv) : (i32) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i64) llvm.func @body(i64)
llvm.func @test_omp_wsloop_dynamic_ordered(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @test_omp_wsloop_dynamic_ordered(%lb : i64, %ub : i64, %step : i64) -> () {
omp.wsloop schedule(dynamic) ordered(0) omp.wsloop schedule(dynamic) ordered(0)
for (%iv) : i64 = (%lb) to (%ub) step (%step) { for (%iv) : i64 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 67, i64 1, i64 %{{.*}}, i64 1, i64 1) // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 67, i64 1, i64 %{{.*}}, i64 1, i64 1)
// CHECK: call void @__kmpc_dispatch_fini_8u // CHECK: call void @__kmpc_dispatch_fini_8u
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i64) -> () llvm.call @body(%iv) : (i64) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i64) llvm.func @body(i64)
llvm.func @test_omp_wsloop_auto_ordered(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @test_omp_wsloop_auto_ordered(%lb : i64, %ub : i64, %step : i64) -> () {
omp.wsloop schedule(auto) ordered(0) omp.wsloop schedule(auto) ordered(0)
for (%iv) : i64 = (%lb) to (%ub) step (%step) { for (%iv) : i64 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 70, i64 1, i64 %{{.*}}, i64 1, i64 1) // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 70, i64 1, i64 %{{.*}}, i64 1, i64 1)
// CHECK: call void @__kmpc_dispatch_fini_8u // CHECK: call void @__kmpc_dispatch_fini_8u
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i64) -> () llvm.call @body(%iv) : (i64) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i64) llvm.func @body(i64)
llvm.func @test_omp_wsloop_runtime_ordered(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @test_omp_wsloop_runtime_ordered(%lb : i64, %ub : i64, %step : i64) -> () {
omp.wsloop schedule(runtime) ordered(0) omp.wsloop schedule(runtime) ordered(0)
for (%iv) : i64 = (%lb) to (%ub) step (%step) { for (%iv) : i64 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 69, i64 1, i64 %{{.*}}, i64 1, i64 1) // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 69, i64 1, i64 %{{.*}}, i64 1, i64 1)
// CHECK: call void @__kmpc_dispatch_fini_8u // CHECK: call void @__kmpc_dispatch_fini_8u
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i64) -> () llvm.call @body(%iv) : (i64) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i64) llvm.func @body(i64)
llvm.func @test_omp_wsloop_guided_ordered(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @test_omp_wsloop_guided_ordered(%lb : i64, %ub : i64, %step : i64) -> () {
omp.wsloop schedule(guided) ordered(0) omp.wsloop schedule(guided) ordered(0)
for (%iv) : i64 = (%lb) to (%ub) step (%step) { for (%iv) : i64 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 68, i64 1, i64 %{{.*}}, i64 1, i64 1) // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 68, i64 1, i64 %{{.*}}, i64 1, i64 1)
// CHECK: call void @__kmpc_dispatch_fini_8u // CHECK: call void @__kmpc_dispatch_fini_8u
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i64) -> () llvm.call @body(%iv) : (i64) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i64) llvm.func @body(i64)
llvm.func @test_omp_wsloop_dynamic_nonmonotonic_ordered(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @test_omp_wsloop_dynamic_nonmonotonic_ordered(%lb : i64, %ub : i64, %step : i64) -> () {
omp.wsloop schedule(dynamic, nonmonotonic) ordered(0) omp.wsloop schedule(dynamic, nonmonotonic) ordered(0)
for (%iv) : i64 = (%lb) to (%ub) step (%step) { for (%iv) : i64 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 1073741891, i64 1, i64 %{{.*}}, i64 1, i64 1) // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741891, i64 1, i64 %{{.*}}, i64 1, i64 1)
// CHECK: call void @__kmpc_dispatch_fini_8u // CHECK: call void @__kmpc_dispatch_fini_8u
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i64) -> () llvm.call @body(%iv) : (i64) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
llvm.func @body(i64) llvm.func @body(i64)
llvm.func @test_omp_wsloop_dynamic_monotonic_ordered(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @test_omp_wsloop_dynamic_monotonic_ordered(%lb : i64, %ub : i64, %step : i64) -> () {
omp.wsloop schedule(dynamic, monotonic) ordered(0) omp.wsloop schedule(dynamic, monotonic) ordered(0)
for (%iv) : i64 = (%lb) to (%ub) step (%step) { for (%iv) : i64 = (%lb) to (%ub) step (%step) {
// CHECK: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @{{.*}}, i32 %{{.*}}, i32 536870979, i64 1, i64 %{{.*}}, i64 1, i64 1) // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 536870979, i64 1, i64 %{{.*}}, i64 1, i64 1)
// CHECK: call void @__kmpc_dispatch_fini_8u // CHECK: call void @__kmpc_dispatch_fini_8u
// CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u
// CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0
// CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}}
llvm.call @body(%iv) : (i64) -> () llvm.call @body(%iv) : (i64) -> ()
omp.yield omp.yield
} }
llvm.return llvm.return
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
// ----- // -----
// Check that the loop bounds are emitted in the correct location in case of // Check that the loop bounds are emitted in the correct location in case of
// collapse. This only checks the overall shape of the IR, detailed checking // collapse. This only checks the overall shape of the IR, detailed checking
// is done by the OpenMPIRBuilder. // is done by the OpenMPIRBuilder.
// CHECK-LABEL: @collapse_wsloop // CHECK-LABEL: @collapse_wsloop
// CHECK: i32* noalias %[[TIDADDR:[0-9A-Za-z.]*]] // CHECK: ptr noalias %[[TIDADDR:[0-9A-Za-z.]*]]
// CHECK: load i32, i32* %[[TIDADDR]] // CHECK: load i32, ptr %[[TIDADDR]]
// CHECK: store // CHECK: store
// CHECK: load // CHECK: load
// CHECK: %[[LB0:.*]] = load i32 // CHECK: %[[LB0:.*]] = load i32
// CHECK: %[[UB0:.*]] = load i32 // CHECK: %[[UB0:.*]] = load i32
// CHECK: %[[STEP0:.*]] = load i32 // CHECK: %[[STEP0:.*]] = load i32
// CHECK: %[[LB1:.*]] = load i32 // CHECK: %[[LB1:.*]] = load i32
// CHECK: %[[UB1:.*]] = load i32 // CHECK: %[[UB1:.*]] = load i32
// CHECK: %[[STEP1:.*]] = load i32 // CHECK: %[[STEP1:.*]] = load i32
Show All 18 Lines omp.parallel {
// CHECK: icmp slt i32 %[[LB2]], 0 // CHECK: icmp slt i32 %[[LB2]], 0
// CHECK-COUNT-4: select // CHECK-COUNT-4: select
// CHECK: %[[TRIPCOUNT2:.*]] = select // CHECK: %[[TRIPCOUNT2:.*]] = select
// CHECK: %[[PROD:.*]] = mul nuw i32 %[[TRIPCOUNT0]], %[[TRIPCOUNT1]] // CHECK: %[[PROD:.*]] = mul nuw i32 %[[TRIPCOUNT0]], %[[TRIPCOUNT1]]
// CHECK: %[[TOTAL:.*]] = mul nuw i32 %[[PROD]], %[[TRIPCOUNT2]] // CHECK: %[[TOTAL:.*]] = mul nuw i32 %[[PROD]], %[[TRIPCOUNT2]]
// CHECK: br label %[[COLLAPSED_PREHEADER:.*]] // CHECK: br label %[[COLLAPSED_PREHEADER:.*]]
// //
// CHECK: [[COLLAPSED_PREHEADER]]: // CHECK: [[COLLAPSED_PREHEADER]]:
// CHECK: store i32 0, i32* // CHECK: store i32 0, ptr
// CHECK: %[[TOTAL_SUB_1:.*]] = sub i32 %[[TOTAL]], 1 // CHECK: %[[TOTAL_SUB_1:.*]] = sub i32 %[[TOTAL]], 1
// CHECK: store i32 %[[TOTAL_SUB_1]], i32* // CHECK: store i32 %[[TOTAL_SUB_1]], ptr
// CHECK: call void @__kmpc_for_static_init_4u // CHECK: call void @__kmpc_for_static_init_4u
omp.wsloop collapse(3) omp.wsloop collapse(3)
for (%arg0, %arg1, %arg2) : i32 = (%0, %1, %2) to (%3, %4, %5) step (%6, %7, %8) { for (%arg0, %arg1, %arg2) : i32 = (%0, %1, %2) to (%3, %4, %5) step (%6, %7, %8) {
%31 = llvm.load %20 : !llvm.ptr<i32> %31 = llvm.load %20 : !llvm.ptr<i32>
%32 = llvm.add %31, %arg0 : i32 %32 = llvm.add %31, %arg0 : i32
%33 = llvm.add %32, %arg1 : i32 %33 = llvm.add %32, %arg1 : i32
%34 = llvm.add %33, %arg2 : i32 %34 = llvm.add %33, %arg2 : i32
llvm.store %34, %20 : !llvm.ptr<i32> llvm.store %34, %20 : !llvm.ptr<i32>
omp.yield omp.yield
} }
omp.terminator omp.terminator
} }
llvm.return llvm.return
} }
// ----- // -----
// Check that the loop bounds are emitted in the correct location in case of // Check that the loop bounds are emitted in the correct location in case of
// collapse for dynamic schedule. This only checks the overall shape of the IR, // collapse for dynamic schedule. This only checks the overall shape of the IR,
// detailed checking is done by the OpenMPIRBuilder. // detailed checking is done by the OpenMPIRBuilder.
// CHECK-LABEL: @collapse_wsloop_dynamic // CHECK-LABEL: @collapse_wsloop_dynamic
// CHECK: i32* noalias %[[TIDADDR:[0-9A-Za-z.]*]] // CHECK: ptr noalias %[[TIDADDR:[0-9A-Za-z.]*]]
// CHECK: load i32, i32* %[[TIDADDR]] // CHECK: load i32, ptr %[[TIDADDR]]
// CHECK: store // CHECK: store
// CHECK: load // CHECK: load
// CHECK: %[[LB0:.*]] = load i32 // CHECK: %[[LB0:.*]] = load i32
// CHECK: %[[UB0:.*]] = load i32 // CHECK: %[[UB0:.*]] = load i32
// CHECK: %[[STEP0:.*]] = load i32 // CHECK: %[[STEP0:.*]] = load i32
// CHECK: %[[LB1:.*]] = load i32 // CHECK: %[[LB1:.*]] = load i32
// CHECK: %[[UB1:.*]] = load i32 // CHECK: %[[UB1:.*]] = load i32
// CHECK: %[[STEP1:.*]] = load i32 // CHECK: %[[STEP1:.*]] = load i32
Show All 19 Lines omp.parallel {
// CHECK: icmp slt i32 %[[LB2]], 0 // CHECK: icmp slt i32 %[[LB2]], 0
// CHECK-COUNT-4: select // CHECK-COUNT-4: select
// CHECK: %[[TRIPCOUNT2:.*]] = select // CHECK: %[[TRIPCOUNT2:.*]] = select
// CHECK: %[[PROD:.*]] = mul nuw i32 %[[TRIPCOUNT0]], %[[TRIPCOUNT1]] // CHECK: %[[PROD:.*]] = mul nuw i32 %[[TRIPCOUNT0]], %[[TRIPCOUNT1]]
// CHECK: %[[TOTAL:.*]] = mul nuw i32 %[[PROD]], %[[TRIPCOUNT2]] // CHECK: %[[TOTAL:.*]] = mul nuw i32 %[[PROD]], %[[TRIPCOUNT2]]
// CHECK: br label %[[COLLAPSED_PREHEADER:.*]] // CHECK: br label %[[COLLAPSED_PREHEADER:.*]]
// //
// CHECK: [[COLLAPSED_PREHEADER]]: // CHECK: [[COLLAPSED_PREHEADER]]:
// CHECK: store i32 1, i32* // CHECK: store i32 1, ptr
// CHECK: store i32 %[[TOTAL]], i32* // CHECK: store i32 %[[TOTAL]], ptr
// CHECK: call void @__kmpc_dispatch_init_4u // CHECK: call void @__kmpc_dispatch_init_4u
omp.wsloop collapse(3) schedule(dynamic) omp.wsloop collapse(3) schedule(dynamic)
for (%arg0, %arg1, %arg2) : i32 = (%0, %1, %2) to (%3, %4, %5) step (%6, %7, %8) { for (%arg0, %arg1, %arg2) : i32 = (%0, %1, %2) to (%3, %4, %5) step (%6, %7, %8) {
%31 = llvm.load %20 : !llvm.ptr<i32> %31 = llvm.load %20 : !llvm.ptr<i32>
%32 = llvm.add %31, %arg0 : i32 %32 = llvm.add %31, %arg0 : i32
%33 = llvm.add %32, %arg1 : i32 %33 = llvm.add %32, %arg1 : i32
%34 = llvm.add %33, %arg2 : i32 %34 = llvm.add %33, %arg2 : i32
llvm.store %34, %20 : !llvm.ptr<i32> llvm.store %34, %20 : !llvm.ptr<i32>
Show All 10 Lines
llvm.func @omp_ordered(%arg0 : i32, %arg1 : i32, %arg2 : i32, %arg3 : i64, llvm.func @omp_ordered(%arg0 : i32, %arg1 : i32, %arg2 : i32, %arg3 : i64,
%arg4: i64, %arg5: i64, %arg6: i64) -> () { %arg4: i64, %arg5: i64, %arg6: i64) -> () {
// CHECK: [[ADDR9:%.*]] = alloca [2 x i64], align 8 // CHECK: [[ADDR9:%.*]] = alloca [2 x i64], align 8
// CHECK: [[ADDR7:%.*]] = alloca [2 x i64], align 8 // CHECK: [[ADDR7:%.*]] = alloca [2 x i64], align 8
// CHECK: [[ADDR5:%.*]] = alloca [2 x i64], align 8 // CHECK: [[ADDR5:%.*]] = alloca [2 x i64], align 8
// CHECK: [[ADDR3:%.*]] = alloca [1 x i64], align 8 // CHECK: [[ADDR3:%.*]] = alloca [1 x i64], align 8
// CHECK: [[ADDR:%.*]] = alloca [1 x i64], align 8 // CHECK: [[ADDR:%.*]] = alloca [1 x i64], align 8
// CHECK: [[OMP_THREAD:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK: [[OMP_THREAD:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_THREAD]]) // CHECK-NEXT: call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_THREAD]])
omp.ordered_region { omp.ordered_region {
omp.terminator omp.terminator
// CHECK: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_THREAD]]) // CHECK: call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_THREAD]])
} }
omp.wsloop ordered(0) omp.wsloop ordered(0)
for (%arg7) : i32 = (%arg0) to (%arg1) step (%arg2) { for (%arg7) : i32 = (%arg0) to (%arg1) step (%arg2) {
// CHECK: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[OMP_THREAD2:%.*]]) // CHECK: call void @__kmpc_ordered(ptr @[[GLOB3:[0-9]+]], i32 [[OMP_THREAD2:%.*]])
omp.ordered_region { omp.ordered_region {
omp.terminator omp.terminator
// CHECK: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB3]], i32 [[OMP_THREAD2]]) // CHECK: call void @__kmpc_end_ordered(ptr @[[GLOB3]], i32 [[OMP_THREAD2]])
} }
omp.yield omp.yield
} }
omp.wsloop ordered(1) omp.wsloop ordered(1)
for (%arg7) : i32 = (%arg0) to (%arg1) step (%arg2) { for (%arg7) : i32 = (%arg0) to (%arg1) step (%arg2) {
// CHECK: [[TMP:%.*]] = getelementptr inbounds [1 x i64], [1 x i64]* [[ADDR]], i64 0, i64 0 // CHECK: [[TMP:%.*]] = getelementptr inbounds [1 x i64], ptr [[ADDR]], i64 0, i64 0
// CHECK: store i64 [[ARG0:%.*]], i64* [[TMP]], align 8 // CHECK: store i64 [[ARG0:%.*]], ptr [[TMP]], align 8
// CHECK: [[TMP2:%.*]] = getelementptr inbounds [1 x i64], [1 x i64]* [[ADDR]], i64 0, i64 0 // CHECK: [[TMP2:%.*]] = getelementptr inbounds [1 x i64], ptr [[ADDR]], i64 0, i64 0
// CHECK: [[OMP_THREAD2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) // CHECK: [[OMP_THREAD2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
// CHECK: call void @__kmpc_doacross_wait(%struct.ident_t* @[[GLOB3]], i32 [[OMP_THREAD2]], i64* [[TMP2]]) // CHECK: call void @__kmpc_doacross_wait(ptr @[[GLOB3]], i32 [[OMP_THREAD2]], ptr [[TMP2]])
omp.ordered depend_type(dependsink) depend_vec(%arg3 : i64) {num_loops_val = 1 : i64} omp.ordered depend_type(dependsink) depend_vec(%arg3 : i64) {num_loops_val = 1 : i64}
// CHECK: [[TMP3:%.*]] = getelementptr inbounds [1 x i64], [1 x i64]* [[ADDR3]], i64 0, i64 0 // CHECK: [[TMP3:%.*]] = getelementptr inbounds [1 x i64], ptr [[ADDR3]], i64 0, i64 0
// CHECK: store i64 [[ARG0]], i64* [[TMP3]], align 8 // CHECK: store i64 [[ARG0]], ptr [[TMP3]], align 8
// CHECK: [[TMP4:%.*]] = getelementptr inbounds [1 x i64], [1 x i64]* [[ADDR3]], i64 0, i64 0 // CHECK: [[TMP4:%.*]] = getelementptr inbounds [1 x i64], ptr [[ADDR3]], i64 0, i64 0
// CHECK: [[OMP_THREAD4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB5:[0-9]+]]) // CHECK: [[OMP_THREAD4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]])
// CHECK: call void @__kmpc_doacross_post(%struct.ident_t* @[[GLOB5]], i32 [[OMP_THREAD4]], i64* [[TMP4]]) // CHECK: call void @__kmpc_doacross_post(ptr @[[GLOB5]], i32 [[OMP_THREAD4]], ptr [[TMP4]])
omp.ordered depend_type(dependsource) depend_vec(%arg3 : i64) {num_loops_val = 1 : i64} omp.ordered depend_type(dependsource) depend_vec(%arg3 : i64) {num_loops_val = 1 : i64}
omp.yield omp.yield
} }
omp.wsloop ordered(2) omp.wsloop ordered(2)
for (%arg7) : i32 = (%arg0) to (%arg1) step (%arg2) { for (%arg7) : i32 = (%arg0) to (%arg1) step (%arg2) {
// CHECK: [[TMP5:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[ADDR5]], i64 0, i64 0 // CHECK: [[TMP5:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR5]], i64 0, i64 0
// CHECK: store i64 [[ARG0]], i64* [[TMP5]], align 8 // CHECK: store i64 [[ARG0]], ptr [[TMP5]], align 8
// CHECK: [[TMP6:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[ADDR5]], i64 0, i64 1 // CHECK: [[TMP6:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR5]], i64 0, i64 1
// CHECK: store i64 [[ARG1:%.*]], i64* [[TMP6]], align 8 // CHECK: store i64 [[ARG1:%.*]], ptr [[TMP6]], align 8
// CHECK: [[TMP7:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[ADDR5]], i64 0, i64 0 // CHECK: [[TMP7:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR5]], i64 0, i64 0
// CHECK: [[OMP_THREAD6:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB7:[0-9]+]]) // CHECK: [[OMP_THREAD6:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]])
// CHECK: call void @__kmpc_doacross_wait(%struct.ident_t* @[[GLOB7]], i32 [[OMP_THREAD6]], i64* [[TMP7]]) // CHECK: call void @__kmpc_doacross_wait(ptr @[[GLOB7]], i32 [[OMP_THREAD6]], ptr [[TMP7]])
// CHECK: [[TMP8:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[ADDR7]], i64 0, i64 0 // CHECK: [[TMP8:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR7]], i64 0, i64 0
// CHECK: store i64 [[ARG2:%.*]], i64* [[TMP8]], align 8 // CHECK: store i64 [[ARG2:%.*]], ptr [[TMP8]], align 8
// CHECK: [[TMP9:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[ADDR7]], i64 0, i64 1 // CHECK: [[TMP9:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR7]], i64 0, i64 1
// CHECK: store i64 [[ARG3:%.*]], i64* [[TMP9]], align 8 // CHECK: store i64 [[ARG3:%.*]], ptr [[TMP9]], align 8
// CHECK: [[TMP10:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[ADDR7]], i64 0, i64 0 // CHECK: [[TMP10:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR7]], i64 0, i64 0
// CHECK: [[OMP_THREAD8:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB7]]) // CHECK: [[OMP_THREAD8:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7]])
// CHECK: call void @__kmpc_doacross_wait(%struct.ident_t* @[[GLOB7]], i32 [[OMP_THREAD8]], i64* [[TMP10]]) // CHECK: call void @__kmpc_doacross_wait(ptr @[[GLOB7]], i32 [[OMP_THREAD8]], ptr [[TMP10]])
omp.ordered depend_type(dependsink) depend_vec(%arg3, %arg4, %arg5, %arg6 : i64, i64, i64, i64) {num_loops_val = 2 : i64} omp.ordered depend_type(dependsink) depend_vec(%arg3, %arg4, %arg5, %arg6 : i64, i64, i64, i64) {num_loops_val = 2 : i64}
// CHECK: [[TMP11:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[ADDR9]], i64 0, i64 0 // CHECK: [[TMP11:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR9]], i64 0, i64 0
// CHECK: store i64 [[ARG0]], i64* [[TMP11]], align 8 // CHECK: store i64 [[ARG0]], ptr [[TMP11]], align 8
// CHECK: [[TMP12:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[ADDR9]], i64 0, i64 1 // CHECK: [[TMP12:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR9]], i64 0, i64 1
// CHECK: store i64 [[ARG1]], i64* [[TMP12]], align 8 // CHECK: store i64 [[ARG1]], ptr [[TMP12]], align 8
// CHECK: [[TMP13:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[ADDR9]], i64 0, i64 0 // CHECK: [[TMP13:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR9]], i64 0, i64 0
// CHECK: [[OMP_THREAD10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB9:[0-9]+]]) // CHECK: [[OMP_THREAD10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]])
// CHECK: call void @__kmpc_doacross_post(%struct.ident_t* @[[GLOB9]], i32 [[OMP_THREAD10]], i64* [[TMP13]]) // CHECK: call void @__kmpc_doacross_post(ptr @[[GLOB9]], i32 [[OMP_THREAD10]], ptr [[TMP13]])
omp.ordered depend_type(dependsource) depend_vec(%arg3, %arg4 : i64, i64) {num_loops_val = 2 : i64} omp.ordered depend_type(dependsource) depend_vec(%arg3, %arg4 : i64, i64) {num_loops_val = 2 : i64}
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
// CHECK-LABEL: @omp_atomic_read // CHECK-LABEL: @omp_atomic_read
// CHECK-SAME: (i32* %[[ARG0:.*]], i32* %[[ARG1:.*]]) // CHECK-SAME: (ptr %[[ARG0:.*]], ptr %[[ARG1:.*]])
llvm.func @omp_atomic_read(%arg0 : !llvm.ptr<i32>, %arg1 : !llvm.ptr<i32>) -> () { llvm.func @omp_atomic_read(%arg0 : !llvm.ptr<i32>, %arg1 : !llvm.ptr<i32>) -> () {
// CHECK: %[[X1:.*]] = load atomic i32, i32* %[[ARG0]] monotonic, align 4 // CHECK: %[[X1:.*]] = load atomic i32, ptr %[[ARG0]] monotonic, align 4
// CHECK: store i32 %[[X1]], i32* %[[ARG1]], align 4 // CHECK: store i32 %[[X1]], ptr %[[ARG1]], align 4
omp.atomic.read %arg1 = %arg0 : !llvm.ptr<i32> omp.atomic.read %arg1 = %arg0 : !llvm.ptr<i32>
// CHECK: %[[X2:.*]] = load atomic i32, i32* %[[ARG0]] seq_cst, align 4 // CHECK: %[[X2:.*]] = load atomic i32, ptr %[[ARG0]] seq_cst, align 4
// CHECK: call void @__kmpc_flush(%{{.*}}) // CHECK: call void @__kmpc_flush(ptr @{{.*}})
// CHECK: store i32 %[[X2]], i32* %[[ARG1]], align 4 // CHECK: store i32 %[[X2]], ptr %[[ARG1]], align 4
omp.atomic.read %arg1 = %arg0 memory_order(seq_cst) : !llvm.ptr<i32> omp.atomic.read %arg1 = %arg0 memory_order(seq_cst) : !llvm.ptr<i32>
// CHECK: %[[X3:.*]] = load atomic i32, i32* %[[ARG0]] acquire, align 4 // CHECK: %[[X3:.*]] = load atomic i32, ptr %[[ARG0]] acquire, align 4
// CHECK: call void @__kmpc_flush(%{{.*}}) // CHECK: call void @__kmpc_flush(ptr @{{.*}})
// CHECK: store i32 %[[X3]], i32* %[[ARG1]], align 4 // CHECK: store i32 %[[X3]], ptr %[[ARG1]], align 4
omp.atomic.read %arg1 = %arg0 memory_order(acquire) : !llvm.ptr<i32> omp.atomic.read %arg1 = %arg0 memory_order(acquire) : !llvm.ptr<i32>
// CHECK: %[[X4:.*]] = load atomic i32, i32* %[[ARG0]] monotonic, align 4 // CHECK: %[[X4:.*]] = load atomic i32, ptr %[[ARG0]] monotonic, align 4
// CHECK: store i32 %[[X4]], i32* %[[ARG1]], align 4 // CHECK: store i32 %[[X4]], ptr %[[ARG1]], align 4
omp.atomic.read %arg1 = %arg0 memory_order(relaxed) : !llvm.ptr<i32> omp.atomic.read %arg1 = %arg0 memory_order(relaxed) : !llvm.ptr<i32>
llvm.return llvm.return
} }
// ----- // -----
// CHECK-LABEL: @omp_atomic_write // CHECK-LABEL: @omp_atomic_write
// CHECK-SAME: (i32* %[[x:.*]], i32 %[[expr:.*]]) // CHECK-SAME: (ptr %[[x:.*]], i32 %[[expr:.*]])
llvm.func @omp_atomic_write(%x: !llvm.ptr<i32>, %expr: i32) -> () { llvm.func @omp_atomic_write(%x: !llvm.ptr<i32>, %expr: i32) -> () {
// CHECK: store atomic i32 %[[expr]], i32* %[[x]] monotonic, align 4 // CHECK: store atomic i32 %[[expr]], ptr %[[x]] monotonic, align 4
omp.atomic.write %x = %expr : !llvm.ptr<i32>, i32 omp.atomic.write %x = %expr : !llvm.ptr<i32>, i32
// CHECK: store atomic i32 %[[expr]], i32* %[[x]] seq_cst, align 4 // CHECK: store atomic i32 %[[expr]], ptr %[[x]] seq_cst, align 4
// CHECK: call void @__kmpc_flush(%struct.ident_t* @{{.*}}) // CHECK: call void @__kmpc_flush(ptr @{{.*}})
omp.atomic.write %x = %expr memory_order(seq_cst) : !llvm.ptr<i32>, i32 omp.atomic.write %x = %expr memory_order(seq_cst) : !llvm.ptr<i32>, i32
// CHECK: store atomic i32 %[[expr]], i32* %[[x]] release, align 4 // CHECK: store atomic i32 %[[expr]], ptr %[[x]] release, align 4
// CHECK: call void @__kmpc_flush(%struct.ident_t* @{{.*}}) // CHECK: call void @__kmpc_flush(ptr @{{.*}})
omp.atomic.write %x = %expr memory_order(release) : !llvm.ptr<i32>, i32 omp.atomic.write %x = %expr memory_order(release) : !llvm.ptr<i32>, i32
// CHECK: store atomic i32 %[[expr]], i32* %[[x]] monotonic, align 4 // CHECK: store atomic i32 %[[expr]], ptr %[[x]] monotonic, align 4
omp.atomic.write %x = %expr memory_order(relaxed) : !llvm.ptr<i32>, i32 omp.atomic.write %x = %expr memory_order(relaxed) : !llvm.ptr<i32>, i32
llvm.return llvm.return
} }
// ----- // -----
// Checking simple atomicrmw and cmpxchg based translation. This also checks for // Checking simple atomicrmw and cmpxchg based translation. This also checks for
// ambigous alloca insert point by putting llvm.mul as the first update operation. // ambigous alloca insert point by putting llvm.mul as the first update operation.
// CHECK-LABEL: @omp_atomic_update // CHECK-LABEL: @omp_atomic_update
// CHECK-SAME: (i32* %[[x:.*]], i32 %[[expr:.*]], i1* %[[xbool:.*]], i1 %[[exprbool:.*]]) // CHECK-SAME: (ptr %[[x:.*]], i32 %[[expr:.*]], ptr %[[xbool:.*]], i1 %[[exprbool:.*]])
llvm.func @omp_atomic_update(%x:!llvm.ptr<i32>, %expr: i32, %xbool: !llvm.ptr<i1>, %exprbool: i1) { llvm.func @omp_atomic_update(%x:!llvm.ptr<i32>, %expr: i32, %xbool: !llvm.ptr<i1>, %exprbool: i1) {
// CHECK: %[[t1:.*]] = mul i32 %[[x_old:.*]], %[[expr]] // CHECK: %[[t1:.*]] = mul i32 %[[x_old:.*]], %[[expr]]
// CHECK: store i32 %[[t1]], i32* %[[x_new:.*]] // CHECK: store i32 %[[t1]], ptr %[[x_new:.*]]
// CHECK: %[[t2:.*]] = load i32, i32* %[[x_new]] // CHECK: %[[t2:.*]] = load i32, ptr %[[x_new]]
// CHECK: cmpxchg i32* %[[x]], i32 %[[x_old]], i32 %[[t2]] // CHECK: cmpxchg ptr %[[x]], i32 %[[x_old]], i32 %[[t2]]
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.mul %xval, %expr : i32 %newval = llvm.mul %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
// CHECK: atomicrmw add i32* %[[x]], i32 %[[expr]] monotonic // CHECK: atomicrmw add ptr %[[x]], i32 %[[expr]] monotonic
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.add %xval, %expr : i32 %newval = llvm.add %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
llvm.return llvm.return
} }
// ----- // -----
// Checking an order-dependent operation when the order is `expr binop x` // Checking an order-dependent operation when the order is `expr binop x`
// CHECK-LABEL: @omp_atomic_update_ordering // CHECK-LABEL: @omp_atomic_update_ordering
// CHECK-SAME: (i32* %[[x:.*]], i32 %[[expr:.*]]) // CHECK-SAME: (ptr %[[x:.*]], i32 %[[expr:.*]])
llvm.func @omp_atomic_update_ordering(%x:!llvm.ptr<i32>, %expr: i32) { llvm.func @omp_atomic_update_ordering(%x:!llvm.ptr<i32>, %expr: i32) {
// CHECK: %[[t1:.*]] = shl i32 %[[expr]], %[[x_old:[^ ,]*]] // CHECK: %[[t1:.*]] = shl i32 %[[expr]], %[[x_old:[^ ,]*]]
// CHECK: store i32 %[[t1]], i32* %[[x_new:.*]] // CHECK: store i32 %[[t1]], ptr %[[x_new:.*]]
// CHECK: %[[t2:.*]] = load i32, i32* %[[x_new]] // CHECK: %[[t2:.*]] = load i32, ptr %[[x_new]]
// CHECK: cmpxchg i32* %[[x]], i32 %[[x_old]], i32 %[[t2]] // CHECK: cmpxchg ptr %[[x]], i32 %[[x_old]], i32 %[[t2]]
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.shl %expr, %xval : i32 %newval = llvm.shl %expr, %xval : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
llvm.return llvm.return
} }
// ----- // -----
// Checking an order-dependent operation when the order is `x binop expr` // Checking an order-dependent operation when the order is `x binop expr`
// CHECK-LABEL: @omp_atomic_update_ordering // CHECK-LABEL: @omp_atomic_update_ordering
// CHECK-SAME: (i32* %[[x:.*]], i32 %[[expr:.*]]) // CHECK-SAME: (ptr %[[x:.*]], i32 %[[expr:.*]])
llvm.func @omp_atomic_update_ordering(%x:!llvm.ptr<i32>, %expr: i32) { llvm.func @omp_atomic_update_ordering(%x:!llvm.ptr<i32>, %expr: i32) {
// CHECK: %[[t1:.*]] = shl i32 %[[x_old:.*]], %[[expr]] // CHECK: %[[t1:.*]] = shl i32 %[[x_old:.*]], %[[expr]]
// CHECK: store i32 %[[t1]], i32* %[[x_new:.*]] // CHECK: store i32 %[[t1]], ptr %[[x_new:.*]]
// CHECK: %[[t2:.*]] = load i32, i32* %[[x_new]] // CHECK: %[[t2:.*]] = load i32, ptr %[[x_new]]
// CHECK: cmpxchg i32* %[[x]], i32 %[[x_old]], i32 %[[t2]] monotonic // CHECK: cmpxchg ptr %[[x]], i32 %[[x_old]], i32 %[[t2]] monotonic
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.shl %xval, %expr : i32 %newval = llvm.shl %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
llvm.return llvm.return
} }
// ----- // -----
// Checking intrinsic translation. // Checking intrinsic translation.
// CHECK-LABEL: @omp_atomic_update_intrinsic // CHECK-LABEL: @omp_atomic_update_intrinsic
// CHECK-SAME: (i32* %[[x:.*]], i32 %[[expr:.*]]) // CHECK-SAME: (ptr %[[x:.*]], i32 %[[expr:.*]])
llvm.func @omp_atomic_update_intrinsic(%x:!llvm.ptr<i32>, %expr: i32) { llvm.func @omp_atomic_update_intrinsic(%x:!llvm.ptr<i32>, %expr: i32) {
// CHECK: %[[t1:.*]] = call i32 @llvm.smax.i32(i32 %[[x_old:.*]], i32 %[[expr]]) // CHECK: %[[t1:.*]] = call i32 @llvm.smax.i32(i32 %[[x_old:.*]], i32 %[[expr]])
// CHECK: store i32 %[[t1]], i32* %[[x_new:.*]] // CHECK: store i32 %[[t1]], ptr %[[x_new:.*]]
// CHECK: %[[t2:.*]] = load i32, i32* %[[x_new]] // CHECK: %[[t2:.*]] = load i32, ptr %[[x_new]]
// CHECK: cmpxchg i32* %[[x]], i32 %[[x_old]], i32 %[[t2]] // CHECK: cmpxchg ptr %[[x]], i32 %[[x_old]], i32 %[[t2]]
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = "llvm.intr.smax"(%xval, %expr) : (i32, i32) -> i32 %newval = "llvm.intr.smax"(%xval, %expr) : (i32, i32) -> i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
// CHECK: %[[t1:.*]] = call i32 @llvm.umax.i32(i32 %[[x_old:.*]], i32 %[[expr]]) // CHECK: %[[t1:.*]] = call i32 @llvm.umax.i32(i32 %[[x_old:.*]], i32 %[[expr]])
// CHECK: store i32 %[[t1]], i32* %[[x_new:.*]] // CHECK: store i32 %[[t1]], ptr %[[x_new:.*]]
// CHECK: %[[t2:.*]] = load i32, i32* %[[x_new]] // CHECK: %[[t2:.*]] = load i32, ptr %[[x_new]]
// CHECK: cmpxchg i32* %[[x]], i32 %[[x_old]], i32 %[[t2]] // CHECK: cmpxchg ptr %[[x]], i32 %[[x_old]], i32 %[[t2]]
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = "llvm.intr.umax"(%xval, %expr) : (i32, i32) -> i32 %newval = "llvm.intr.umax"(%xval, %expr) : (i32, i32) -> i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
llvm.return llvm.return
} }
// ----- // -----
// CHECK-LABEL: @omp_atomic_capture_prefix_update // CHECK-LABEL: @omp_atomic_capture_prefix_update
// CHECK-SAME: (i32* %[[x:.*]], i32* %[[v:.*]], i32 %[[expr:.*]], float* %[[xf:.*]], float* %[[vf:.*]], float %[[exprf:.*]]) // CHECK-SAME: (ptr %[[x:.*]], ptr %[[v:.*]], i32 %[[expr:.*]], ptr %[[xf:.*]], ptr %[[vf:.*]], float %[[exprf:.*]])
llvm.func @omp_atomic_capture_prefix_update( llvm.func @omp_atomic_capture_prefix_update(
%x: !llvm.ptr<i32>, %v: !llvm.ptr<i32>, %expr: i32, %x: !llvm.ptr<i32>, %v: !llvm.ptr<i32>, %expr: i32,
%xf: !llvm.ptr<f32>, %vf: !llvm.ptr<f32>, %exprf: f32) -> () { %xf: !llvm.ptr<f32>, %vf: !llvm.ptr<f32>, %exprf: f32) -> () {
// CHECK: %[[res:.*]] = atomicrmw add i32* %[[x]], i32 %[[expr]] monotonic // CHECK: %[[res:.*]] = atomicrmw add ptr %[[x]], i32 %[[expr]] monotonic
// CHECK-NEXT: %[[newval:.*]] = add i32 %[[res]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = add i32 %[[res]], %[[expr]]
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.add %xval, %expr : i32 %newval = llvm.add %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[res:.*]] = atomicrmw sub i32* %[[x]], i32 %[[expr]] monotonic // CHECK: %[[res:.*]] = atomicrmw sub ptr %[[x]], i32 %[[expr]] monotonic
// CHECK-NEXT: %[[newval:.*]] = sub i32 %[[res]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = sub i32 %[[res]], %[[expr]]
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.sub %xval, %expr : i32 %newval = llvm.sub %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[res:.*]] = atomicrmw and i32* %[[x]], i32 %[[expr]] monotonic // CHECK: %[[res:.*]] = atomicrmw and ptr %[[x]], i32 %[[expr]] monotonic
// CHECK-NEXT: %[[newval:.*]] = and i32 %[[res]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = and i32 %[[res]], %[[expr]]
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.and %xval, %expr : i32 %newval = llvm.and %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[res:.*]] = atomicrmw or i32* %[[x]], i32 %[[expr]] monotonic // CHECK: %[[res:.*]] = atomicrmw or ptr %[[x]], i32 %[[expr]] monotonic
// CHECK-NEXT: %[[newval:.*]] = or i32 %[[res]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = or i32 %[[res]], %[[expr]]
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.or %xval, %expr : i32 %newval = llvm.or %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[res:.*]] = atomicrmw xor i32* %[[x]], i32 %[[expr]] monotonic // CHECK: %[[res:.*]] = atomicrmw xor ptr %[[x]], i32 %[[expr]] monotonic
// CHECK-NEXT: %[[newval:.*]] = xor i32 %[[res]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = xor i32 %[[res]], %[[expr]]
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.xor %xval, %expr : i32 %newval = llvm.xor %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = mul i32 %[[xval]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = mul i32 %[[xval]], %[[expr]]
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.mul %xval, %expr : i32 %newval = llvm.mul %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = sdiv i32 %[[xval]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = sdiv i32 %[[xval]], %[[expr]]
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.sdiv %xval, %expr : i32 %newval = llvm.sdiv %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = udiv i32 %[[xval]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = udiv i32 %[[xval]], %[[expr]]
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.udiv %xval, %expr : i32 %newval = llvm.udiv %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = shl i32 %[[xval]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = shl i32 %[[xval]], %[[expr]]
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.shl %xval, %expr : i32 %newval = llvm.shl %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = lshr i32 %[[xval]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = lshr i32 %[[xval]], %[[expr]]
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.lshr %xval, %expr : i32 %newval = llvm.lshr %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = ashr i32 %[[xval]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = ashr i32 %[[xval]], %[[expr]]
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.ashr %xval, %expr : i32 %newval = llvm.ashr %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.smax.i32(i32 %[[xval]], i32 %[[expr]]) // CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.smax.i32(i32 %[[xval]], i32 %[[expr]])
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = "llvm.intr.smax"(%xval, %expr) : (i32, i32) -> i32 %newval = "llvm.intr.smax"(%xval, %expr) : (i32, i32) -> i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.smin.i32(i32 %[[xval]], i32 %[[expr]]) // CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.smin.i32(i32 %[[xval]], i32 %[[expr]])
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = "llvm.intr.smin"(%xval, %expr) : (i32, i32) -> i32 %newval = "llvm.intr.smin"(%xval, %expr) : (i32, i32) -> i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.umax.i32(i32 %[[xval]], i32 %[[expr]]) // CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.umax.i32(i32 %[[xval]], i32 %[[expr]])
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = "llvm.intr.umax"(%xval, %expr) : (i32, i32) -> i32 %newval = "llvm.intr.umax"(%xval, %expr) : (i32, i32) -> i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.umin.i32(i32 %[[xval]], i32 %[[expr]]) // CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.umin.i32(i32 %[[xval]], i32 %[[expr]])
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[newval]], i32* %[[v]] // CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = "llvm.intr.umin"(%xval, %expr) : (i32, i32) -> i32 %newval = "llvm.intr.umin"(%xval, %expr) : (i32, i32) -> i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK: %[[newval:.*]] = fadd float %{{.*}}, %[[exprf]] // CHECK: %[[newval:.*]] = fadd float %{{.*}}, %[[exprf]]
// CHECK: store float %[[newval]], float* %{{.*}} // CHECK: store float %[[newval]], ptr %{{.*}}
// CHECK: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK: %[[xf_bitcast:.*]] = bitcast float* %[[xf]] to i32* // CHECK: %{{.*}} = cmpxchg ptr %[[xf]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: %{{.*}} = cmpxchg i32* %[[xf_bitcast]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK: store float %[[newval]], ptr %[[vf]]
// CHECK: store float %[[newval]], float* %[[vf]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %xf : !llvm.ptr<f32> { omp.atomic.update %xf : !llvm.ptr<f32> {
^bb0(%xval: f32): ^bb0(%xval: f32):
%newval = llvm.fadd %xval, %exprf : f32 %newval = llvm.fadd %xval, %exprf : f32
omp.yield(%newval : f32) omp.yield(%newval : f32)
} }
omp.atomic.read %vf = %xf : !llvm.ptr<f32> omp.atomic.read %vf = %xf : !llvm.ptr<f32>
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK: %[[newval:.*]] = fsub float %{{.*}}, %[[exprf]] // CHECK: %[[newval:.*]] = fsub float %{{.*}}, %[[exprf]]
// CHECK: store float %[[newval]], float* %{{.*}} // CHECK: store float %[[newval]], ptr %{{.*}}
// CHECK: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK: %[[xf_bitcast:.*]] = bitcast float* %[[xf]] to i32* // CHECK: %{{.*}} = cmpxchg ptr %[[xf]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: %{{.*}} = cmpxchg i32* %[[xf_bitcast]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK: store float %[[newval]], ptr %[[vf]]
// CHECK: store float %[[newval]], float* %[[vf]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.update %xf : !llvm.ptr<f32> { omp.atomic.update %xf : !llvm.ptr<f32> {
^bb0(%xval: f32): ^bb0(%xval: f32):
%newval = llvm.fsub %xval, %exprf : f32 %newval = llvm.fsub %xval, %exprf : f32
omp.yield(%newval : f32) omp.yield(%newval : f32)
} }
omp.atomic.read %vf = %xf : !llvm.ptr<f32> omp.atomic.read %vf = %xf : !llvm.ptr<f32>
} }
llvm.return llvm.return
} }
// ----- // -----
// CHECK-LABEL: @omp_atomic_capture_postfix_update // CHECK-LABEL: @omp_atomic_capture_postfix_update
// CHECK-SAME: (i32* %[[x:.*]], i32* %[[v:.*]], i32 %[[expr:.*]], float* %[[xf:.*]], float* %[[vf:.*]], float %[[exprf:.*]]) // CHECK-SAME: (ptr %[[x:.*]], ptr %[[v:.*]], i32 %[[expr:.*]], ptr %[[xf:.*]], ptr %[[vf:.*]], float %[[exprf:.*]])
llvm.func @omp_atomic_capture_postfix_update( llvm.func @omp_atomic_capture_postfix_update(
%x: !llvm.ptr<i32>, %v: !llvm.ptr<i32>, %expr: i32, %x: !llvm.ptr<i32>, %v: !llvm.ptr<i32>, %expr: i32,
%xf: !llvm.ptr<f32>, %vf: !llvm.ptr<f32>, %exprf: f32) -> () { %xf: !llvm.ptr<f32>, %vf: !llvm.ptr<f32>, %exprf: f32) -> () {
// CHECK: %[[res:.*]] = atomicrmw add i32* %[[x]], i32 %[[expr]] monotonic // CHECK: %[[res:.*]] = atomicrmw add ptr %[[x]], i32 %[[expr]] monotonic
// CHECK: store i32 %[[res]], i32* %[[v]] // CHECK: store i32 %[[res]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.add %xval, %expr : i32 %newval = llvm.add %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[res:.*]] = atomicrmw sub i32* %[[x]], i32 %[[expr]] monotonic // CHECK: %[[res:.*]] = atomicrmw sub ptr %[[x]], i32 %[[expr]] monotonic
// CHECK: store i32 %[[res]], i32* %[[v]] // CHECK: store i32 %[[res]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.sub %xval, %expr : i32 %newval = llvm.sub %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[res:.*]] = atomicrmw and i32* %[[x]], i32 %[[expr]] monotonic // CHECK: %[[res:.*]] = atomicrmw and ptr %[[x]], i32 %[[expr]] monotonic
// CHECK: store i32 %[[res]], i32* %[[v]] // CHECK: store i32 %[[res]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.and %xval, %expr : i32 %newval = llvm.and %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[res:.*]] = atomicrmw or i32* %[[x]], i32 %[[expr]] monotonic // CHECK: %[[res:.*]] = atomicrmw or ptr %[[x]], i32 %[[expr]] monotonic
// CHECK: store i32 %[[res]], i32* %[[v]] // CHECK: store i32 %[[res]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.or %xval, %expr : i32 %newval = llvm.or %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[res:.*]] = atomicrmw xor i32* %[[x]], i32 %[[expr]] monotonic // CHECK: %[[res:.*]] = atomicrmw xor ptr %[[x]], i32 %[[expr]] monotonic
// CHECK: store i32 %[[res]], i32* %[[v]] // CHECK: store i32 %[[res]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.xor %xval, %expr : i32 %newval = llvm.xor %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = mul i32 %[[xval]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = mul i32 %[[xval]], %[[expr]]
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[xval]], i32* %[[v]] // CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.mul %xval, %expr : i32 %newval = llvm.mul %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = sdiv i32 %[[xval]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = sdiv i32 %[[xval]], %[[expr]]
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[xval]], i32* %[[v]] // CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.sdiv %xval, %expr : i32 %newval = llvm.sdiv %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = udiv i32 %[[xval]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = udiv i32 %[[xval]], %[[expr]]
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[xval]], i32* %[[v]] // CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.udiv %xval, %expr : i32 %newval = llvm.udiv %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = shl i32 %[[xval]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = shl i32 %[[xval]], %[[expr]]
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[xval]], i32* %[[v]] // CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.shl %xval, %expr : i32 %newval = llvm.shl %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = lshr i32 %[[xval]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = lshr i32 %[[xval]], %[[expr]]
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[xval]], i32* %[[v]] // CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.lshr %xval, %expr : i32 %newval = llvm.lshr %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = ashr i32 %[[xval]], %[[expr]] // CHECK-NEXT: %[[newval:.*]] = ashr i32 %[[xval]], %[[expr]]
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[xval]], i32* %[[v]] // CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.ashr %xval, %expr : i32 %newval = llvm.ashr %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.smax.i32(i32 %[[xval]], i32 %[[expr]]) // CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.smax.i32(i32 %[[xval]], i32 %[[expr]])
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[xval]], i32* %[[v]] // CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = "llvm.intr.smax"(%xval, %expr) : (i32, i32) -> i32 %newval = "llvm.intr.smax"(%xval, %expr) : (i32, i32) -> i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.smin.i32(i32 %[[xval]], i32 %[[expr]]) // CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.smin.i32(i32 %[[xval]], i32 %[[expr]])
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[xval]], i32* %[[v]] // CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = "llvm.intr.smin"(%xval, %expr) : (i32, i32) -> i32 %newval = "llvm.intr.smin"(%xval, %expr) : (i32, i32) -> i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.umax.i32(i32 %[[xval]], i32 %[[expr]]) // CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.umax.i32(i32 %[[xval]], i32 %[[expr]])
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[xval]], i32* %[[v]] // CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = "llvm.intr.umax"(%xval, %expr) : (i32, i32) -> i32 %newval = "llvm.intr.umax"(%xval, %expr) : (i32, i32) -> i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.umin.i32(i32 %[[xval]], i32 %[[expr]]) // CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.umin.i32(i32 %[[xval]], i32 %[[expr]])
// CHECK-NEXT: store i32 %[[newval]], i32* %{{.*}} // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
// CHECK-NEXT: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK-NEXT: %{{.*}} = cmpxchg i32* %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: store i32 %[[xval]], i32* %[[v]] // CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = "llvm.intr.umin"(%xval, %expr) : (i32, i32) -> i32 %newval = "llvm.intr.umin"(%xval, %expr) : (i32, i32) -> i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK: %[[xvalf:.*]] = bitcast i32 %[[xval]] to float // CHECK: %[[xvalf:.*]] = bitcast i32 %[[xval]] to float
// CHECK: %[[newval:.*]] = fadd float %{{.*}}, %[[exprf]] // CHECK: %[[newval:.*]] = fadd float %{{.*}}, %[[exprf]]
// CHECK: store float %[[newval]], float* %{{.*}} // CHECK: store float %[[newval]], ptr %{{.*}}
// CHECK: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK: %[[xf_bitcast:.*]] = bitcast float* %[[xf]] to i32* // CHECK: %{{.*}} = cmpxchg ptr %[[xf]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: %{{.*}} = cmpxchg i32* %[[xf_bitcast]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK: store float %[[xvalf]], ptr %[[vf]]
// CHECK: store float %[[xvalf]], float* %[[vf]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %vf = %xf : !llvm.ptr<f32> omp.atomic.read %vf = %xf : !llvm.ptr<f32>
omp.atomic.update %xf : !llvm.ptr<f32> { omp.atomic.update %xf : !llvm.ptr<f32> {
^bb0(%xval: f32): ^bb0(%xval: f32):
%newval = llvm.fadd %xval, %exprf : f32 %newval = llvm.fadd %xval, %exprf : f32
omp.yield(%newval : f32) omp.yield(%newval : f32)
} }
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK: %[[xvalf:.*]] = bitcast i32 %[[xval]] to float // CHECK: %[[xvalf:.*]] = bitcast i32 %[[xval]] to float
// CHECK: %[[newval:.*]] = fsub float %{{.*}}, %[[exprf]] // CHECK: %[[newval:.*]] = fsub float %{{.*}}, %[[exprf]]
// CHECK: store float %[[newval]], float* %{{.*}} // CHECK: store float %[[newval]], ptr %{{.*}}
// CHECK: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK: %[[xf_bitcast:.*]] = bitcast float* %[[xf]] to i32* // CHECK: %{{.*}} = cmpxchg ptr %[[xf]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: %{{.*}} = cmpxchg i32* %[[xf_bitcast]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK: store float %[[xvalf]], ptr %[[vf]]
// CHECK: store float %[[xvalf]], float* %[[vf]]
omp.atomic.capture { omp.atomic.capture {
omp.atomic.read %vf = %xf : !llvm.ptr<f32> omp.atomic.read %vf = %xf : !llvm.ptr<f32>
omp.atomic.update %xf : !llvm.ptr<f32> { omp.atomic.update %xf : !llvm.ptr<f32> {
^bb0(%xval: f32): ^bb0(%xval: f32):
%newval = llvm.fsub %xval, %exprf : f32 %newval = llvm.fsub %xval, %exprf : f32
omp.yield(%newval : f32) omp.yield(%newval : f32)
} }
} }
llvm.return llvm.return
} }
// ----- // -----
// CHECK-LABEL: @omp_atomic_capture_misc // CHECK-LABEL: @omp_atomic_capture_misc
// CHECK-SAME: (i32* %[[x:.*]], i32* %[[v:.*]], i32 %[[expr:.*]], float* %[[xf:.*]], float* %[[vf:.*]], float %[[exprf:.*]]) // CHECK-SAME: (ptr %[[x:.*]], ptr %[[v:.*]], i32 %[[expr:.*]], ptr %[[xf:.*]], ptr %[[vf:.*]], float %[[exprf:.*]])
llvm.func @omp_atomic_capture_misc( llvm.func @omp_atomic_capture_misc(
%x: !llvm.ptr<i32>, %v: !llvm.ptr<i32>, %expr: i32, %x: !llvm.ptr<i32>, %v: !llvm.ptr<i32>, %expr: i32,
%xf: !llvm.ptr<f32>, %vf: !llvm.ptr<f32>, %exprf: f32) -> () { %xf: !llvm.ptr<f32>, %vf: !llvm.ptr<f32>, %exprf: f32) -> () {
// CHECK: %[[xval:.*]] = atomicrmw xchg i32* %[[x]], i32 %[[expr]] monotonic // CHECK: %[[xval:.*]] = atomicrmw xchg ptr %[[x]], i32 %[[expr]] monotonic
// CHECK: store i32 %[[xval]], i32* %[[v]] // CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture{ omp.atomic.capture{
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.write %x = %expr : !llvm.ptr<i32>, i32 omp.atomic.write %x = %expr : !llvm.ptr<i32>, i32
} }
// CHECK: %[[xval:.*]] = phi i32 // CHECK: %[[xval:.*]] = phi i32
// CHECK: %[[xvalf:.*]] = bitcast i32 %[[xval]] to float // CHECK: %[[xvalf:.*]] = bitcast i32 %[[xval]] to float
// CHECK: store float %[[exprf]], float* %{{.*}} // CHECK: store float %[[exprf]], ptr %{{.*}}
// CHECK: %[[newval_:.*]] = load i32, i32* %{{.*}} // CHECK: %[[newval_:.*]] = load i32, ptr %{{.*}}
// CHECK: %[[xf_bitcast:.*]] = bitcast float* %[[xf]] to i32* // CHECK: %{{.*}} = cmpxchg ptr %[[xf]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
// CHECK: %{{.*}} = cmpxchg i32* %[[xf_bitcast]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic // CHECK: store float %[[xvalf]], ptr %[[vf]]
// CHECK: store float %[[xvalf]], float* %[[vf]]
omp.atomic.capture{ omp.atomic.capture{
omp.atomic.read %vf = %xf : !llvm.ptr<f32> omp.atomic.read %vf = %xf : !llvm.ptr<f32>
omp.atomic.write %xf = %exprf : !llvm.ptr<f32>, f32 omp.atomic.write %xf = %exprf : !llvm.ptr<f32>, f32
} }
// CHECK: %[[res:.*]] = atomicrmw add i32* %[[x]], i32 %[[expr]] seq_cst // CHECK: %[[res:.*]] = atomicrmw add ptr %[[x]], i32 %[[expr]] seq_cst
// CHECK: store i32 %[[res]], i32* %[[v]] // CHECK: store i32 %[[res]], ptr %[[v]]
omp.atomic.capture memory_order(seq_cst) { omp.atomic.capture memory_order(seq_cst) {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.add %xval, %expr : i32 %newval = llvm.add %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[res:.*]] = atomicrmw add i32* %[[x]], i32 %[[expr]] acquire // CHECK: %[[res:.*]] = atomicrmw add ptr %[[x]], i32 %[[expr]] acquire
// CHECK: store i32 %[[res]], i32* %[[v]] // CHECK: store i32 %[[res]], ptr %[[v]]
omp.atomic.capture memory_order(acquire) { omp.atomic.capture memory_order(acquire) {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.add %xval, %expr : i32 %newval = llvm.add %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[res:.*]] = atomicrmw add i32* %[[x]], i32 %[[expr]] release // CHECK: %[[res:.*]] = atomicrmw add ptr %[[x]], i32 %[[expr]] release
// CHECK: store i32 %[[res]], i32* %[[v]] // CHECK: store i32 %[[res]], ptr %[[v]]
omp.atomic.capture memory_order(release) { omp.atomic.capture memory_order(release) {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.add %xval, %expr : i32 %newval = llvm.add %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[res:.*]] = atomicrmw add i32* %[[x]], i32 %[[expr]] monotonic // CHECK: %[[res:.*]] = atomicrmw add ptr %[[x]], i32 %[[expr]] monotonic
// CHECK: store i32 %[[res]], i32* %[[v]] // CHECK: store i32 %[[res]], ptr %[[v]]
omp.atomic.capture memory_order(relaxed) { omp.atomic.capture memory_order(relaxed) {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.add %xval, %expr : i32 %newval = llvm.add %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
// CHECK: %[[res:.*]] = atomicrmw add i32* %[[x]], i32 %[[expr]] acq_rel // CHECK: %[[res:.*]] = atomicrmw add ptr %[[x]], i32 %[[expr]] acq_rel
// CHECK: store i32 %[[res]], i32* %[[v]] // CHECK: store i32 %[[res]], ptr %[[v]]
omp.atomic.capture memory_order(acq_rel) { omp.atomic.capture memory_order(acq_rel) {
omp.atomic.read %v = %x : !llvm.ptr<i32> omp.atomic.read %v = %x : !llvm.ptr<i32>
omp.atomic.update %x : !llvm.ptr<i32> { omp.atomic.update %x : !llvm.ptr<i32> {
^bb0(%xval: i32): ^bb0(%xval: i32):
%newval = llvm.add %xval, %expr : i32 %newval = llvm.add %xval, %expr : i32
omp.yield(%newval : i32) omp.yield(%newval : i32)
} }
} }
▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines omp.section {
omp.terminator omp.terminator
} }
omp.section { omp.section {
// CHECK: [[SECTION3]]: // CHECK: [[SECTION3]]:
// CHECK: br label %[[REGION3:[^ ,]*]] // CHECK: br label %[[REGION3:[^ ,]*]]
// CHECK: [[REGION3]]: // CHECK: [[REGION3]]:
// CHECK: %11 = add i32 %{{.*}}, %{{.*}} // CHECK: %11 = add i32 %{{.*}}, %{{.*}}
%add = llvm.add %arg0, %arg1 : i32 %add = llvm.add %arg0, %arg1 : i32
// CHECK: store i32 %{{.*}}, i32* %{{.*}}, align 4 // CHECK: store i32 %{{.*}}, ptr %{{.*}}, align 4
// CHECK: br label %{{.*}} // CHECK: br label %{{.*}}
llvm.store %add, %arg2 : !llvm.ptr<i32> llvm.store %add, %arg2 : !llvm.ptr<i32>
omp.terminator omp.terminator
} }
omp.terminator omp.terminator
} }
llvm.return llvm.return
} }
Show All 33 Lines ^bb1(%0: i64): // 2 preds: ^bb0, ^bb0
omp.yield omp.yield
} }
llvm.return llvm.return
} }
// ----- // -----
// CHECK-LABEL: @single // CHECK-LABEL: @single
// CHECK-SAME: (i32 %[[x:.*]], i32 %[[y:.*]], i32* %[[zaddr:.*]]) // CHECK-SAME: (i32 %[[x:.*]], i32 %[[y:.*]], ptr %[[zaddr:.*]])
llvm.func @single(%x: i32, %y: i32, %zaddr: !llvm.ptr<i32>) { llvm.func @single(%x: i32, %y: i32, %zaddr: !llvm.ptr<i32>) {
// CHECK: %[[a:.*]] = sub i32 %[[x]], %[[y]] // CHECK: %[[a:.*]] = sub i32 %[[x]], %[[y]]
%a = llvm.sub %x, %y : i32 %a = llvm.sub %x, %y : i32
// CHECK: store i32 %[[a]], i32* %[[zaddr]] // CHECK: store i32 %[[a]], ptr %[[zaddr]]
llvm.store %a, %zaddr : !llvm.ptr<i32> llvm.store %a, %zaddr : !llvm.ptr<i32>
// CHECK: call i32 @__kmpc_single // CHECK: call i32 @__kmpc_single
omp.single { omp.single {
// CHECK: %[[z:.*]] = add i32 %[[x]], %[[y]] // CHECK: %[[z:.*]] = add i32 %[[x]], %[[y]]
%z = llvm.add %x, %y : i32 %z = llvm.add %x, %y : i32
// CHECK: store i32 %[[z]], i32* %[[zaddr]] // CHECK: store i32 %[[z]], ptr %[[zaddr]]
llvm.store %z, %zaddr : !llvm.ptr<i32> llvm.store %z, %zaddr : !llvm.ptr<i32>
// CHECK: call void @__kmpc_end_single // CHECK: call void @__kmpc_end_single
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
omp.terminator omp.terminator
} }
// CHECK: %[[b:.*]] = mul i32 %[[x]], %[[y]] // CHECK: %[[b:.*]] = mul i32 %[[x]], %[[y]]
%b = llvm.mul %x, %y : i32 %b = llvm.mul %x, %y : i32
// CHECK: store i32 %[[b]], i32* %[[zaddr]] // CHECK: store i32 %[[b]], ptr %[[zaddr]]
llvm.store %b, %zaddr : !llvm.ptr<i32> llvm.store %b, %zaddr : !llvm.ptr<i32>
// CHECK: ret void // CHECK: ret void
llvm.return llvm.return
} }
// ----- // -----
// CHECK-LABEL: @single_nowait // CHECK-LABEL: @single_nowait
// CHECK-SAME: (i32 %[[x:.*]], i32 %[[y:.*]], i32* %[[zaddr:.*]]) // CHECK-SAME: (i32 %[[x:.*]], i32 %[[y:.*]], ptr %[[zaddr:.*]])
llvm.func @single_nowait(%x: i32, %y: i32, %zaddr: !llvm.ptr<i32>) { llvm.func @single_nowait(%x: i32, %y: i32, %zaddr: !llvm.ptr<i32>) {
// CHECK: %[[a:.*]] = sub i32 %[[x]], %[[y]] // CHECK: %[[a:.*]] = sub i32 %[[x]], %[[y]]
%a = llvm.sub %x, %y : i32 %a = llvm.sub %x, %y : i32
// CHECK: store i32 %[[a]], i32* %[[zaddr]] // CHECK: store i32 %[[a]], ptr %[[zaddr]]
llvm.store %a, %zaddr : !llvm.ptr<i32> llvm.store %a, %zaddr : !llvm.ptr<i32>
// CHECK: call i32 @__kmpc_single // CHECK: call i32 @__kmpc_single
omp.single nowait { omp.single nowait {
// CHECK: %[[z:.*]] = add i32 %[[x]], %[[y]] // CHECK: %[[z:.*]] = add i32 %[[x]], %[[y]]
%z = llvm.add %x, %y : i32 %z = llvm.add %x, %y : i32
// CHECK: store i32 %[[z]], i32* %[[zaddr]] // CHECK: store i32 %[[z]], ptr %[[zaddr]]
llvm.store %z, %zaddr : !llvm.ptr<i32> llvm.store %z, %zaddr : !llvm.ptr<i32>
// CHECK: call void @__kmpc_end_single // CHECK: call void @__kmpc_end_single
// CHECK-NOT: call void @__kmpc_barrier // CHECK-NOT: call void @__kmpc_barrier
omp.terminator omp.terminator
} }
// CHECK: %[[t:.*]] = mul i32 %[[x]], %[[y]] // CHECK: %[[t:.*]] = mul i32 %[[x]], %[[y]]
%t = llvm.mul %x, %y : i32 %t = llvm.mul %x, %y : i32
// CHECK: store i32 %[[t]], i32* %[[zaddr]] // CHECK: store i32 %[[t]], ptr %[[zaddr]]
llvm.store %t, %zaddr : !llvm.ptr<i32> llvm.store %t, %zaddr : !llvm.ptr<i32>
// CHECK: ret void // CHECK: ret void
llvm.return llvm.return
} }
// ----- // -----
// CHECK: @_QFsubEx = internal global i32 undef // CHECK: @_QFsubEx = internal global i32 undef
// CHECK: @_QFsubEx.cache = common global i8** null // CHECK: @_QFsubEx.cache = common global ptr null
// CHECK-LABEL: @omp_threadprivate // CHECK-LABEL: @omp_threadprivate
llvm.func @omp_threadprivate() { llvm.func @omp_threadprivate() {
// CHECK: [[THREAD:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB:[0-9]+]]) // CHECK: [[THREAD:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB:[0-9]+]])
// CHECK: [[TMP1:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB]], i32 [[THREAD]], i8* bitcast (i32* @_QFsubEx to i8*), i64 4, i8*** @_QFsubEx.cache) // CHECK: [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB]], i32 [[THREAD]], ptr @_QFsubEx, i64 4, ptr @_QFsubEx.cache)
// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* // CHECK: store i32 1, ptr [[TMP1]], align 4
// CHECK: store i32 1, i32* [[TMP2]], align 4 // CHECK: store i32 3, ptr [[TMP1]], align 4
// CHECK: store i32 3, i32* [[TMP2]], align 4
// CHECK-LABEL: omp.par.region{{.*}} // CHECK-LABEL: omp.par.region{{.*}}
// CHECK: [[THREAD2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK: [[THREAD2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK: [[TMP3:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB2]], i32 [[THREAD2]], i8* bitcast (i32* @_QFsubEx to i8*), i64 4, i8*** @_QFsubEx.cache) // CHECK: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB2]], i32 [[THREAD2]], ptr @_QFsubEx, i64 4, ptr @_QFsubEx.cache)
// CHECK: [[TMP4:%.*]] = bitcast i8* [[TMP3]] to i32* // CHECK: store i32 2, ptr [[TMP3]], align 4
// CHECK: store i32 2, i32* [[TMP4]], align 4
%0 = llvm.mlir.constant(1 : i32) : i32 %0 = llvm.mlir.constant(1 : i32) : i32
%1 = llvm.mlir.constant(2 : i32) : i32 %1 = llvm.mlir.constant(2 : i32) : i32
%2 = llvm.mlir.constant(3 : i32) : i32 %2 = llvm.mlir.constant(3 : i32) : i32
%3 = llvm.mlir.addressof @_QFsubEx : !llvm.ptr<i32> %3 = llvm.mlir.addressof @_QFsubEx : !llvm.ptr<i32>
%4 = omp.threadprivate %3 : !llvm.ptr<i32> -> !llvm.ptr<i32> %4 = omp.threadprivate %3 : !llvm.ptr<i32> -> !llvm.ptr<i32>
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mlir/test/Target/LLVMIR/openmp-nested.mlir

Show All 28 Lines omp.parallel {
omp.terminator omp.terminator
} }
%a4 = llvm.mlir.constant(0 : i32) : i32 %a4 = llvm.mlir.constant(0 : i32) : i32
llvm.return %a4 : i32 llvm.return %a4 : i32
} }
} }
// CHECK: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @1, i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @[[inner1:.+]] to void (i32*, i32*, ...)*)) // CHECK: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @1, i32 0, ptr @[[inner1:.+]])
// CHECK: define internal void @[[inner1]] // CHECK: define internal void @[[inner1]]
// CHECK: %[[structArg:.+]] = alloca { i64* } // CHECK: %[[structArg:.+]] = alloca { ptr }
// CHECK: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @3, i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, { i64* }*)* @[[inner2:.+]] to void (i32*, i32*, ...)*), { i64* }* %[[structArg]]) // CHECK: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @3, i32 1, ptr @[[inner2:.+]], ptr %[[structArg]])

mlir/test/Target/LLVMIR/openmp-reduction.mlir

Show All 40 Lines
// CHECK: call void {{.*}} @__kmpc_fork_call // CHECK: call void {{.*}} @__kmpc_fork_call
// CHECK-SAME: @[[OUTLINED:[A-Za-z_.][A-Za-z0-9_.]*]] // CHECK-SAME: @[[OUTLINED:[A-Za-z_.][A-Za-z0-9_.]*]]
// Outlined function. // Outlined function.
// CHECK: define internal void @[[OUTLINED]] // CHECK: define internal void @[[OUTLINED]]
// Private reduction variable and its initialization. // Private reduction variable and its initialization.
// CHECK: %[[PRIVATE:.+]] = alloca float // CHECK: %[[PRIVATE:.+]] = alloca float
// CHECK: store float 0.000000e+00, float* %[[PRIVATE]] // CHECK: store float 0.000000e+00, ptr %[[PRIVATE]]
// Call to the reduction function. // Call to the reduction function.
// CHECK: call i32 @__kmpc_reduce // CHECK: call i32 @__kmpc_reduce
// CHECK-SAME: @[[REDFUNC:[A-Za-z_.][A-Za-z0-9_.]*]] // CHECK-SAME: @[[REDFUNC:[A-Za-z_.][A-Za-z0-9_.]*]]
// Atomic reduction. // Atomic reduction.
// CHECK: %[[PARTIAL:.+]] = load float, float* %[[PRIVATE]] // CHECK: %[[PARTIAL:.+]] = load float, ptr %[[PRIVATE]]
// CHECK: atomicrmw fadd float* %{{.*}}, float %[[PARTIAL]] // CHECK: atomicrmw fadd ptr %{{.*}}, float %[[PARTIAL]]
// Non-atomic reduction: // Non-atomic reduction:
// CHECK: fadd float // CHECK: fadd float
// CHECK: call void @__kmpc_end_reduce // CHECK: call void @__kmpc_end_reduce
// CHECK: br label %[[FINALIZE:.+]] // CHECK: br label %[[FINALIZE:.+]]
// CHECK: [[FINALIZE]]: // CHECK: [[FINALIZE]]:
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
// Update of the private variable using the reduction region // Update of the private variable using the reduction region
// (the body block currently comes after all the other blocks). // (the body block currently comes after all the other blocks).
// CHECK: %[[PARTIAL:.+]] = load float, float* %[[PRIVATE]] // CHECK: %[[PARTIAL:.+]] = load float, ptr %[[PRIVATE]]
// CHECK: %[[UPDATED:.+]] = fadd float %[[PARTIAL]], 2.000000e+00 // CHECK: %[[UPDATED:.+]] = fadd float %[[PARTIAL]], 2.000000e+00
// CHECK: store float %[[UPDATED]], float* %[[PRIVATE]] // CHECK: store float %[[UPDATED]], ptr %[[PRIVATE]]
// Reduction function. // Reduction function.
// CHECK: define internal void @[[REDFUNC]] // CHECK: define internal void @[[REDFUNC]]
// CHECK: fadd float // CHECK: fadd float
// ----- // -----
omp.reduction.declare @add_f32 : f32 omp.reduction.declare @add_f32 : f32
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// CHECK-SAME: @[[OUTLINED:[A-Za-z_.][A-Za-z0-9_.]*]] // CHECK-SAME: @[[OUTLINED:[A-Za-z_.][A-Za-z0-9_.]*]]
// Outlined function. // Outlined function.
// CHECK: define internal void @[[OUTLINED]] // CHECK: define internal void @[[OUTLINED]]
// Private reduction variable and its initialization. // Private reduction variable and its initialization.
// CHECK: %[[PRIVATE1:.+]] = alloca float // CHECK: %[[PRIVATE1:.+]] = alloca float
// CHECK: %[[PRIVATE2:.+]] = alloca float // CHECK: %[[PRIVATE2:.+]] = alloca float
// CHECK: store float 0.000000e+00, float* %[[PRIVATE1]] // CHECK: store float 0.000000e+00, ptr %[[PRIVATE1]]
// CHECK: store float 0.000000e+00, float* %[[PRIVATE2]] // CHECK: store float 0.000000e+00, ptr %[[PRIVATE2]]
// Call to the reduction function. // Call to the reduction function.
// CHECK: call i32 @__kmpc_reduce // CHECK: call i32 @__kmpc_reduce
// CHECK-SAME: @[[REDFUNC:[A-Za-z_.][A-Za-z0-9_.]*]] // CHECK-SAME: @[[REDFUNC:[A-Za-z_.][A-Za-z0-9_.]*]]
// Atomic reduction. // Atomic reduction.
// CHECK: %[[PARTIAL1:.+]] = load float, float* %[[PRIVATE1]] // CHECK: %[[PARTIAL1:.+]] = load float, ptr %[[PRIVATE1]]
// CHECK: atomicrmw fadd float* %{{.*}}, float %[[PARTIAL1]] // CHECK: atomicrmw fadd ptr %{{.*}}, float %[[PARTIAL1]]
// CHECK: %[[PARTIAL2:.+]] = load float, float* %[[PRIVATE2]] // CHECK: %[[PARTIAL2:.+]] = load float, ptr %[[PRIVATE2]]
// CHECK: atomicrmw fadd float* %{{.*}}, float %[[PARTIAL2]] // CHECK: atomicrmw fadd ptr %{{.*}}, float %[[PARTIAL2]]
// Non-atomic reduction: // Non-atomic reduction:
// CHECK: fadd float // CHECK: fadd float
// CHECK: fadd float // CHECK: fadd float
// CHECK: call void @__kmpc_end_reduce // CHECK: call void @__kmpc_end_reduce
// CHECK: br label %[[FINALIZE:.+]] // CHECK: br label %[[FINALIZE:.+]]
// CHECK: [[FINALIZE]]: // CHECK: [[FINALIZE]]:
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
// Update of the private variable using the reduction region // Update of the private variable using the reduction region
// (the body block currently comes after all the other blocks). // (the body block currently comes after all the other blocks).
// CHECK: %[[PARTIAL1:.+]] = load float, float* %[[PRIVATE1]] // CHECK: %[[PARTIAL1:.+]] = load float, ptr %[[PRIVATE1]]
// CHECK: %[[UPDATED1:.+]] = fadd float %[[PARTIAL1]], 2.000000e+00 // CHECK: %[[UPDATED1:.+]] = fadd float %[[PARTIAL1]], 2.000000e+00
// CHECK: store float %[[UPDATED1]], float* %[[PRIVATE1]] // CHECK: store float %[[UPDATED1]], ptr %[[PRIVATE1]]
// CHECK: %[[PARTIAL2:.+]] = load float, float* %[[PRIVATE2]] // CHECK: %[[PARTIAL2:.+]] = load float, ptr %[[PRIVATE2]]
// CHECK: %[[UPDATED2:.+]] = fadd float %[[PARTIAL2]], 2.000000e+00 // CHECK: %[[UPDATED2:.+]] = fadd float %[[PARTIAL2]], 2.000000e+00
// CHECK: store float %[[UPDATED2]], float* %[[PRIVATE2]] // CHECK: store float %[[UPDATED2]], ptr %[[PRIVATE2]]
// Reduction function. // Reduction function.
// CHECK: define internal void @[[REDFUNC]] // CHECK: define internal void @[[REDFUNC]]
// CHECK: fadd float // CHECK: fadd float
// CHECK: fadd float // CHECK: fadd float
// ----- // -----
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// CHECK-SAME: @[[OUTLINED:[A-Za-z_.][A-Za-z0-9_.]*]] // CHECK-SAME: @[[OUTLINED:[A-Za-z_.][A-Za-z0-9_.]*]]
// Outlined function. // Outlined function.
// CHECK: define internal void @[[OUTLINED]] // CHECK: define internal void @[[OUTLINED]]
// Private reduction variable and its initialization. // Private reduction variable and its initialization.
// CHECK: %[[PRIVATE1:.+]] = alloca float // CHECK: %[[PRIVATE1:.+]] = alloca float
// CHECK: %[[PRIVATE2:.+]] = alloca float // CHECK: %[[PRIVATE2:.+]] = alloca float
// CHECK: store float 0.000000e+00, float* %[[PRIVATE1]] // CHECK: store float 0.000000e+00, ptr %[[PRIVATE1]]
// CHECK: store float 0.000000e+00, float* %[[PRIVATE2]] // CHECK: store float 0.000000e+00, ptr %[[PRIVATE2]]
// Call to the reduction function. // Call to the reduction function.
// CHECK: call i32 @__kmpc_reduce // CHECK: call i32 @__kmpc_reduce
// CHECK-SAME: @[[REDFUNC:[A-Za-z_.][A-Za-z0-9_.]*]] // CHECK-SAME: @[[REDFUNC:[A-Za-z_.][A-Za-z0-9_.]*]]
// Atomic reduction. // Atomic reduction.
// CHECK: %[[PARTIAL1:.+]] = load float, float* %[[PRIVATE1]] // CHECK: %[[PARTIAL1:.+]] = load float, ptr %[[PRIVATE1]]
// CHECK: atomicrmw fadd float* %{{.*}}, float %[[PARTIAL1]] // CHECK: atomicrmw fadd ptr %{{.*}}, float %[[PARTIAL1]]
// CHECK: %[[PARTIAL2:.+]] = load float, float* %[[PRIVATE2]] // CHECK: %[[PARTIAL2:.+]] = load float, ptr %[[PRIVATE2]]
// CHECK: atomicrmw fadd float* %{{.*}}, float %[[PARTIAL2]] // CHECK: atomicrmw fadd ptr %{{.*}}, float %[[PARTIAL2]]
// Non-atomic reduction: // Non-atomic reduction:
// CHECK: fadd float // CHECK: fadd float
// CHECK: fadd float // CHECK: fadd float
// CHECK: call void @__kmpc_end_reduce // CHECK: call void @__kmpc_end_reduce
// CHECK: br label %[[FINALIZE:.+]] // CHECK: br label %[[FINALIZE:.+]]
// CHECK: [[FINALIZE]]: // CHECK: [[FINALIZE]]:
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
// Update of the private variable using the reduction region // Update of the private variable using the reduction region
// (the body block currently comes after all the other blocks). // (the body block currently comes after all the other blocks).
// CHECK: %[[PARTIAL1:.+]] = load float, float* %[[PRIVATE1]] // CHECK: %[[PARTIAL1:.+]] = load float, ptr %[[PRIVATE1]]
// CHECK: %[[UPDATED1:.+]] = fadd float %[[PARTIAL1]], 2.000000e+00 // CHECK: %[[UPDATED1:.+]] = fadd float %[[PARTIAL1]], 2.000000e+00
// CHECK: store float %[[UPDATED1]], float* %[[PRIVATE1]] // CHECK: store float %[[UPDATED1]], ptr %[[PRIVATE1]]
// CHECK-NOT: %{{.*}} = load float, float* %[[PRIVATE2]] // CHECK-NOT: %{{.*}} = load float, ptr %[[PRIVATE2]]
// CHECK-NOT: %{{.*}} = fadd float %[[PARTIAL2]], 2.000000e+00 // CHECK-NOT: %{{.*}} = fadd float %[[PARTIAL2]], 2.000000e+00
// Reduction function. // Reduction function.
// CHECK: define internal void @[[REDFUNC]] // CHECK: define internal void @[[REDFUNC]]
// CHECK: fadd float // CHECK: fadd float
// CHECK: fadd float // CHECK: fadd float
// ----- // -----
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// CHECK: call void {{.*}} @__kmpc_fork_call // CHECK: call void {{.*}} @__kmpc_fork_call
// CHECK-SAME: @[[OUTLINED:[A-Za-z_.][A-Za-z0-9_.]*]] // CHECK-SAME: @[[OUTLINED:[A-Za-z_.][A-Za-z0-9_.]*]]
// Outlined function. // Outlined function.
// CHECK: define internal void @[[OUTLINED]] // CHECK: define internal void @[[OUTLINED]]
// Private reduction variable and its initialization. // Private reduction variable and its initialization.
// CHECK: %[[PRIVATE:.+]] = alloca float // CHECK: %[[PRIVATE:.+]] = alloca float
// CHECK: store float 0.000000e+00, float* %[[PRIVATE]] // CHECK: store float 0.000000e+00, ptr %[[PRIVATE]]
// Call to the reduction function. // Call to the reduction function.
// CHECK: call i32 @__kmpc_reduce // CHECK: call i32 @__kmpc_reduce
// CHECK-SAME: @[[REDFUNC:[A-Za-z_.][A-Za-z0-9_.]*]] // CHECK-SAME: @[[REDFUNC:[A-Za-z_.][A-Za-z0-9_.]*]]
// Atomic reduction. // Atomic reduction.
// CHECK: %[[PARTIAL:.+]] = load float, float* %[[PRIVATE]] // CHECK: %[[PARTIAL:.+]] = load float, ptr %[[PRIVATE]]
// CHECK: atomicrmw fadd float* %{{.*}}, float %[[PARTIAL]] // CHECK: atomicrmw fadd ptr %{{.*}}, float %[[PARTIAL]]
// Non-atomic reduction: // Non-atomic reduction:
// CHECK: fadd float // CHECK: fadd float
// CHECK: call void @__kmpc_end_reduce // CHECK: call void @__kmpc_end_reduce
// CHECK: br label %[[FINALIZE:.+]] // CHECK: br label %[[FINALIZE:.+]]
// CHECK: [[FINALIZE]]: // CHECK: [[FINALIZE]]:
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
// Update of the private variable using the reduction region // Update of the private variable using the reduction region
// (the body block currently comes after all the other blocks). // (the body block currently comes after all the other blocks).
// CHECK: %[[PARTIAL:.+]] = load float, float* %[[PRIVATE]] // CHECK: %[[PARTIAL:.+]] = load float, ptr %[[PRIVATE]]
// CHECK: %[[UPDATED:.+]] = fadd float %[[PARTIAL]], 2.000000e+00 // CHECK: %[[UPDATED:.+]] = fadd float %[[PARTIAL]], 2.000000e+00
// CHECK: store float %[[UPDATED]], float* %[[PRIVATE]] // CHECK: store float %[[UPDATED]], ptr %[[PRIVATE]]
// CHECK: %[[PARTIAL:.+]] = load float, float* %[[PRIVATE]] // CHECK: %[[PARTIAL:.+]] = load float, ptr %[[PRIVATE]]
// CHECK: %[[UPDATED:.+]] = fadd float %[[PARTIAL]], 2.000000e+00 // CHECK: %[[UPDATED:.+]] = fadd float %[[PARTIAL]], 2.000000e+00
// CHECK: store float %[[UPDATED]], float* %[[PRIVATE]] // CHECK: store float %[[UPDATED]], ptr %[[PRIVATE]]
// Reduction function. // Reduction function.
// CHECK: define internal void @[[REDFUNC]] // CHECK: define internal void @[[REDFUNC]]
// CHECK: fadd float // CHECK: fadd float
// ----- // -----
omp.reduction.declare @add_f32 : f32 omp.reduction.declare @add_f32 : f32
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// CHECK-SAME: @[[OUTLINED:[A-Za-z_.][A-Za-z0-9_.]*]] // CHECK-SAME: @[[OUTLINED:[A-Za-z_.][A-Za-z0-9_.]*]]
// Outlined function. // Outlined function.
// CHECK: define internal void @[[OUTLINED]] // CHECK: define internal void @[[OUTLINED]]
// Private reduction variable and its initialization. // Private reduction variable and its initialization.
// CHECK: %[[PRIVATE1:.+]] = alloca float // CHECK: %[[PRIVATE1:.+]] = alloca float
// CHECK: %[[PRIVATE2:.+]] = alloca float // CHECK: %[[PRIVATE2:.+]] = alloca float
// CHECK: store float 0.000000e+00, float* %[[PRIVATE1]] // CHECK: store float 0.000000e+00, ptr %[[PRIVATE1]]
// CHECK: store float 1.000000e+00, float* %[[PRIVATE2]] // CHECK: store float 1.000000e+00, ptr %[[PRIVATE2]]
// Call to the reduction function. // Call to the reduction function.
// CHECK: call i32 @__kmpc_reduce // CHECK: call i32 @__kmpc_reduce
// CHECK-SAME: @[[REDFUNC:[A-Za-z_.][A-Za-z0-9_.]*]] // CHECK-SAME: @[[REDFUNC:[A-Za-z_.][A-Za-z0-9_.]*]]
// Atomic reduction not provided. // Atomic reduction not provided.
// CHECK: unreachable // CHECK: unreachable
// Non-atomic reduction: // Non-atomic reduction:
// CHECK: fadd float // CHECK: fadd float
// CHECK: fmul float // CHECK: fmul float
// CHECK: call void @__kmpc_end_reduce // CHECK: call void @__kmpc_end_reduce
// CHECK: br label %[[FINALIZE:.+]] // CHECK: br label %[[FINALIZE:.+]]
// CHECK: [[FINALIZE]]: // CHECK: [[FINALIZE]]:
// CHECK: call void @__kmpc_barrier // CHECK: call void @__kmpc_barrier
// Update of the private variable using the reduction region // Update of the private variable using the reduction region
// (the body block currently comes after all the other blocks). // (the body block currently comes after all the other blocks).
// CHECK: %[[PARTIAL1:.+]] = load float, float* %[[PRIVATE1]] // CHECK: %[[PARTIAL1:.+]] = load float, ptr %[[PRIVATE1]]
// CHECK: %[[UPDATED1:.+]] = fadd float %[[PARTIAL1]], 2.000000e+00 // CHECK: %[[UPDATED1:.+]] = fadd float %[[PARTIAL1]], 2.000000e+00
// CHECK: store float %[[UPDATED1]], float* %[[PRIVATE1]] // CHECK: store float %[[UPDATED1]], ptr %[[PRIVATE1]]
// CHECK: %[[PARTIAL2:.+]] = load float, float* %[[PRIVATE2]] // CHECK: %[[PARTIAL2:.+]] = load float, ptr %[[PRIVATE2]]
// CHECK: %[[UPDATED2:.+]] = fmul float %[[PARTIAL2]], 2.000000e+00 // CHECK: %[[UPDATED2:.+]] = fmul float %[[PARTIAL2]], 2.000000e+00
// CHECK: store float %[[UPDATED2]], float* %[[PRIVATE2]] // CHECK: store float %[[UPDATED2]], ptr %[[PRIVATE2]]
// Reduction function. // Reduction function.
// CHECK: define internal void @[[REDFUNC]] // CHECK: define internal void @[[REDFUNC]]
// CHECK: fadd float // CHECK: fadd float
// CHECK: fmul float // CHECK: fmul float

polly/test/CodeGen/non-affine-exit-node-dominance.ll

; RUN: opt %loadPolly -polly-codegen -S < %s | FileCheck %s ; RUN: opt %loadPolly -polly-codegen -S < %s | FileCheck %s
; ;
; llvm.org/PR25439 ; llvm.org/PR25439
; The dominance of the generated non-affine subregion block was based on the ; The dominance of the generated non-affine subregion block was based on the
; scop's merge block, therefore resulted in an invalid DominanceTree. ; scop's merge block, therefore resulted in an invalid DominanceTree.
; It resulted in some values as assumed to be unusable in the actual generated ; It resulted in some values as assumed to be unusable in the actual generated
; exit block. Here we check whether the value %escaping is taken from the ; exit block. Here we check whether the value %escaping is taken from the
; generated block. ; generated block.
; ;
; CHECK-LABEL: polly.stmt.subregion_entry: ; CHECK-LABEL: polly.stmt.subregion_entry:
; CHECK: %p_escaping = select i1 undef, i32 undef, i32 undef ; CHECK: %p_escaping = select i1 undef, i32 undef, i32 undef
; ;
; CHECK-LABEL: polly.stmt.polly.merge_new_and_old.exit: ; CHECK-LABEL: polly.stmt.polly.merge_new_and_old.exit:
; CHECK: store i32 %p_escaping, i32* %escaping.s2a ; CHECK: store i32 %p_escaping, ptr %escaping.s2a
define i32 @func() { define i32 @func() {
entry: entry:
br label %subregion_entry br label %subregion_entry
subregion_entry: subregion_entry:
%escaping = select i1 undef, i32 undef, i32 undef %escaping = select i1 undef, i32 undef, i32 undef
%cond = or i1 undef, undef %cond = or i1 undef, undef
br i1 %cond, label %subregion_exit, label %subregion_if br i1 %cond, label %subregion_exit, label %subregion_if
subregion_if: subregion_if:
br label %subregion_exit br label %subregion_exit
subregion_exit: subregion_exit:
ret i32 %escaping ret i32 %escaping
} }

polly/test/CodeGen/non-affine-region-implicit-store.ll

; RUN: opt %loadPolly -polly-codegen -S < %s | FileCheck %s ; RUN: opt %loadPolly -polly-codegen -S < %s | FileCheck %s
; ;
; llvm.org/PR25438 ; llvm.org/PR25438
; After loop versioning, a dominance check of a non-affine subregion's exit node ; After loop versioning, a dominance check of a non-affine subregion's exit node
; causes the dominance check to always fail any block in the scop. The ; causes the dominance check to always fail any block in the scop. The
; subregion's exit block has become polly_merge_new_and_old, which also receives ; subregion's exit block has become polly_merge_new_and_old, which also receives
; the control flow of the generated code. This would cause that any value for ; the control flow of the generated code. This would cause that any value for
; implicit stores is assumed to be not from the scop. ; implicit stores is assumed to be not from the scop.
; ;
; This checks that the stored value is indeed from the generated code. ; This checks that the stored value is indeed from the generated code.
; ;
; CHECK-LABEL: polly.stmt.do.body.entry: ; CHECK-LABEL: polly.stmt.do.body.entry:
; CHECK: a.phiops.reload = load i32, i32* %a.phiops ; CHECK: a.phiops.reload = load i32, ptr %a.phiops
; ;
; CHECK-LABEL: polly.stmt.polly.merge_new_and_old.exit: ; CHECK-LABEL: polly.stmt.polly.merge_new_and_old.exit:
; CHECK: store i32 %polly.a, i32* %a.s2a ; CHECK: store i32 %polly.a, ptr %a.s2a
define void @func() { define void @func() {
entry: entry:
br label %while.body br label %while.body
while.body: while.body:
br label %do.body br label %do.body
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polly/test/CodeGen/out-of-scop-phi-node-use.ll

; RUN: opt %loadPolly -polly-codegen -S < %s | FileCheck %s ; RUN: opt %loadPolly -polly-codegen -S < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; CHECK-LABEL: polly.merge_new_and_old: ; CHECK-LABEL: polly.merge_new_and_old:
; CHECK-NEXT: %_s.sroa.343.0.ph5161118.ph.merge = phi i32 [ %_s.sroa.343.0.ph5161118.ph.final_reload, %polly.exiting ], [ %_s.sroa.343.0.ph516.lcssa2357, %for.cond.981.region_exiting ] ; CHECK-NEXT: %_s.sroa.343.0.ph5161118.ph.merge = phi i32 [ %_s.sroa.343.0.ph5161118.ph.final_reload, %polly.exiting ], [ %_s.sroa.343.0.ph516.lcssa2357, %for.cond.981.region_exiting ]
; CHECK-LABEL: for.cond.981: ; CHECK-LABEL: for.cond.981:
; CHECK-NEXT: %_s.sroa.343.0.ph5161118 = phi i32 [ undef, %for.cond ], [ %_s.sroa.343.0.ph5161118.ph.merge, %polly.merge_new_and_old ] ; CHECK-NEXT: %_s.sroa.343.0.ph5161118 = phi i32 [ undef, %for.cond ], [ %_s.sroa.343.0.ph5161118.ph.merge, %polly.merge_new_and_old ]
; CHECK-LABEL: polly.exiting: ; CHECK-LABEL: polly.exiting:
; CHECK-NEXT: %_s.sroa.343.0.ph5161118.ph.final_reload = load i32, i32* %_s.sroa.343.0.ph5161118.s2a ; CHECK-NEXT: %_s.sroa.343.0.ph5161118.ph.final_reload = load i32, ptr %_s.sroa.343.0.ph5161118.s2a
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define void @lzmaDecode() #0 { define void @lzmaDecode() #0 {
entry: entry:
br label %for.cond.outer.outer.outer br label %for.cond.outer.outer.outer
for.cond: ; preds = %for.cond.outer.outer.outer for.cond: ; preds = %for.cond.outer.outer.outer
switch i32 undef, label %cleanup.1072 [ switch i32 undef, label %cleanup.1072 [
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polly/test/CodeGen/synthesizable_phi_write_after_loop.ll

; RUN: opt %loadPolly -polly-codegen -S < %s | FileCheck %s ; RUN: opt %loadPolly -polly-codegen -S < %s | FileCheck %s
; ;
; Check for the correct written value of a scalar phi write whose value is ; Check for the correct written value of a scalar phi write whose value is
; defined within the loop, but its effective value is its last definition when ; defined within the loop, but its effective value is its last definition when
; leaving the loop (in this test it is the value 2 for %i.inc). This can be ; leaving the loop (in this test it is the value 2 for %i.inc). This can be
; either computed: ; either computed:
; - Using SCEVExpander: ; - Using SCEVExpander:
; In this case the Loop passed to the expander must NOT be the loop ; In this case the Loop passed to the expander must NOT be the loop
; - Overwriting the same alloca in each iteration s.t. the last value will ; - Overwriting the same alloca in each iteration s.t. the last value will
; retain in %i.inc.s2a ; retain in %i.inc.s2a
; The first is currently generated by Polly and tested here. ; The first is currently generated by Polly and tested here.
; CHECK: polly.stmt.next: ; CHECK: polly.stmt.next:
; CHECK-NEXT: store i32 2, i32* %phi.phiops ; CHECK-NEXT: store i32 2, ptr %phi.phiops
; CHECK-NEXT: br label %polly.stmt.join ; CHECK-NEXT: br label %polly.stmt.join
define i32 @func() { define i32 @func() {
entry: entry:
br label %start br label %start
start: start:
br i1 true, label %loop, label %join br i1 true, label %loop, label %join
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polly/test/ScopInfo/out-of-scop-use-in-region-entry-phi-node-nonaffine-subregion.ll

; RUN: opt %loadPolly -polly-codegen -S < %s | FileCheck %s ; RUN: opt %loadPolly -polly-codegen -S < %s | FileCheck %s
; ;
; Check whether %newval is identified as escaping value, even though it is used ; Check whether %newval is identified as escaping value, even though it is used
; in a phi that is in the region. Non-affine subregion case. ; in a phi that is in the region. Non-affine subregion case.
; ;
; CHECK-LABEL: subregion_entry.region_entering: ; CHECK-LABEL: subregion_entry.region_entering:
; CHECK: %loop_carried.ph = phi float [ %newval.merge, %backedge ], [ undef, %entry ] ; CHECK: %loop_carried.ph = phi float [ %newval.merge, %backedge ], [ undef, %entry ]
; ;
; CHECK-LABEL: polly.merge_new_and_old: ; CHECK-LABEL: polly.merge_new_and_old:
; CHECK: %newval.merge = phi float [ %newval.final_reload, %polly.exiting ], [ %newval, %subregion_exit.region_exiting ] ; CHECK: %newval.merge = phi float [ %newval.final_reload, %polly.exiting ], [ %newval, %subregion_exit.region_exiting ]
; ;
; CHECK-LABEL: polly.start: ; CHECK-LABEL: polly.start:
; CHECK: store float %loop_carried.ph, float* %loop_carried.phiops ; CHECK: store float %loop_carried.ph, ptr %loop_carried.phiops
; ;
; CHECK-LABEL: polly.stmt.subregion_entry.entry: ; CHECK-LABEL: polly.stmt.subregion_entry.entry:
; CHECK: %loop_carried.phiops.reload = load float, float* %loop_carried.phiops ; CHECK: %loop_carried.phiops.reload = load float, ptr %loop_carried.phiops
; ;
; CHECK-LABEL: polly.stmt.subregion_entry: ; CHECK-LABEL: polly.stmt.subregion_entry:
; CHECK: %polly.loop_carried = phi float [ %loop_carried.phiops.reload, %polly.stmt.subregion_entry.entry ] ; CHECK: %polly.loop_carried = phi float [ %loop_carried.phiops.reload, %polly.stmt.subregion_entry.entry ]
; CHECK: %p_newval = fadd float %polly.loop_carried, 1.000000e+00 ; CHECK: %p_newval = fadd float %polly.loop_carried, 1.000000e+00
; ;
; CHECK-LABEL: polly.stmt.polly.merge_new_and_old.exit: ; CHECK-LABEL: polly.stmt.polly.merge_new_and_old.exit:
; CHECK: %newval.final_reload = load float, float* %newval.s2a ; CHECK: %newval.final_reload = load float, ptr %newval.s2a
define void @func() { define void @func() {
entry: entry:
br label %subregion_entry br label %subregion_entry
subregion_entry: subregion_entry:
%loop_carried = phi float [ undef, %entry ], [ %newval, %backedge ] %loop_carried = phi float [ undef, %entry ], [ %newval, %backedge ]
%indvar = phi i32 [ 1, %entry ], [ %indvar_next, %backedge ] %indvar = phi i32 [ 1, %entry ], [ %indvar_next, %backedge ]
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