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gysit (Tobias Gysi)
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User Since
Feb 7 2020, 5:34 AM (33 w, 9 h)

Recent Activity

Jul 29 2020

gysit committed rG77c3b016c424: [mlir] fix error handling in rocm runtime wrapper (authored by gysit).
[mlir] fix error handling in rocm runtime wrapper
Jul 29 2020, 1:11 PM
gysit closed D84861: [mlir] fix error handling in rocm runtime wrapper.
Jul 29 2020, 1:11 PM · Restricted Project
gysit requested review of D84861: [mlir] fix error handling in rocm runtime wrapper.
Jul 29 2020, 8:53 AM · Restricted Project

Jun 29 2020

gysit committed rG10643c9ad85b: [mlir] make the bitwidth of device side index computations configurable (reland) (authored by gysit).
[mlir] make the bitwidth of device side index computations configurable (reland)
Jun 29 2020, 3:45 AM
gysit added a reverting change for rGd10b1a38a7df: [mlir] make the bitwidth of device side index computations configurable: rG10643c9ad85b: [mlir] make the bitwidth of device side index computations configurable (reland).
Jun 29 2020, 3:45 AM
gysit closed D82475: [mlir] make the bitwidth of device side index computations configurable.
Jun 29 2020, 3:44 AM · Restricted Project

Jun 27 2020

gysit updated the diff for D82475: [mlir] make the bitwidth of device side index computations configurable.
  • revert to using static instead of thread_local
  • removed more inconsistent spaces
Jun 27 2020, 1:31 AM · Restricted Project

Jun 26 2020

gysit updated the diff for D82475: [mlir] make the bitwidth of device side index computations configurable.

Adressed Alex's comments:

  • make default configuration thread_local
  • fixed clang tidy issues
  • removed unnecessary spaces
Jun 26 2020, 8:10 AM · Restricted Project
gysit committed rG652a79659a89: [mlir] fix off-by-one error in collapseParallelLoops (authored by gysit).
[mlir] fix off-by-one error in collapseParallelLoops
Jun 26 2020, 7:04 AM
gysit closed D82634: [mlir] fix off-by-one error in collapseParallelLoops.
Jun 26 2020, 7:03 AM · Restricted Project
gysit created D82634: [mlir] fix off-by-one error in collapseParallelLoops.
Jun 26 2020, 2:40 AM · Restricted Project
gysit committed rG48f1d4fcd27c: [mlir] parallel loop canonicalization (authored by gysit).
[mlir] parallel loop canonicalization
Jun 26 2020, 1:04 AM
gysit closed D82191: [mlir] parallel loop canonicalization.
Jun 26 2020, 1:04 AM · Restricted Project

Jun 25 2020

gysit updated the diff for D82191: [mlir] parallel loop canonicalization.
  • Added a comment that reflects the discussions about clone (can be reverted) vs inline (performance).
  • The current implementation is revertible at the cost of cloning the loop body.
  • Use std::tie to improve the code readability.
Jun 25 2020, 11:20 AM · Restricted Project
gysit committed rGcd730816058b: [mlir] parallel loop tiling optimization for loops with static bounds (authored by gysit).
[mlir] parallel loop tiling optimization for loops with static bounds
Jun 25 2020, 12:30 AM
gysit closed D82003: [mlir] parallel loop tiling optimization for loops with static bounds.
Jun 25 2020, 12:30 AM · Restricted Project

Jun 24 2020

gysit created D82475: [mlir] make the bitwidth of device side index computations configurable.
Jun 24 2020, 9:10 AM · Restricted Project

Jun 23 2020

gysit added inline comments to D80285: [mlir] make the bitwidth of device side index computations configurable.
Jun 23 2020, 2:32 PM · Restricted Project, Restricted Project
gysit added inline comments to D80285: [mlir] make the bitwidth of device side index computations configurable.
Jun 23 2020, 11:15 AM · Restricted Project, Restricted Project
gysit committed rG2ff6fad70049: Revert "[mlir] make the bitwidth of device side index computations configurable" (authored by gysit).
Revert "[mlir] make the bitwidth of device side index computations configurable"
Jun 23 2020, 10:43 AM
gysit added a reverting change for rGd10b1a38a7df: [mlir] make the bitwidth of device side index computations configurable: rG2ff6fad70049: Revert "[mlir] make the bitwidth of device side index computations configurable".
Jun 23 2020, 10:43 AM
gysit abandoned D82364: [mlir] fix ConvertToLLVMPattern constructor.
Jun 23 2020, 10:43 AM · Restricted Project
gysit added inline comments to D82191: [mlir] parallel loop canonicalization.
Jun 23 2020, 9:04 AM · Restricted Project
gysit updated the diff for D82364: [mlir] fix ConvertToLLVMPattern constructor.
  • copy the options instead of keeping a reference
Jun 23 2020, 7:58 AM · Restricted Project
gysit added inline comments to D80285: [mlir] make the bitwidth of device side index computations configurable.
Jun 23 2020, 5:17 AM · Restricted Project, Restricted Project
gysit added inline comments to D80285: [mlir] make the bitwidth of device side index computations configurable.
Jun 23 2020, 4:12 AM · Restricted Project, Restricted Project
gysit created D82364: [mlir] fix ConvertToLLVMPattern constructor.
Jun 23 2020, 3:40 AM · Restricted Project
gysit added inline comments to D80285: [mlir] make the bitwidth of device side index computations configurable.
Jun 23 2020, 2:36 AM · Restricted Project, Restricted Project

Jun 22 2020

gysit added inline comments to D82191: [mlir] parallel loop canonicalization.
Jun 22 2020, 11:04 PM · Restricted Project
gysit committed rG30140cd24920: [llvm] Fix typo in test case comment (NFC) (authored by gysit).
[llvm] Fix typo in test case comment (NFC)
Jun 22 2020, 11:17 AM

Jun 20 2020

gysit updated the diff for D82003: [mlir] parallel loop tiling optimization for loops with static bounds.
  • addressed the review comments
  • use ceil division by the step to compute the number of loop iterations (to support the cases where the number of loop iterations is known but not a multiple of the step)
  • adapted one of the test cases to test this scenario
  • removed some unnecessary headers
Jun 20 2020, 7:54 AM · Restricted Project
gysit added inline comments to D82191: [mlir] parallel loop canonicalization.
Jun 20 2020, 3:08 AM · Restricted Project
gysit updated the diff for D82191: [mlir] parallel loop canonicalization.
  • cleanup includes
Jun 20 2020, 2:36 AM · Restricted Project

Jun 19 2020

gysit updated the diff for D82191: [mlir] parallel loop canonicalization.
  • added additional test
Jun 19 2020, 9:44 AM · Restricted Project
gysit added inline comments to D82191: [mlir] parallel loop canonicalization.
Jun 19 2020, 9:12 AM · Restricted Project
gysit updated the diff for D82003: [mlir] parallel loop tiling optimization for loops with static bounds.
  • separated the loop tiling patch from the canonicalization
  • addressed Stephan's comments
Jun 19 2020, 8:37 AM · Restricted Project
gysit created D82191: [mlir] parallel loop canonicalization.
Jun 19 2020, 8:04 AM · Restricted Project
gysit added a comment to D82003: [mlir] parallel loop tiling optimization for loops with static bounds.

Ok I try to split the stuff.

Jun 19 2020, 7:32 AM · Restricted Project
gysit updated the diff for D80285: [mlir] make the bitwidth of device side index computations configurable.

updated to the latest master

Jun 19 2020, 5:21 AM · Restricted Project, Restricted Project
gysit added a comment to D82003: [mlir] parallel loop tiling optimization for loops with static bounds.

I may missunderstand the thing but in mlir/test/Transforms/parallel-loop-collapsing.mlir the computation of I3 directly uses NEW_I0 and multiplies it by 10 and adds 9. Since NEW_I0 takes the values 0 and 1 this means we get the value 19 for I3 but we have the loop range 9 to 11 in the original loop. I guess NEW_I0 should be divided by two before computing the index I3?

Jun 19 2020, 4:49 AM · Restricted Project
gysit updated the diff for D82003: [mlir] parallel loop tiling optimization for loops with static bounds.
  • I started from the fixed tiling pass and tried to apply minimal changes (drop the minimum operation if the loop sizes is a multiple of the tile size)
  • I added a canonicalization to drop single iteration loops
  • I use CX / VX instead of VAL_X
Jun 19 2020, 4:49 AM · Restricted Project

Jun 17 2020

gysit created D82003: [mlir] parallel loop tiling optimization for loops with static bounds.
Jun 17 2020, 4:17 AM · Restricted Project

Jun 9 2020

gysit updated the diff for D80285: [mlir] make the bitwidth of device side index computations configurable.

The update passes the options structure to the type converter and to the conversion pattern base class (replaces the llvm type converter customizations). I also extended the patch to the rocdl backend.

Jun 9 2020, 2:09 AM · Restricted Project, Restricted Project

May 26 2020

gysit added a comment to D80285: [mlir] make the bitwidth of device side index computations configurable.

If we want to strive to little bit bigger refactoring we can postpone landing

May 26 2020, 1:02 AM · Restricted Project, Restricted Project
gysit updated the diff for D80285: [mlir] make the bitwidth of device side index computations configurable.

I fixed the typo and added extended the existing tests a little bit to test 32-bit index computations

May 26 2020, 1:02 AM · Restricted Project, Restricted Project

May 20 2020

gysit created D80285: [mlir] make the bitwidth of device side index computations configurable.
May 20 2020, 2:40 AM · Restricted Project, Restricted Project
gysit added a comment to D80285: [mlir] make the bitwidth of device side index computations configurable.

My assumption is that the LLVMTypeConverterCustomization do not interfere with the address space conversion. Should the address space conversion be an integral part of the LLVMTypeConverterCustomization class?

May 20 2020, 2:40 AM · Restricted Project, Restricted Project

May 18 2020

gysit created D80113: [mlir] Support optional attributes in assembly formats.
May 18 2020, 2:38 AM · Restricted Project

Apr 16 2020

gysit abandoned D76350: [mlir] lower loop.if operations that yield a result.
Apr 16 2020, 2:14 AM · Restricted Project

Apr 3 2020

gysit accepted D77418: [mlir] LoopToStandard conversion: support "if/else" with results.

Thanks for fixing this. Should have had that idea myself!

Apr 3 2020, 12:57 PM · Restricted Project

Mar 18 2020

gysit added a comment to D76350: [mlir] lower loop.if operations that yield a result.

Unfortunately, this is harder than it looks. We need to make sure all IR changes in the pattern go through rewriter and we currently don't have a way of adding new block arguments there. If you are blocked by this, feel free to temporarily loop.if lowering from the pattern rewriter infra and run it as a plain IR-mutating pass.

Mar 18 2020, 7:02 AM · Restricted Project
gysit created D76350: [mlir] lower loop.if operations that yield a result.
Mar 18 2020, 3:46 AM · Restricted Project

Mar 2 2020

gysit created D75449: [MLIR][GPU] fix loop trip count computation in LoopsToGPU.
Mar 2 2020, 5:52 AM · Restricted Project

Feb 12 2020

gysit updated the diff for D74474: [mlir] support creating memref descriptors from static shape with non-zero offset.

I added a test for a memref with a non-zero offset and non-standard strides. Let me know if you had another test in mind...

Feb 12 2020, 7:09 AM · Restricted Project
gysit created D74474: [mlir] support creating memref descriptors from static shape with non-zero offset.
Feb 12 2020, 3:10 AM · Restricted Project

Feb 8 2020

gysit created D74280: [mlir] subview op lowering for target memrefs with const offset.
Feb 8 2020, 9:09 AM · Restricted Project