Modified DAGCombiner to pass the shift the bittest input and the shift amount
to hasBitTest. This matches the other call to hasBitTest in TargetLowering.h
This is an alternative to D122454.
Paths
| Differential D122458
[RISCV][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI. ClosedPublic Authored by craig.topper on Mar 24 2022, 9:53 PM.
Details Summary Modified DAGCombiner to pass the shift the bittest input and the shift amount This is an alternative to D122454.
Diff Detail
Event TimelineComment Actions Seems fine to me. If I'm seeing it correctly, we wouldn't expect any x86 or Hexagon changes because they don't check for a bit range, just any scalar type. Comment Actions
Correct. I'm not sure if I ran the X86/Hexagon tests before I posted or not. I might have just ran it on RISCV. I'll make sure I do that and maybe add more tests. craig.topper retitled this revision from [RISCV][WIP] Enable TargetLowering::hasBitTest for masks that fit in ANDI. to [RISCV] Enable TargetLowering::hasBitTest for masks that fit in ANDI..Mar 27 2022, 11:24 PM craig.topper retitled this revision from [RISCV] Enable TargetLowering::hasBitTest for masks that fit in ANDI. to [RISCV][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI.. This revision is now accepted and ready to land.Mar 28 2022, 11:02 AM This revision was landed with ongoing or failed builds.Mar 28 2022, 12:47 PM Closed by commit rGe68257fceee7: [RISCV][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in… (authored by craig.topper). · Explain Why This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 418681 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/bittest.ll
llvm/test/CodeGen/RISCV/rv32zbs.ll
llvm/test/CodeGen/RISCV/rv64zbs.ll
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