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Miss_Grape (LiqinWeng)
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Oct 21 2021, 6:53 PM (36 w, 19 h)

Recent Activity

Yesterday

Miss_Grape added a comment to D128806: [RISCV] Fix wrong position of prologue_end.

FYI I looked before at adding a flags arg to storeRegToStackSlot, but ultimately got distracted with other things https://reviews.llvm.org/D30115

Thu, Jun 30, 5:35 PM · Restricted Project, Restricted Project
Miss_Grape added a comment to D128806: [RISCV] Fix wrong position of prologue_end.

I think removing debug location is problematic. Because storeRegToStackSlot method is used in many places, for example, register spillers use it to spill a register to stack frame. If the spill instruction's debug location info were removed, its debug location would follow the previous instruction's location when emitting debug location info. It is ok to do that in -O0, but if the optimization level were -O2, instructions would be hoisted or sink which would cause the spill instruction to have wrong debug location info.

Thu, Jun 30, 5:30 PM · Restricted Project, Restricted Project

Wed, Jun 29

Miss_Grape added a comment to D128806: [RISCV] Fix wrong position of prologue_end.
Wed, Jun 29, 7:48 PM · Restricted Project, Restricted Project
Miss_Grape added a comment to D128806: [RISCV] Fix wrong position of prologue_end.

Isn't the problem just that spill/restoreCalleeSavedRegisters need to set FrameSetup/Destroy on their stores/loads (which is also a problem with the generic implementation that we used to use before implementing -msave-restore)?

I think we may remove debug-location instead of adding FrameSetup flags for spill/restoreCalleeSavedRegisters, Because dwarf information is added for debugging convenience, At this stage, people should not care when debugging

Wed, Jun 29, 7:45 PM · Restricted Project, Restricted Project
Miss_Grape updated the diff for D128806: [RISCV] Fix wrong position of prologue_end.

address the comments

Wed, Jun 29, 7:37 PM · Restricted Project, Restricted Project
Miss_Grape added a comment to D128806: [RISCV] Fix wrong position of prologue_end.

> Does the test actually need to check the DWARF? Can't we just check the assembly, namely that the .loc prologue_end directive is inserted in the correct place?
Need Dwarf
Through Dwarf, I am verifying that the address of the current Prologue_end is the address of the end of the fuction prologue

Wed, Jun 29, 7:25 PM · Restricted Project, Restricted Project
Miss_Grape added a comment to D128806: [RISCV] Fix wrong position of prologue_end.

Is removing the if (I != MBB.end()) DL = I->getDebugLoc(); actually correct? I'm wondering why do several other targets have that if it can just be removed.

Wed, Jun 29, 7:23 PM · Restricted Project, Restricted Project
Miss_Grape added a comment to D128806: [RISCV] Fix wrong position of prologue_end.

Is removing the if (I != MBB.end()) DL = I->getDebugLoc(); actually correct? I'm wondering why do several other targets have that if it can just be removed.

How about instead adding a MachineInstr::FrameSetup flag to the appropriate instructions? That also seems to fix the issue. Don't we want to add that flag anyway?

Does the test actually need to check the DWARF? Can't we just check the assembly, namely that the .loc prologue_end directive is inserted in the correct place?

Wed, Jun 29, 7:02 PM · Restricted Project, Restricted Project
Miss_Grape retitled D128806: [RISCV] Fix wrong position of prologue_end from [RISCV] Fix wrong position progue_end to [RISCV] Fix wrong position of prologue_end.
Wed, Jun 29, 5:31 AM · Restricted Project, Restricted Project
Miss_Grape added a comment to D128806: [RISCV] Fix wrong position of prologue_end.
int global_a = 10;
__attribute__((noinline)) int test2() {
  int a = global_a ;
  int b = 10;
  return a + b;
}
Wed, Jun 29, 5:28 AM · Restricted Project, Restricted Project
Miss_Grape retitled D128806: [RISCV] Fix wrong position of prologue_end from [RISCV] Remove DL Information when storeRegToStackSlot to [RISCV] Fix wrong position progue_end.
Wed, Jun 29, 5:10 AM · Restricted Project, Restricted Project
Miss_Grape requested review of D128806: [RISCV] Fix wrong position of prologue_end.
Wed, Jun 29, 5:08 AM · Restricted Project, Restricted Project

Mon, Jun 13

Miss_Grape abandoned D125747: [RISCV] Enable scalable vectorization by default for RVV.
Mon, Jun 13, 12:15 AM · Restricted Project, Restricted Project

Jun 1 2022

Miss_Grape added a reviewer for D126443: [NFC] Modify the test case: benshi001.
Jun 1 2022, 4:25 AM · Restricted Project, Restricted Project

May 31 2022

Miss_Grape added a comment to D125271: [riscv] Enable strict assertions in InsertVSETVLI data flow.

Form your IR,

call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> zeroinitializer, <4 x ptr> %1, i32 0, <4 x i1> undef)

I think this is not loop vectorization as scale-vector,set -mllvm -scalable-vectorization=off , may also core dump? Could you try it?

Yes, it will cause core dump even with -mllvm -scalable-vectorization=off, but will not if we remove -mllvm -riscv-v-vector-bits-max=128 -mllvm -riscv-v-vector-bits-min=128.
So, it seems that there are two problems here I guess:

  1. Some loops can't be vectorized by scalable vectorization and fixed-width vectorization is took as a fallback.
  2. There are some bugs in codes generated by fixed-width vectorization.
May 31 2022, 2:08 AM · Restricted Project, Restricted Project
Miss_Grape added a comment to D125747: [RISCV] Enable scalable vectorization by default for RVV.

Do you have any performance data?

I use the TSCV test suit, then run on the spike,

when option: -scalable-vectorization=on, the performance more better. But I'm not sure if the performance data from the spike run can be used as a standard to measure performance

Better than specifying -riscv-v-vector-bits-min to match the machine width?

@craig.topper I think this is somewhat the wrong question here. While I agree that fixed length should be our eventual default for known vector lengths, we currently don't enable any vectorization. If we can show either form of vectorization is generally profitable over the no-vectorization configuration, we should enable. We can then evaluate the other configuration against that new baseline.

@Miss_Grape I struggle to make out what that screenshot is conveying. Could you summarize please? Also, a text attachment is greatly preferred over images.

May 31 2022, 2:05 AM · Restricted Project, Restricted Project

May 29 2022

Miss_Grape added a comment to D125271: [riscv] Enable strict assertions in InsertVSETVLI data flow.

Here is an issue found in D125747. It seems that we will get compilation failures with -mllvm -scalable-vectorization=on using latest LLVM upstream.
Full command is: clang -O2 -march=rv64gcv -mllvm -riscv-v-vector-bits-max=128 -mllvm -riscv-v-vector-bits-min=128 -mllvm -scalable-vectorization=on .
When compiling TSVC, I got:

clang-15: llvm-project-upstream/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1172: void {anonymous}::RISCVInsertVSETVLI::emitVSETVLIs(llvm::MachineBasicBlock&): Assertion `CurInfo == Info.Exit && "InsertVSETVLI dataflow invariant violated"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace, preprocessed source, and associated run script.
Stack dump:
0.      Program arguments: software/clang-riscv-upstream/bin/clang-15 -cc1 -triple riscv64-unknown-linux-gnu -emit-obj --mrelax-relocations -disable-free -clear-ast-before-backend -main-file-name tsc.c -mrelocation-model pic -pic-level 2 -pic-is-pie -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -target-feature +m -target-feature +a -target-feature +f -target-feature +d -target-feature +c -target-feature +v -target-feature +zve32f -target-feature +zve32x -target-feature +zve64d -target-feature +zve64f -target-feature +zve64x -target-feature +zvl128b -target-feature +zvl32b -target-feature +zvl64b -target-feature +relax -target-feature -save-restore -target-abi lp64d -msmall-data-limit 8 -mllvm -treat-scalable-fixed-error-as-warning -debugger-tuning=gdb -fcoverage-compilation-dir=workspace/issues/vectorize/TSVC -resource-dir software/clang-riscv-upstream/lib/clang/15.0.0 -isysroot software/release/sysroot/ -internal-isystem software/clang-riscv-upstream/lib/clang/15.0.0/include -internal-isystem software/release/sysroot//usr/local/include -internal-isystem software/release/lib/gcc/riscv64-unknown-linux-gnu/10.2.0/../../../../riscv64-unknown-linux-gnu/include -internal-externc-isystem software/release/sysroot//include -internal-externc-isystem software/release/sysroot//usr/include -O2 -fdebug-compilation-dir=workspace/issues/vectorize/TSVC -ferror-limit 19 -fno-signed-char -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -mllvm -riscv-v-vector-bits-max=128 -mllvm -riscv-v-vector-bits-min=128 -mllvm -scalable-vectorization=on -faddrsig -o /tmp/tsc-ef6646.o -x c tsc.c
1.      <eof> parser at end of file
2.      Code generation
3.      Running pass 'Function Pass Manager' on module 'tsc.c'.
4.      Running pass 'RISCV Insert VSETVLI pass' on function '@init'
 #0 0x0000563161942c8e llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) llvm-project-upstream/llvm/lib/Support/Unix/Signals.inc:565:0
 #1 0x0000563161942d45 PrintStackTraceSignalHandler(void*) llvm-project-upstream/llvm/lib/Support/Unix/Signals.inc:632:0
 #2 0x00005631619409ec llvm::sys::RunSignalHandlers() llvm-project-upstream/llvm/lib/Support/Signals.cpp:103:0
 #3 0x000056316194260f SignalHandler(int) llvm-project-upstream/llvm/lib/Support/Unix/Signals.inc:407:0
 #4 0x00007fb119b9e980 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x12980)
 #5 0x00007fb11884fe87 raise /build/glibc-uZu3wS/glibc-2.27/signal/../sysdeps/unix/sysv/linux/raise.c:51:0
 #6 0x00007fb1188517f1 abort /build/glibc-uZu3wS/glibc-2.27/stdlib/abort.c:81:0
 #7 0x00007fb1188413fa __assert_fail_base /build/glibc-uZu3wS/glibc-2.27/assert/assert.c:89:0
 #8 0x00007fb118841472 (/lib/x86_64-linux-gnu/libc.so.6+0x30472)
 #9 0x000056315f2af865 (anonymous namespace)::RISCVInsertVSETVLI::emitVSETVLIs(llvm::MachineBasicBlock&) llvm-project-upstream/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1171:0
#10 0x000056315f2b0f8c (anonymous namespace)::RISCVInsertVSETVLI::runOnMachineFunction(llvm::MachineFunction&) llvm-project-upstream/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1476:0
#11 0x0000563160757cff llvm::MachineFunctionPass::runOnFunction(llvm::Function&) llvm-project-upstream/llvm/lib/CodeGen/MachineFunctionPass.cpp:73:0
#12 0x0000563160eb0894 llvm::FPPassManager::runOnFunction(llvm::Function&) llvm-project-upstream/llvm/lib/IR/LegacyPassManager.cpp:1430:0
#13 0x0000563160eb0b3d llvm::FPPassManager::runOnModule(llvm::Module&) llvm-project-upstream/llvm/lib/IR/LegacyPassManager.cpp:1476:0
#14 0x0000563160eb0f65 (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) llvm-project-upstream/llvm/lib/IR/LegacyPassManager.cpp:1545:0
#15 0x0000563160eabf87 llvm::legacy::PassManagerImpl::run(llvm::Module&) llvm-project-upstream/llvm/lib/IR/LegacyPassManager.cpp:535:0
#16 0x0000563160eb17ef llvm::legacy::PassManager::run(llvm::Module&) llvm-project-upstream/llvm/lib/IR/LegacyPassManager.cpp:1673:0
#17 0x0000563161e2b800 (anonymous namespace)::EmitAssemblyHelper::RunCodegenPipeline(clang::BackendAction, std::unique_ptr<llvm::raw_pwrite_stream, std::default_delete<llvm::raw_pwrite_stream>>&, std::unique_ptr<llvm::ToolOutputFile, std::default_delete<llvm::ToolOutputFile>>&) llvm-project-upstream/clang/lib/CodeGen/BackendUtil.cpp:1000:0
#18 0x0000563161e2ba04 (anonymous namespace)::EmitAssemblyHelper::EmitAssembly(clang::BackendAction, std::unique_ptr<llvm::raw_pwrite_stream, std::default_delete<llvm::raw_pwrite_stream>>) llvm-project-upstream/clang/lib/CodeGen/BackendUtil.cpp:1025:0
#19 0x0000563161e2ca1c clang::EmitBackendOutput(clang::DiagnosticsEngine&, clang::HeaderSearchOptions const&, clang::CodeGenOptions const&, clang::TargetOptions const&, clang::LangOptions const&, llvm::StringRef, llvm::Module*, clang::BackendAction, std::unique_ptr<llvm::raw_pwrite_stream, std::default_delete<llvm::raw_pwrite_stream>>) llvm-project-upstream/clang/lib/CodeGen/BackendUtil.cpp:1181:0
#20 0x00005631632689b0 clang::BackendConsumer::HandleTranslationUnit(clang::ASTContext&) llvm-project-upstream/clang/lib/CodeGen/CodeGenAction.cpp:379:0
#21 0x0000563164ffc402 clang::ParseAST(clang::Sema&, bool, bool) llvm-project-upstream/clang/lib/Parse/ParseAST.cpp:182:0
#22 0x00005631628ea47f clang::ASTFrontendAction::ExecuteAction() llvm-project-upstream/clang/lib/Frontend/FrontendAction.cpp:1139:0
#23 0x0000563163265160 clang::CodeGenAction::ExecuteAction() llvm-project-upstream/clang/lib/CodeGen/CodeGenAction.cpp:1144:0
#24 0x00005631628e9d48 clang::FrontendAction::Execute() llvm-project-upstream/clang/lib/Frontend/FrontendAction.cpp:1036:0
#25 0x000056316281ed6b clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) llvm-project-upstream/clang/lib/Frontend/CompilerInstance.cpp:1036:0
#26 0x0000563162a89d7c clang::ExecuteCompilerInvocation(clang::CompilerInstance*) llvm-project-upstream/clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp:266:0
#27 0x000056315f2336b1 cc1_main(llvm::ArrayRef<char const*>, char const*, void*) llvm-project-upstream/clang/tools/driver/cc1_main.cpp:248:0
#28 0x000056315f227195 ExecuteCC1Tool(llvm::SmallVectorImpl<char const*>&) llvm-project-upstream/clang/tools/driver/driver.cpp:317:0
#29 0x000056315f2278b2 main llvm-project-upstream/clang/tools/driver/driver.cpp:388:0
#30 0x00007fb118832c87 __libc_start_main /build/glibc-uZu3wS/glibc-2.27/csu/../csu/libc-start.c:344:0
#31 0x000056315f22590a _start (software/clang-riscv-upstream/bin/clang-15+0x2ce490a)

Reduced LLVM IRs via llvm-reduce:

target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
target triple = "riscv64-unknown-linux-gnu"

define i32 @init(ptr %b, i1 %0) {
entry:
  br label %vector.body8501

vector.body8501:                                  ; preds = %vector.body8501, %entry
  %vec.ind8503 = phi <4 x i64> [ %vec.ind.next8506, %vector.body8501 ], [ zeroinitializer, %entry ]
  %step.add8504 = add <4 x i64> %vec.ind8503, zeroinitializer
  %1 = getelementptr inbounds float, ptr %b, <4 x i64> %step.add8504
  call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> zeroinitializer, <4 x ptr> %1, i32 0, <4 x i1> undef)
  %vec.ind.next8506 = add <4 x i64> %vec.ind8503, <i64 16, i64 16, i64 16, i64 16>
  br i1 %0, label %vector.body8513, label %vector.body8501

vector.body8513:                                  ; preds = %vector.body8513, %vector.body8501
  call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> <float -1.000000e+00, float -1.000000e+00, float -1.000000e+00, float -1.000000e+00>, <4 x ptr> undef, i32 0, <4 x i1> undef)
  br label %vector.body8513
}

; Function Attrs: nocallback nofree nosync nounwind willreturn writeonly
declare void @llvm.masked.scatter.v4f32.v4p0(<4 x float>, <4 x ptr>, i32 immarg, <4 x i1>) #0

; uselistorder directives
uselistorder ptr @llvm.masked.scatter.v4f32.v4p0, { 1, 0 }

attributes #0 = { nocallback nofree nosync nounwind willreturn writeonly }

@reames can you take a look at this?

May 29 2022, 11:39 PM · Restricted Project, Restricted Project
Miss_Grape added a comment to D125747: [RISCV] Enable scalable vectorization by default for RVV.

Do you have any performance data?

I use the TSCV test suit, then run on the spike,

when option: -scalable-vectorization=on, the performance more better. But I'm not sure if the performance data from the spike run can be used as a standard to measure performance

Better than specifying -riscv-v-vector-bits-min to match the machine width?

@craig.topper I think this is somewhat the wrong question here. While I agree that fixed length should be our eventual default for known vector lengths, we currently don't enable any vectorization. If we can show either form of vectorization is generally profitable over the no-vectorization configuration, we should enable. We can then evaluate the other configuration against that new baseline.

@Miss_Grape I struggle to make out what that screenshot is conveying. Could you summarize please? Also, a text attachment is greatly preferred over images.

May 29 2022, 7:59 PM · Restricted Project, Restricted Project
Miss_Grape added a comment to D126443: [NFC] Modify the test case.

ping

May 29 2022, 7:16 PM · Restricted Project, Restricted Project

May 27 2022

Miss_Grape added a comment to D125747: [RISCV] Enable scalable vectorization by default for RVV.

Do you have any performance data?

May 27 2022, 1:07 AM · Restricted Project, Restricted Project

May 26 2022

Miss_Grape committed rGa84026821bf6: [RISCV] Add test for experimental.vector.reverse (authored by Miss_Grape).
[RISCV] Add test for experimental.vector.reverse
May 26 2022, 11:31 PM · Restricted Project, Restricted Project
Miss_Grape closed D125866: [RISCV] Add test for experimental.vector.reverse.
May 26 2022, 11:30 PM · Restricted Project, Restricted Project
Miss_Grape added a reviewer for D126440: [RISCV] Return an invalid cost for memory ops with unsupported types: kmclaughlin.
May 26 2022, 8:31 PM · Restricted Project, Restricted Project

May 25 2022

Miss_Grape retitled D126443: [NFC] Modify the test case from [AArch64][NFC] Modify the test case to [NFC] Modify the test case.
May 25 2022, 11:34 PM · Restricted Project, Restricted Project
Miss_Grape requested review of D126443: [NFC] Modify the test case.
May 25 2022, 8:25 PM · Restricted Project, Restricted Project
Miss_Grape added inline comments to D125866: [RISCV] Add test for experimental.vector.reverse.
May 25 2022, 8:14 PM · Restricted Project, Restricted Project
Miss_Grape updated the diff for D126440: [RISCV] Return an invalid cost for memory ops with unsupported types.
May 25 2022, 8:10 PM · Restricted Project, Restricted Project
Miss_Grape requested review of D126440: [RISCV] Return an invalid cost for memory ops with unsupported types.
May 25 2022, 8:05 PM · Restricted Project, Restricted Project
Miss_Grape added a comment to D123663: [PPC][CodeGen][NFC] Use ArrayRef in TargetLowering functions.

While I certainly appreciate the work to refactor this behemoth of a function, I am about as lukewarm on how much of a readability improvement this is. If all the targets are being similarly refactored, I won't stand in the way of doing the same to PPC. So if you get the approval for the other targets, we'll go ahead with PPC as well.

May 25 2022, 2:10 AM · Restricted Project, Restricted Project
Miss_Grape added a comment to D125856: [RISCV] Add cost model for SK_Reverse.
May 25 2022, 2:06 AM · Restricted Project, Restricted Project
Miss_Grape added inline comments to D125856: [RISCV] Add cost model for SK_Reverse.
May 25 2022, 2:02 AM · Restricted Project, Restricted Project
Miss_Grape updated the diff for D125856: [RISCV] Add cost model for SK_Reverse.
May 25 2022, 1:59 AM · Restricted Project, Restricted Project
Miss_Grape updated the diff for D125856: [RISCV] Add cost model for SK_Reverse.
May 25 2022, 1:54 AM · Restricted Project, Restricted Project

May 22 2022

Miss_Grape added a comment to D125866: [RISCV] Add test for experimental.vector.reverse.

ping

May 22 2022, 6:35 PM · Restricted Project, Restricted Project

May 18 2022

Miss_Grape updated the summary of D125866: [RISCV] Add test for experimental.vector.reverse.
May 18 2022, 3:08 AM · Restricted Project, Restricted Project
Miss_Grape added a comment to D125866: [RISCV] Add test for experimental.vector.reverse.

Add test for https://reviews.llvm.org/D125856

May 18 2022, 2:56 AM · Restricted Project, Restricted Project
Miss_Grape added a comment to D125866: [RISCV] Add test for experimental.vector.reverse.
May 18 2022, 2:54 AM · Restricted Project, Restricted Project
Miss_Grape added inline comments to D125856: [RISCV] Add cost model for SK_Reverse.
May 18 2022, 2:53 AM · Restricted Project, Restricted Project
Miss_Grape requested review of D125866: [RISCV] Add test for experimental.vector.reverse.
May 18 2022, 2:51 AM · Restricted Project, Restricted Project
Miss_Grape retitled D125856: [RISCV] Add cost model for SK_Reverse from [RISCV] Add cost model for SK_Reverse to [WIP] [RISCV] Add cost model for SK_Reverse.
May 18 2022, 1:14 AM · Restricted Project, Restricted Project
Miss_Grape added inline comments to D125856: [RISCV] Add cost model for SK_Reverse.
May 18 2022, 12:33 AM · Restricted Project, Restricted Project
Miss_Grape requested review of D125856: [RISCV] Add cost model for SK_Reverse.
May 18 2022, 12:21 AM · Restricted Project, Restricted Project

May 17 2022

Miss_Grape requested review of D125747: [RISCV] Enable scalable vectorization by default for RVV.
May 17 2022, 12:48 AM · Restricted Project, Restricted Project

May 16 2022

Miss_Grape committed rGff3f4988ed58: [CodeGen] Use ArrayRef in TargetLowering functions (authored by Miss_Grape).
[CodeGen] Use ArrayRef in TargetLowering functions
May 16 2022, 6:31 AM · Restricted Project, Restricted Project
Miss_Grape closed D123656: [CodeGen] Use ArrayRef in TargetLowering functions.
May 16 2022, 6:31 AM · Restricted Project, Restricted Project
Miss_Grape committed rGd95513ae3a73: [RISCV] remove useless code (authored by Miss_Grape).
[RISCV] remove useless code
May 16 2022, 5:55 AM · Restricted Project, Restricted Project
Miss_Grape closed D125460: [RISCV] remove useless code.
May 16 2022, 5:55 AM · Restricted Project, Restricted Project
Miss_Grape added a comment to D125460: [RISCV] remove useless code.

hasVInstructions() check be unneeded. RISCV can only loop vectorization with hasVInstructions()

For long term, I think that's not true, P/Packed-SIMD extensions should be able to apply loop vectorization too, but I am not opposite this getting merge, just remind we might need to add back in future.

May 16 2022, 5:50 AM · Restricted Project, Restricted Project

May 12 2022

Miss_Grape added a comment to D123659: [MIPS][CodeGen][NFC] Use ArrayRef in TargetLowering functions.

ping

May 12 2022, 7:25 PM · Restricted Project, Restricted Project
Miss_Grape added a comment to D125460: [RISCV] remove useless code.

LGTM, but please fix the description to use hasVInstructions instead of hasStdExtV since that's what's in the code.

May 12 2022, 7:20 PM · Restricted Project, Restricted Project
Miss_Grape updated the summary of D125460: [RISCV] remove useless code.
May 12 2022, 7:20 PM · Restricted Project, Restricted Project
Miss_Grape updated the summary of D125460: [RISCV] remove useless code.
May 12 2022, 4:20 AM · Restricted Project, Restricted Project
Miss_Grape requested review of D125460: [RISCV] remove useless code.
May 12 2022, 4:17 AM · Restricted Project, Restricted Project
Miss_Grape added a comment to D123656: [CodeGen] Use ArrayRef in TargetLowering functions.

ping

May 12 2022, 4:04 AM · Restricted Project, Restricted Project

May 9 2022

Herald added a project to D101469: [RISCV] Enable interleaved vectorization for RVV: Restricted Project.
May 9 2022, 2:06 AM · Restricted Project, Restricted Project

Apr 27 2022

Miss_Grape added a comment to D123659: [MIPS][CodeGen][NFC] Use ArrayRef in TargetLowering functions.

ping

Apr 27 2022, 7:10 PM · Restricted Project, Restricted Project
Miss_Grape committed rG6365bde65856: [XCORE][CodeGen][NFC] Use ArrayRef in TargetLowering functions (authored by Miss_Grape).
[XCORE][CodeGen][NFC] Use ArrayRef in TargetLowering functions
Apr 27 2022, 7:07 PM · Restricted Project, Restricted Project
Miss_Grape closed D123661: [XCORE][CodeGen][NFC] Use ArrayRef in TargetLowering functions.
Apr 27 2022, 7:07 PM · Restricted Project, Restricted Project
Miss_Grape committed rGca3cd345a0d0: [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in… (authored by Miss_Grape).
[MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in…
Apr 27 2022, 2:04 AM · Restricted Project, Restricted Project
Miss_Grape closed D123577: [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI..
Apr 27 2022, 2:04 AM · Restricted Project, Restricted Project

Apr 23 2022

Miss_Grape added a comment to D123577: [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI..

ping

Apr 23 2022, 6:48 PM · Restricted Project, Restricted Project

Apr 20 2022

Miss_Grape added inline comments to D124096: [RISCV] Use default promotion for (i32 (shl 1, X)) on RV64 when Zbs is enabled..
Apr 20 2022, 8:04 PM · Restricted Project, Restricted Project
Miss_Grape added inline comments to D124096: [RISCV] Use default promotion for (i32 (shl 1, X)) on RV64 when Zbs is enabled..
Apr 20 2022, 7:51 PM · Restricted Project, Restricted Project

Apr 19 2022

Miss_Grape added inline comments to D123577: [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI..
Apr 19 2022, 7:37 PM · Restricted Project, Restricted Project
Miss_Grape retitled D123577: [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI. from [WIP][MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI. to [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI..
Apr 19 2022, 7:36 PM · Restricted Project, Restricted Project
Miss_Grape updated the diff for D123577: [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI..

1,address comment

Apr 19 2022, 7:36 PM · Restricted Project, Restricted Project
Miss_Grape retitled D123577: [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI. from [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI. to [WIP][MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI..
Apr 19 2022, 7:02 PM · Restricted Project, Restricted Project
Miss_Grape updated the diff for D123577: [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI..
Apr 19 2022, 6:53 PM · Restricted Project, Restricted Project
Miss_Grape added inline comments to D123577: [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI..
Apr 19 2022, 6:51 PM · Restricted Project, Restricted Project
Miss_Grape updated the diff for D123577: [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI..

Fix the comment

Apr 19 2022, 6:46 PM · Restricted Project, Restricted Project

Apr 18 2022

Herald added a project to D119787: [ELF][PPC64] Fix assertion failure for branches to hidden undefined weak for -no-pie: Restricted Project.
Apr 18 2022, 7:51 PM · Restricted Project, Restricted Project

Apr 17 2022

Miss_Grape added a comment to D123656: [CodeGen] Use ArrayRef in TargetLowering functions.

ping

Apr 17 2022, 7:30 PM · Restricted Project, Restricted Project
Miss_Grape added a comment to D123577: [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI..

ping

Apr 17 2022, 7:30 PM · Restricted Project, Restricted Project

Apr 13 2022

Miss_Grape updated the diff for D123656: [CodeGen] Use ArrayRef in TargetLowering functions.
Apr 13 2022, 7:00 PM · Restricted Project, Restricted Project
Miss_Grape updated the diff for D123656: [CodeGen] Use ArrayRef in TargetLowering functions.
Apr 13 2022, 4:04 AM · Restricted Project, Restricted Project
Miss_Grape updated the diff for D123656: [CodeGen] Use ArrayRef in TargetLowering functions.
Apr 13 2022, 3:58 AM · Restricted Project, Restricted Project
Miss_Grape added a reviewer for D123656: [CodeGen] Use ArrayRef in TargetLowering functions: lkail.
Apr 13 2022, 3:57 AM · Restricted Project, Restricted Project
Miss_Grape added inline comments to D123663: [PPC][CodeGen][NFC] Use ArrayRef in TargetLowering functions.
Apr 13 2022, 3:32 AM · Restricted Project, Restricted Project
Miss_Grape added a comment to D123656: [CodeGen] Use ArrayRef in TargetLowering functions.

If this patch Ok, need to update the following patch:
D123659 D123663 D123661 D123654 D123653

Apr 13 2022, 1:54 AM · Restricted Project, Restricted Project
Miss_Grape updated the diff for D123656: [CodeGen] Use ArrayRef in TargetLowering functions.
Apr 13 2022, 1:47 AM · Restricted Project, Restricted Project
Miss_Grape added reviewers for D123663: [PPC][CodeGen][NFC] Use ArrayRef in TargetLowering functions: sunshaoce, stefanp.
Apr 13 2022, 1:43 AM · Restricted Project, Restricted Project
Miss_Grape requested review of D123663: [PPC][CodeGen][NFC] Use ArrayRef in TargetLowering functions.
Apr 13 2022, 1:35 AM · Restricted Project, Restricted Project
Miss_Grape requested review of D123661: [XCORE][CodeGen][NFC] Use ArrayRef in TargetLowering functions.
Apr 13 2022, 1:16 AM · Restricted Project, Restricted Project
Miss_Grape retitled D123656: [CodeGen] Use ArrayRef in TargetLowering functions from [NFC][CodeGen] Use ArrayRef in TargetLowering functions to [CodeGen] Use ArrayRef in TargetLowering functions.
Apr 13 2022, 1:11 AM · Restricted Project, Restricted Project
Miss_Grape added inline comments to D123656: [CodeGen] Use ArrayRef in TargetLowering functions.
Apr 13 2022, 12:42 AM · Restricted Project, Restricted Project
Miss_Grape updated the diff for D123656: [CodeGen] Use ArrayRef in TargetLowering functions.

Fix comment

Apr 13 2022, 12:41 AM · Restricted Project, Restricted Project
Miss_Grape retitled D123659: [MIPS][CodeGen][NFC] Use ArrayRef in TargetLowering functions from [NFC][MIPS][CodeGen] Use ArrayRef in TargetLowering functions to [MIPS][CodeGen][NFC] Use ArrayRef in TargetLowering functions.
Apr 13 2022, 12:35 AM · Restricted Project, Restricted Project
Miss_Grape requested review of D123659: [MIPS][CodeGen][NFC] Use ArrayRef in TargetLowering functions.
Apr 13 2022, 12:34 AM · Restricted Project, Restricted Project
Miss_Grape requested review of D123656: [CodeGen] Use ArrayRef in TargetLowering functions.
Apr 13 2022, 12:06 AM · Restricted Project, Restricted Project

Apr 12 2022

Miss_Grape updated the diff for D123577: [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI..

Add test

Apr 12 2022, 8:40 PM · Restricted Project, Restricted Project
Miss_Grape added a comment to D123181: [RISCV] [NFC] Refactor the type promotion of fsl/fsr/becompress/bdecompress/bfp.

LGTM, but please update the commit title since you also changed becompress, bdecompress and bfp.

Apr 12 2022, 7:48 PM · Restricted Project, Restricted Project
Miss_Grape retitled D123181: [RISCV] [NFC] Refactor the type promotion of fsl/fsr/becompress/bdecompress/bfp from [RISCV] Refactoring the type promotion process of instructions fsl/fsr to [RISCV] [NFC] Refactor the type promotion of fsl/fsr/becompress/bdecompress/bfp.
Apr 12 2022, 7:47 PM · Restricted Project, Restricted Project
Miss_Grape added inline comments to D123648: Restrict lvalue-to-rvalue conversions in CGExprConstant..
Apr 12 2022, 6:59 PM · Restricted Project, Restricted Project
Miss_Grape updated the diff for D123181: [RISCV] [NFC] Refactor the type promotion of fsl/fsr/becompress/bdecompress/bfp.

fix the comment

Apr 12 2022, 2:45 AM · Restricted Project, Restricted Project
Miss_Grape added a comment to D123577: [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI..

TODO: add test cases

Apr 12 2022, 2:18 AM · Restricted Project, Restricted Project
Miss_Grape requested review of D123577: [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI..
Apr 12 2022, 2:17 AM · Restricted Project, Restricted Project

Apr 11 2022

Miss_Grape updated the diff for D123486: [InstCombine] fold more constant remainder to select-of-constants remainder.
Apr 11 2022, 2:20 AM · Restricted Project, Restricted Project
Miss_Grape requested review of D123486: [InstCombine] fold more constant remainder to select-of-constants remainder.
Apr 11 2022, 12:37 AM · Restricted Project, Restricted Project
Miss_Grape added a comment to D123181: [RISCV] [NFC] Refactor the type promotion of fsl/fsr/becompress/bdecompress/bfp.

ping

Apr 11 2022, 12:33 AM · Restricted Project, Restricted Project

Apr 6 2022

Miss_Grape updated the diff for D122644: [RISCV] Add CMOV isel pattern for (select (setgt X, Imm), Y, Z).

Update the test case

Apr 6 2022, 8:44 PM · Restricted Project, Restricted Project