[RISCV] (and (not (srl X, C)), 1) to (sltiu (andi X, 2 << C), 1) when Zbs extension disable

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

384

This comment is duplicated from ImmPlus32.

llvm/test/CodeGen/RISCV/rv64zbs.ll

518

Shouldn't this be 128 not 256?

[craig.topper]

I just put up an alternative that gets the same codegen https://reviews.llvm.org/D122458 I did not limit to cases where Zbs is disabled. It needs more testing.

[Miss_Grape]

In D122454#3407237, @craig.topper wrote:

I just put up an alternative that gets the same codegen https://reviews.llvm.org/D122458 I did not limit to cases where Zbs is disabled. It needs more testing.

OK, I will discard this Merge Requst。

llvm/lib/Target/RISCV/RISCV.td

 
 def FeatureStdExtZba
     : SubtargetFeature<"zba", "HasStdExtZba", "true",
                        "'Zba' (Address Generation Instructions)">;
 def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
                              AssemblerPredicate<(all_of FeatureStdExtZba),
                              "'Zba' (Address Generation Instructions)">;
 def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
+def NotHasStdExtZbs : Predicate<"!Subtarget->hasStdExtZbs()">;
 
 def FeatureStdExtZbb
     : SubtargetFeature<"zbb", "HasStdExtZbb", "true",
                        "'Zbb' (Basic Bit-Manipulation)">;
 def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
                              AssemblerPredicate<(all_of FeatureStdExtZbb),
                              "'Zbb' (Basic Bit-Manipulation)">;
 

llvm/lib/Target/RISCV/RISCVInstrInfo.td

let MCOperandPredicate = [{
     if (STI.getTargetTriple().isArch64Bit())
       return isUInt<6>(Imm);
     return isUInt<5>(Imm);
   }];
   let OperandType = "OPERAND_UIMMLOG2XLEN";
   let OperandNamespace = "RISCVOp";
 }
 
+// A 6-bit constant greater than 32.
+def uimmlt11 : ImmLeaf<XLenVT, [{
+  if (Subtarget->is64Bit())
+      return isUInt<6>(Imm) && Imm < 11;
+  return isUInt<5>(Imm) && Imm < 11;
+}]>;
+
+
 def uimm2 : Operand<XLenVT> {
   let ParserMatchClass = UImmAsmOperand<2>;
   let DecoderMethod = "decodeUImmOperand<2>";
   let OperandType = "OPERAND_UIMM2";
   let OperandNamespace = "RISCVOp";
 }
 
 def uimm3 : Operand<XLenVT> {

 }]>;
 
 // Return an immediate value minus 32.
 def ImmSub32 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(N->getSExtValue() - 32, SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
 // Return an immediate value plus 32.
+def ImmPow2: SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(2 << (N->getSExtValue()), SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+// Return an immediate value plus 32.
 def ImmPlus32 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(N->getSExtValue() + 32, SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
 // Return an immediate subtracted from XLen.
 def ImmSubFromXLen : SDNodeXForm<imm, [{
   uint64_t XLen = Subtarget->getXLen();

 // This is a special case of the ADD instruction used to facilitate the use of a
 // fourth operand to emit a relocation on a symbol relating to this instruction.
 // The relocation does not affect any bits of the instruction itself but is used
 // as a hint to the linker.
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0 in
 def PseudoAddTPRel : Pseudo<(outs GPR:$rd),
                             (ins GPR:$rs1, GPR:$rs2, tprel_add_symbol:$src), [],
                             "add", "$rd, $rs1, $rs2, $src">;
+let Predicates = [NotHasStdExtZbs] in
+def : Pat<(and (not (srl GPR:$rs1, uimmlt11:$shamt)), (XLenVT 1)),
+          (SLTIU (ANDI GPR:$rs1, (ImmPow2 uimmlt11:$shamt)), (XLenVT 1))>;
 
 /// FrameIndex calculations
 
 def : Pat<(add (XLenVT AddrFI:$Rs), simm12:$imm12),
           (ADDI (XLenVT AddrFI:$Rs), simm12:$imm12)>;
 def : Pat<(IsOrAdd (XLenVT AddrFI:$Rs), simm12:$imm12),
           (ADDI (XLenVT AddrFI:$Rs), simm12:$imm12)>;
 

llvm/test/CodeGen/RISCV/rv32zbs.ll

; RV32ZBS-NEXT:    ret
   %shr = lshr i64 %a, 5
   %and = and i64 %shr, 1
   ret i64 %and
 }
 
 define i32 @bexti_xor_i32(i32 %a) nounwind {
 ; RV32I-LABEL: bexti_xor_i32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a0, a0, 7
-; RV32I-NEXT:    not a0, a0
-; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    andi a0, a0, 256
+; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBS-LABEL: bexti_xor_i32:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bexti a0, a0, 7
 ; RV32ZBS-NEXT:    xori a0, a0, 1
 ; RV32ZBS-NEXT:    ret
   %shr = lshr i32 %a, 7
   %not = xor i32 %shr, -1
   %and = and i32 %not, 1
   ret i32 %and
 }
 
-define i64 @bexti_xor_i64(i64 %a) nounwind {
-; RV32I-LABEL: bexti_xor_i64:
+define i32 @bexti_xor_i32_11(i32 %a) nounwind {
+; RV32I-LABEL: bexti_xor_i32_11:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a0, a0, 7
+; RV32I-NEXT:    srli a0, a0, 11
 ; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    ret
+;
+; RV32ZBS-LABEL: bexti_xor_i32_11:
+; RV32ZBS:       # %bb.0:
+; RV32ZBS-NEXT:    bexti a0, a0, 11
+; RV32ZBS-NEXT:    xori a0, a0, 1
+; RV32ZBS-NEXT:    ret
+  %shr = lshr i32 %a, 11
+  %not = xor i32 %shr, -1
+  %and = and i32 %not, 1
+  ret i32 %and
+}
+
+define i64 @bexti_xor_i64(i64 %a) nounwind {
+; RV32I-LABEL: bexti_xor_i64:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a0, a0, 256
+; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBS-LABEL: bexti_xor_i64:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bexti a0, a0, 7
 ; RV32ZBS-NEXT:    xori a0, a0, 1
 ; RV32ZBS-NEXT:    li a1, 0
 ; RV32ZBS-NEXT:    ret
   %shr = lshr i64 %a, 7
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
-define i32 @bexti_xor_i32_1(i32 %a) nounwind {
-; RV32I-LABEL: bexti_xor_i32_1:
+define i64 @bexti_xor_i64_11(i64 %a) nounwind {
+; RV32I-LABEL: bexti_xor_i64_11:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a0, a0, 7
+; RV32I-NEXT:    srli a0, a0, 11
 ; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    ret
+;
+; RV32ZBS-LABEL: bexti_xor_i64_11:
+; RV32ZBS:       # %bb.0:
+; RV32ZBS-NEXT:    bexti a0, a0, 11
+; RV32ZBS-NEXT:    xori a0, a0, 1
+; RV32ZBS-NEXT:    li a1, 0
+; RV32ZBS-NEXT:    ret
+  %shr = lshr i64 %a, 11
+  %not = xor i64 %shr, -1
+  %and = and i64 %not, 1
+  ret i64 %and
+}
+
+define i32 @bexti_xor_i32_1(i32 %a) nounwind {
+; RV32I-LABEL: bexti_xor_i32_1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a0, a0, 256
+; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBS-LABEL: bexti_xor_i32_1:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bexti a0, a0, 7
 ; RV32ZBS-NEXT:    xori a0, a0, 1
 ; RV32ZBS-NEXT:    ret
   %shr = lshr i32 %a, 7
   %and = and i32 %shr, 1
   %xor = xor i32 %and, 1
   ret i32 %xor
 }
 
 define i64 @bexti_xor_i64_1(i64 %a) nounwind {
 ; RV32I-LABEL: bexti_xor_i64_1:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a0, a0, 7
-; RV32I-NEXT:    not a0, a0
-; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    andi a0, a0, 256
+; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBS-LABEL: bexti_xor_i64_1:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bexti a0, a0, 7
 ; RV32ZBS-NEXT:    xori a0, a0, 1
 ; RV32ZBS-NEXT:    li a1, 0

llvm/test/CodeGen/RISCV/rv64zbs.ll

; RV64ZBS-NEXT:    ret
   %shr = lshr i64 %a, 5
   %and = and i64 %shr, 1
   ret i64 %and
 }
 
 define signext i32 @bexti_xor_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: bexti_xor_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a0, a0, 7
-; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    andi a0, a0, 256
+; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bexti_xor_i32:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bexti a0, a0, 7
 ; RV64ZBS-NEXT:    xori a0, a0, 1
 ; RV64ZBS-NEXT:    ret
   %shr = lshr i32 %a, 7
   %not = xor i32 %shr, -1
   %and = and i32 %not, 1
   ret i32 %and
 }
 
-define i64 @bexti_xor_i64(i64 %a) nounwind {
-; RV64I-LABEL: bexti_xor_i64:
+define signext i32 @bexti_xor_i32_11(i32 signext %a) nounwind {
+; RV64I-LABEL: bexti_xor_i32_11:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a0, a0, 7
+; RV64I-NEXT:    srli a0, a0, 11
 ; RV64I-NEXT:    not a0, a0
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    ret
 ;
+; RV64ZBS-LABEL: bexti_xor_i32_11:
+; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    bexti a0, a0, 11
+; RV64ZBS-NEXT:    xori a0, a0, 1
+; RV64ZBS-NEXT:    ret
+  %shr = lshr i32 %a, 11
+  %not = xor i32 %shr, -1
+  %and = and i32 %not, 1
+  ret i32 %and
+}
+
+define i64 @bexti_xor_i64(i64 %a) nounwind {
+; RV64I-LABEL: bexti_xor_i64:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a0, a0, 256
+; RV64I-NEXT:    seqz a0, a0
+; RV64I-NEXT:    ret
+;
 ; RV64ZBS-LABEL: bexti_xor_i64:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bexti a0, a0, 7
 ; RV64ZBS-NEXT:    xori a0, a0, 1
 ; RV64ZBS-NEXT:    ret
   %shr = lshr i64 %a, 7
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
-define signext i32 @bexti_xor_i32_1(i32 signext %a) nounwind {
-; RV64I-LABEL: bexti_xor_i32_1:
+define i64 @bexti_xor_i64_11(i64 %a) nounwind {
+; RV64I-LABEL: bexti_xor_i64_11:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a0, a0, 7
+; RV64I-NEXT:    srli a0, a0, 11
 ; RV64I-NEXT:    not a0, a0
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    ret
 ;
+; RV64ZBS-LABEL: bexti_xor_i64_11:
+; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    bexti a0, a0, 11
+; RV64ZBS-NEXT:    xori a0, a0, 1
+; RV64ZBS-NEXT:    ret
+  %shr = lshr i64 %a, 11
+  %not = xor i64 %shr, -1
+  %and = and i64 %not, 1
+  ret i64 %and
+}
+
+define signext i32 @bexti_xor_i32_1(i32 signext %a) nounwind {
+; RV64I-LABEL: bexti_xor_i32_1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a0, a0, 256
+; RV64I-NEXT:    seqz a0, a0
+; RV64I-NEXT:    ret
+;
 ; RV64ZBS-LABEL: bexti_xor_i32_1:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bexti a0, a0, 7
 ; RV64ZBS-NEXT:    xori a0, a0, 1
 ; RV64ZBS-NEXT:    ret
   %shr = lshr i32 %a, 7
   %and = and i32 %shr, 1
   %xor = xor i32 %and, 1
   ret i32 %xor
 }
 
 define i64 @bexti_xor_i64_1(i64 %a) nounwind {
 ; RV64I-LABEL: bexti_xor_i64_1:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a0, a0, 7
-; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    andi a0, a0, 256
+; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bexti_xor_i64_1:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bexti a0, a0, 7
 ; RV64ZBS-NEXT:    xori a0, a0, 1
 ; RV64ZBS-NEXT:    ret
   %shr = lshr i64 %a, 7