[RISCV][VP] Custom lower VP_STRIDED_LOAD and VP_STRIDED_STORE

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

476

Why do we need to Custom legalize the narrow scalar types? Shouldn't they be promoted by generic type legalization PromoteIntOp?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

6099

Should we be using INTRINSIC_W_CHAIN and intrinsic_riscv_vlse/vlse_mask similar to what we do for other VP load/store?

[loralb]

Changelog:

• Remove unnecessary custom legalization of narrow scalar types
• Do not add new RISCVISD nodes, use existing intrinsics instead

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll

146

Use poison instead of undef

[loralb]

Changelog:

• Address review comment

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll

26

This should have ".i32" on the end of the intrinsic name. Same for all of the intrinsics with i32 stride.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

484

Why do we need custom legalization for i32 on rv64? Shouldn't we have a generic PromoteIntOp for this?

[loralb]

Changelog:

• Address review comments

I added a new parent revision: D123112.

[loralb]

Changelog:

• Rebase

[craig.topper]

LGTM

[loralb]

I do not have commit rights, may I ask you to commit this for me? @craig.topper

[loralb]

Thanks @craig.topper!

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
   // FP to 32 bit int conversions for RV64. These are used to keep track of the
   // result being sign extended to 64 bit. These saturate out of range inputs.
   STRICT_FCVT_W_RV64 = ISD::FIRST_TARGET_STRICTFP_OPCODE,
   STRICT_FCVT_WU_RV64,
 
   // Memory opcodes start here.
   VLE_VL = ISD::FIRST_TARGET_MEMORY_OPCODE,
   VSE_VL,
+  VLSE_VL,
+  VSSE_VL,
 
   // WARNING: Do not add anything in the end unless you want the node to
   // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
   // opcodes will be thought as target memory ops!
 };
 } // namespace RISCVISD
 
 class RISCVTargetLowering : public TargetLowering {
private:
   SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
                                             SelectionDAG &DAG) const;
   SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
                             bool HasMask = true) const;
   SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc) const;
   SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG, unsigned MaskOpc,
                          unsigned VecOpc) const;
+  SDValue lowerVPStridedLoad(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerVPStridedStore(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
                                             unsigned ExtendOpc) const;
   SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
   SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
 

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.hasVInstructions()) {
     setOperationAction(ISD::VSCALE, XLenVT, Custom);
 
     // RVV intrinsics may have illegal operands.
     // We also need to custom legalize vmv.x.s.
     setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i8, Custom);
     setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom);
     setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
     setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i16, Custom);
+
+    setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_LOAD, MVT::i8, Custom);
+    setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_LOAD, MVT::i16, Custom);
+    setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_STORE, MVT::i8, Custom);
+    setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_STORE, MVT::i16, Custom);
+
     if (Subtarget.is64Bit()) {
       setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i32, Custom);
+
+      setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_LOAD, MVT::i32, Custom);
+      setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_STORE, MVT::i32, Custom);
     } else {
       setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
       setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
+
+      setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_LOAD, MVT::i64, Custom);
+      setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_STORE, MVT::i64, Custom);
     }
 
     setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
     setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
 
     static const unsigned IntegerVPOps[] = {
         ISD::VP_ADD,         ISD::VP_SUB,         ISD::VP_MUL,
         ISD::VP_SDIV,        ISD::VP_UDIV,        ISD::VP_SREM,
for (MVT VT : IntVecVTs) {
 
       setOperationAction(ISD::MLOAD, VT, Custom);
       setOperationAction(ISD::MSTORE, VT, Custom);
       setOperationAction(ISD::MGATHER, VT, Custom);
       setOperationAction(ISD::MSCATTER, VT, Custom);
 
       setOperationAction(ISD::VP_LOAD, VT, Custom);
       setOperationAction(ISD::VP_STORE, VT, Custom);
+      setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_LOAD, VT, Custom);
+      setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_STORE, VT, Custom);
       setOperationAction(ISD::VP_GATHER, VT, Custom);
       setOperationAction(ISD::VP_SCATTER, VT, Custom);
 
       setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
       setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
       setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
 
       setOperationAction(ISD::SELECT, VT, Custom);
const auto SetCommonVFPActions = [&](MVT VT) {
 
       setOperationAction(ISD::MLOAD, VT, Custom);
       setOperationAction(ISD::MSTORE, VT, Custom);
       setOperationAction(ISD::MGATHER, VT, Custom);
       setOperationAction(ISD::MSCATTER, VT, Custom);
 
       setOperationAction(ISD::VP_LOAD, VT, Custom);
       setOperationAction(ISD::VP_STORE, VT, Custom);
+      setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_LOAD, VT, Custom);
+      setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_STORE, VT, Custom);
       setOperationAction(ISD::VP_GATHER, VT, Custom);
       setOperationAction(ISD::VP_SCATTER, VT, Custom);
 
       setOperationAction(ISD::SELECT, VT, Custom);
       setOperationAction(ISD::SELECT_CC, VT, Expand);
 
       setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
       setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
if (Subtarget.useRVVForFixedLengthVectors()) {
 
         setOperationAction(ISD::MLOAD, VT, Custom);
         setOperationAction(ISD::MSTORE, VT, Custom);
         setOperationAction(ISD::MGATHER, VT, Custom);
         setOperationAction(ISD::MSCATTER, VT, Custom);
 
         setOperationAction(ISD::VP_LOAD, VT, Custom);
         setOperationAction(ISD::VP_STORE, VT, Custom);
+        setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_LOAD, VT, Custom);
+        setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_STORE, VT, Custom);
         setOperationAction(ISD::VP_GATHER, VT, Custom);
         setOperationAction(ISD::VP_SCATTER, VT, Custom);
 
         setOperationAction(ISD::ADD, VT, Custom);
         setOperationAction(ISD::MUL, VT, Custom);
         setOperationAction(ISD::SUB, VT, Custom);
         setOperationAction(ISD::AND, VT, Custom);
         setOperationAction(ISD::OR, VT, Custom);
if (Subtarget.useRVVForFixedLengthVectors()) {
         setOperationAction(ISD::STORE, VT, Custom);
         setOperationAction(ISD::MLOAD, VT, Custom);
         setOperationAction(ISD::MSTORE, VT, Custom);
         setOperationAction(ISD::MGATHER, VT, Custom);
         setOperationAction(ISD::MSCATTER, VT, Custom);
 
         setOperationAction(ISD::VP_LOAD, VT, Custom);
         setOperationAction(ISD::VP_STORE, VT, Custom);
+        setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_LOAD, VT, Custom);
+        setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_STORE, VT, Custom);
         setOperationAction(ISD::VP_GATHER, VT, Custom);
         setOperationAction(ISD::VP_SCATTER, VT, Custom);
 
         setOperationAction(ISD::FADD, VT, Custom);
         setOperationAction(ISD::FSUB, VT, Custom);
         setOperationAction(ISD::FMUL, VT, Custom);
         setOperationAction(ISD::FDIV, VT, Custom);
         setOperationAction(ISD::FNEG, VT, Custom);
SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::VP_FMUL:
     return lowerVPOp(Op, DAG, RISCVISD::FMUL_VL);
   case ISD::VP_FDIV:
     return lowerVPOp(Op, DAG, RISCVISD::FDIV_VL);
   case ISD::VP_FNEG:
     return lowerVPOp(Op, DAG, RISCVISD::FNEG_VL);
   case ISD::VP_FMA:
     return lowerVPOp(Op, DAG, RISCVISD::FMA_VL);
+  case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
+    return lowerVPStridedLoad(Op, DAG);
+  case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
+    return lowerVPStridedStore(Op, DAG);
   }
 }
 
 static SDValue getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty,
                              SelectionDAG &DAG, unsigned Flags) {
   return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
 }
 
SDValue RISCVTargetLowering::lowerLogicVPOp(SDValue Op, SelectionDAG &DAG,
 
   SDLoc DL(Op);
   SDValue Val = DAG.getNode(MaskOpc, DL, ContainerVT, Op1, Op2, VL);
   if (!IsFixed)
     return Val;
   return convertFromScalableVector(VT, Val, DAG, Subtarget);
 }
 
+SDValue RISCVTargetLowering::lowerVPStridedLoad(SDValue Op,
+                                                SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  MVT VT = Op.getSimpleValueType();
+  MVT ContainerVT = VT;
+  if (VT.isFixedLengthVector())
+    ContainerVT = getContainerForFixedLengthVector(VT);
+
+  SDVTList VTs = DAG.getVTList({ContainerVT, MVT::Other});
+  auto *VPNode = cast<VPStridedLoadSDNode>(Op);
+  // Check that the Stride type is legal
+  SDValue Stride =
+      DAG.getSExtOrTrunc(VPNode->getStride(), DL, Subtarget.getXLenVT());
+  SDValue Mask = VPNode->getMask();
+  if (VT.isFixedLengthVector()) {
+    MVT MaskVT = ContainerVT.changeVectorElementType(MVT::i1);
+    Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget);
+  }
+  SDValue Result =
+      DAG.getMemIntrinsicNode(RISCVISD::VLSE_VL, DL, VTs,
+                              {VPNode->getChain(), VPNode->getBasePtr(), Stride,
+                               Mask, VPNode->getVectorLength()},
+                              VPNode->getMemoryVT(), VPNode->getMemOperand());
+
+  if (VT.isFixedLengthVector())
+    Result = convertFromScalableVector(VT, Result, DAG, Subtarget);
+
+  return DAG.getMergeValues({Result, VPNode->getChain()}, DL);
+}
+
+SDValue RISCVTargetLowering::lowerVPStridedStore(SDValue Op,
+                                                 SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  auto *VPNode = cast<VPStridedStoreSDNode>(Op);
+  SDValue StoreVal = VPNode->getValue();
+  SDValue Mask = VPNode->getMask();
+  MVT VT = StoreVal.getSimpleValueType();
+  MVT ContainerVT = VT;
+  if (VT.isFixedLengthVector()) {
+    ContainerVT = getContainerForFixedLengthVector(VT);
+    StoreVal = convertToScalableVector(ContainerVT, StoreVal, DAG, Subtarget);
+    MVT MaskVT = ContainerVT.changeVectorElementType(MVT::i1);
+    Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget);
+  }
+
+  // Check that the Stride type is legal
+  SDValue Stride =
+      DAG.getSExtOrTrunc(VPNode->getStride(), DL, Subtarget.getXLenVT());
+  return DAG.getMemIntrinsicNode(
+      RISCVISD::VSSE_VL, DL, DAG.getVTList(MVT::Other),
+      {VPNode->getChain(), StoreVal, VPNode->getBasePtr(), Stride, Mask,
+       VPNode->getVectorLength()},
+      VPNode->getMemoryVT(), VPNode->getMemOperand());
+}
+
 // Custom lower MGATHER/VP_GATHER to a legalized form for RVV. It will then be
 // matched to a RVV indexed load. The RVV indexed load instructions only
 // support the "unsigned unscaled" addressing mode; indices are implicitly
 // zero-extended or truncated to XLEN and are treated as byte offsets. Any
 // signed or scaled indexing is extended to the XLEN value type and scaled
 // accordingly.
 SDValue RISCVTargetLowering::lowerMaskedGather(SDValue Op,
                                                SelectionDAG &DAG) const {
#define NODE_NAME_CASE(NODE)                                                   \
   NODE_NAME_CASE(VRGATHER_VX_VL)
   NODE_NAME_CASE(VRGATHER_VV_VL)
   NODE_NAME_CASE(VRGATHEREI16_VV_VL)
   NODE_NAME_CASE(VSEXT_VL)
   NODE_NAME_CASE(VZEXT_VL)
   NODE_NAME_CASE(VCPOP_VL)
   NODE_NAME_CASE(VLE_VL)
   NODE_NAME_CASE(VSE_VL)
+  NODE_NAME_CASE(VLSE_VL)
+  NODE_NAME_CASE(VSSE_VL)
   NODE_NAME_CASE(READ_CSR)
   NODE_NAME_CASE(WRITE_CSR)
   NODE_NAME_CASE(SWAP_CSR)
   }
   // clang-format on
   return nullptr;
 #undef NODE_NAME_CASE
 }

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

 //===----------------------------------------------------------------------===//
 // Helpers to define the VL patterns.
 //===----------------------------------------------------------------------===//
 
 def SDT_RISCVVLE_VL : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisPtrTy<1>,
                                            SDTCisVT<2, XLenVT>]>;
 def SDT_RISCVVSE_VL : SDTypeProfile<0, 3, [SDTCisVec<0>, SDTCisPtrTy<1>,
                                            SDTCisVT<2, XLenVT>]>;
+def SDT_RISCVVLSE_VL : SDTypeProfile<1, 4, [SDTCisVec<0>,
+                                           SDTCisPtrTy<1>,
+                                           SDTCisInt<2>,
+                                           SDTCVecEltisVT<3, i1>,
+                                           SDTCisSameNumEltsAs<0, 3>,
+                                           SDTCisVT<4, XLenVT>]>;
+def SDT_RISCVVSSE_VL : SDTypeProfile<0, 5, [SDTCisVec<0>,
+                                           SDTCisPtrTy<1>,
+                                           SDTCisInt<2>,
+                                           SDTCVecEltisVT<3, i1>,
+                                           SDTCisSameNumEltsAs<0, 3>,
+                                           SDTCisVT<4, XLenVT>]>;
 
 def SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
                                                 SDTCisSameAs<0, 2>,
                                                 SDTCisVec<0>, SDTCisInt<0>,
                                                 SDTCVecEltisVT<3, i1>,
                                                 SDTCisSameNumEltsAs<0, 3>,
                                                 SDTCisVT<4, XLenVT>]>;
 
def riscv_vfmv_s_f_vl : SDNode<"RISCVISD::VFMV_S_F_VL",
                                                     SDTCisFP<0>,
                                                     SDTCisEltOfVec<2, 0>,
                                                     SDTCisVT<3, XLenVT>]>>;
 
 def riscv_vle_vl : SDNode<"RISCVISD::VLE_VL", SDT_RISCVVLE_VL,
                           [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def riscv_vse_vl : SDNode<"RISCVISD::VSE_VL", SDT_RISCVVSE_VL,
                           [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
+def riscv_vlse_vl : SDNode<"RISCVISD::VLSE_VL", SDT_RISCVVLSE_VL,
+                          [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+def riscv_vsse_vl : SDNode<"RISCVISD::VSSE_VL", SDT_RISCVVSSE_VL,
+                          [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
 def riscv_add_vl   : SDNode<"RISCVISD::ADD_VL",   SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
 def riscv_sub_vl   : SDNode<"RISCVISD::SUB_VL",   SDT_RISCVIntBinOp_VL>;
 def riscv_mul_vl   : SDNode<"RISCVISD::MUL_VL",   SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
 def riscv_mulhs_vl : SDNode<"RISCVISD::MULHS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
 def riscv_mulhu_vl : SDNode<"RISCVISD::MULHU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
 def riscv_and_vl   : SDNode<"RISCVISD::AND_VL",   SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
 def riscv_or_vl    : SDNode<"RISCVISD::OR_VL",    SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
foreach mti = AllMasks in {
   defvar store_instr = !cast<Instruction>("PseudoVSM_V_"#mti.BX);
   def : Pat<(mti.Mask (riscv_vle_vl BaseAddr:$rs1, VLOpFrag)),
             (load_instr BaseAddr:$rs1, GPR:$vl, mti.Log2SEW)>;
   def : Pat<(riscv_vse_vl (mti.Mask VR:$rs2), BaseAddr:$rs1,
                           VLOpFrag),
             (store_instr VR:$rs2, BaseAddr:$rs1, GPR:$vl, mti.Log2SEW)>;
 }
 
+// Vector Strided Instructions
+foreach vti = AllVectors in {
+  defvar load_instr = !cast<Instruction>("PseudoVLSE"#vti.SEW#"_V_"#vti.LMul.MX);
+  defvar load_instr_masked = !cast<Instruction>("PseudoVLSE"#vti.SEW#"_V_"#vti.LMul.MX#"_MASK");
+  defvar store_instr = !cast<Instruction>("PseudoVSSE"#vti.SEW#"_V_"#vti.LMul.MX);
+  defvar store_instr_masked = !cast<Instruction>("PseudoVSSE"#vti.SEW#"_V_"#vti.LMul.MX#"_MASK");
+
+  // Load
+  def : Pat<(vti.Vector (riscv_vlse_vl BaseAddr:$rs1,
+                                      GPR:$rs2,
+                                      (vti.Mask true_mask),
+                                      VLOpFrag)),
+            (load_instr BaseAddr:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
+  def : Pat<(vti.Vector (riscv_vlse_vl BaseAddr:$rs1,
+                                      GPR:$rs2,
+                                      (vti.Mask V0),
+                                      VLOpFrag)),
+            (load_instr_masked (vti.Vector (IMPLICIT_DEF)), BaseAddr:$rs1, GPR:$rs2,
+                               (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
+
+  // Store
+  def : Pat<(riscv_vsse_vl (vti.Vector vti.RegClass:$rs2),
+                          BaseAddr:$rs1,
+                          GPR:$rs3,
+                          (vti.Mask true_mask),
+                          VLOpFrag),
+            (store_instr vti.RegClass:$rs2, BaseAddr:$rs1,
+                         GPR:$rs3, GPR:$vl, vti.Log2SEW)>;
+  def : Pat<(riscv_vsse_vl (vti.Vector vti.RegClass:$rs2),
+                          BaseAddr:$rs1,
+                          GPR:$rs3,
+                          (vti.Mask V0),
+                          VLOpFrag),
+            (store_instr_masked vti.RegClass:$rs2, BaseAddr:$rs1, GPR:$rs3,
+                                (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
+}
+
 // 12.1. Vector Single-Width Integer Add and Subtract
 defm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">;
 defm : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">;
 // Handle VRSUB specially since it's the only integer binary op with reversed
 // pattern operands
 foreach vti = AllIntegerVectors in {
   def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))),
                           (vti.Vector vti.RegClass:$rs1), (vti.Mask V0),

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+v -riscv-v-vector-bits-min=128 \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-RV32
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+v -riscv-v-vector-bits-min=128 \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-RV64
+
+declare <2 x i8> @llvm.experimental.vp.strided.load.v2i8.i64(i8*, i64, <2 x i1>, i32)
+
+define <2 x i8> @strided_vpload_v2i8_i64(i8* %ptr, i64 %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v2i8_i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a3, e8, mf8, ta, mu
+; CHECK-RV32-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v2i8_i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV64-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8.i64(i8* %ptr, i64 %stride, <2 x i1> %m, i32 %evl)
+  ret <2 x i8> %load
+}
+
+declare <2 x i8> @llvm.experimental.vp.strided.load.v2i8(i8*, i32, <2 x i1>, i32)
+
+define <2 x i8> @strided_vpload_v2i8(i8* %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v2i8:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV32-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v2i8:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV64-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8(i8* %ptr, i32 %stride, <2 x i1> %m, i32 %evl)
+  ret <2 x i8> %load
+}
+
+declare <4 x i8> @llvm.experimental.vp.strided.load.v4i8(i8*, i32, <4 x i1>, i32)
+
+define <4 x i8> @strided_vpload_v4i8(i8* %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v4i8:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf4, ta, mu
+; CHECK-RV32-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v4i8:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf4, ta, mu
+; CHECK-RV64-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <4 x i8> @llvm.experimental.vp.strided.load.v4i8(i8* %ptr, i32 %stride, <4 x i1> %m, i32 %evl)
+  ret <4 x i8> %load
+}
+
+define <4 x i8> @strided_vpload_v4i8_allones_mask(i8* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v4i8_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf4, ta, mu
+; CHECK-RV32-NEXT:    vlse8.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v4i8_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf4, ta, mu
+; CHECK-RV64-NEXT:    vlse8.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <4 x i1> undef, i1 true, i32 0
+  %b = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> zeroinitializer
+  %load = call <4 x i8> @llvm.experimental.vp.strided.load.v4i8(i8* %ptr, i32 %stride, <4 x i1> %b, i32 %evl)
+  ret <4 x i8> %load
+}
+
+declare <8 x i8> @llvm.experimental.vp.strided.load.v8i8(i8*, i32, <8 x i1>, i32)
+
+define <8 x i8> @strided_vpload_v8i8(i8* %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v8i8:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf2, ta, mu
+; CHECK-RV32-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v8i8:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf2, ta, mu
+; CHECK-RV64-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <8 x i8> @llvm.experimental.vp.strided.load.v8i8(i8* %ptr, i32 %stride, <8 x i1> %m, i32 %evl)
+  ret <8 x i8> %load
+}
+
+declare <2 x i16> @llvm.experimental.vp.strided.load.v2i16(i16*, i32, <2 x i1>, i32)
+
+define <2 x i16> @strided_vpload_v2i16(i16* %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v2i16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v2i16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <2 x i16> @llvm.experimental.vp.strided.load.v2i16(i16* %ptr, i32 %stride, <2 x i1> %m, i32 %evl)
+  ret <2 x i16> %load
+}
+
+declare <4 x i16> @llvm.experimental.vp.strided.load.v4i16(i16*, i32, <4 x i1>, i32)
+
+define <4 x i16> @strided_vpload_v4i16(i16* %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v4i16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v4i16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <4 x i16> @llvm.experimental.vp.strided.load.v4i16(i16* %ptr, i32 %stride, <4 x i1> %m, i32 %evl)
+  ret <4 x i16> %load
+}
+
+declare <8 x i16> @llvm.experimental.vp.strided.load.v8i16(i16*, i32, <8 x i1>, i32)
+
+define <8 x i16> @strided_vpload_v8i16(i16* %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v8i16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v8i16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <8 x i16> @llvm.experimental.vp.strided.load.v8i16(i16* %ptr, i32 %stride, <8 x i1> %m, i32 %evl)
+  ret <8 x i16> %load
+}
+
+define <8 x i16> @strided_vpload_v8i16_allones_mask(i16* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v8i16_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v8i16_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <8 x i1> undef, i1 true, i32 0
+  %b = shufflevector <8 x i1> %a, <8 x i1> poison, <8 x i32> zeroinitializer
+  %load = call <8 x i16> @llvm.experimental.vp.strided.load.v8i16(i16* %ptr, i32 %stride, <8 x i1> %b, i32 %evl)
+  ret <8 x i16> %load
+}
+
+declare <2 x i32> @llvm.experimental.vp.strided.load.v2i32(i32*, i32, <2 x i1>, i32)
+
+define <2 x i32> @strided_vpload_v2i32(i32* %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v2i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v2i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <2 x i32> @llvm.experimental.vp.strided.load.v2i32(i32* %ptr, i32 %stride, <2 x i1> %m, i32 %evl)
+  ret <2 x i32> %load
+}
+
+declare <4 x i32> @llvm.experimental.vp.strided.load.v4i32(i32*, i32, <4 x i1>, i32)
+
+define <4 x i32> @strided_vpload_v4i32(i32* %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v4i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v4i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <4 x i32> @llvm.experimental.vp.strided.load.v4i32(i32* %ptr, i32 %stride, <4 x i1> %m, i32 %evl)
+  ret <4 x i32> %load
+}
+
+declare <8 x i32> @llvm.experimental.vp.strided.load.v8i32(i32*, i32, <8 x i1>, i32)
+
+define <8 x i32> @strided_vpload_v8i32(i32* %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v8i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v8i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <8 x i32> @llvm.experimental.vp.strided.load.v8i32(i32* %ptr, i32 %stride, <8 x i1> %m, i32 %evl)
+  ret <8 x i32> %load
+}
+
+define <8 x i32> @strided_vpload_v8i32_allones_mask(i32* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v8i32_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v8i32_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <8 x i1> undef, i1 true, i32 0
+  %b = shufflevector <8 x i1> %a, <8 x i1> poison, <8 x i32> zeroinitializer
+  %load = call <8 x i32> @llvm.experimental.vp.strided.load.v8i32(i32* %ptr, i32 %stride, <8 x i1> %b, i32 %evl)
+  ret <8 x i32> %load
+}
+
+declare <2 x i64> @llvm.experimental.vp.strided.load.v2i64(i64*, i32, <2 x i1>, i32)
+
+define <2 x i64> @strided_vpload_v2i64(i64* %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v2i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v2i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <2 x i64> @llvm.experimental.vp.strided.load.v2i64(i64* %ptr, i32 %stride, <2 x i1> %m, i32 %evl)
+  ret <2 x i64> %load
+}
+
+declare <4 x i64> @llvm.experimental.vp.strided.load.v4i64(i64*, i32, <4 x i1>, i32)
+
+define <4 x i64> @strided_vpload_v4i64(i64* %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v4i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v4i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <4 x i64> @llvm.experimental.vp.strided.load.v4i64(i64* %ptr, i32 %stride, <4 x i1> %m, i32 %evl)
+  ret <4 x i64> %load
+}
+
+define <4 x i64> @strided_vpload_v4i64_allones_mask(i64* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v4i64_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v4i64_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <4 x i1> undef, i1 true, i32 0
+  %b = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> zeroinitializer
+  %load = call <4 x i64> @llvm.experimental.vp.strided.load.v4i64(i64* %ptr, i32 %stride, <4 x i1> %b, i32 %evl)
+  ret <4 x i64> %load
+}
+
+declare <8 x i64> @llvm.experimental.vp.strided.load.v8i64(i64*, i32, <8 x i1>, i32)
+
+define <8 x i64> @strided_vpload_v8i64(i64* %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v8i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v8i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <8 x i64> @llvm.experimental.vp.strided.load.v8i64(i64* %ptr, i32 %stride, <8 x i1> %m, i32 %evl)
+  ret <8 x i64> %load
+}
+
+declare <2 x half> @llvm.experimental.vp.strided.load.v2f16(half*, i32, <2 x i1>, i32)
+
+define <2 x half> @strided_vpload_v2f16(half* %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v2f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v2f16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <2 x half> @llvm.experimental.vp.strided.load.v2f16(half* %ptr, i32 %stride, <2 x i1> %m, i32 %evl)
+  ret <2 x half> %load
+}
+
+define <2 x half> @strided_vpload_v2f16_allones_mask(half* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v2f16_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v2f16_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <2 x i1> undef, i1 true, i32 0
+  %b = shufflevector <2 x i1> %a, <2 x i1> poison, <2 x i32> zeroinitializer
+  %load = call <2 x half> @llvm.experimental.vp.strided.load.v2f16(half* %ptr, i32 %stride, <2 x i1> %b, i32 %evl)
+  ret <2 x half> %load
+}
+
+declare <4 x half> @llvm.experimental.vp.strided.load.v4f16(half*, i32, <4 x i1>, i32)
+
+define <4 x half> @strided_vpload_v4f16(half* %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v4f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v4f16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <4 x half> @llvm.experimental.vp.strided.load.v4f16(half* %ptr, i32 %stride, <4 x i1> %m, i32 %evl)
+  ret <4 x half> %load
+}
+
+declare <8 x half> @llvm.experimental.vp.strided.load.v8f16(half*, i32, <8 x i1>, i32)
+
+define <8 x half> @strided_vpload_v8f16(half* %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v8f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v8f16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <8 x half> @llvm.experimental.vp.strided.load.v8f16(half* %ptr, i32 %stride, <8 x i1> %m, i32 %evl)
+  ret <8 x half> %load
+}
+
+declare <2 x float> @llvm.experimental.vp.strided.load.v2f32(float*, i32, <2 x i1>, i32)
+
+define <2 x float> @strided_vpload_v2f32(float* %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v2f32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v2f32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <2 x float> @llvm.experimental.vp.strided.load.v2f32(float* %ptr, i32 %stride, <2 x i1> %m, i32 %evl)
+  ret <2 x float> %load
+}
+
+declare <4 x float> @llvm.experimental.vp.strided.load.v4f32(float*, i32, <4 x i1>, i32)
+
+define <4 x float> @strided_vpload_v4f32(float* %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v4f32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v4f32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <4 x float> @llvm.experimental.vp.strided.load.v4f32(float* %ptr, i32 %stride, <4 x i1> %m, i32 %evl)
+  ret <4 x float> %load
+}
+
+declare <8 x float> @llvm.experimental.vp.strided.load.v8f32(float*, i32, <8 x i1>, i32)
+
+define <8 x float> @strided_vpload_v8f32(float* %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v8f32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v8f32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <8 x float> @llvm.experimental.vp.strided.load.v8f32(float* %ptr, i32 %stride, <8 x i1> %m, i32 %evl)
+  ret <8 x float> %load
+}
+
+define <8 x float> @strided_vpload_v8f32_allones_mask(float* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v8f32_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v8f32_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <8 x i1> undef, i1 true, i32 0
+  %b = shufflevector <8 x i1> %a, <8 x i1> poison, <8 x i32> zeroinitializer
+  %load = call <8 x float> @llvm.experimental.vp.strided.load.v8f32(float* %ptr, i32 %stride, <8 x i1> %b, i32 %evl)
+  ret <8 x float> %load
+}
+
+declare <2 x double> @llvm.experimental.vp.strided.load.v2f64(double*, i32, <2 x i1>, i32)
+
+define <2 x double> @strided_vpload_v2f64(double* %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v2f64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v2f64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <2 x double> @llvm.experimental.vp.strided.load.v2f64(double* %ptr, i32 %stride, <2 x i1> %m, i32 %evl)
+  ret <2 x double> %load
+}
+
+declare <4 x double> @llvm.experimental.vp.strided.load.v4f64(double*, i32, <4 x i1>, i32)
+
+define <4 x double> @strided_vpload_v4f64(double* %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v4f64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v4f64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <4 x double> @llvm.experimental.vp.strided.load.v4f64(double* %ptr, i32 %stride, <4 x i1> %m, i32 %evl)
+  ret <4 x double> %load
+}
+
+define <4 x double> @strided_vpload_v4f64_allones_mask(double* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v4f64_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v4f64_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <4 x i1> undef, i1 true, i32 0
+  %b = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> zeroinitializer
+  %load = call <4 x double> @llvm.experimental.vp.strided.load.v4f64(double* %ptr, i32 %stride, <4 x i1> %b, i32 %evl)
+  ret <4 x double> %load
+}
+
+declare <8 x double> @llvm.experimental.vp.strided.load.v8f64(double*, i32, <8 x i1>, i32)
+
+define <8 x double> @strided_vpload_v8f64(double* %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_v8f64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_v8f64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <8 x double> @llvm.experimental.vp.strided.load.v8f64(double* %ptr, i32 %stride, <8 x i1> %m, i32 %evl)
+  ret <8 x double> %load
+}

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+v -riscv-v-vector-bits-min=128 \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-RV32
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+v -riscv-v-vector-bits-min=128 \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-RV64
+
+declare void @llvm.experimental.vp.strided.store.v2i8.i64(<2 x i8>, i8*, i64, <2 x i1>, i32)
+
+define void @strided_vpstore_v2i8_i64(<2 x i8> %val, i8* %ptr, i64 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v2i8_i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a3, e8, mf8, ta, mu
+; CHECK-RV32-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v2i8_i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV64-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v2i8.i64(<2 x i8> %val, i8* %ptr, i64 %stride, <2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v2i8(<2 x i8>, i8*, i32, <2 x i1>, i32)
+
+define void @strided_vpstore_v2i8(<2 x i8> %val, i8* %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v2i8:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV32-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v2i8:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV64-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v2i8(<2 x i8> %val, i8* %ptr, i32 %stride, <2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v4i8(<4 x i8>, i8*, i32, <4 x i1>, i32)
+
+define void @strided_vpstore_v4i8(<4 x i8> %val, i8* %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v4i8:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf4, ta, mu
+; CHECK-RV32-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v4i8:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf4, ta, mu
+; CHECK-RV64-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v4i8(<4 x i8> %val, i8* %ptr, i32 %stride, <4 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v8i8(<8 x i8>, i8*, i32, <8 x i1>, i32)
+
+define void @strided_vpstore_v8i8(<8 x i8> %val, i8* %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v8i8:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf2, ta, mu
+; CHECK-RV32-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v8i8:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf2, ta, mu
+; CHECK-RV64-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v8i8(<8 x i8> %val, i8* %ptr, i32 %stride, <8 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v2i16(<2 x i16>, i16*, i32, <2 x i1>, i32)
+
+define void @strided_vpstore_v2i16(<2 x i16> %val, i16* %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v2i16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV32-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v2i16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV64-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v2i16(<2 x i16> %val, i16* %ptr, i32 %stride, <2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v4i16(<4 x i16>, i16*, i32, <4 x i1>, i32)
+
+define void @strided_vpstore_v4i16(<4 x i16> %val, i16* %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v4i16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV32-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v4i16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV64-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v4i16(<4 x i16> %val, i16* %ptr, i32 %stride, <4 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v8i16(<8 x i16>, i16*, i32, <8 x i1>, i32)
+
+define void @strided_vpstore_v8i16(<8 x i16> %val, i16* %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v8i16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV32-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v8i16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV64-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v8i16(<8 x i16> %val, i16* %ptr, i32 %stride, <8 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v2i32(<2 x i32>, i32*, i32, <2 x i1>, i32)
+
+define void @strided_vpstore_v2i32(<2 x i32> %val, i32* %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v2i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV32-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v2i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV64-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v2i32(<2 x i32> %val, i32* %ptr, i32 %stride, <2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v4i32(<4 x i32>, i32*, i32, <4 x i1>, i32)
+
+define void @strided_vpstore_v4i32(<4 x i32> %val, i32* %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v4i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV32-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v4i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV64-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v4i32(<4 x i32> %val, i32* %ptr, i32 %stride, <4 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v8i32(<8 x i32>, i32*, i32, <8 x i1>, i32)
+
+define void @strided_vpstore_v8i32(<8 x i32> %val, i32* %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v8i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV32-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v8i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV64-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v8i32(<8 x i32> %val, i32* %ptr, i32 %stride, <8 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v2i64(<2 x i64>, i64*, i32, <2 x i1>, i32)
+
+define void @strided_vpstore_v2i64(<2 x i64> %val, i64* %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v2i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV32-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v2i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV64-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v2i64(<2 x i64> %val, i64* %ptr, i32 %stride, <2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v4i64(<4 x i64>, i64*, i32, <4 x i1>, i32)
+
+define void @strided_vpstore_v4i64(<4 x i64> %val, i64* %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v4i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV32-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v4i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV64-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v4i64(<4 x i64> %val, i64* %ptr, i32 %stride, <4 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v8i64(<8 x i64>, i64*, i32, <8 x i1>, i32)
+
+define void @strided_vpstore_v8i64(<8 x i64> %val, i64* %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v8i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV32-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v8i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV64-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v8i64(<8 x i64> %val, i64* %ptr, i32 %stride, <8 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v2f16(<2 x half>, half*, i32, <2 x i1>, i32)
+
+define void @strided_vpstore_v2f16(<2 x half> %val, half* %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v2f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV32-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v2f16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV64-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v2f16(<2 x half> %val, half* %ptr, i32 %stride, <2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v4f16(<4 x half>, half*, i32, <4 x i1>, i32)
+
+define void @strided_vpstore_v4f16(<4 x half> %val, half* %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v4f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV32-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v4f16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV64-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v4f16(<4 x half> %val, half* %ptr, i32 %stride, <4 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v8f16(<8 x half>, half*, i32, <8 x i1>, i32)
+
+define void @strided_vpstore_v8f16(<8 x half> %val, half* %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v8f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV32-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v8f16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV64-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v8f16(<8 x half> %val, half* %ptr, i32 %stride, <8 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v2f32(<2 x float>, float*, i32, <2 x i1>, i32)
+
+define void @strided_vpstore_v2f32(<2 x float> %val, float* %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v2f32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV32-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v2f32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV64-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v2f32(<2 x float> %val, float* %ptr, i32 %stride, <2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v4f32(<4 x float>, float*, i32, <4 x i1>, i32)
+
+define void @strided_vpstore_v4f32(<4 x float> %val, float* %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v4f32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV32-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v4f32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV64-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v4f32(<4 x float> %val, float* %ptr, i32 %stride, <4 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v8f32(<8 x float>, float*, i32, <8 x i1>, i32)
+
+define void @strided_vpstore_v8f32(<8 x float> %val, float* %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v8f32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV32-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v8f32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV64-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v8f32(<8 x float> %val, float* %ptr, i32 %stride, <8 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v2f64(<2 x double>, double*, i32, <2 x i1>, i32)
+
+define void @strided_vpstore_v2f64(<2 x double> %val, double* %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v2f64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV32-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v2f64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV64-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v2f64(<2 x double> %val, double* %ptr, i32 %stride, <2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v4f64(<4 x double>, double*, i32, <4 x i1>, i32)
+
+define void @strided_vpstore_v4f64(<4 x double> %val, double* %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v4f64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV32-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v4f64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV64-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v4f64(<4 x double> %val, double* %ptr, i32 %stride, <4 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.v8f64(<8 x double>, double*, i32, <8 x i1>, i32)
+
+define void @strided_vpstore_v8f64(<8 x double> %val, double* %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v8f64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV32-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v8f64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV64-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.v8f64(<8 x double> %val, double* %ptr, i32 %stride, <8 x i1> %m, i32 %evl)
+  ret void
+}
+
+define void @strided_vpstore_v2i8_allones_mask(<2 x i8> %val, i8* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_v2i8_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV32-NEXT:    vsse8.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_v2i8_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV64-NEXT:    vsse8.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <2 x i1> undef, i1 true, i32 0
+  %b = shufflevector <2 x i1> %a, <2 x i1> poison, <2 x i32> zeroinitializer
+  call void @llvm.experimental.vp.strided.store.v2i8(<2 x i8> %val, i8* %ptr, i32 %stride, <2 x i1> %b, i32 %evl)
+  ret void
+}

llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+v \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-RV32
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+v \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-RV64
+
+declare <vscale x 1 x i8> @llvm.experimental.vp.strided.load.nxv1i8.i64(i8*, i64, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x i8> @strided_vpload_nxv1i8_i64(i8* %ptr, i64 %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv1i8_i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a3, e8, mf8, ta, mu
+; CHECK-RV32-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv1i8_i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV64-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 1 x i8> @llvm.experimental.vp.strided.load.nxv1i8.i64(i8* %ptr, i64 %stride, <vscale x 1 x i1> %m, i32 %evl)
+  ret <vscale x 1 x i8> %load
+}
+
+define <vscale x 1 x i8> @strided_vpload_nxv1i8_i64_allones_mask(i8* %ptr, i64 %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv1i8_i64_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a3, e8, mf8, ta, mu
+; CHECK-RV32-NEXT:    vlse8.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv1i8_i64_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV64-NEXT:    vlse8.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <vscale x 1 x i1> undef, i1 true, i32 0
+  %b = shufflevector <vscale x 1 x i1> %a, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
+  %load = call <vscale x 1 x i8> @llvm.experimental.vp.strided.load.nxv1i8.i64(i8* %ptr, i64 %stride, <vscale x 1 x i1> %b, i32 %evl)
+  ret <vscale x 1 x i8> %load
+}
+
+declare <vscale x 1 x i8> @llvm.experimental.vp.strided.load.nxv1i8(i8*, i32, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x i8> @strided_vpload_nxv1i8(i8* %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv1i8:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV32-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv1i8:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV64-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 1 x i8> @llvm.experimental.vp.strided.load.nxv1i8(i8* %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)
+  ret <vscale x 1 x i8> %load
+}
+
+define <vscale x 1 x i8> @strided_vpload_nxv1i8_allones_mask(i8* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv1i8_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV32-NEXT:    vlse8.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv1i8_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV64-NEXT:    vlse8.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <vscale x 1 x i1> undef, i1 true, i32 0
+  %b = shufflevector <vscale x 1 x i1> %a, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
+  %load = call <vscale x 1 x i8> @llvm.experimental.vp.strided.load.nxv1i8(i8* %ptr, i32 signext %stride, <vscale x 1 x i1> %b, i32 %evl)
+  ret <vscale x 1 x i8> %load
+}
+
+declare <vscale x 2 x i8> @llvm.experimental.vp.strided.load.nxv2i8(i8*, i32, <vscale x 2 x i1>, i32)
+
+define <vscale x 2 x i8> @strided_vpload_nxv2i8(i8* %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv2i8:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf4, ta, mu
+; CHECK-RV32-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv2i8:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf4, ta, mu
+; CHECK-RV64-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 2 x i8> @llvm.experimental.vp.strided.load.nxv2i8(i8* %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)
+  ret <vscale x 2 x i8> %load
+}
+
+declare <vscale x 4 x i8> @llvm.experimental.vp.strided.load.nxv4i8(i8*, i32, <vscale x 4 x i1>, i32)
+
+define <vscale x 4 x i8> @strided_vpload_nxv4i8(i8* %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv4i8:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf2, ta, mu
+; CHECK-RV32-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv4i8:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf2, ta, mu
+; CHECK-RV64-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 4 x i8> @llvm.experimental.vp.strided.load.nxv4i8(i8* %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)
+  ret <vscale x 4 x i8> %load
+}
+
+declare <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8(i8*, i32, <vscale x 8 x i1>, i32)
+
+define <vscale x 8 x i8> @strided_vpload_nxv8i8(i8* %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv8i8:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv8i8:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8(i8* %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)
+  ret <vscale x 8 x i8> %load
+}
+
+define <vscale x 8 x i8> @strided_vpload_nxv8i8_allones_mask(i8* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv8i8_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse8.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv8i8_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse8.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <vscale x 8 x i1> undef, i1 true, i32 0
+  %b = shufflevector <vscale x 8 x i1> %a, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
+  %load = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8(i8* %ptr, i32 signext %stride, <vscale x 8 x i1> %b, i32 %evl)
+  ret <vscale x 8 x i8> %load
+}
+
+declare <vscale x 1 x i16> @llvm.experimental.vp.strided.load.nxv1i16(i16*, i32, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x i16> @strided_vpload_nxv1i16(i16* %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv1i16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv1i16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 1 x i16> @llvm.experimental.vp.strided.load.nxv1i16(i16* %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)
+  ret <vscale x 1 x i16> %load
+}
+
+declare <vscale x 2 x i16> @llvm.experimental.vp.strided.load.nxv2i16(i16*, i32, <vscale x 2 x i1>, i32)
+
+define <vscale x 2 x i16> @strided_vpload_nxv2i16(i16* %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv2i16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv2i16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 2 x i16> @llvm.experimental.vp.strided.load.nxv2i16(i16* %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)
+  ret <vscale x 2 x i16> %load
+}
+
+define <vscale x 2 x i16> @strided_vpload_nxv2i16_allones_mask(i16* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv2i16_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv2i16_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <vscale x 2 x i1> undef, i1 true, i32 0
+  %b = shufflevector <vscale x 2 x i1> %a, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
+  %load = call <vscale x 2 x i16> @llvm.experimental.vp.strided.load.nxv2i16(i16* %ptr, i32 signext %stride, <vscale x 2 x i1> %b, i32 %evl)
+  ret <vscale x 2 x i16> %load
+}
+
+declare <vscale x 4 x i16> @llvm.experimental.vp.strided.load.nxv4i16(i16*, i32, <vscale x 4 x i1>, i32)
+
+define <vscale x 4 x i16> @strided_vpload_nxv4i16(i16* %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv4i16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv4i16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 4 x i16> @llvm.experimental.vp.strided.load.nxv4i16(i16* %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)
+  ret <vscale x 4 x i16> %load
+}
+
+declare <vscale x 8 x i16> @llvm.experimental.vp.strided.load.nxv8i16(i16*, i32, <vscale x 8 x i1>, i32)
+
+define <vscale x 8 x i16> @strided_vpload_nxv8i16(i16* %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv8i16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv8i16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 8 x i16> @llvm.experimental.vp.strided.load.nxv8i16(i16* %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)
+  ret <vscale x 8 x i16> %load
+}
+
+declare <vscale x 1 x i32> @llvm.experimental.vp.strided.load.nxv1i32(i32*, i32, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x i32> @strided_vpload_nxv1i32(i32* %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv1i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv1i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 1 x i32> @llvm.experimental.vp.strided.load.nxv1i32(i32* %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)
+  ret <vscale x 1 x i32> %load
+}
+
+declare <vscale x 2 x i32> @llvm.experimental.vp.strided.load.nxv2i32(i32*, i32, <vscale x 2 x i1>, i32)
+
+define <vscale x 2 x i32> @strided_vpload_nxv2i32(i32* %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv2i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv2i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 2 x i32> @llvm.experimental.vp.strided.load.nxv2i32(i32* %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)
+  ret <vscale x 2 x i32> %load
+}
+
+declare <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32(i32*, i32, <vscale x 4 x i1>, i32)
+
+define <vscale x 4 x i32> @strided_vpload_nxv4i32(i32* %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv4i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv4i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32(i32* %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)
+  ret <vscale x 4 x i32> %load
+}
+
+define <vscale x 4 x i32> @strided_vpload_nxv4i32_allones_mask(i32* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv4i32_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv4i32_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <vscale x 4 x i1> undef, i1 true, i32 0
+  %b = shufflevector <vscale x 4 x i1> %a, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
+  %load = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32(i32* %ptr, i32 signext %stride, <vscale x 4 x i1> %b, i32 %evl)
+  ret <vscale x 4 x i32> %load
+}
+
+declare <vscale x 8 x i32> @llvm.experimental.vp.strided.load.nxv8i32(i32*, i32, <vscale x 8 x i1>, i32)
+
+define <vscale x 8 x i32> @strided_vpload_nxv8i32(i32* %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv8i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv8i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 8 x i32> @llvm.experimental.vp.strided.load.nxv8i32(i32* %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)
+  ret <vscale x 8 x i32> %load
+}
+
+declare <vscale x 1 x i64> @llvm.experimental.vp.strided.load.nxv1i64(i64*, i32, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x i64> @strided_vpload_nxv1i64(i64* %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv1i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv1i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 1 x i64> @llvm.experimental.vp.strided.load.nxv1i64(i64* %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)
+  ret <vscale x 1 x i64> %load
+}
+
+define <vscale x 1 x i64> @strided_vpload_nxv1i64_allones_mask(i64* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv1i64_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv1i64_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <vscale x 1 x i1> undef, i1 true, i32 0
+  %b = shufflevector <vscale x 1 x i1> %a, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
+  %load = call <vscale x 1 x i64> @llvm.experimental.vp.strided.load.nxv1i64(i64* %ptr, i32 signext %stride, <vscale x 1 x i1> %b, i32 %evl)
+  ret <vscale x 1 x i64> %load
+}
+
+declare <vscale x 2 x i64> @llvm.experimental.vp.strided.load.nxv2i64(i64*, i32, <vscale x 2 x i1>, i32)
+
+define <vscale x 2 x i64> @strided_vpload_nxv2i64(i64* %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv2i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv2i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 2 x i64> @llvm.experimental.vp.strided.load.nxv2i64(i64* %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)
+  ret <vscale x 2 x i64> %load
+}
+
+declare <vscale x 4 x i64> @llvm.experimental.vp.strided.load.nxv4i64(i64*, i32, <vscale x 4 x i1>, i32)
+
+define <vscale x 4 x i64> @strided_vpload_nxv4i64(i64* %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv4i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv4i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 4 x i64> @llvm.experimental.vp.strided.load.nxv4i64(i64* %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)
+  ret <vscale x 4 x i64> %load
+}
+
+declare <vscale x 8 x i64> @llvm.experimental.vp.strided.load.nxv8i64(i64*, i32, <vscale x 8 x i1>, i32)
+
+define <vscale x 8 x i64> @strided_vpload_nxv8i64(i64* %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv8i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv8i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 8 x i64> @llvm.experimental.vp.strided.load.nxv8i64(i64* %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)
+  ret <vscale x 8 x i64> %load
+}
+
+declare <vscale x 1 x half> @llvm.experimental.vp.strided.load.nxv1f16(half*, i32, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x half> @strided_vpload_nxv1f16(half* %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv1f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv1f16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 1 x half> @llvm.experimental.vp.strided.load.nxv1f16(half* %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)
+  ret <vscale x 1 x half> %load
+}
+
+declare <vscale x 2 x half> @llvm.experimental.vp.strided.load.nxv2f16(half*, i32, <vscale x 2 x i1>, i32)
+
+define <vscale x 2 x half> @strided_vpload_nxv2f16(half* %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv2f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv2f16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 2 x half> @llvm.experimental.vp.strided.load.nxv2f16(half* %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)
+  ret <vscale x 2 x half> %load
+}
+
+define <vscale x 2 x half> @strided_vpload_nxv2f16_allones_mask(half* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv2f16_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv2f16_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <vscale x 2 x i1> undef, i1 true, i32 0
+  %b = shufflevector <vscale x 2 x i1> %a, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
+  %load = call <vscale x 2 x half> @llvm.experimental.vp.strided.load.nxv2f16(half* %ptr, i32 signext %stride, <vscale x 2 x i1> %b, i32 %evl)
+  ret <vscale x 2 x half> %load
+}
+
+declare <vscale x 4 x half> @llvm.experimental.vp.strided.load.nxv4f16(half*, i32, <vscale x 4 x i1>, i32)
+
+define <vscale x 4 x half> @strided_vpload_nxv4f16(half* %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv4f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv4f16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 4 x half> @llvm.experimental.vp.strided.load.nxv4f16(half* %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)
+  ret <vscale x 4 x half> %load
+}
+
+declare <vscale x 8 x half> @llvm.experimental.vp.strided.load.nxv8f16(half*, i32, <vscale x 8 x i1>, i32)
+
+define <vscale x 8 x half> @strided_vpload_nxv8f16(half* %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv8f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv8f16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 8 x half> @llvm.experimental.vp.strided.load.nxv8f16(half* %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)
+  ret <vscale x 8 x half> %load
+}
+
+declare <vscale x 1 x float> @llvm.experimental.vp.strided.load.nxv1f32(float*, i32, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x float> @strided_vpload_nxv1f32(float* %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv1f32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv1f32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 1 x float> @llvm.experimental.vp.strided.load.nxv1f32(float* %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)
+  ret <vscale x 1 x float> %load
+}
+
+declare <vscale x 2 x float> @llvm.experimental.vp.strided.load.nxv2f32(float*, i32, <vscale x 2 x i1>, i32)
+
+define <vscale x 2 x float> @strided_vpload_nxv2f32(float* %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv2f32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv2f32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 2 x float> @llvm.experimental.vp.strided.load.nxv2f32(float* %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)
+  ret <vscale x 2 x float> %load
+}
+
+declare <vscale x 4 x float> @llvm.experimental.vp.strided.load.nxv4f32(float*, i32, <vscale x 4 x i1>, i32)
+
+define <vscale x 4 x float> @strided_vpload_nxv4f32(float* %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv4f32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv4f32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 4 x float> @llvm.experimental.vp.strided.load.nxv4f32(float* %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)
+  ret <vscale x 4 x float> %load
+}
+
+declare <vscale x 8 x float> @llvm.experimental.vp.strided.load.nxv8f32(float*, i32, <vscale x 8 x i1>, i32)
+
+define <vscale x 8 x float> @strided_vpload_nxv8f32(float* %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv8f32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv8f32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 8 x float> @llvm.experimental.vp.strided.load.nxv8f32(float* %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)
+  ret <vscale x 8 x float> %load
+}
+
+define <vscale x 8 x float> @strided_vpload_nxv8f32_allones_mask(float* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv8f32_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
+; CHECK-RV32-NEXT:    vlse32.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv8f32_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
+; CHECK-RV64-NEXT:    vlse32.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <vscale x 8 x i1> undef, i1 true, i32 0
+  %b = shufflevector <vscale x 8 x i1> %a, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
+  %load = call <vscale x 8 x float> @llvm.experimental.vp.strided.load.nxv8f32(float* %ptr, i32 signext %stride, <vscale x 8 x i1> %b, i32 %evl)
+  ret <vscale x 8 x float> %load
+}
+
+declare <vscale x 1 x double> @llvm.experimental.vp.strided.load.nxv1f64(double*, i32, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @strided_vpload_nxv1f64(double* %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv1f64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv1f64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 1 x double> @llvm.experimental.vp.strided.load.nxv1f64(double* %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)
+  ret <vscale x 1 x double> %load
+}
+
+declare <vscale x 2 x double> @llvm.experimental.vp.strided.load.nxv2f64(double*, i32, <vscale x 2 x i1>, i32)
+
+define <vscale x 2 x double> @strided_vpload_nxv2f64(double* %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv2f64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv2f64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 2 x double> @llvm.experimental.vp.strided.load.nxv2f64(double* %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)
+  ret <vscale x 2 x double> %load
+}
+
+declare <vscale x 4 x double> @llvm.experimental.vp.strided.load.nxv4f64(double*, i32, <vscale x 4 x i1>, i32)
+
+define <vscale x 4 x double> @strided_vpload_nxv4f64(double* %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv4f64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv4f64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 4 x double> @llvm.experimental.vp.strided.load.nxv4f64(double* %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)
+  ret <vscale x 4 x double> %load
+}
+
+define <vscale x 4 x double> @strided_vpload_nxv4f64_allones_mask(double* %ptr, i32 signext %stride, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv4f64_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv4f64_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <vscale x 4 x i1> undef, i1 true, i32 0
+  %b = shufflevector <vscale x 4 x i1> %a, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
+  %load = call <vscale x 4 x double> @llvm.experimental.vp.strided.load.nxv4f64(double* %ptr, i32 signext %stride, <vscale x 4 x i1> %b, i32 %evl)
+  ret <vscale x 4 x double> %load
+}
+
+declare <vscale x 8 x double> @llvm.experimental.vp.strided.load.nxv8f64(double*, i32, <vscale x 8 x i1>, i32)
+
+define <vscale x 8 x double> @strided_vpload_nxv8f64(double* %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpload_nxv8f64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
+; CHECK-RV32-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpload_nxv8f64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
+; CHECK-RV64-NEXT:    vlse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  %load = call <vscale x 8 x double> @llvm.experimental.vp.strided.load.nxv8f64(double* %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)
+  ret <vscale x 8 x double> %load
+}

llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+v \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-RV32
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+v \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-RV64
+
+declare void @llvm.experimental.vp.strided.store.nxv1i8.i64(<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i32)
+
+define void @strided_vpstore_nxv1i8_i64(<vscale x 1 x i8> %val, i8* %ptr, i64 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv1i8_i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a3, e8, mf8, ta, mu
+; CHECK-RV32-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv1i8_i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV64-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv1i8.i64(<vscale x 1 x i8> %val, i8* %ptr, i64 %stride, <vscale x 1 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv1i8(<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)
+
+define void @strided_vpstore_nxv1i8(<vscale x 1 x i8> %val, i8* %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv1i8:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV32-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv1i8:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV64-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv1i8(<vscale x 1 x i8> %val, i8* %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv2i8(<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)
+
+define void @strided_vpstore_nxv2i8(<vscale x 2 x i8> %val, i8* %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv2i8:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf4, ta, mu
+; CHECK-RV32-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv2i8:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf4, ta, mu
+; CHECK-RV64-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv2i8(<vscale x 2 x i8> %val, i8* %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv4i8(<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)
+
+define void @strided_vpstore_nxv4i8(<vscale x 4 x i8> %val, i8* %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv4i8:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf2, ta, mu
+; CHECK-RV32-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv4i8:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf2, ta, mu
+; CHECK-RV64-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv4i8(<vscale x 4 x i8> %val, i8* %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv8i8(<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)
+
+define void @strided_vpstore_nxv8i8(<vscale x 8 x i8> %val, i8* %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv8i8:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, m1, ta, mu
+; CHECK-RV32-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv8i8:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, m1, ta, mu
+; CHECK-RV64-NEXT:    vsse8.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv8i8(<vscale x 8 x i8> %val, i8* %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv1i16(<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)
+
+define void @strided_vpstore_nxv1i16(<vscale x 1 x i16> %val, i16* %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv1i16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV32-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv1i16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV64-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv1i16(<vscale x 1 x i16> %val, i16* %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv2i16(<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)
+
+define void @strided_vpstore_nxv2i16(<vscale x 2 x i16> %val, i16* %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv2i16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV32-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv2i16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV64-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv2i16(<vscale x 2 x i16> %val, i16* %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv4i16(<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)
+
+define void @strided_vpstore_nxv4i16(<vscale x 4 x i16> %val, i16* %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv4i16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV32-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv4i16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV64-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv4i16(<vscale x 4 x i16> %val, i16* %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv8i16(<vscale x 8 x i16>, i16*, i32, <vscale x 8 x i1>, i32)
+
+define void @strided_vpstore_nxv8i16(<vscale x 8 x i16> %val, i16* %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv8i16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m2, ta, mu
+; CHECK-RV32-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv8i16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, m2, ta, mu
+; CHECK-RV64-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv8i16(<vscale x 8 x i16> %val, i16* %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv1i32(<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)
+
+define void @strided_vpstore_nxv1i32(<vscale x 1 x i32> %val, i32* %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv1i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV32-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv1i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV64-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv1i32(<vscale x 1 x i32> %val, i32* %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv2i32(<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)
+
+define void @strided_vpstore_nxv2i32(<vscale x 2 x i32> %val, i32* %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv2i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV32-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv2i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV64-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv2i32(<vscale x 2 x i32> %val, i32* %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv4i32(<vscale x 4 x i32>, i32*, i32, <vscale x 4 x i1>, i32)
+
+define void @strided_vpstore_nxv4i32(<vscale x 4 x i32> %val, i32* %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv4i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV32-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv4i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV64-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv4i32(<vscale x 4 x i32> %val, i32* %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv8i32(<vscale x 8 x i32>, i32*, i32, <vscale x 8 x i1>, i32)
+
+define void @strided_vpstore_nxv8i32(<vscale x 8 x i32> %val, i32* %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv8i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
+; CHECK-RV32-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv8i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
+; CHECK-RV64-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv8i32(<vscale x 8 x i32> %val, i32* %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv1i64(<vscale x 1 x i64>, i64*, i32, <vscale x 1 x i1>, i32)
+
+define void @strided_vpstore_nxv1i64(<vscale x 1 x i64> %val, i64* %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv1i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV32-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv1i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV64-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv1i64(<vscale x 1 x i64> %val, i64* %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv2i64(<vscale x 2 x i64>, i64*, i32, <vscale x 2 x i1>, i32)
+
+define void @strided_vpstore_nxv2i64(<vscale x 2 x i64> %val, i64* %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv2i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV32-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv2i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV64-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv2i64(<vscale x 2 x i64> %val, i64* %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv4i64(<vscale x 4 x i64>, i64*, i32, <vscale x 4 x i1>, i32)
+
+define void @strided_vpstore_nxv4i64(<vscale x 4 x i64> %val, i64* %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv4i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV32-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv4i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV64-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv4i64(<vscale x 4 x i64> %val, i64* %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv8i64(<vscale x 8 x i64>, i64*, i32, <vscale x 8 x i1>, i32)
+
+define void @strided_vpstore_nxv8i64(<vscale x 8 x i64> %val, i64* %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv8i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
+; CHECK-RV32-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv8i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
+; CHECK-RV64-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv8i64(<vscale x 8 x i64> %val, i64* %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv1f16(<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)
+
+define void @strided_vpstore_nxv1f16(<vscale x 1 x half> %val, half* %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv1f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV32-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv1f16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf4, ta, mu
+; CHECK-RV64-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv1f16(<vscale x 1 x half> %val, half* %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv2f16(<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)
+
+define void @strided_vpstore_nxv2f16(<vscale x 2 x half> %val, half* %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv2f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV32-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv2f16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, mf2, ta, mu
+; CHECK-RV64-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv2f16(<vscale x 2 x half> %val, half* %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv4f16(<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)
+
+define void @strided_vpstore_nxv4f16(<vscale x 4 x half> %val, half* %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv4f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV32-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv4f16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, m1, ta, mu
+; CHECK-RV64-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv4f16(<vscale x 4 x half> %val, half* %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv8f16(<vscale x 8 x half>, half*, i32, <vscale x 8 x i1>, i32)
+
+define void @strided_vpstore_nxv8f16(<vscale x 8 x half> %val, half* %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv8f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m2, ta, mu
+; CHECK-RV32-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv8f16:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e16, m2, ta, mu
+; CHECK-RV64-NEXT:    vsse16.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv8f16(<vscale x 8 x half> %val, half* %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv1f32(<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)
+
+define void @strided_vpstore_nxv1f32(<vscale x 1 x float> %val, float* %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv1f32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV32-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv1f32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, mf2, ta, mu
+; CHECK-RV64-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv1f32(<vscale x 1 x float> %val, float* %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv2f32(<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)
+
+define void @strided_vpstore_nxv2f32(<vscale x 2 x float> %val, float* %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv2f32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV32-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv2f32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m1, ta, mu
+; CHECK-RV64-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv2f32(<vscale x 2 x float> %val, float* %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv4f32(<vscale x 4 x float>, float*, i32, <vscale x 4 x i1>, i32)
+
+define void @strided_vpstore_nxv4f32(<vscale x 4 x float> %val, float* %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv4f32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV32-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv4f32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m2, ta, mu
+; CHECK-RV64-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv4f32(<vscale x 4 x float> %val, float* %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv8f32(<vscale x 8 x float>, float*, i32, <vscale x 8 x i1>, i32)
+
+define void @strided_vpstore_nxv8f32(<vscale x 8 x float> %val, float* %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv8f32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
+; CHECK-RV32-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv8f32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
+; CHECK-RV64-NEXT:    vsse32.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv8f32(<vscale x 8 x float> %val, float* %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv1f64(<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)
+
+define void @strided_vpstore_nxv1f64(<vscale x 1 x double> %val, double* %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv1f64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV32-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv1f64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
+; CHECK-RV64-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv1f64(<vscale x 1 x double> %val, double* %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv2f64(<vscale x 2 x double>, double*, i32, <vscale x 2 x i1>, i32)
+
+define void @strided_vpstore_nxv2f64(<vscale x 2 x double> %val, double* %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv2f64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV32-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv2f64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
+; CHECK-RV64-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv2f64(<vscale x 2 x double> %val, double* %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv4f64(<vscale x 4 x double>, double*, i32, <vscale x 4 x i1>, i32)
+
+define void @strided_vpstore_nxv4f64(<vscale x 4 x double> %val, double* %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv4f64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV32-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv4f64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
+; CHECK-RV64-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv4f64(<vscale x 4 x double> %val, double* %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
+  ret void
+}
+
+declare void @llvm.experimental.vp.strided.store.nxv8f64(<vscale x 8 x double>, double*, i32, <vscale x 8 x i1>, i32)
+
+define void @strided_vpstore_nxv8f64(<vscale x 8 x double> %val, double* %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv8f64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
+; CHECK-RV32-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv8f64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
+; CHECK-RV64-NEXT:    vsse64.v v8, (a0), a1, v0.t
+; CHECK-RV64-NEXT:    ret
+  call void @llvm.experimental.vp.strided.store.nxv8f64(<vscale x 8 x double> %val, double* %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
+  ret void
+}
+
+define void @strided_vpstore_nxv1i8_allones_mask(<vscale x 1 x i8> %val, i8* %ptr, i32 signext %strided, i32 zeroext %evl) {
+; CHECK-RV32-LABEL: strided_vpstore_nxv1i8_allones_mask:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV32-NEXT:    vsse8.v v8, (a0), a1
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: strided_vpstore_nxv1i8_allones_mask:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf8, ta, mu
+; CHECK-RV64-NEXT:    vsse8.v v8, (a0), a1
+; CHECK-RV64-NEXT:    ret
+  %a = insertelement <vscale x 1 x i1> undef, i1 true, i32 0
+  %b = shufflevector <vscale x 1 x i1> %a, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
+  call void @llvm.experimental.vp.strided.store.nxv1i8(<vscale x 1 x i8> %val, i8* %ptr, i32 %strided, <vscale x 1 x i1> %b, i32 %evl)
+  ret void
+}