This is an archive of the discontinued LLVM Phabricator instance.

Differential D110339

SelectionDAGBuilder: Improve canonicalization by not swapping branch targets
AbandonedPublic

Authored by MatzeB on Sep 23 2021, 8:53 AM.

Details

Reviewers
craig.topper
rnk
RKSimon
Jiangning
mcrosier
efriedma
yonghong-song
bogner
lebedev.ri
Summary

Introduces a TargetLowerig::optimizeFallthroughsEarly() switch to
stop SelectionDAG flipping jump targets to create fallthroughs. Optimizing
for fallthroughs can negatively affect canonicalization and we can usually
leave the decision to MachineBlockPlacement.

Motivation

In most targets comparison instructions produce results for multiple
relations, so a program like if (x == C) { ... } else if (x > C) { ... }
can use a single compare instructions for 2 conditional branches. This pattern
is widespread in one of our systems (a decref operation with support for
immortal objects).

Machine-CSE would not consistently trigger, because:
SelectionDAG would often optimizes for fallthroughs,
flip true/false and negate the condition:

x > C
--> !(x > C) with true/false branches flipped
--> X <= C
--> X < (C + 1)  canonicalization

So we end up with a different constant inhibiting CSE!

However with MachineBlockPlacement optimzing control flow
and fallthroughs anyway there is no real benefit from
SelectionDAG optimizing early when it negatively affects
canonicalization.

Target Specifics

I did not apply the change to most targets:

  • ARM: IfConverter pass currently relies on fallthroughs existing
  • AArch64: Has a custom AArch64ConditionOptimizer pass to CSE comparison. Strangely the unit tests do not show consistent behavior with and without these changes. Glancing at the code I wonder if the algorithm only checks control flow among the "true" direction of a conditional branch and misses opportunities in the "false" direction.
  • PowerPC+Mips: It seems in some tests not instructions are inserted when optimizing for fallthrough instead of flipping true/false.
  • BPF+WebAssembly: The TargetInstrInfo::analyzeBranch implementation appears to be incomplete so MachineBlockPlacement cannot optimize for fallthroughs.
  • Other targets: Test regressions that I did not understand.

The changes are enabled for: X86, RISCV, Lanai, XCore and by default
for new targets.

Test Changes

There is a lot of test churn. Most is benign because of different
canonicalization (which in fact makes it more likely to see the same
constant in LLVM-IR and assembly now).

There are a number of tests containing unoptimized conditional branches
jumping on true/false, getting better or worse. But those are just
artifacts of bugpoint reduction or manual construction and
won't happen in practice after InstCombine:

est/CodeGen/X86/callbr-asm-blockplacement.ll
test/CodeGen/X86/pr29170.ll
test/CodeGen/X86/pr46585.ll
test/CodeGen/X86/setcc-freeze.ll
test/CodeGen/X86/2008-04-17-CoalescerBug.ll
test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
test/CodeGen/X86/2007-03-01-SpillerCrash.ll
test/CodeGen/X86/2007-12-18-LoadCSEBug.ll
test/CodeGen/X86/legalize-shift-64.ll
test/CodeGen/X86/avx-cmp.ll
test/CodeGen/X86/setcc-freeze.ll
test/CodeGen/X86/shrink-compare-pgso.ll

These tests show improved codegen because duplicated CMPs get
eliminated:

test/CodeGen/X86/speculative-load-hardening-indirect.ll
test/CodeGen/X86/switch-density.ll
test/CodeGen/X86/cse-cmp.ll (new test)

These appear to improve because of different normalization:

test/CodeGen/X86/cmp-bool.ll
test/CodeGen/X86/fp128-select.ll
test/CodeGen/X86/xmulo.ll

Diff Detail

Unit TestsFailed

TimeTest
150 msx64 debian > ORC-x86_64-linux.TestCases/Linux/x86-64::trivial-cxa-atexit.S
160 msx64 debian > ORC-x86_64-linux.TestCases/Linux/x86-64::trivial-static-initializer.S
160 msx64 debian > ORC-x86_64-linux.TestCases/Linux/x86-64::trivial-tls.S

Event Timeline

MatzeB created this revision.Sep 23 2021, 8:53 AM
Herald added subscribers: foad, frasercrmck, wenlei and 43 others. · View Herald TranscriptSep 23 2021, 8:53 AM
MatzeB requested review of this revision.Sep 23 2021, 8:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 23 2021, 8:53 AM
Herald added subscribers: llvm-commits, MaskRay, aheejin. · View Herald Transcript
MatzeB edited the summary of this revision. (Show Details)Sep 23 2021, 8:55 AM
arsenm added a comment.Sep 23 2021, 8:57 AM

I always found this annoying. Can we just unconditionally remove it?

MatzeB added a subscriber: ast.Sep 23 2021, 8:57 AM
ast added a reviewer: yonghong-song.Sep 23 2021, 9:03 AM
MatzeB added a comment.Sep 23 2021, 9:08 AM

I always found this annoying. Can we just unconditionally remove it?

I would love to, but I am not in a position to deal with all the test churn (and I tried for the last couple days). Theres little details that need fixing (see "Target Specifics" section in the summary) and general test churn that needs review.

RKSimon added inline comments.Sep 23 2021, 9:17 AM
llvm/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll
15

This kind of thing is going to increase EFLAGS usage - I addressed this for CMOVs + SETs with SGT/UGT in D101074 but haven't had time to address JMP/BRANCH, or add the SLE/ULE equivalent yet.

MatzeB added inline comments.Sep 23 2021, 9:28 AM
llvm/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll
15

This kind of thing is going to increase EFLAGS usage

Wow, I was not aware that affects performance. Does that mean MachineCodePlacement / analyzeBranch can pessimize code when it flips the true/false branches and negates the condition of a jump?

craig.topper added inline comments.Sep 23 2021, 9:38 AM
llvm/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll
15

At least on Intel CPUs, I'm not aware of a performance issue for jumps. There is an extra uop for CMOV and SETCC conditions that use the C flag and Z flag. That would cmovbe, cmova, setbe, and seta. There is no extra uop for branches on the same conditions.

I can't speak to AMD CPUs.

RKSimon added inline comments.Sep 23 2021, 9:44 AM
llvm/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll
15

Its often tricky to see the effect of this in real world code, but yes we should always be trying to minimize the number of EFLAGS bits we depend on. Some x86 cpus split the dependencies into individual/groups of bits, others keep them together, its quite a mess and isn't something we've properly tried to model......

I'll see if I can resurrect the followups to D101074 - iirc I encountered a similar mammoth test churn to you in this patch.

Harbormaster completed remote builds in B125370: Diff 374571.Sep 23 2021, 9:44 AM
MatzeB added a comment.Sep 30 2021, 11:38 AM

Without having a good way to progress here, I went for a new approach of making X86InstrInfo::optimizeCompareInstr more powerful in D110862, D110863, D110865 and D110867...

lebedev.ri resigned from this revision.Jan 12 2023, 5:24 PM

This review seems to be stuck/dead, consider abandoning if no longer relevant.

Herald added a project: Restricted Project. · View Herald TranscriptJan 12 2023, 5:24 PM
Herald added subscribers: kosarev, mattd, gchakrabarti and 5 others. · View Herald Transcript
bogner resigned from this revision.Feb 7 2023, 3:43 PM
Herald added subscribers: jobnoorman, luke. · View Herald TranscriptFeb 7 2023, 3:43 PM
MatzeB abandoned this revision.Feb 7 2023, 4:02 PM

I still think this is a good idea in theory. But I solved my problem by other means and don't plan to push this further. Abandoning.

Revision Contents

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include/
llvm/
CodeGen/
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SelectionDAG/
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Diff 374571

llvm/include/llvm/CodeGen/TargetLowering.h

Show First 20 Lines • Show All 619 Lines • ▼ Show 20 Linespublic:
/// Return true if instruction generated for equality comparison is folded /// Return true if instruction generated for equality comparison is folded
/// with instruction generated for signed comparison. /// with instruction generated for signed comparison.
virtual bool isEqualityCmpFoldedWithSignedCmp() const { return true; } virtual bool isEqualityCmpFoldedWithSignedCmp() const { return true; }
/// Return true if the heuristic to prefer icmp eq zero should be used in code /// Return true if the heuristic to prefer icmp eq zero should be used in code
/// gen prepare. /// gen prepare.
virtual bool preferZeroCompareBranch() const { return false; } virtual bool preferZeroCompareBranch() const { return false; }
/// Flip comparison conditions to optimize for fallthroughs.
/// It is recommended to disable this as it hurts canonicalization; instead
/// implement TargetInstrInfo::analyzeBranch so branches get optimized after
/// instruction selection.
virtual bool optimizeFallthroughsEarly() const { return false; }
/// Return true if it is safe to transform an integer-domain bitwise operation /// Return true if it is safe to transform an integer-domain bitwise operation
/// into the equivalent floating-point operation. This should be set to true /// into the equivalent floating-point operation. This should be set to true
/// if the target has IEEE-754-compliant fabs/fneg operations for the input /// if the target has IEEE-754-compliant fabs/fneg operations for the input
/// type. /// type.
virtual bool hasBitPreservingFPLogic(EVT VT) const { virtual bool hasBitPreservingFPLogic(EVT VT) const {
return false; return false;
} }
▲ Show 20 Lines • Show All 4,075 Lines • Show Last 20 Lines

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,506 Lines • ▼ Show 20 Linesvoid SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
// TrueBB and FalseBB are always different unless the incoming IR is // TrueBB and FalseBB are always different unless the incoming IR is
// degenerate. This only happens when running llc on weird IR. // degenerate. This only happens when running llc on weird IR.
if (CB.TrueBB != CB.FalseBB) if (CB.TrueBB != CB.FalseBB)
addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb); addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb);
SwitchBB->normalizeSuccProbs(); SwitchBB->normalizeSuccProbs();
// If the lhs block is the next block, invert the condition so that we can // If the lhs block is the next block, invert the condition so that we can
// fall through to the lhs instead of the rhs block. // fall through to the lhs instead of the rhs block.
if (CB.TrueBB == NextBlock(SwitchBB)) { if (TLI.optimizeFallthroughsEarly() && CB.TrueBB == NextBlock(SwitchBB)) {
std::swap(CB.TrueBB, CB.FalseBB); std::swap(CB.TrueBB, CB.FalseBB);
SDValue True = DAG.getConstant(1, dl, Cond.getValueType()); SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
} }
SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
MVT::Other, getControlRoot(), Cond, MVT::Other, getControlRoot(), Cond,
DAG.getBasicBlock(CB.TrueBB)); DAG.getBasicBlock(CB.TrueBB));
▲ Show 20 Lines • Show All 8,756 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64ISelLowering.h

Show First 20 Lines • Show All 762 Lines • ▼ Show 20 Lines bool shouldTransformSignedTruncationCheck(EVT XVT,
// We are ok with KeptBitsVT being byte/word/dword, what SXT supports. // We are ok with KeptBitsVT being byte/word/dword, what SXT supports.
// XVT will be larger than KeptBitsVT. // XVT will be larger than KeptBitsVT.
MVT KeptBitsVT = MVT::getIntegerVT(KeptBits); MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
return VTIsOk(XVT) && VTIsOk(KeptBitsVT); return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
} }
bool preferIncOfAddToSubOfNot(EVT VT) const override; bool preferIncOfAddToSubOfNot(EVT VT) const override;
bool optimizeFallthroughsEarly() const override {
// Enabled because AArch64ConditionOptimizer does not consistently optimize
// lit tests.
return true;
}
bool hasBitPreservingFPLogic(EVT VT) const override { bool hasBitPreservingFPLogic(EVT VT) const override {
// FIXME: Is this always true? It should be true for vectors at least. // FIXME: Is this always true? It should be true for vectors at least.
return VT == MVT::f32 || VT == MVT::f64; return VT == MVT::f32 || VT == MVT::f64;
} }
bool supportSplitCSR(MachineFunction *MF) const override { bool supportSplitCSR(MachineFunction *MF) const override {
return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
MF->getFunction().hasFnAttribute(Attribute::NoUnwind); MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
▲ Show 20 Lines • Show All 359 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

Show First 20 Lines • Show All 182 Lines • ▼ Show 20 Lines bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG,
const MachineMemOperand &MMO) const final; const MachineMemOperand &MMO) const final;
bool storeOfVectorConstantIsCheap(EVT MemVT, bool storeOfVectorConstantIsCheap(EVT MemVT,
unsigned NumElem, unsigned NumElem,
unsigned AS) const override; unsigned AS) const override;
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override; bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
bool isCheapToSpeculateCttz() const override; bool isCheapToSpeculateCttz() const override;
bool isCheapToSpeculateCtlz() const override; bool isCheapToSpeculateCtlz() const override;
bool optimizeFallthroughsEarly() const override;
bool isSDNodeAlwaysUniform(const SDNode *N) const override; bool isSDNodeAlwaysUniform(const SDNode *N) const override;
static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg); static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg); static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
▲ Show 20 Lines • Show All 338 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 830 Lines • ▼ Show 20 Lines
bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const { bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
return true; return true;
} }
bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const { bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
return true; return true;
} }
bool AMDGPUTargetLowering::optimizeFallthroughsEarly() const { return true; }
bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode *N) const { bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode *N) const {
switch (N->getOpcode()) { switch (N->getOpcode()) {
case ISD::EntryToken: case ISD::EntryToken:
case ISD::TokenFactor: case ISD::TokenFactor:
return true; return true;
case ISD::INTRINSIC_WO_CHAIN: { case ISD::INTRINSIC_WO_CHAIN: {
unsigned IntrID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); unsigned IntrID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
switch (IntrID) { switch (IntrID) {
▲ Show 20 Lines • Show All 4,016 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMISelLowering.h

Show First 20 Lines • Show All 585 Lines • ▼ Show 20 Lines public:
/// or null if the target does not support "fast" ISel. /// or null if the target does not support "fast" ISel.
FastISel *createFastISel(FunctionLoweringInfo &funcInfo, FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo) const override; const TargetLibraryInfo *libInfo) const override;
Sched::Preference getSchedulingPreference(SDNode *N) const override; Sched::Preference getSchedulingPreference(SDNode *N) const override;
bool preferZeroCompareBranch() const override { return true; } bool preferZeroCompareBranch() const override { return true; }
bool bool optimizeFallthroughsEarly() const override {
isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; // IfConversion pass only recognizes patterns when fallthroughs are used
// so we currently cannot disable this.
return true;
}
bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
/// isFPImmLegal - Returns true if the target can instruction select the /// isFPImmLegal - Returns true if the target can instruction select the
/// specified FP immediate natively. If false, the legalizer will /// specified FP immediate natively. If false, the legalizer will
/// materialize the FP immediate as a load from a constant pool. /// materialize the FP immediate as a load from a constant pool.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize = false) const override; bool ForCodeSize = false) const override;
▲ Show 20 Lines • Show All 388 Lines • Show Last 20 Lines

llvm/lib/Target/AVR/AVRISelLowering.h

Show First 20 Lines • Show All 135 Lines • ▼ Show 20 Linespublic:
Register getRegisterByName(const char *RegName, LLT VT, Register getRegisterByName(const char *RegName, LLT VT,
const MachineFunction &MF) const override; const MachineFunction &MF) const override;
bool shouldSplitFunctionArgumentsAsLittleEndian( bool shouldSplitFunctionArgumentsAsLittleEndian(
const DataLayout &DL) const override { const DataLayout &DL) const override {
return false; return false;
} }
bool optimizeFallthroughsEarly() const override { return true; }
private: private:
SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc, SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
SelectionDAG &DAG, SDLoc dl) const; SelectionDAG &DAG, SDLoc dl) const;
SDValue getAVRCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDValue getAVRCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
SDLoc dl) const; SDLoc dl) const;
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
Show All 40 Lines

llvm/lib/Target/BPF/BPFISelLowering.h

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Linespublic:
bool getHasJmp32() const { return HasJmp32; } bool getHasJmp32() const { return HasJmp32; }
bool getHasJmpExt() const { return HasJmpExt; } bool getHasJmpExt() const { return HasJmpExt; }
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
EVT VT) const override; EVT VT) const override;
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
bool optimizeFallthroughsEarly() const override;
private: private:
// Control Instruction Selection Features // Control Instruction Selection Features
bool HasAlu32; bool HasAlu32;
bool HasJmp32; bool HasJmp32;
bool HasJmpExt; bool HasJmpExt;
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
▲ Show 20 Lines • Show All 77 Lines • Show Last 20 Lines

llvm/lib/Target/BPF/BPFISelLowering.cpp

Show First 20 Lines • Show All 853 Lines • ▼ Show 20 LinesEVT BPFTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
EVT VT) const { EVT VT) const {
return getHasAlu32() ? MVT::i32 : MVT::i64; return getHasAlu32() ? MVT::i32 : MVT::i64;
} }
MVT BPFTargetLowering::getScalarShiftAmountTy(const DataLayout &DL, MVT BPFTargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
EVT VT) const { EVT VT) const {
return (getHasAlu32() && VT == MVT::i32) ? MVT::i32 : MVT::i64; return (getHasAlu32() && VT == MVT::i32) ? MVT::i32 : MVT::i64;
} }
bool BPFTargetLowering::optimizeFallthroughsEarly() const {
// Cannot disable this until BPFInstrInfo::analyzeBranch can optimize
// fallthroughs.
return true;
}

llvm/lib/Target/Hexagon/HexagonISelLowering.h

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
unsigned Intrinsic) const override; unsigned Intrinsic) const override;
bool isTruncateFree(Type *Ty1, Type *Ty2) const override; bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
bool isTruncateFree(EVT VT1, EVT VT2) const override; bool isTruncateFree(EVT VT1, EVT VT2) const override;
bool isCheapToSpeculateCttz() const override { return true; } bool isCheapToSpeculateCttz() const override { return true; }
bool isCheapToSpeculateCtlz() const override { return true; } bool isCheapToSpeculateCtlz() const override { return true; }
bool isCtlzFast() const override { return true; } bool isCtlzFast() const override { return true; }
bool optimizeFallthroughsEarly() const override { return true; }
bool hasBitTest(SDValue X, SDValue Y) const override; bool hasBitTest(SDValue X, SDValue Y) const override;
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
/// Return true if an FMA operation is faster than a pair of mul and add /// Return true if an FMA operation is faster than a pair of mul and add
/// instructions. fmuladd intrinsics will be expanded to FMAs when this /// instructions. fmuladd intrinsics will be expanded to FMAs when this
/// method returns true (and FMAs are legal), otherwise fmuladd is /// method returns true (and FMAs are legal), otherwise fmuladd is
▲ Show 20 Lines • Show All 359 Lines • Show Last 20 Lines

llvm/lib/Target/Mips/MipsISelLowering.h

Show First 20 Lines • Show All 276 Lines • ▼ Show 20 Lines MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
return MVT::i32; return MVT::i32;
} }
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
ISD::NodeType) const override; ISD::NodeType) const override;
bool isCheapToSpeculateCttz() const override; bool isCheapToSpeculateCttz() const override;
bool isCheapToSpeculateCtlz() const override; bool isCheapToSpeculateCtlz() const override;
bool optimizeFallthroughsEarly() const override;
bool shouldFoldConstantShiftPairToMask(const SDNode *N, bool shouldFoldConstantShiftPairToMask(const SDNode *N,
CombineLevel Level) const override; CombineLevel Level) const override;
/// Return the register type for a given MVT, ensuring vectors are treated /// Return the register type for a given MVT, ensuring vectors are treated
/// as a series of gpr sized integers. /// as a series of gpr sized integers.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
EVT VT) const override; EVT VT) const override;
▲ Show 20 Lines • Show All 426 Lines • Show Last 20 Lines

llvm/lib/Target/Mips/MipsISelLowering.cpp

Show First 20 Lines • Show All 1,185 Lines • ▼ Show 20 Lines
bool MipsTargetLowering::isCheapToSpeculateCttz() const { bool MipsTargetLowering::isCheapToSpeculateCttz() const {
return Subtarget.hasMips32(); return Subtarget.hasMips32();
} }
bool MipsTargetLowering::isCheapToSpeculateCtlz() const { bool MipsTargetLowering::isCheapToSpeculateCtlz() const {
return Subtarget.hasMips32(); return Subtarget.hasMips32();
} }
bool MipsTargetLowering::optimizeFallthroughsEarly() const { return true; }
bool MipsTargetLowering::shouldFoldConstantShiftPairToMask( bool MipsTargetLowering::shouldFoldConstantShiftPairToMask(
const SDNode *N, CombineLevel Level) const { const SDNode *N, CombineLevel Level) const {
if (N->getOperand(0).getValueType().isVector()) if (N->getOperand(0).getValueType().isVector())
return false; return false;
return true; return true;
} }
void void
▲ Show 20 Lines • Show All 3,823 Lines • Show Last 20 Lines

llvm/lib/Target/NVPTX/NVPTXISelLowering.h

Show First 20 Lines • Show All 545 Lines • ▼ Show 20 Linespublic:
bool enableAggressiveFMAFusion(EVT VT) const override { return true; } bool enableAggressiveFMAFusion(EVT VT) const override { return true; }
// The default is to transform llvm.ctlz(x, false) (where false indicates that // The default is to transform llvm.ctlz(x, false) (where false indicates that
// x == 0 is not undefined behavior) into a branch that checks whether x is 0 // x == 0 is not undefined behavior) into a branch that checks whether x is 0
// and avoids calling ctlz in that case. We have a dedicated ctlz // and avoids calling ctlz in that case. We have a dedicated ctlz
// instruction, so we say that ctlz is cheap to speculate. // instruction, so we say that ctlz is cheap to speculate.
bool isCheapToSpeculateCtlz() const override { return true; } bool isCheapToSpeculateCtlz() const override { return true; }
bool optimizeFallthroughsEarly() const override { return true; }
private: private:
const NVPTXSubtarget &STI; // cache the subtarget here const NVPTXSubtarget &STI; // cache the subtarget here
SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const; SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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llvm/lib/Target/PowerPC/PPCISelLowering.h

Show First 20 Lines • Show All 773 Lines • ▼ Show 20 Lines public:
bool isCtlzFast() const override { bool isCtlzFast() const override {
return true; return true;
} }
bool isEqualityCmpFoldedWithSignedCmp() const override { bool isEqualityCmpFoldedWithSignedCmp() const override {
return false; return false;
} }
bool optimizeFallthroughsEarly() const override {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    bool optimizeFallthroughsEarly() const override {
-      return true;
-    }
+    bool optimizeFallthroughsEarly() const override { return true; }
Lint: Pre-merge checks: clang-format: please reformat the code ``` - bool optimizeFallthroughsEarly() const override…
return true;
}
bool hasAndNotCompare(SDValue) const override { bool hasAndNotCompare(SDValue) const override {
return true; return true;
} }
bool preferIncOfAddToSubOfNot(EVT VT) const override; bool preferIncOfAddToSubOfNot(EVT VT) const override;
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
return VT.isScalarInteger(); return VT.isScalarInteger();
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llvm/lib/Target/Sparc/SparcISelLowering.h

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Linesnamespace llvm {
class SparcTargetLowering : public TargetLowering { class SparcTargetLowering : public TargetLowering {
const SparcSubtarget *Subtarget; const SparcSubtarget *Subtarget;
public: public:
SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI); SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI);
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
bool useSoftFloat() const override; bool useSoftFloat() const override;
bool optimizeFallthroughsEarly() const override;
/// computeKnownBitsForTargetNode - Determine which of the bits specified /// computeKnownBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the /// in Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets. /// KnownZero/KnownOne bitsets.
void computeKnownBitsForTargetNode(const SDValue Op, void computeKnownBitsForTargetNode(const SDValue Op,
KnownBits &Known, KnownBits &Known,
const APInt &DemandedElts, const APInt &DemandedElts,
const SelectionDAG &DAG, const SelectionDAG &DAG,
unsigned Depth = 0) const override; unsigned Depth = 0) const override;
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llvm/lib/Target/Sparc/SparcISelLowering.cpp

Show First 20 Lines • Show All 1,820 Lines • ▼ Show 20 LinesSparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
computeRegisterProperties(Subtarget->getRegisterInfo()); computeRegisterProperties(Subtarget->getRegisterInfo());
} }
bool SparcTargetLowering::useSoftFloat() const { bool SparcTargetLowering::useSoftFloat() const {
return Subtarget->useSoftFloat(); return Subtarget->useSoftFloat();
} }
bool SparcTargetLowering::optimizeFallthroughsEarly() const { return true; }
const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch ((SPISD::NodeType)Opcode) { switch ((SPISD::NodeType)Opcode) {
case SPISD::FIRST_NUMBER: break; case SPISD::FIRST_NUMBER: break;
case SPISD::CMPICC: return "SPISD::CMPICC"; case SPISD::CMPICC: return "SPISD::CMPICC";
case SPISD::CMPFCC: return "SPISD::CMPFCC"; case SPISD::CMPFCC: return "SPISD::CMPFCC";
case SPISD::BRICC: return "SPISD::BRICC"; case SPISD::BRICC: return "SPISD::BRICC";
case SPISD::BRXCC: return "SPISD::BRXCC"; case SPISD::BRXCC: return "SPISD::BRXCC";
case SPISD::BRFCC: return "SPISD::BRFCC"; case SPISD::BRFCC: return "SPISD::BRFCC";
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llvm/lib/Target/SystemZ/SystemZISelLowering.h

Show First 20 Lines • Show All 427 Lines • ▼ Show 20 Lines getNumRegisters(LLVMContext &Context, EVT VT,
// i128 inline assembly operand. // i128 inline assembly operand.
if (VT == MVT::i128 && if (VT == MVT::i128 &&
RegisterVT.hasValue() && RegisterVT.getValue() == MVT::Untyped) RegisterVT.hasValue() && RegisterVT.getValue() == MVT::Untyped)
return 1; return 1;
return TargetLowering::getNumRegisters(Context, VT); return TargetLowering::getNumRegisters(Context, VT);
} }
bool isCheapToSpeculateCtlz() const override { return true; } bool isCheapToSpeculateCtlz() const override { return true; }
bool preferZeroCompareBranch() const override { return true; } bool preferZeroCompareBranch() const override { return true; }
bool optimizeFallthroughsEarly() const override { return true; }
bool hasBitPreservingFPLogic(EVT VT) const override { bool hasBitPreservingFPLogic(EVT VT) const override {
EVT ScVT = VT.getScalarType(); EVT ScVT = VT.getScalarType();
return ScVT == MVT::f32 || ScVT == MVT::f64 || ScVT == MVT::f128; return ScVT == MVT::f32 || ScVT == MVT::f64 || ScVT == MVT::f128;
} }
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override { bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override {
ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1)); ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));
return Mask && Mask->getValue().isIntN(16); return Mask && Mask->getValue().isIntN(16);
} }
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llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Linesprivate:
EmitInstrWithCustomInserter(MachineInstr &MI, EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *MBB) const override; MachineBasicBlock *MBB) const override;
const char *getTargetNodeName(unsigned Opcode) const override; const char *getTargetNodeName(unsigned Opcode) const override;
std::pair<unsigned, const TargetRegisterClass *> std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override; StringRef Constraint, MVT VT) const override;
bool isCheapToSpeculateCttz() const override; bool isCheapToSpeculateCttz() const override;
bool isCheapToSpeculateCtlz() const override; bool isCheapToSpeculateCtlz() const override;
bool optimizeFallthroughsEarly() const override;
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
unsigned AS, unsigned AS,
Instruction *I = nullptr) const override; Instruction *I = nullptr) const override;
bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, Align Alignment, bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, Align Alignment,
MachineMemOperand::Flags Flags, MachineMemOperand::Flags Flags,
bool *Fast) const override; bool *Fast) const override;
bool isIntDivCheap(EVT VT, AttributeList Attr) const override; bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
bool isVectorLoadExtDesirable(SDValue ExtVal) const override; bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
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llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

Show First 20 Lines • Show All 715 Lines • ▼ Show 20 Linesbool WebAssemblyTargetLowering::isCheapToSpeculateCttz() const {
return true; return true;
} }
bool WebAssemblyTargetLowering::isCheapToSpeculateCtlz() const { bool WebAssemblyTargetLowering::isCheapToSpeculateCtlz() const {
// Assume clz is a relatively cheap operation. // Assume clz is a relatively cheap operation.
return true; return true;
} }
bool WebAssemblyTargetLowering::optimizeFallthroughsEarly() const {
// Cannot disable this until WebAssemblyInstrInfo::analyzeBranch can optimize
// fallthroughs.
return true;
}
bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL, bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL,
const AddrMode &AM, const AddrMode &AM,
Type *Ty, unsigned AS, Type *Ty, unsigned AS,
Instruction *I) const { Instruction *I) const {
// WebAssembly offsets are added as unsigned without wrapping. The // WebAssembly offsets are added as unsigned without wrapping. The
// isLegalAddressingMode gives us no way to determine if wrapping could be // isLegalAddressingMode gives us no way to determine if wrapping could be
// happening, so we approximate this by accepting only non-negative offsets. // happening, so we approximate this by accepting only non-negative offsets.
if (AM.BaseOffs < 0) if (AM.BaseOffs < 0)
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llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Lines
; CHECK-LABEL: cmp_gt0: ; CHECK-LABEL: cmp_gt0:
; CHECK: ! %bb.0: ! %entry ; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: st %fp, [--%sp] ; CHECK-NEXT: st %fp, [--%sp]
; CHECK-NEXT: add %sp, 0x8, %fp ; CHECK-NEXT: add %sp, 0x8, %fp
; CHECK-NEXT: mov hi(t), %r3 ; CHECK-NEXT: mov hi(t), %r3
; CHECK-NEXT: or %r3, lo(t), %r3 ; CHECK-NEXT: or %r3, lo(t), %r3
; CHECK-NEXT: ld 0[%r3], %r3 ; CHECK-NEXT: ld 0[%r3], %r3
; CHECK-NEXT: sub %r3, 0x11, %r3 ; CHECK-NEXT: sub %r3, 0x11, %r3
; CHECK-NEXT: sub.f %r3, 0x1, %r0 ; CHECK-NEXT: sub.f %r3, 0x0, %r0
; CHECK-NEXT: blt .LBB6_2 ; CHECK-NEXT: ble .LBB6_2
; CHECK-NEXT: sub %sp, 0x10, %sp ; CHECK-NEXT: sub %sp, 0x10, %sp
; CHECK-NEXT: .LBB6_1: ! %if.then ; CHECK-NEXT: .LBB6_1: ! %if.then
; CHECK-NEXT: add %pc, 0x10, %rca ; CHECK-NEXT: add %pc, 0x10, %rca
; CHECK-NEXT: st %rca, [--%sp] ; CHECK-NEXT: st %rca, [--%sp]
; CHECK-NEXT: bt abort ; CHECK-NEXT: bt abort
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: .LBB6_2: ! %if.else ; CHECK-NEXT: .LBB6_2: ! %if.else
; CHECK-NEXT: st %r0, 0[%sp] ; CHECK-NEXT: st %r0, 0[%sp]
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llvm/test/CodeGen/RISCV/codemodel-lowering.ll

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; Check lowering of blockaddress that forces a displacement to be added ; Check lowering of blockaddress that forces a displacement to be added
define signext i32 @lower_blockaddress_displ(i32 signext %w) nounwind { define signext i32 @lower_blockaddress_displ(i32 signext %w) nounwind {
; RV32I-SMALL-LABEL: lower_blockaddress_displ: ; RV32I-SMALL-LABEL: lower_blockaddress_displ:
; RV32I-SMALL: # %bb.0: # %entry ; RV32I-SMALL: # %bb.0: # %entry
; RV32I-SMALL-NEXT: addi sp, sp, -16 ; RV32I-SMALL-NEXT: addi sp, sp, -16
; RV32I-SMALL-NEXT: lui a1, %hi(.Ltmp0) ; RV32I-SMALL-NEXT: lui a1, %hi(.Ltmp0)
; RV32I-SMALL-NEXT: addi a1, a1, %lo(.Ltmp0) ; RV32I-SMALL-NEXT: addi a1, a1, %lo(.Ltmp0)
; RV32I-SMALL-NEXT: addi a2, zero, 101 ; RV32I-SMALL-NEXT: addi a2, zero, 100
; RV32I-SMALL-NEXT: sw a1, 8(sp) ; RV32I-SMALL-NEXT: sw a1, 8(sp)
; RV32I-SMALL-NEXT: blt a0, a2, .LBB2_3 ; RV32I-SMALL-NEXT: bge a2, a0, .LBB2_3
; RV32I-SMALL-NEXT: # %bb.1: # %if.then ; RV32I-SMALL-NEXT: # %bb.1: # %if.then
; RV32I-SMALL-NEXT: lw a0, 8(sp) ; RV32I-SMALL-NEXT: lw a0, 8(sp)
; RV32I-SMALL-NEXT: jr a0 ; RV32I-SMALL-NEXT: jr a0
; RV32I-SMALL-NEXT: .Ltmp0: # Block address taken ; RV32I-SMALL-NEXT: .Ltmp0: # Block address taken
; RV32I-SMALL-NEXT: .LBB2_2: # %return ; RV32I-SMALL-NEXT: .LBB2_2: # %return
; RV32I-SMALL-NEXT: addi a0, zero, 4 ; RV32I-SMALL-NEXT: addi a0, zero, 4
; RV32I-SMALL-NEXT: addi sp, sp, 16 ; RV32I-SMALL-NEXT: addi sp, sp, 16
; RV32I-SMALL-NEXT: ret ; RV32I-SMALL-NEXT: ret
; RV32I-SMALL-NEXT: .LBB2_3: # %return.clone ; RV32I-SMALL-NEXT: .LBB2_3: # %return.clone
; RV32I-SMALL-NEXT: addi a0, zero, 3 ; RV32I-SMALL-NEXT: addi a0, zero, 3
; RV32I-SMALL-NEXT: addi sp, sp, 16 ; RV32I-SMALL-NEXT: addi sp, sp, 16
; RV32I-SMALL-NEXT: ret ; RV32I-SMALL-NEXT: ret
; ;
; RV32I-MEDIUM-LABEL: lower_blockaddress_displ: ; RV32I-MEDIUM-LABEL: lower_blockaddress_displ:
; RV32I-MEDIUM: # %bb.0: # %entry ; RV32I-MEDIUM: # %bb.0: # %entry
; RV32I-MEDIUM-NEXT: addi sp, sp, -16 ; RV32I-MEDIUM-NEXT: addi sp, sp, -16
; RV32I-MEDIUM-NEXT: .LBB2_4: # %entry ; RV32I-MEDIUM-NEXT: .LBB2_4: # %entry
; RV32I-MEDIUM-NEXT: # Label of block must be emitted ; RV32I-MEDIUM-NEXT: # Label of block must be emitted
; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.Ltmp0) ; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.Ltmp0)
; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB2_4) ; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB2_4)
; RV32I-MEDIUM-NEXT: addi a2, zero, 101 ; RV32I-MEDIUM-NEXT: addi a2, zero, 100
; RV32I-MEDIUM-NEXT: sw a1, 8(sp) ; RV32I-MEDIUM-NEXT: sw a1, 8(sp)
; RV32I-MEDIUM-NEXT: blt a0, a2, .LBB2_3 ; RV32I-MEDIUM-NEXT: bge a2, a0, .LBB2_3
; RV32I-MEDIUM-NEXT: # %bb.1: # %if.then ; RV32I-MEDIUM-NEXT: # %bb.1: # %if.then
; RV32I-MEDIUM-NEXT: lw a0, 8(sp) ; RV32I-MEDIUM-NEXT: lw a0, 8(sp)
; RV32I-MEDIUM-NEXT: jr a0 ; RV32I-MEDIUM-NEXT: jr a0
; RV32I-MEDIUM-NEXT: .Ltmp0: # Block address taken ; RV32I-MEDIUM-NEXT: .Ltmp0: # Block address taken
; RV32I-MEDIUM-NEXT: .LBB2_2: # %return ; RV32I-MEDIUM-NEXT: .LBB2_2: # %return
; RV32I-MEDIUM-NEXT: addi a0, zero, 4 ; RV32I-MEDIUM-NEXT: addi a0, zero, 4
; RV32I-MEDIUM-NEXT: addi sp, sp, 16 ; RV32I-MEDIUM-NEXT: addi sp, sp, 16
; RV32I-MEDIUM-NEXT: ret ; RV32I-MEDIUM-NEXT: ret
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llvm/test/CodeGen/RISCV/double-br-fcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
declare void @abort() declare void @abort()
declare void @exit(i32) declare void @exit(i32)
define void @br_fcmp_false(double %a, double %b) nounwind { define void @br_fcmp_false(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_false: ; RV32IFD-LABEL: br_fcmp_false:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi a0, zero, 1 ; RV32IFD-NEXT: beqz zero, .LBB0_2
; RV32IFD-NEXT: bnez a0, .LBB0_2
; RV32IFD-NEXT: # %bb.1: # %if.then ; RV32IFD-NEXT: # %bb.1: # %if.then
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB0_2: # %if.else ; RV32IFD-NEXT: .LBB0_2: # %if.else
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call abort@plt ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_false: ; RV64IFD-LABEL: br_fcmp_false:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi a0, zero, 1 ; RV64IFD-NEXT: beqz zero, .LBB0_2
; RV64IFD-NEXT: bnez a0, .LBB0_2
; RV64IFD-NEXT: # %bb.1: # %if.then ; RV64IFD-NEXT: # %bb.1: # %if.then
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB0_2: # %if.else ; RV64IFD-NEXT: .LBB0_2: # %if.else
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call abort@plt ; RV64IFD-NEXT: call abort@plt
%1 = fcmp false double %a, %b %1 = fcmp false double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
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llvm/test/CodeGen/RISCV/double-previous-failure.ll

Show All 13 Lines
define i32 @main() nounwind { define i32 @main() nounwind {
; RV32IFD-LABEL: main: ; RV32IFD-LABEL: main:
; RV32IFD: # %bb.0: # %entry ; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a1, 262144 ; RV32IFD-NEXT: lui a1, 262144
; RV32IFD-NEXT: mv a0, zero ; RV32IFD-NEXT: mv a0, zero
; RV32IFD-NEXT: call test ; RV32IFD-NEXT: call test@plt
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IFD-NEXT: fld ft1, %lo(.LCPI1_0)(a0) ; RV32IFD-NEXT: fld ft1, %lo(.LCPI1_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
; RV32IFD-NEXT: fld ft2, %lo(.LCPI1_1)(a0) ; RV32IFD-NEXT: fld ft2, %lo(.LCPI1_1)(a0)
; RV32IFD-NEXT: flt.d a0, ft0, ft1 ; RV32IFD-NEXT: flt.d a0, ft0, ft1
; RV32IFD-NEXT: not a0, a0
; RV32IFD-NEXT: flt.d a1, ft2, ft0 ; RV32IFD-NEXT: flt.d a1, ft2, ft0
; RV32IFD-NEXT: xori a1, a1, 1 ; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: and a0, a0, a1 ; RV32IFD-NEXT: beqz a0, .LBB1_2
; RV32IFD-NEXT: bnez a0, .LBB1_2
; RV32IFD-NEXT: # %bb.1: # %if.then ; RV32IFD-NEXT: # %bb.1: # %if.then
; RV32IFD-NEXT: call abort@plt ; RV32IFD-NEXT: call abort@plt
; RV32IFD-NEXT: .LBB1_2: # %if.end ; RV32IFD-NEXT: .LBB1_2: # %if.end
; RV32IFD-NEXT: mv a0, zero ; RV32IFD-NEXT: mv a0, zero
; RV32IFD-NEXT: call exit@plt ; RV32IFD-NEXT: call exit@plt
entry: entry:
%call = call double @test(double 2.000000e+00) %call = call double @test(double 2.000000e+00)
%cmp = fcmp olt double %call, 2.400000e-01 %cmp = fcmp olt double %call, 2.400000e-01
Show All 16 Lines

llvm/test/CodeGen/RISCV/float-br-fcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: | FileCheck -check-prefix=RV64IF %s
declare void @abort() declare void @abort()
declare void @exit(i32) declare void @exit(i32)
declare float @dummy(float) declare float @dummy(float)
define void @br_fcmp_false(float %a, float %b) nounwind { define void @br_fcmp_false(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_false: ; RV32IF-LABEL: br_fcmp_false:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi a0, zero, 1 ; RV32IF-NEXT: beqz zero, .LBB0_2
; RV32IF-NEXT: bnez a0, .LBB0_2
; RV32IF-NEXT: # %bb.1: # %if.then ; RV32IF-NEXT: # %bb.1: # %if.then
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB0_2: # %if.else ; RV32IF-NEXT: .LBB0_2: # %if.else
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort@plt ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_false: ; RV64IF-LABEL: br_fcmp_false:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi a0, zero, 1 ; RV64IF-NEXT: beqz zero, .LBB0_2
; RV64IF-NEXT: bnez a0, .LBB0_2
; RV64IF-NEXT: # %bb.1: # %if.then ; RV64IF-NEXT: # %bb.1: # %if.then
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB0_2: # %if.else ; RV64IF-NEXT: .LBB0_2: # %if.else
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort@plt ; RV64IF-NEXT: call abort@plt
%1 = fcmp false float %a, %b %1 = fcmp false float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
▲ Show 20 Lines • Show All 663 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/half-br-fcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s ; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
declare void @abort() declare void @abort()
declare void @exit(i32) declare void @exit(i32)
declare half @dummy(half) declare half @dummy(half)
define void @br_fcmp_false(half %a, half %b) nounwind { define void @br_fcmp_false(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_false: ; RV32IZFH-LABEL: br_fcmp_false:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi a0, zero, 1 ; RV32IZFH-NEXT: beqz zero, .LBB0_2
; RV32IZFH-NEXT: bnez a0, .LBB0_2
; RV32IZFH-NEXT: # %bb.1: # %if.then ; RV32IZFH-NEXT: # %bb.1: # %if.then
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB0_2: # %if.else ; RV32IZFH-NEXT: .LBB0_2: # %if.else
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: call abort@plt ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_false: ; RV64IZFH-LABEL: br_fcmp_false:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi a0, zero, 1 ; RV64IZFH-NEXT: beqz zero, .LBB0_2
; RV64IZFH-NEXT: bnez a0, .LBB0_2
; RV64IZFH-NEXT: # %bb.1: # %if.then ; RV64IZFH-NEXT: # %bb.1: # %if.then
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB0_2: # %if.else ; RV64IZFH-NEXT: .LBB0_2: # %if.else
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: call abort@plt ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp false half %a, %b %1 = fcmp false half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
▲ Show 20 Lines • Show All 522 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/jumptable.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I-SMALL ; RUN: | FileCheck %s -check-prefix=RV32I-SMALL
; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I-MEDIUM ; RUN: | FileCheck %s -check-prefix=RV32I-MEDIUM
; RUN: llc -mtriple=riscv64 -code-model=small -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -code-model=small -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I-SMALL ; RUN: | FileCheck %s -check-prefix=RV64I-SMALL
; RUN: llc -mtriple=riscv64 -code-model=medium -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -code-model=medium -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I-MEDIUM ; RUN: | FileCheck %s -check-prefix=RV64I-MEDIUM
define void @below_threshold(i32 %in, i32* %out) nounwind { define void @below_threshold(i32 %in, i32* %out) nounwind {
; RV32I-SMALL-LABEL: below_threshold: ; RV32I-SMALL-LABEL: below_threshold:
; RV32I-SMALL: # %bb.0: # %entry ; RV32I-SMALL: # %bb.0: # %entry
; RV32I-SMALL-NEXT: addi a2, zero, 2 ; RV32I-SMALL-NEXT: addi a2, zero, 3
; RV32I-SMALL-NEXT: blt a2, a0, .LBB0_4 ; RV32I-SMALL-NEXT: bge a0, a2, .LBB0_4
; RV32I-SMALL-NEXT: # %bb.1: # %entry ; RV32I-SMALL-NEXT: # %bb.1: # %entry
; RV32I-SMALL-NEXT: addi a2, zero, 1 ; RV32I-SMALL-NEXT: addi a2, zero, 1
; RV32I-SMALL-NEXT: beq a0, a2, .LBB0_7 ; RV32I-SMALL-NEXT: beq a0, a2, .LBB0_7
; RV32I-SMALL-NEXT: # %bb.2: # %entry ; RV32I-SMALL-NEXT: # %bb.2: # %entry
; RV32I-SMALL-NEXT: addi a2, zero, 2 ; RV32I-SMALL-NEXT: addi a2, zero, 2
; RV32I-SMALL-NEXT: bne a0, a2, .LBB0_10 ; RV32I-SMALL-NEXT: bne a0, a2, .LBB0_10
; RV32I-SMALL-NEXT: # %bb.3: # %bb2 ; RV32I-SMALL-NEXT: # %bb.3: # %bb2
; RV32I-SMALL-NEXT: addi a0, zero, 3 ; RV32I-SMALL-NEXT: addi a0, zero, 3
; RV32I-SMALL-NEXT: j .LBB0_9 ; RV32I-SMALL-NEXT: j .LBB0_9
; RV32I-SMALL-NEXT: .LBB0_4: # %entry ; RV32I-SMALL-NEXT: .LBB0_4: # %entry
; RV32I-SMALL-NEXT: addi a2, zero, 3
; RV32I-SMALL-NEXT: beq a0, a2, .LBB0_8 ; RV32I-SMALL-NEXT: beq a0, a2, .LBB0_8
; RV32I-SMALL-NEXT: # %bb.5: # %entry ; RV32I-SMALL-NEXT: # %bb.5: # %entry
; RV32I-SMALL-NEXT: addi a2, zero, 4 ; RV32I-SMALL-NEXT: addi a2, zero, 4
; RV32I-SMALL-NEXT: bne a0, a2, .LBB0_10 ; RV32I-SMALL-NEXT: bne a0, a2, .LBB0_10
; RV32I-SMALL-NEXT: # %bb.6: # %bb4 ; RV32I-SMALL-NEXT: # %bb.6: # %bb4
; RV32I-SMALL-NEXT: addi a0, zero, 1 ; RV32I-SMALL-NEXT: addi a0, zero, 1
; RV32I-SMALL-NEXT: j .LBB0_9 ; RV32I-SMALL-NEXT: j .LBB0_9
; RV32I-SMALL-NEXT: .LBB0_7: # %bb1 ; RV32I-SMALL-NEXT: .LBB0_7: # %bb1
; RV32I-SMALL-NEXT: addi a0, zero, 4 ; RV32I-SMALL-NEXT: addi a0, zero, 4
; RV32I-SMALL-NEXT: j .LBB0_9 ; RV32I-SMALL-NEXT: j .LBB0_9
; RV32I-SMALL-NEXT: .LBB0_8: # %bb3 ; RV32I-SMALL-NEXT: .LBB0_8: # %bb3
; RV32I-SMALL-NEXT: addi a0, zero, 2 ; RV32I-SMALL-NEXT: addi a0, zero, 2
; RV32I-SMALL-NEXT: .LBB0_9: # %exit ; RV32I-SMALL-NEXT: .LBB0_9: # %exit
; RV32I-SMALL-NEXT: sw a0, 0(a1) ; RV32I-SMALL-NEXT: sw a0, 0(a1)
; RV32I-SMALL-NEXT: .LBB0_10: # %exit ; RV32I-SMALL-NEXT: .LBB0_10: # %exit
; RV32I-SMALL-NEXT: ret ; RV32I-SMALL-NEXT: ret
; ;
; RV32I-MEDIUM-LABEL: below_threshold: ; RV32I-MEDIUM-LABEL: below_threshold:
; RV32I-MEDIUM: # %bb.0: # %entry ; RV32I-MEDIUM: # %bb.0: # %entry
; RV32I-MEDIUM-NEXT: addi a2, zero, 2 ; RV32I-MEDIUM-NEXT: addi a2, zero, 3
; RV32I-MEDIUM-NEXT: blt a2, a0, .LBB0_4 ; RV32I-MEDIUM-NEXT: bge a0, a2, .LBB0_4
; RV32I-MEDIUM-NEXT: # %bb.1: # %entry ; RV32I-MEDIUM-NEXT: # %bb.1: # %entry
; RV32I-MEDIUM-NEXT: addi a2, zero, 1 ; RV32I-MEDIUM-NEXT: addi a2, zero, 1
; RV32I-MEDIUM-NEXT: beq a0, a2, .LBB0_7 ; RV32I-MEDIUM-NEXT: beq a0, a2, .LBB0_7
; RV32I-MEDIUM-NEXT: # %bb.2: # %entry ; RV32I-MEDIUM-NEXT: # %bb.2: # %entry
; RV32I-MEDIUM-NEXT: addi a2, zero, 2 ; RV32I-MEDIUM-NEXT: addi a2, zero, 2
; RV32I-MEDIUM-NEXT: bne a0, a2, .LBB0_10 ; RV32I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
; RV32I-MEDIUM-NEXT: # %bb.3: # %bb2 ; RV32I-MEDIUM-NEXT: # %bb.3: # %bb2
; RV32I-MEDIUM-NEXT: addi a0, zero, 3 ; RV32I-MEDIUM-NEXT: addi a0, zero, 3
; RV32I-MEDIUM-NEXT: j .LBB0_9 ; RV32I-MEDIUM-NEXT: j .LBB0_9
; RV32I-MEDIUM-NEXT: .LBB0_4: # %entry ; RV32I-MEDIUM-NEXT: .LBB0_4: # %entry
; RV32I-MEDIUM-NEXT: addi a2, zero, 3
; RV32I-MEDIUM-NEXT: beq a0, a2, .LBB0_8 ; RV32I-MEDIUM-NEXT: beq a0, a2, .LBB0_8
; RV32I-MEDIUM-NEXT: # %bb.5: # %entry ; RV32I-MEDIUM-NEXT: # %bb.5: # %entry
; RV32I-MEDIUM-NEXT: addi a2, zero, 4 ; RV32I-MEDIUM-NEXT: addi a2, zero, 4
; RV32I-MEDIUM-NEXT: bne a0, a2, .LBB0_10 ; RV32I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
; RV32I-MEDIUM-NEXT: # %bb.6: # %bb4 ; RV32I-MEDIUM-NEXT: # %bb.6: # %bb4
; RV32I-MEDIUM-NEXT: addi a0, zero, 1 ; RV32I-MEDIUM-NEXT: addi a0, zero, 1
; RV32I-MEDIUM-NEXT: j .LBB0_9 ; RV32I-MEDIUM-NEXT: j .LBB0_9
; RV32I-MEDIUM-NEXT: .LBB0_7: # %bb1 ; RV32I-MEDIUM-NEXT: .LBB0_7: # %bb1
; RV32I-MEDIUM-NEXT: addi a0, zero, 4 ; RV32I-MEDIUM-NEXT: addi a0, zero, 4
; RV32I-MEDIUM-NEXT: j .LBB0_9 ; RV32I-MEDIUM-NEXT: j .LBB0_9
; RV32I-MEDIUM-NEXT: .LBB0_8: # %bb3 ; RV32I-MEDIUM-NEXT: .LBB0_8: # %bb3
; RV32I-MEDIUM-NEXT: addi a0, zero, 2 ; RV32I-MEDIUM-NEXT: addi a0, zero, 2
; RV32I-MEDIUM-NEXT: .LBB0_9: # %exit ; RV32I-MEDIUM-NEXT: .LBB0_9: # %exit
; RV32I-MEDIUM-NEXT: sw a0, 0(a1) ; RV32I-MEDIUM-NEXT: sw a0, 0(a1)
; RV32I-MEDIUM-NEXT: .LBB0_10: # %exit ; RV32I-MEDIUM-NEXT: .LBB0_10: # %exit
; RV32I-MEDIUM-NEXT: ret ; RV32I-MEDIUM-NEXT: ret
; ;
; RV64I-SMALL-LABEL: below_threshold: ; RV64I-SMALL-LABEL: below_threshold:
; RV64I-SMALL: # %bb.0: # %entry ; RV64I-SMALL: # %bb.0: # %entry
; RV64I-SMALL-NEXT: sext.w a0, a0 ; RV64I-SMALL-NEXT: sext.w a0, a0
; RV64I-SMALL-NEXT: addi a2, zero, 2 ; RV64I-SMALL-NEXT: addi a2, zero, 3
; RV64I-SMALL-NEXT: blt a2, a0, .LBB0_4 ; RV64I-SMALL-NEXT: bge a0, a2, .LBB0_4
; RV64I-SMALL-NEXT: # %bb.1: # %entry ; RV64I-SMALL-NEXT: # %bb.1: # %entry
; RV64I-SMALL-NEXT: addi a2, zero, 1 ; RV64I-SMALL-NEXT: addi a2, zero, 1
; RV64I-SMALL-NEXT: beq a0, a2, .LBB0_7 ; RV64I-SMALL-NEXT: beq a0, a2, .LBB0_7
; RV64I-SMALL-NEXT: # %bb.2: # %entry ; RV64I-SMALL-NEXT: # %bb.2: # %entry
; RV64I-SMALL-NEXT: addi a2, zero, 2 ; RV64I-SMALL-NEXT: addi a2, zero, 2
; RV64I-SMALL-NEXT: bne a0, a2, .LBB0_10 ; RV64I-SMALL-NEXT: bne a0, a2, .LBB0_10
; RV64I-SMALL-NEXT: # %bb.3: # %bb2 ; RV64I-SMALL-NEXT: # %bb.3: # %bb2
; RV64I-SMALL-NEXT: addi a0, zero, 3 ; RV64I-SMALL-NEXT: addi a0, zero, 3
; RV64I-SMALL-NEXT: j .LBB0_9 ; RV64I-SMALL-NEXT: j .LBB0_9
; RV64I-SMALL-NEXT: .LBB0_4: # %entry ; RV64I-SMALL-NEXT: .LBB0_4: # %entry
; RV64I-SMALL-NEXT: addi a2, zero, 3
; RV64I-SMALL-NEXT: beq a0, a2, .LBB0_8 ; RV64I-SMALL-NEXT: beq a0, a2, .LBB0_8
; RV64I-SMALL-NEXT: # %bb.5: # %entry ; RV64I-SMALL-NEXT: # %bb.5: # %entry
; RV64I-SMALL-NEXT: addi a2, zero, 4 ; RV64I-SMALL-NEXT: addi a2, zero, 4
; RV64I-SMALL-NEXT: bne a0, a2, .LBB0_10 ; RV64I-SMALL-NEXT: bne a0, a2, .LBB0_10
; RV64I-SMALL-NEXT: # %bb.6: # %bb4 ; RV64I-SMALL-NEXT: # %bb.6: # %bb4
; RV64I-SMALL-NEXT: addi a0, zero, 1 ; RV64I-SMALL-NEXT: addi a0, zero, 1
; RV64I-SMALL-NEXT: j .LBB0_9 ; RV64I-SMALL-NEXT: j .LBB0_9
; RV64I-SMALL-NEXT: .LBB0_7: # %bb1 ; RV64I-SMALL-NEXT: .LBB0_7: # %bb1
; RV64I-SMALL-NEXT: addi a0, zero, 4 ; RV64I-SMALL-NEXT: addi a0, zero, 4
; RV64I-SMALL-NEXT: j .LBB0_9 ; RV64I-SMALL-NEXT: j .LBB0_9
; RV64I-SMALL-NEXT: .LBB0_8: # %bb3 ; RV64I-SMALL-NEXT: .LBB0_8: # %bb3
; RV64I-SMALL-NEXT: addi a0, zero, 2 ; RV64I-SMALL-NEXT: addi a0, zero, 2
; RV64I-SMALL-NEXT: .LBB0_9: # %exit ; RV64I-SMALL-NEXT: .LBB0_9: # %exit
; RV64I-SMALL-NEXT: sw a0, 0(a1) ; RV64I-SMALL-NEXT: sw a0, 0(a1)
; RV64I-SMALL-NEXT: .LBB0_10: # %exit ; RV64I-SMALL-NEXT: .LBB0_10: # %exit
; RV64I-SMALL-NEXT: ret ; RV64I-SMALL-NEXT: ret
; ;
; RV64I-MEDIUM-LABEL: below_threshold: ; RV64I-MEDIUM-LABEL: below_threshold:
; RV64I-MEDIUM: # %bb.0: # %entry ; RV64I-MEDIUM: # %bb.0: # %entry
; RV64I-MEDIUM-NEXT: sext.w a0, a0 ; RV64I-MEDIUM-NEXT: sext.w a0, a0
; RV64I-MEDIUM-NEXT: addi a2, zero, 2 ; RV64I-MEDIUM-NEXT: addi a2, zero, 3
; RV64I-MEDIUM-NEXT: blt a2, a0, .LBB0_4 ; RV64I-MEDIUM-NEXT: bge a0, a2, .LBB0_4
; RV64I-MEDIUM-NEXT: # %bb.1: # %entry ; RV64I-MEDIUM-NEXT: # %bb.1: # %entry
; RV64I-MEDIUM-NEXT: addi a2, zero, 1 ; RV64I-MEDIUM-NEXT: addi a2, zero, 1
; RV64I-MEDIUM-NEXT: beq a0, a2, .LBB0_7 ; RV64I-MEDIUM-NEXT: beq a0, a2, .LBB0_7
; RV64I-MEDIUM-NEXT: # %bb.2: # %entry ; RV64I-MEDIUM-NEXT: # %bb.2: # %entry
; RV64I-MEDIUM-NEXT: addi a2, zero, 2 ; RV64I-MEDIUM-NEXT: addi a2, zero, 2
; RV64I-MEDIUM-NEXT: bne a0, a2, .LBB0_10 ; RV64I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
; RV64I-MEDIUM-NEXT: # %bb.3: # %bb2 ; RV64I-MEDIUM-NEXT: # %bb.3: # %bb2
; RV64I-MEDIUM-NEXT: addi a0, zero, 3 ; RV64I-MEDIUM-NEXT: addi a0, zero, 3
; RV64I-MEDIUM-NEXT: j .LBB0_9 ; RV64I-MEDIUM-NEXT: j .LBB0_9
; RV64I-MEDIUM-NEXT: .LBB0_4: # %entry ; RV64I-MEDIUM-NEXT: .LBB0_4: # %entry
; RV64I-MEDIUM-NEXT: addi a2, zero, 3
; RV64I-MEDIUM-NEXT: beq a0, a2, .LBB0_8 ; RV64I-MEDIUM-NEXT: beq a0, a2, .LBB0_8
; RV64I-MEDIUM-NEXT: # %bb.5: # %entry ; RV64I-MEDIUM-NEXT: # %bb.5: # %entry
; RV64I-MEDIUM-NEXT: addi a2, zero, 4 ; RV64I-MEDIUM-NEXT: addi a2, zero, 4
; RV64I-MEDIUM-NEXT: bne a0, a2, .LBB0_10 ; RV64I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
; RV64I-MEDIUM-NEXT: # %bb.6: # %bb4 ; RV64I-MEDIUM-NEXT: # %bb.6: # %bb4
; RV64I-MEDIUM-NEXT: addi a0, zero, 1 ; RV64I-MEDIUM-NEXT: addi a0, zero, 1
; RV64I-MEDIUM-NEXT: j .LBB0_9 ; RV64I-MEDIUM-NEXT: j .LBB0_9
; RV64I-MEDIUM-NEXT: .LBB0_7: # %bb1 ; RV64I-MEDIUM-NEXT: .LBB0_7: # %bb1
▲ Show 20 Lines • Show All 203 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/shrinkwrap.ll

Show All 9 Lines
declare void @abort() declare void @abort()
define void @eliminate_restore(i32 %n) nounwind { define void @eliminate_restore(i32 %n) nounwind {
; RV32I-SW-NO-LABEL: eliminate_restore: ; RV32I-SW-NO-LABEL: eliminate_restore:
; RV32I-SW-NO: # %bb.0: ; RV32I-SW-NO: # %bb.0:
; RV32I-SW-NO-NEXT: addi sp, sp, -16 ; RV32I-SW-NO-NEXT: addi sp, sp, -16
; RV32I-SW-NO-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-SW-NO-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-SW-NO-NEXT: addi a1, zero, 32 ; RV32I-SW-NO-NEXT: addi a1, zero, 33
; RV32I-SW-NO-NEXT: bgeu a1, a0, .LBB0_2 ; RV32I-SW-NO-NEXT: bltu a0, a1, .LBB0_2
; RV32I-SW-NO-NEXT: # %bb.1: # %if.end ; RV32I-SW-NO-NEXT: # %bb.1: # %if.end
; RV32I-SW-NO-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-SW-NO-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-SW-NO-NEXT: addi sp, sp, 16 ; RV32I-SW-NO-NEXT: addi sp, sp, 16
; RV32I-SW-NO-NEXT: ret ; RV32I-SW-NO-NEXT: ret
; RV32I-SW-NO-NEXT: .LBB0_2: # %if.then ; RV32I-SW-NO-NEXT: .LBB0_2: # %if.then
; RV32I-SW-NO-NEXT: call abort@plt ; RV32I-SW-NO-NEXT: call abort@plt
; ;
; RV32I-SW-LABEL: eliminate_restore: ; RV32I-SW-LABEL: eliminate_restore:
; RV32I-SW: # %bb.0: ; RV32I-SW: # %bb.0:
; RV32I-SW-NEXT: addi a1, zero, 32 ; RV32I-SW-NEXT: addi a1, zero, 33
; RV32I-SW-NEXT: bgeu a1, a0, .LBB0_2 ; RV32I-SW-NEXT: bltu a0, a1, .LBB0_2
; RV32I-SW-NEXT: # %bb.1: # %if.end ; RV32I-SW-NEXT: # %bb.1: # %if.end
; RV32I-SW-NEXT: ret ; RV32I-SW-NEXT: ret
; RV32I-SW-NEXT: .LBB0_2: # %if.then ; RV32I-SW-NEXT: .LBB0_2: # %if.then
; RV32I-SW-NEXT: addi sp, sp, -16 ; RV32I-SW-NEXT: addi sp, sp, -16
; RV32I-SW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-SW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-SW-NEXT: call abort@plt ; RV32I-SW-NEXT: call abort@plt
; ;
; RV32I-SW-SR-LABEL: eliminate_restore: ; RV32I-SW-SR-LABEL: eliminate_restore:
; RV32I-SW-SR: # %bb.0: ; RV32I-SW-SR: # %bb.0:
; RV32I-SW-SR-NEXT: addi a1, zero, 32 ; RV32I-SW-SR-NEXT: addi a1, zero, 33
; RV32I-SW-SR-NEXT: bgeu a1, a0, .LBB0_2 ; RV32I-SW-SR-NEXT: bltu a0, a1, .LBB0_2
; RV32I-SW-SR-NEXT: # %bb.1: # %if.end ; RV32I-SW-SR-NEXT: # %bb.1: # %if.end
; RV32I-SW-SR-NEXT: ret ; RV32I-SW-SR-NEXT: ret
; RV32I-SW-SR-NEXT: .LBB0_2: # %if.then ; RV32I-SW-SR-NEXT: .LBB0_2: # %if.then
; RV32I-SW-SR-NEXT: call t0, __riscv_save_0 ; RV32I-SW-SR-NEXT: call t0, __riscv_save_0
; RV32I-SW-SR-NEXT: call abort@plt ; RV32I-SW-SR-NEXT: call abort@plt
; ;
; RV64I-SW-LABEL: eliminate_restore: ; RV64I-SW-LABEL: eliminate_restore:
; RV64I-SW: # %bb.0: ; RV64I-SW: # %bb.0:
; RV64I-SW-NEXT: sext.w a0, a0 ; RV64I-SW-NEXT: sext.w a0, a0
; RV64I-SW-NEXT: addi a1, zero, 32 ; RV64I-SW-NEXT: addi a1, zero, 33
; RV64I-SW-NEXT: bgeu a1, a0, .LBB0_2 ; RV64I-SW-NEXT: bltu a0, a1, .LBB0_2
; RV64I-SW-NEXT: # %bb.1: # %if.end ; RV64I-SW-NEXT: # %bb.1: # %if.end
; RV64I-SW-NEXT: ret ; RV64I-SW-NEXT: ret
; RV64I-SW-NEXT: .LBB0_2: # %if.then ; RV64I-SW-NEXT: .LBB0_2: # %if.then
; RV64I-SW-NEXT: addi sp, sp, -16 ; RV64I-SW-NEXT: addi sp, sp, -16
; RV64I-SW-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-SW-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-SW-NEXT: call abort@plt ; RV64I-SW-NEXT: call abort@plt
%cmp = icmp ule i32 %n, 32 %cmp = icmp ule i32 %n, 32
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
Show All 10 Lines
define void @conditional_alloca(i32 %n) nounwind { define void @conditional_alloca(i32 %n) nounwind {
; RV32I-SW-NO-LABEL: conditional_alloca: ; RV32I-SW-NO-LABEL: conditional_alloca:
; RV32I-SW-NO: # %bb.0: ; RV32I-SW-NO: # %bb.0:
; RV32I-SW-NO-NEXT: addi sp, sp, -16 ; RV32I-SW-NO-NEXT: addi sp, sp, -16
; RV32I-SW-NO-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-SW-NO-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-SW-NO-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-SW-NO-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-SW-NO-NEXT: addi s0, sp, 16 ; RV32I-SW-NO-NEXT: addi s0, sp, 16
; RV32I-SW-NO-NEXT: addi a1, zero, 32 ; RV32I-SW-NO-NEXT: addi a1, zero, 33
; RV32I-SW-NO-NEXT: bltu a1, a0, .LBB1_2 ; RV32I-SW-NO-NEXT: bgeu a0, a1, .LBB1_2
; RV32I-SW-NO-NEXT: # %bb.1: # %if.then ; RV32I-SW-NO-NEXT: # %bb.1: # %if.then
; RV32I-SW-NO-NEXT: addi a0, a0, 15 ; RV32I-SW-NO-NEXT: addi a0, a0, 15
; RV32I-SW-NO-NEXT: andi a0, a0, -16 ; RV32I-SW-NO-NEXT: andi a0, a0, -16
; RV32I-SW-NO-NEXT: sub a0, sp, a0 ; RV32I-SW-NO-NEXT: sub a0, sp, a0
; RV32I-SW-NO-NEXT: mv sp, a0 ; RV32I-SW-NO-NEXT: mv sp, a0
; RV32I-SW-NO-NEXT: call notdead@plt ; RV32I-SW-NO-NEXT: call notdead@plt
; RV32I-SW-NO-NEXT: .LBB1_2: # %if.end ; RV32I-SW-NO-NEXT: .LBB1_2: # %if.end
; RV32I-SW-NO-NEXT: addi sp, s0, -16 ; RV32I-SW-NO-NEXT: addi sp, s0, -16
; RV32I-SW-NO-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-SW-NO-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-SW-NO-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-SW-NO-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-SW-NO-NEXT: addi sp, sp, 16 ; RV32I-SW-NO-NEXT: addi sp, sp, 16
; RV32I-SW-NO-NEXT: ret ; RV32I-SW-NO-NEXT: ret
; ;
; RV32I-SW-LABEL: conditional_alloca: ; RV32I-SW-LABEL: conditional_alloca:
; RV32I-SW: # %bb.0: ; RV32I-SW: # %bb.0:
; RV32I-SW-NEXT: addi a1, zero, 32 ; RV32I-SW-NEXT: addi a1, zero, 33
; RV32I-SW-NEXT: bltu a1, a0, .LBB1_2 ; RV32I-SW-NEXT: bgeu a0, a1, .LBB1_2
; RV32I-SW-NEXT: # %bb.1: # %if.then ; RV32I-SW-NEXT: # %bb.1: # %if.then
; RV32I-SW-NEXT: addi sp, sp, -16 ; RV32I-SW-NEXT: addi sp, sp, -16
; RV32I-SW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-SW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-SW-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-SW-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-SW-NEXT: addi s0, sp, 16 ; RV32I-SW-NEXT: addi s0, sp, 16
; RV32I-SW-NEXT: addi a0, a0, 15 ; RV32I-SW-NEXT: addi a0, a0, 15
; RV32I-SW-NEXT: andi a0, a0, -16 ; RV32I-SW-NEXT: andi a0, a0, -16
; RV32I-SW-NEXT: sub a0, sp, a0 ; RV32I-SW-NEXT: sub a0, sp, a0
; RV32I-SW-NEXT: mv sp, a0 ; RV32I-SW-NEXT: mv sp, a0
; RV32I-SW-NEXT: call notdead@plt ; RV32I-SW-NEXT: call notdead@plt
; RV32I-SW-NEXT: addi sp, s0, -16 ; RV32I-SW-NEXT: addi sp, s0, -16
; RV32I-SW-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-SW-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-SW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-SW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-SW-NEXT: addi sp, sp, 16 ; RV32I-SW-NEXT: addi sp, sp, 16
; RV32I-SW-NEXT: .LBB1_2: # %if.end ; RV32I-SW-NEXT: .LBB1_2: # %if.end
; RV32I-SW-NEXT: ret ; RV32I-SW-NEXT: ret
; ;
; RV32I-SW-SR-LABEL: conditional_alloca: ; RV32I-SW-SR-LABEL: conditional_alloca:
; RV32I-SW-SR: # %bb.0: ; RV32I-SW-SR: # %bb.0:
; RV32I-SW-SR-NEXT: addi a1, zero, 32 ; RV32I-SW-SR-NEXT: addi a1, zero, 33
; RV32I-SW-SR-NEXT: bltu a1, a0, .LBB1_2 ; RV32I-SW-SR-NEXT: bgeu a0, a1, .LBB1_2
; RV32I-SW-SR-NEXT: # %bb.1: # %if.then ; RV32I-SW-SR-NEXT: # %bb.1: # %if.then
; RV32I-SW-SR-NEXT: call t0, __riscv_save_1 ; RV32I-SW-SR-NEXT: call t0, __riscv_save_1
; RV32I-SW-SR-NEXT: addi s0, sp, 16 ; RV32I-SW-SR-NEXT: addi s0, sp, 16
; RV32I-SW-SR-NEXT: addi a0, a0, 15 ; RV32I-SW-SR-NEXT: addi a0, a0, 15
; RV32I-SW-SR-NEXT: andi a0, a0, -16 ; RV32I-SW-SR-NEXT: andi a0, a0, -16
; RV32I-SW-SR-NEXT: sub a0, sp, a0 ; RV32I-SW-SR-NEXT: sub a0, sp, a0
; RV32I-SW-SR-NEXT: mv sp, a0 ; RV32I-SW-SR-NEXT: mv sp, a0
; RV32I-SW-SR-NEXT: call notdead@plt ; RV32I-SW-SR-NEXT: call notdead@plt
; RV32I-SW-SR-NEXT: addi sp, s0, -16 ; RV32I-SW-SR-NEXT: addi sp, s0, -16
; RV32I-SW-SR-NEXT: tail __riscv_restore_1 ; RV32I-SW-SR-NEXT: tail __riscv_restore_1
; RV32I-SW-SR-NEXT: .LBB1_2: # %if.end ; RV32I-SW-SR-NEXT: .LBB1_2: # %if.end
; RV32I-SW-SR-NEXT: ret ; RV32I-SW-SR-NEXT: ret
; ;
; RV64I-SW-LABEL: conditional_alloca: ; RV64I-SW-LABEL: conditional_alloca:
; RV64I-SW: # %bb.0: ; RV64I-SW: # %bb.0:
; RV64I-SW-NEXT: sext.w a1, a0 ; RV64I-SW-NEXT: sext.w a1, a0
; RV64I-SW-NEXT: addi a2, zero, 32 ; RV64I-SW-NEXT: addi a2, zero, 33
; RV64I-SW-NEXT: bltu a2, a1, .LBB1_2 ; RV64I-SW-NEXT: bgeu a1, a2, .LBB1_2
; RV64I-SW-NEXT: # %bb.1: # %if.then ; RV64I-SW-NEXT: # %bb.1: # %if.then
; RV64I-SW-NEXT: addi sp, sp, -16 ; RV64I-SW-NEXT: addi sp, sp, -16
; RV64I-SW-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-SW-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-SW-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-SW-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-SW-NEXT: addi s0, sp, 16 ; RV64I-SW-NEXT: addi s0, sp, 16
; RV64I-SW-NEXT: slli a0, a0, 32 ; RV64I-SW-NEXT: slli a0, a0, 32
; RV64I-SW-NEXT: srli a0, a0, 32 ; RV64I-SW-NEXT: srli a0, a0, 32
; RV64I-SW-NEXT: addi a0, a0, 15 ; RV64I-SW-NEXT: addi a0, a0, 15
Show All 21 Lines

llvm/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mcpu=i386 | FileCheck %s ; RUN: llc < %s -mtriple=i686-- -mcpu=i386 | FileCheck %s
define i32 @foo(i32 %t, i32 %C) { define i32 @foo(i32 %t, i32 %C) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: decl %eax ; CHECK-NEXT: decl %eax
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %cond_true ; CHECK-NEXT: .LBB0_1: # %cond_true
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: incl %eax ; CHECK-NEXT: incl %eax
; CHECK-NEXT: cmpl $40, %ecx ; CHECK-NEXT: cmpl $39, %ecx
; CHECK-NEXT: jl .LBB0_1 ; CHECK-NEXT: jle .LBB0_1
RKSimonUnsubmitted
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This kind of thing is going to increase EFLAGS usage - I addressed this for CMOVs + SETs with SGT/UGT in D101074 but haven't had time to address JMP/BRANCH, or add the SLE/ULE equivalent yet.

RKSimon: This kind of thing is going to increase EFLAGS usage - I addressed this for CMOVs + SETs with…
MatzeBAuthorUnsubmitted
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This kind of thing is going to increase EFLAGS usage

Wow, I was not aware that affects performance. Does that mean MachineCodePlacement / analyzeBranch can pessimize code when it flips the true/false branches and negates the condition of a jump?

MatzeB: > This kind of thing is going to increase EFLAGS usage Wow, I was not aware that affects…
craig.topperUnsubmitted
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At least on Intel CPUs, I'm not aware of a performance issue for jumps. There is an extra uop for CMOV and SETCC conditions that use the C flag and Z flag. That would cmovbe, cmova, setbe, and seta. There is no extra uop for branches on the same conditions.

I can't speak to AMD CPUs.

craig.topper: At least on Intel CPUs, I'm not aware of a performance issue for jumps. There is an extra uop…
RKSimonUnsubmitted
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Its often tricky to see the effect of this in real world code, but yes we should always be trying to minimize the number of EFLAGS bits we depend on. Some x86 cpus split the dependencies into individual/groups of bits, others keep them together, its quite a mess and isn't something we've properly tried to model......

I'll see if I can resurrect the followups to D101074 - iirc I encountered a similar mammoth test churn to you in this patch.

RKSimon: Its often tricky to see the effect of this in real world code, but yes we should always be…
; CHECK-NEXT: # %bb.2: # %bb12 ; CHECK-NEXT: # %bb.2: # %bb12
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
br label %cond_true br label %cond_true
cond_true: ; preds = %cond_true, %entry cond_true: ; preds = %cond_true, %entry
%t_addr.0.0 = phi i32 [ %t, %entry ], [ %tmp7, %cond_true ] ; <i32> [#uses=2] %t_addr.0.0 = phi i32 [ %t, %entry ], [ %tmp7, %cond_true ] ; <i32> [#uses=2]
%tmp7 = add i32 %t_addr.0.0, 1 ; <i32> [#uses=1] %tmp7 = add i32 %t_addr.0.0, 1 ; <i32> [#uses=1]
%tmp = icmp sgt i32 %C, 39 ; <i1> [#uses=1] %tmp = icmp sgt i32 %C, 39 ; <i1> [#uses=1]
br i1 %tmp, label %bb12, label %cond_true br i1 %tmp, label %bb12, label %cond_true
bb12: ; preds = %cond_true bb12: ; preds = %cond_true
ret i32 %t_addr.0.0 ret i32 %t_addr.0.0
} }

llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
define void @handle_vector_size_attribute() nounwind { define void @handle_vector_size_attribute() nounwind {
; CHECK-LABEL: handle_vector_size_attribute: ; CHECK-LABEL: handle_vector_size_attribute:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl 0, %eax ; CHECK-NEXT: movl 0, %eax
; CHECK-NEXT: decl %eax ; CHECK-NEXT: decl %eax
; CHECK-NEXT: cmpl $1, %eax ; CHECK-NEXT: cmpl $2, %eax
; CHECK-NEXT: ja .LBB0_2 ; CHECK-NEXT: jae .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb77 ; CHECK-NEXT: # %bb.1: # %bb77
; CHECK-NEXT: movb 0, %al ; CHECK-NEXT: movb 0, %al
; CHECK-NEXT: movb 0, %al ; CHECK-NEXT: movb 0, %al
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: .LBB0_2: # %bb84 ; CHECK-NEXT: .LBB0_2: # %bb84
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
Show All 35 Lines

llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll

Show All 10 Lines
; CHECK: # %bb.0: # %b ; CHECK: # %bb.0: # %b
; CHECK-NEXT: pushq %rbp ; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbp, -16 ; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rsp, %rbp ; CHECK-NEXT: movq %rsp, %rbp
; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: movslq (%rdi), %rdi ; CHECK-NEXT: movslq (%rdi), %rdi
; CHECK-NEXT: movslq (%rsi), %r8 ; CHECK-NEXT: movslq (%rsi), %r8
; CHECK-NEXT: movslq (%rdx), %r10 ; CHECK-NEXT: movslq (%rdx), %rax
; CHECK-NEXT: movl (%rcx), %esi ; CHECK-NEXT: movl (%rcx), %esi
; CHECK-NEXT: movq %rsp, %rcx ; CHECK-NEXT: movq %rsp, %rcx
; CHECK-NEXT: subl %edi, %r8d ; CHECK-NEXT: subl %edi, %r8d
; CHECK-NEXT: movslq %r8d, %rdx ; CHECK-NEXT: movslq %r8d, %rdx
; CHECK-NEXT: js .LBB0_1 ; CHECK-NEXT: js .LBB0_1
; CHECK-NEXT: # %bb.11: # %b63 ; CHECK-NEXT: # %bb.11: # %b63
; CHECK-NEXT: testq %rdx, %rdx ; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: js .LBB0_14 ; CHECK-NEXT: js .LBB0_14
; CHECK-NEXT: # %bb.12: ; CHECK-NEXT: # %bb.12:
; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_13: # %a25b ; CHECK-NEXT: .LBB0_13: # %a25b
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: je .LBB0_13 ; CHECK-NEXT: je .LBB0_13
; CHECK-NEXT: .LBB0_14: # %b85 ; CHECK-NEXT: .LBB0_14: # %b85
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: jne .LBB0_1 ; CHECK-NEXT: je .LBB0_1
; CHECK-NEXT: # %bb.15: ; CHECK-NEXT: # %bb.15:
; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_16: # %a25b140 ; CHECK-NEXT: .LBB0_16: # %a25b140
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: je .LBB0_16 ; CHECK-NEXT: je .LBB0_16
; CHECK-NEXT: .LBB0_1: # %a29b ; CHECK-NEXT: .LBB0_1: # %a29b
; CHECK-NEXT: cmpl %r10d, %esi ; CHECK-NEXT: cmpl %eax, %esi
; CHECK-NEXT: js .LBB0_10 ; CHECK-NEXT: js .LBB0_10
; CHECK-NEXT: # %bb.2: # %b158 ; CHECK-NEXT: # %bb.2: # %b158
; CHECK-NEXT: movslq (%r9), %rsi ; CHECK-NEXT: movslq (%r9), %rsi
; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movb $1, %r9b
; CHECK-NEXT: jmp .LBB0_3 ; CHECK-NEXT: jmp .LBB0_3
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_9: # %b1606 ; CHECK-NEXT: .LBB0_9: # %b1606
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: je .LBB0_10 ; CHECK-NEXT: je .LBB0_10
; CHECK-NEXT: .LBB0_3: # %a29b173 ; CHECK-NEXT: .LBB0_3: # %a29b173
; CHECK-NEXT: # =>This Loop Header: Depth=1 ; CHECK-NEXT: # =>This Loop Header: Depth=1
Show All 20 Lines
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_37: # %a30b ; CHECK-NEXT: .LBB0_37: # %a30b
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 ; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2
; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: je .LBB0_37 ; CHECK-NEXT: je .LBB0_37
; CHECK-NEXT: .LBB0_18: # %b188 ; CHECK-NEXT: .LBB0_18: # %b188
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: testb %r9b, %r9b ; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: jne .LBB0_4 ; CHECK-NEXT: je .LBB0_4
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_19: # %a30b294 ; CHECK-NEXT: .LBB0_19: # %a30b294
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 ; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2
; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: je .LBB0_19 ; CHECK-NEXT: je .LBB0_19
; CHECK-NEXT: .LBB0_4: # %a33b ; CHECK-NEXT: .LBB0_4: # %a33b
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: movl %esi, %r10d ; CHECK-NEXT: movl %esi, %r9d
; CHECK-NEXT: orl %r8d, %r10d ; CHECK-NEXT: orl %r8d, %r9d
; CHECK-NEXT: jns .LBB0_20 ; CHECK-NEXT: jns .LBB0_20
; CHECK-NEXT: .LBB0_5: # %a50b ; CHECK-NEXT: .LBB0_5: # %a50b
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: shrl $31, %r10d ; CHECK-NEXT: shrl $31, %r9d
; CHECK-NEXT: movl %r8d, %eax ; CHECK-NEXT: movl %r8d, %eax
; CHECK-NEXT: orl %esi, %eax ; CHECK-NEXT: orl %esi, %eax
; CHECK-NEXT: jns .LBB0_26 ; CHECK-NEXT: jns .LBB0_26
; CHECK-NEXT: .LBB0_6: # %a57b ; CHECK-NEXT: .LBB0_6: # %a57b
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: shrl $31, %eax ; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: testb %r10b, %r10b ; CHECK-NEXT: testb %r9b, %r9b
; CHECK-NEXT: je .LBB0_30 ; CHECK-NEXT: je .LBB0_30
; CHECK-NEXT: .LBB0_7: # %a66b ; CHECK-NEXT: .LBB0_7: # %a66b
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_8 ; CHECK-NEXT: jne .LBB0_8
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_34: # %a74b ; CHECK-NEXT: .LBB0_34: # %a74b
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 ; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
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; CHECK-NEXT: .LBB0_38: # %a53b ; CHECK-NEXT: .LBB0_38: # %a53b
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 ; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # Parent Loop BB0_26 Depth=2 ; CHECK-NEXT: # Parent Loop BB0_26 Depth=2
; CHECK-NEXT: # => This Inner Loop Header: Depth=3 ; CHECK-NEXT: # => This Inner Loop Header: Depth=3
; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: je .LBB0_38 ; CHECK-NEXT: je .LBB0_38
; CHECK-NEXT: .LBB0_27: # %b879 ; CHECK-NEXT: .LBB0_27: # %b879
; CHECK-NEXT: # in Loop: Header=BB0_26 Depth=2 ; CHECK-NEXT: # in Loop: Header=BB0_26 Depth=2
; CHECK-NEXT: testb %r9b, %r9b ; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: jne .LBB0_28 ; CHECK-NEXT: je .LBB0_28
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_29: # %a53b1019 ; CHECK-NEXT: .LBB0_29: # %a53b1019
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 ; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # Parent Loop BB0_26 Depth=2 ; CHECK-NEXT: # Parent Loop BB0_26 Depth=2
; CHECK-NEXT: # => This Inner Loop Header: Depth=3 ; CHECK-NEXT: # => This Inner Loop Header: Depth=3
; CHECK-NEXT: testq %rdx, %rdx ; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: jle .LBB0_29 ; CHECK-NEXT: jle .LBB0_29
; CHECK-NEXT: jmp .LBB0_28 ; CHECK-NEXT: jmp .LBB0_28
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llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin8 -mattr=+sse2 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin8 -mattr=+sse2 | FileCheck %s
define void @test() nounwind { define void @test() nounwind {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: ## %bb.0: ## %test.exit ; CHECK: ## %bb.0: ## %test.exit
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: ud2 ; CHECK-NEXT: ud2
test.exit: test.exit:
fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:0 [#uses=4] fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:0 [#uses=4]
load <4 x float>, <4 x float>* null ; <<4 x float>>:1 [#uses=1] load <4 x float>, <4 x float>* null ; <<4 x float>>:1 [#uses=1]
shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x float>>:2 [#uses=1] shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x float>>:2 [#uses=1]
fmul <4 x float> %0, %2 ; <<4 x float>>:3 [#uses=1] fmul <4 x float> %0, %2 ; <<4 x float>>:3 [#uses=1]
fsub <4 x float> zeroinitializer, %3 ; <<4 x float>>:4 [#uses=1] fsub <4 x float> zeroinitializer, %3 ; <<4 x float>>:4 [#uses=1]
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llvm/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll

Show All 16 Lines
; CHECK-NEXT: subl $8, %esp ; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: movl (%esp), %eax ; CHECK-NEXT: movl (%esp), %eax
; CHECK-NEXT: testl %eax, %eax ; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: je .LBB0_3 ; CHECK-NEXT: je .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: orl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: orl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: jne .LBB0_3 ; CHECK-NEXT: jne .LBB0_3
; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # %bb.2: # %entry
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: .LBB0_3: # %bb5507 ; CHECK-NEXT: .LBB0_3: # %bb5507
; CHECK-NEXT: movl %ebp, %esp ; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp ; CHECK-NEXT: popl %ebp
; CHECK-NEXT: .cfi_def_cfa %esp, 4 ; CHECK-NEXT: .cfi_def_cfa %esp, 4
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%x8 = alloca %struct.c34007g__pkg__parent, align 8 ; <%struct.c34007g__pkg__parent*> [#uses=2] %x8 = alloca %struct.c34007g__pkg__parent, align 8 ; <%struct.c34007g__pkg__parent*> [#uses=2]
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llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll

Show All 17 Lines
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je LBB0_1 ; CHECK-NEXT: je LBB0_1
; CHECK-NEXT: ## %bb.3: ## %bb28 ; CHECK-NEXT: ## %bb.3: ## %bb28
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ebx ; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ebx
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ebp ; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ebp
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: movw $-2, %si ; CHECK-NEXT: movw $-2, %si
; CHECK-NEXT: jne LBB0_6 ; CHECK-NEXT: je LBB0_6
; CHECK-NEXT: ## %bb.4: ## %bb37 ; CHECK-NEXT: ## %bb.4: ## %bb37
; CHECK-NEXT: movw $0, 40(%edi) ; CHECK-NEXT: movw $0, 40(%edi)
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: leal (,%ecx,4), %ecx ; CHECK-NEXT: leal (,%ecx,4), %ecx
; CHECK-NEXT: leal (,%ebx,4), %edx ; CHECK-NEXT: leal (,%ebx,4), %edx
; CHECK-NEXT: subl $12, %esp ; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: movzwl %bp, %eax ; CHECK-NEXT: movzwl %bp, %eax
; CHECK-NEXT: movswl %cx, %ecx ; CHECK-NEXT: movswl %cx, %ecx
; CHECK-NEXT: movswl %dx, %edx ; CHECK-NEXT: movswl %dx, %edx
; CHECK-NEXT: pushl $87 ; CHECK-NEXT: pushl $87
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llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll

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; CHECK-NEXT: movl 0, %eax ; CHECK-NEXT: movl 0, %eax
; CHECK-NEXT: cmpl $121, %eax ; CHECK-NEXT: cmpl $121, %eax
; CHECK-NEXT: ja LBB0_25 ; CHECK-NEXT: ja LBB0_25
; CHECK-NEXT: ## %bb.8: ## %bb3314 ; CHECK-NEXT: ## %bb.8: ## %bb3314
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: jmpl *LJTI0_0(,%eax,4) ; CHECK-NEXT: jmpl *LJTI0_0(,%eax,4)
; CHECK-NEXT: LBB0_10: ## %bb5809 ; CHECK-NEXT: LBB0_10: ## %bb5809
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %bh, %bh
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: je LBB0_25
; CHECK-NEXT: jne LBB0_25
; CHECK-NEXT: ## %bb.11: ## %bb5809 ; CHECK-NEXT: ## %bb.11: ## %bb5809
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: testb %bh, %bh
; CHECK-NEXT: je LBB0_25 ; CHECK-NEXT: je LBB0_25
; CHECK-NEXT: ## %bb.12: ## %bb91.i8504 ; CHECK-NEXT: ## %bb.12: ## %bb91.i8504
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: testb $1, %bl ; CHECK-NEXT: testb $1, %bl
; CHECK-NEXT: je LBB0_14 ; CHECK-NEXT: je LBB0_14
; CHECK-NEXT: ## %bb.13: ## %bb155.i8541 ; CHECK-NEXT: ## %bb.13: ## %bb155.i8541
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: Ltmp4: ; CHECK-NEXT: Ltmp4:
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llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll

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; CHECK-NEXT: .LBB0_2: # %bb497 ; CHECK-NEXT: .LBB0_2: # %bb497
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: testb $1, %cl ; CHECK-NEXT: testb $1, %cl
; CHECK-NEXT: jne .LBB0_1 ; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: jmp .LBB0_3 ; CHECK-NEXT: jmp .LBB0_3
; CHECK-NEXT: .LBB0_3: # %bb502 ; CHECK-NEXT: .LBB0_3: # %bb502
; CHECK-NEXT: testb $1, %cl ; CHECK-NEXT: testb $1, %cl
; CHECK-NEXT: je .LBB0_5 ; CHECK-NEXT: jne .LBB0_4
; CHECK-NEXT: jmp .LBB0_4 ; CHECK-NEXT: jmp .LBB0_5
; CHECK-NEXT: .LBB0_4: # %bb507 ; CHECK-NEXT: .LBB0_4: # %bb507
; CHECK-NEXT: movl $0, (%esi) ; CHECK-NEXT: movl $0, (%esi)
; CHECK-NEXT: jmp .LBB0_5 ; CHECK-NEXT: jmp .LBB0_5
; CHECK-NEXT: .LBB0_5: # %bb841 ; CHECK-NEXT: .LBB0_5: # %bb841
entry: entry:
br label %bb497 br label %bb497
bb483: ; preds = %bb497 bb483: ; preds = %bb497
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llvm/test/CodeGen/X86/2012-08-17-legalizer-crash.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
; Check that an overly large immediate created by SROA doesn't crash the ; Check that an overly large immediate created by SROA doesn't crash the
; legalizer. ; legalizer.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.8.0" target triple = "x86_64-apple-macosx10.8.0"
%struct._GtkSheetRow = type { i32*, i32, i32, i32, %struct._GtkSheetButton, i32, i32 } %struct._GtkSheetRow = type { i32*, i32, i32, i32, %struct._GtkSheetButton, i32, i32 }
%struct._GtkSheetButton = type { i32, i32*, i32, i32*, i32 } %struct._GtkSheetButton = type { i32, i32*, i32, i32*, i32 }
@a = common global %struct._GtkSheetRow* null, align 8 @a = common global %struct._GtkSheetRow* null, align 8
define void @fn1() nounwind uwtable ssp { define void @fn1() nounwind uwtable ssp {
; CHECK-LABEL: fn1:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq _a@GOTPCREL(%rip), %rax
; CHECK-NEXT: movq (%rax), %rax
; CHECK-NEXT: movq 64(%rax), %rcx
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl $4294967295, %esi ## imm = 0xFFFFFFFF
; CHECK-NEXT: cmpq %rcx, %rsi
; CHECK-NEXT: movl $0, %esi
; CHECK-NEXT: sbbq %rsi, %rsi
; CHECK-NEXT: movl $0, %esi
; CHECK-NEXT: sbbq %rsi, %rsi
; CHECK-NEXT: movl $0, %esi
; CHECK-NEXT: sbbq %rsi, %rsi
; CHECK-NEXT: movl $0, %esi
; CHECK-NEXT: sbbq %rsi, %rsi
; CHECK-NEXT: movl $0, %esi
; CHECK-NEXT: sbbq %rsi, %rsi
; CHECK-NEXT: movl $0, %esi
; CHECK-NEXT: sbbq %rsi, %rsi
; CHECK-NEXT: sbbq %rdx, %rdx
; CHECK-NEXT: jae LBB0_2
; CHECK-NEXT: ## %bb.1: ## %if.then
; CHECK-NEXT: movq 56(%rax), %r8
; CHECK-NEXT: movq 48(%rax), %r9
; CHECK-NEXT: movq 40(%rax), %r10
; CHECK-NEXT: movq 32(%rax), %r11
; CHECK-NEXT: movq 24(%rax), %rsi
; CHECK-NEXT: movq 16(%rax), %rdi
; CHECK-NEXT: movq (%rax), %rdx
; CHECK-NEXT: movq 8(%rax), %rbx
; CHECK-NEXT: movq %rdx, (%rax)
; CHECK-NEXT: movq %rbx, 8(%rax)
; CHECK-NEXT: movq %rdi, 16(%rax)
; CHECK-NEXT: movq %rsi, 24(%rax)
; CHECK-NEXT: movq %r11, 32(%rax)
; CHECK-NEXT: movq %r10, 40(%rax)
; CHECK-NEXT: movq %r9, 48(%rax)
; CHECK-NEXT: movq %r8, 56(%rax)
; CHECK-NEXT: movq %rcx, 64(%rax)
; CHECK-NEXT: LBB0_2: ## %if.end
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
entry: entry:
%0 = load %struct._GtkSheetRow*, %struct._GtkSheetRow** @a, align 8 %0 = load %struct._GtkSheetRow*, %struct._GtkSheetRow** @a, align 8
%1 = bitcast %struct._GtkSheetRow* %0 to i576* %1 = bitcast %struct._GtkSheetRow* %0 to i576*
%srcval2 = load i576, i576* %1, align 8 %srcval2 = load i576, i576* %1, align 8
%tobool = icmp ugt i576 %srcval2, 57586096570152913699974892898380567793532123114264532903689671329431521032595044740083720782129802971518987656109067457577065805510327036019308994315074097345724415 %tobool = icmp ugt i576 %srcval2, 57586096570152913699974892898380567793532123114264532903689671329431521032595044740083720782129802971518987656109067457577065805510327036019308994315074097345724415
br i1 %tobool, label %if.then, label %if.end br i1 %tobool, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
store i576 %srcval2, i576* %1, align 8 store i576 %srcval2, i576* %1, align 8
br label %if.end br label %if.end
if.end: ; preds = %if.then, %entry if.end: ; preds = %if.then, %entry
ret void ret void
; CHECK-LABEL: fn1:
; CHECK: jb
} }

llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movb %bpl, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movb %bpl, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movw %bx, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movw %bx, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movb %bpl, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movb %bpl, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq foo ; CHECK-NEXT: callq foo
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB1_3 ; CHECK-NEXT: je .LBB1_3
; CHECK-NEXT: # %bb.1: # %if.true ; CHECK-NEXT: # %bb.1: # %if.true
; CHECK-NEXT: movw $8, %ax ; CHECK-NEXT: movw $8, %ax
; CHECK-NEXT: tilezero %tmm0 ; CHECK-NEXT: tilezero %tmm0
; CHECK-NEXT: movl $32, %ecx ; CHECK-NEXT: movl $32, %ecx
; CHECK-NEXT: movl $buf+1024, %edx ; CHECK-NEXT: movl $buf+1024, %edx
; CHECK-NEXT: tileloadd (%rdx,%rcx), %tmm1 ; CHECK-NEXT: tileloadd (%rdx,%rcx), %tmm1
; CHECK-NEXT: movl $buf+2048, %edx ; CHECK-NEXT: movl $buf+2048, %edx
; CHECK-NEXT: tileloadd (%rdx,%rcx), %tmm2 ; CHECK-NEXT: tileloadd (%rdx,%rcx), %tmm2
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; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vpxord %zmm0, %zmm0, %zmm0 ; CHECK-NEXT: vpxord %zmm0, %zmm0, %zmm0
; CHECK-NEXT: vmovdqu64 %zmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: vmovdqu64 %zmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movb $1, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movb $1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movw %si, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movw %si, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB2_2 ; CHECK-NEXT: je .LBB2_2
; CHECK-NEXT: # %bb.1: # %if.true ; CHECK-NEXT: # %bb.1: # %if.true
; CHECK-NEXT: incl %edi ; CHECK-NEXT: incl %edi
; CHECK-NEXT: jmp .LBB2_3 ; CHECK-NEXT: jmp .LBB2_3
; CHECK-NEXT: .LBB2_2: # %if.false ; CHECK-NEXT: .LBB2_2: # %if.false
; CHECK-NEXT: decl %edi ; CHECK-NEXT: decl %edi
; CHECK-NEXT: .LBB2_3: # %exit ; CHECK-NEXT: .LBB2_3: # %exit
; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp) ; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
Show All 26 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vpxord %zmm0, %zmm0, %zmm0 ; CHECK-NEXT: vpxord %zmm0, %zmm0, %zmm0
; CHECK-NEXT: vmovdqu64 %zmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: vmovdqu64 %zmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movb $1, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movb $1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movw %si, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movw %si, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB3_3 ; CHECK-NEXT: je .LBB3_3
; CHECK-NEXT: # %bb.1: # %if.true ; CHECK-NEXT: # %bb.1: # %if.true
; CHECK-NEXT: incl %edi ; CHECK-NEXT: incl %edi
; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp) ; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB3_4 ; CHECK-NEXT: jne .LBB3_4
; CHECK-NEXT: .LBB3_2: # %amx2 ; CHECK-NEXT: .LBB3_2: # %amx2
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; CHECK-NEXT: movl %ecx, %esi ; CHECK-NEXT: movl %ecx, %esi
; CHECK-NEXT: movw %cx, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movw %cx, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: cmpw $7, %si ; CHECK-NEXT: cmpw $7, %si
; CHECK-NEXT: jne .LBB4_5 ; CHECK-NEXT: jne .LBB4_5
; CHECK-NEXT: .LBB4_1: # %loop.bb1 ; CHECK-NEXT: .LBB4_1: # %loop.bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp) ; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB4_3 ; CHECK-NEXT: je .LBB4_3
; CHECK-NEXT: # %bb.2: # %if.true ; CHECK-NEXT: # %bb.2: # %if.true
; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1
; CHECK-NEXT: tilezero %tmm0 ; CHECK-NEXT: tilezero %tmm0
; CHECK-NEXT: tilestored %tmm0, (%r8,%rdx) ; CHECK-NEXT: tilestored %tmm0, (%r8,%rdx)
; CHECK-NEXT: cmpw $7, %si ; CHECK-NEXT: cmpw $7, %si
; CHECK-NEXT: je .LBB4_1 ; CHECK-NEXT: je .LBB4_1
; CHECK-NEXT: .LBB4_5: # %exit ; CHECK-NEXT: .LBB4_5: # %exit
; CHECK-NEXT: tilerelease ; CHECK-NEXT: tilerelease
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; CHECK-NEXT: cmpw $7, %si ; CHECK-NEXT: cmpw $7, %si
; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp) ; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
; CHECK-NEXT: tilezero %tmm0 ; CHECK-NEXT: tilezero %tmm0
; CHECK-NEXT: tilestored %tmm0, (%rcx,%rdx) ; CHECK-NEXT: tilestored %tmm0, (%rcx,%rdx)
; CHECK-NEXT: jne .LBB5_5 ; CHECK-NEXT: jne .LBB5_5
; CHECK-NEXT: .LBB5_1: # %loop.bb1 ; CHECK-NEXT: .LBB5_1: # %loop.bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: testb %r8b, %r8b ; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: jne .LBB5_3 ; CHECK-NEXT: je .LBB5_3
; CHECK-NEXT: # %bb.2: # %if.true ; CHECK-NEXT: # %bb.2: # %if.true
; CHECK-NEXT: # in Loop: Header=BB5_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB5_1 Depth=1
; CHECK-NEXT: incl %esi ; CHECK-NEXT: incl %esi
; CHECK-NEXT: jmp .LBB5_4 ; CHECK-NEXT: jmp .LBB5_4
; CHECK-NEXT: .LBB5_5: # %exit ; CHECK-NEXT: .LBB5_5: # %exit
; CHECK-NEXT: tilerelease ; CHECK-NEXT: tilerelease
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll

Show All 20 Lines
; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; CHECK-NEXT: movl $64, %eax ; CHECK-NEXT: movl $64, %eax
; CHECK-NEXT: movw $8, %r14w ; CHECK-NEXT: movw $8, %r14w
; CHECK-NEXT: tileloadd (%rdi,%rax), %tmm3 ; CHECK-NEXT: tileloadd (%rdi,%rax), %tmm3
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_3 ; CHECK-NEXT: je .LBB0_3
; CHECK-NEXT: # %bb.1: # %loop.header.preheader ; CHECK-NEXT: # %bb.1: # %loop.header.preheader
; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: xorl %ebp, %ebp ; CHECK-NEXT: xorl %ebp, %ebp
; CHECK-NEXT: movl $32, %r15d ; CHECK-NEXT: movl $32, %r15d
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_2: # %loop.header ; CHECK-NEXT: .LBB0_2: # %loop.header
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movabsq $64, %rax ; CHECK-NEXT: movabsq $64, %rax
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; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; CHECK-NEXT: movw $8, %r14w ; CHECK-NEXT: movw $8, %r14w
; CHECK-NEXT: tilezero %tmm0 ; CHECK-NEXT: tilezero %tmm0
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB1_3 ; CHECK-NEXT: je .LBB1_3
; CHECK-NEXT: # %bb.1: # %loop.header.preheader ; CHECK-NEXT: # %bb.1: # %loop.header.preheader
; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: xorl %ebp, %ebp ; CHECK-NEXT: xorl %ebp, %ebp
; CHECK-NEXT: movl $32, %r15d ; CHECK-NEXT: movl $32, %r15d
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB1_2: # %loop.header ; CHECK-NEXT: .LBB1_2: # %loop.header
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: tilezero %tmm0 ; CHECK-NEXT: tilezero %tmm0
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llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll

Show All 30 Lines
; CHECK-NEXT: movw %bx, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movw %bx, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movb %bpl, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movb %bpl, {{[0-9]+}}(%rsp)
; CHECK-NEXT: ldtilecfg (%rsp) ; CHECK-NEXT: ldtilecfg (%rsp)
; CHECK-NEXT: movl $32, %r14d ; CHECK-NEXT: movl $32, %r14d
; CHECK-NEXT: movl $buf+2048, %r15d ; CHECK-NEXT: movl $buf+2048, %r15d
; CHECK-NEXT: tileloadd (%r15,%r14), %tmm5 ; CHECK-NEXT: tileloadd (%r15,%r14), %tmm5
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.true ; CHECK-NEXT: # %bb.1: # %if.true
; CHECK-NEXT: movl $buf, %eax ; CHECK-NEXT: movl $buf, %eax
; CHECK-NEXT: movw $8, %cx ; CHECK-NEXT: movw $8, %cx
; CHECK-NEXT: tileloadd (%rax,%r14), %tmm0 ; CHECK-NEXT: tileloadd (%rax,%r14), %tmm0
; CHECK-NEXT: movl $buf+1024, %eax ; CHECK-NEXT: movl $buf+1024, %eax
; CHECK-NEXT: tileloadd (%rax,%r14), %tmm1 ; CHECK-NEXT: tileloadd (%rax,%r14), %tmm1
; CHECK-NEXT: movabsq $64, %rax ; CHECK-NEXT: movabsq $64, %rax
; CHECK-NEXT: tilestored %tmm5, 1088(%rsp,%rax) # 1024-byte Folded Spill ; CHECK-NEXT: tilestored %tmm5, 1088(%rsp,%rax) # 1024-byte Folded Spill
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; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
; CHECK-NEXT: movw $8, %r15w ; CHECK-NEXT: movw $8, %r15w
; CHECK-NEXT: tilezero %tmm0 ; CHECK-NEXT: tilezero %tmm0
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB1_3 ; CHECK-NEXT: je .LBB1_3
; CHECK-NEXT: # %bb.1: # %loop.header.preheader ; CHECK-NEXT: # %bb.1: # %loop.header.preheader
; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $32, %r14d ; CHECK-NEXT: movl $32, %r14d
; CHECK-NEXT: xorl %ebp, %ebp ; CHECK-NEXT: xorl %ebp, %ebp
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB1_2: # %loop.header ; CHECK-NEXT: .LBB1_2: # %loop.header
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: tilestored %tmm0, (%rbx,%r14) ; CHECK-NEXT: tilestored %tmm0, (%rbx,%r14)
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llvm/test/CodeGen/X86/atomic-unordered.ll

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; CHECK-O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload ; CHECK-O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
; CHECK-O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload ; CHECK-O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
; CHECK-O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload ; CHECK-O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
; CHECK-O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx # 8-byte Reload ; CHECK-O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx # 8-byte Reload
; CHECK-O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload ; CHECK-O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
; CHECK-O0-NEXT: lock cmpxchg16b (%rsi) ; CHECK-O0-NEXT: lock cmpxchg16b (%rsi)
; CHECK-O0-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-O0-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-O0-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-O0-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-O0-NEXT: jne .LBB16_1 ; CHECK-O0-NEXT: je .LBB16_2
; CHECK-O0-NEXT: jmp .LBB16_2 ; CHECK-O0-NEXT: jmp .LBB16_1
; CHECK-O0-NEXT: .LBB16_2: # %atomicrmw.end ; CHECK-O0-NEXT: .LBB16_2: # %atomicrmw.end
; CHECK-O0-NEXT: popq %rbx ; CHECK-O0-NEXT: popq %rbx
; CHECK-O0-NEXT: .cfi_def_cfa_offset 8 ; CHECK-O0-NEXT: .cfi_def_cfa_offset 8
; CHECK-O0-NEXT: retq ; CHECK-O0-NEXT: retq
; ;
; CHECK-O3-LABEL: store_i128: ; CHECK-O3-LABEL: store_i128:
; CHECK-O3: # %bb.0: ; CHECK-O3: # %bb.0:
; CHECK-O3-NEXT: pushq %rbx ; CHECK-O3-NEXT: pushq %rbx
▲ Show 20 Lines • Show All 2,413 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/atomic64.ll

Show First 20 Lines • Show All 393 Lines • ▼ Show 20 Lines
; I486-NEXT: movl $sc64, (%eax) ; I486-NEXT: movl $sc64, (%eax)
; I486-NEXT: calll __atomic_compare_exchange_8@PLT ; I486-NEXT: calll __atomic_compare_exchange_8@PLT
; I486-NEXT: movb %al, %dl ; I486-NEXT: movb %al, %dl
; I486-NEXT: movl {{[0-9]+}}(%esp), %ecx ; I486-NEXT: movl {{[0-9]+}}(%esp), %ecx
; I486-NEXT: movl {{[0-9]+}}(%esp), %eax ; I486-NEXT: movl {{[0-9]+}}(%esp), %eax
; I486-NEXT: testb %dl, %dl ; I486-NEXT: testb %dl, %dl
; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: je .LBB6_1 ; I486-NEXT: jne .LBB6_2
; I486-NEXT: jmp .LBB6_2 ; I486-NEXT: jmp .LBB6_1
; I486-NEXT: .LBB6_2: # %atomicrmw.end ; I486-NEXT: .LBB6_2: # %atomicrmw.end
; I486-NEXT: leal -4(%ebp), %esp ; I486-NEXT: leal -4(%ebp), %esp
; I486-NEXT: popl %esi ; I486-NEXT: popl %esi
; I486-NEXT: popl %ebp ; I486-NEXT: popl %ebp
; I486-NEXT: retl ; I486-NEXT: retl
%t1 = atomicrmw max i64* @sc64, i64 %x acquire %t1 = atomicrmw max i64* @sc64, i64 %x acquire
ret void ret void
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; I486-NEXT: movl $sc64, (%eax) ; I486-NEXT: movl $sc64, (%eax)
; I486-NEXT: calll __atomic_compare_exchange_8@PLT ; I486-NEXT: calll __atomic_compare_exchange_8@PLT
; I486-NEXT: movb %al, %dl ; I486-NEXT: movb %al, %dl
; I486-NEXT: movl {{[0-9]+}}(%esp), %ecx ; I486-NEXT: movl {{[0-9]+}}(%esp), %ecx
; I486-NEXT: movl {{[0-9]+}}(%esp), %eax ; I486-NEXT: movl {{[0-9]+}}(%esp), %eax
; I486-NEXT: testb %dl, %dl ; I486-NEXT: testb %dl, %dl
; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: je .LBB7_1 ; I486-NEXT: jne .LBB7_2
; I486-NEXT: jmp .LBB7_2 ; I486-NEXT: jmp .LBB7_1
; I486-NEXT: .LBB7_2: # %atomicrmw.end ; I486-NEXT: .LBB7_2: # %atomicrmw.end
; I486-NEXT: leal -4(%ebp), %esp ; I486-NEXT: leal -4(%ebp), %esp
; I486-NEXT: popl %esi ; I486-NEXT: popl %esi
; I486-NEXT: popl %ebp ; I486-NEXT: popl %ebp
; I486-NEXT: retl ; I486-NEXT: retl
%t1 = atomicrmw min i64* @sc64, i64 %x acquire %t1 = atomicrmw min i64* @sc64, i64 %x acquire
ret void ret void
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; I486-NEXT: movl $sc64, (%eax) ; I486-NEXT: movl $sc64, (%eax)
; I486-NEXT: calll __atomic_compare_exchange_8@PLT ; I486-NEXT: calll __atomic_compare_exchange_8@PLT
; I486-NEXT: movb %al, %dl ; I486-NEXT: movb %al, %dl
; I486-NEXT: movl {{[0-9]+}}(%esp), %ecx ; I486-NEXT: movl {{[0-9]+}}(%esp), %ecx
; I486-NEXT: movl {{[0-9]+}}(%esp), %eax ; I486-NEXT: movl {{[0-9]+}}(%esp), %eax
; I486-NEXT: testb %dl, %dl ; I486-NEXT: testb %dl, %dl
; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: je .LBB8_1 ; I486-NEXT: jne .LBB8_2
; I486-NEXT: jmp .LBB8_2 ; I486-NEXT: jmp .LBB8_1
; I486-NEXT: .LBB8_2: # %atomicrmw.end ; I486-NEXT: .LBB8_2: # %atomicrmw.end
; I486-NEXT: leal -4(%ebp), %esp ; I486-NEXT: leal -4(%ebp), %esp
; I486-NEXT: popl %esi ; I486-NEXT: popl %esi
; I486-NEXT: popl %ebp ; I486-NEXT: popl %ebp
; I486-NEXT: retl ; I486-NEXT: retl
%t1 = atomicrmw umax i64* @sc64, i64 %x acquire %t1 = atomicrmw umax i64* @sc64, i64 %x acquire
ret void ret void
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; I486-NEXT: movl $sc64, (%eax) ; I486-NEXT: movl $sc64, (%eax)
; I486-NEXT: calll __atomic_compare_exchange_8@PLT ; I486-NEXT: calll __atomic_compare_exchange_8@PLT
; I486-NEXT: movb %al, %dl ; I486-NEXT: movb %al, %dl
; I486-NEXT: movl {{[0-9]+}}(%esp), %ecx ; I486-NEXT: movl {{[0-9]+}}(%esp), %ecx
; I486-NEXT: movl {{[0-9]+}}(%esp), %eax ; I486-NEXT: movl {{[0-9]+}}(%esp), %eax
; I486-NEXT: testb %dl, %dl ; I486-NEXT: testb %dl, %dl
; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: je .LBB9_1 ; I486-NEXT: jne .LBB9_2
; I486-NEXT: jmp .LBB9_2 ; I486-NEXT: jmp .LBB9_1
; I486-NEXT: .LBB9_2: # %atomicrmw.end ; I486-NEXT: .LBB9_2: # %atomicrmw.end
; I486-NEXT: leal -4(%ebp), %esp ; I486-NEXT: leal -4(%ebp), %esp
; I486-NEXT: popl %esi ; I486-NEXT: popl %esi
; I486-NEXT: popl %ebp ; I486-NEXT: popl %ebp
; I486-NEXT: retl ; I486-NEXT: retl
%t1 = atomicrmw umin i64* @sc64, i64 %x acquire %t1 = atomicrmw umin i64* @sc64, i64 %x acquire
ret void ret void
▲ Show 20 Lines • Show All 114 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/atomic6432.ll

Show All 21 Lines
; X32-NEXT: addl $1, %ebx ; X32-NEXT: addl $1, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: movl %edx, %ecx
; X32-NEXT: adcl $0, %ecx ; X32-NEXT: adcl $0, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB0_1 ; X32-NEXT: je .LBB0_2
; X32-NEXT: jmp .LBB0_2 ; X32-NEXT: jmp .LBB0_1
; X32-NEXT: .LBB0_2: # %atomicrmw.end ; X32-NEXT: .LBB0_2: # %atomicrmw.end
; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64+4, %edx
; X32-NEXT: movl sc64, %eax ; X32-NEXT: movl sc64, %eax
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jmp .LBB0_3 ; X32-NEXT: jmp .LBB0_3
; X32-NEXT: .LBB0_3: # %atomicrmw.start2 ; X32-NEXT: .LBB0_3: # %atomicrmw.start2
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: addl $3, %ebx ; X32-NEXT: addl $3, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: movl %edx, %ecx
; X32-NEXT: adcl $0, %ecx ; X32-NEXT: adcl $0, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB0_3 ; X32-NEXT: je .LBB0_4
; X32-NEXT: jmp .LBB0_4 ; X32-NEXT: jmp .LBB0_3
; X32-NEXT: .LBB0_4: # %atomicrmw.end1 ; X32-NEXT: .LBB0_4: # %atomicrmw.end1
; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64+4, %edx
; X32-NEXT: movl sc64, %eax ; X32-NEXT: movl sc64, %eax
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jmp .LBB0_5 ; X32-NEXT: jmp .LBB0_5
; X32-NEXT: .LBB0_5: # %atomicrmw.start8 ; X32-NEXT: .LBB0_5: # %atomicrmw.start8
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: addl $5, %ebx ; X32-NEXT: addl $5, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: movl %edx, %ecx
; X32-NEXT: adcl $0, %ecx ; X32-NEXT: adcl $0, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB0_5 ; X32-NEXT: je .LBB0_6
; X32-NEXT: jmp .LBB0_6 ; X32-NEXT: jmp .LBB0_5
; X32-NEXT: .LBB0_6: # %atomicrmw.end7 ; X32-NEXT: .LBB0_6: # %atomicrmw.end7
; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64+4, %edx
; X32-NEXT: movl sc64, %eax ; X32-NEXT: movl sc64, %eax
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jmp .LBB0_7 ; X32-NEXT: jmp .LBB0_7
; X32-NEXT: .LBB0_7: # %atomicrmw.start14 ; X32-NEXT: .LBB0_7: # %atomicrmw.start14
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: addl %ecx, %ebx ; X32-NEXT: addl %ecx, %ebx
; X32-NEXT: movl %ebx, (%esp) # 4-byte Spill ; X32-NEXT: movl %ebx, (%esp) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: movl %edx, %ecx
; X32-NEXT: adcl %esi, %ecx ; X32-NEXT: adcl %esi, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB0_7 ; X32-NEXT: je .LBB0_8
; X32-NEXT: jmp .LBB0_8 ; X32-NEXT: jmp .LBB0_7
; X32-NEXT: .LBB0_8: # %atomicrmw.end13 ; X32-NEXT: .LBB0_8: # %atomicrmw.end13
; X32-NEXT: addl $72, %esp ; X32-NEXT: addl $72, %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: retl ; X32-NEXT: retl
entry: entry:
%t1 = atomicrmw add i64* @sc64, i64 1 acquire %t1 = atomicrmw add i64* @sc64, i64 1 acquire
%t2 = atomicrmw add i64* @sc64, i64 3 acquire %t2 = atomicrmw add i64* @sc64, i64 3 acquire
Show All 21 Lines
; X32-NEXT: addl $-1, %ebx ; X32-NEXT: addl $-1, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: movl %edx, %ecx
; X32-NEXT: adcl $-1, %ecx ; X32-NEXT: adcl $-1, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB1_1 ; X32-NEXT: je .LBB1_2
; X32-NEXT: jmp .LBB1_2 ; X32-NEXT: jmp .LBB1_1
; X32-NEXT: .LBB1_2: # %atomicrmw.end ; X32-NEXT: .LBB1_2: # %atomicrmw.end
; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64+4, %edx
; X32-NEXT: movl sc64, %eax ; X32-NEXT: movl sc64, %eax
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jmp .LBB1_3 ; X32-NEXT: jmp .LBB1_3
; X32-NEXT: .LBB1_3: # %atomicrmw.start2 ; X32-NEXT: .LBB1_3: # %atomicrmw.start2
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: addl $-3, %ebx ; X32-NEXT: addl $-3, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: movl %edx, %ecx
; X32-NEXT: adcl $-1, %ecx ; X32-NEXT: adcl $-1, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB1_3 ; X32-NEXT: je .LBB1_4
; X32-NEXT: jmp .LBB1_4 ; X32-NEXT: jmp .LBB1_3
; X32-NEXT: .LBB1_4: # %atomicrmw.end1 ; X32-NEXT: .LBB1_4: # %atomicrmw.end1
; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64+4, %edx
; X32-NEXT: movl sc64, %eax ; X32-NEXT: movl sc64, %eax
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jmp .LBB1_5 ; X32-NEXT: jmp .LBB1_5
; X32-NEXT: .LBB1_5: # %atomicrmw.start8 ; X32-NEXT: .LBB1_5: # %atomicrmw.start8
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: addl $-5, %ebx ; X32-NEXT: addl $-5, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: movl %edx, %ecx
; X32-NEXT: adcl $-1, %ecx ; X32-NEXT: adcl $-1, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB1_5 ; X32-NEXT: je .LBB1_6
; X32-NEXT: jmp .LBB1_6 ; X32-NEXT: jmp .LBB1_5
; X32-NEXT: .LBB1_6: # %atomicrmw.end7 ; X32-NEXT: .LBB1_6: # %atomicrmw.end7
; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64+4, %edx
; X32-NEXT: movl sc64, %eax ; X32-NEXT: movl sc64, %eax
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jmp .LBB1_7 ; X32-NEXT: jmp .LBB1_7
; X32-NEXT: .LBB1_7: # %atomicrmw.start14 ; X32-NEXT: .LBB1_7: # %atomicrmw.start14
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: subl %ecx, %ebx ; X32-NEXT: subl %ecx, %ebx
; X32-NEXT: movl %ebx, (%esp) # 4-byte Spill ; X32-NEXT: movl %ebx, (%esp) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: movl %edx, %ecx
; X32-NEXT: sbbl %esi, %ecx ; X32-NEXT: sbbl %esi, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB1_7 ; X32-NEXT: je .LBB1_8
; X32-NEXT: jmp .LBB1_8 ; X32-NEXT: jmp .LBB1_7
; X32-NEXT: .LBB1_8: # %atomicrmw.end13 ; X32-NEXT: .LBB1_8: # %atomicrmw.end13
; X32-NEXT: addl $72, %esp ; X32-NEXT: addl $72, %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: retl ; X32-NEXT: retl
%t1 = atomicrmw sub i64* @sc64, i64 1 acquire %t1 = atomicrmw sub i64* @sc64, i64 1 acquire
%t2 = atomicrmw sub i64* @sc64, i64 3 acquire %t2 = atomicrmw sub i64* @sc64, i64 3 acquire
%t3 = atomicrmw sub i64* @sc64, i64 5 acquire %t3 = atomicrmw sub i64* @sc64, i64 5 acquire
Show All 18 Lines
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: andl $3, %ebx ; X32-NEXT: andl $3, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: xorl %ecx, %ecx
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB2_1 ; X32-NEXT: je .LBB2_2
; X32-NEXT: jmp .LBB2_2 ; X32-NEXT: jmp .LBB2_1
; X32-NEXT: .LBB2_2: # %atomicrmw.end ; X32-NEXT: .LBB2_2: # %atomicrmw.end
; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64+4, %edx
; X32-NEXT: movl sc64, %eax ; X32-NEXT: movl sc64, %eax
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jmp .LBB2_3 ; X32-NEXT: jmp .LBB2_3
; X32-NEXT: .LBB2_3: # %atomicrmw.start2 ; X32-NEXT: .LBB2_3: # %atomicrmw.start2
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: andl $1, %ebx ; X32-NEXT: andl $1, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: movl %edx, %ecx
; X32-NEXT: andl $1, %ecx ; X32-NEXT: andl $1, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB2_3 ; X32-NEXT: je .LBB2_4
; X32-NEXT: jmp .LBB2_4 ; X32-NEXT: jmp .LBB2_3
; X32-NEXT: .LBB2_4: # %atomicrmw.end1 ; X32-NEXT: .LBB2_4: # %atomicrmw.end1
; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64+4, %edx
; X32-NEXT: movl sc64, %eax ; X32-NEXT: movl sc64, %eax
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jmp .LBB2_5 ; X32-NEXT: jmp .LBB2_5
; X32-NEXT: .LBB2_5: # %atomicrmw.start8 ; X32-NEXT: .LBB2_5: # %atomicrmw.start8
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: andl %ecx, %ebx ; X32-NEXT: andl %ecx, %ebx
; X32-NEXT: movl %ebx, (%esp) # 4-byte Spill ; X32-NEXT: movl %ebx, (%esp) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: movl %edx, %ecx
; X32-NEXT: andl %esi, %ecx ; X32-NEXT: andl %esi, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB2_5 ; X32-NEXT: je .LBB2_6
; X32-NEXT: jmp .LBB2_6 ; X32-NEXT: jmp .LBB2_5
; X32-NEXT: .LBB2_6: # %atomicrmw.end7 ; X32-NEXT: .LBB2_6: # %atomicrmw.end7
; X32-NEXT: addl $52, %esp ; X32-NEXT: addl $52, %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: retl ; X32-NEXT: retl
%t1 = atomicrmw and i64* @sc64, i64 3 acquire %t1 = atomicrmw and i64* @sc64, i64 3 acquire
%t2 = atomicrmw and i64* @sc64, i64 4294967297 acquire %t2 = atomicrmw and i64* @sc64, i64 4294967297 acquire
%t3 = atomicrmw and i64* @sc64, i64 %t2 acquire %t3 = atomicrmw and i64* @sc64, i64 %t2 acquire
Show All 17 Lines
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: orl $3, %ebx ; X32-NEXT: orl $3, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %ecx, %edx ; X32-NEXT: movl %ecx, %edx
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB3_1 ; X32-NEXT: je .LBB3_2
; X32-NEXT: jmp .LBB3_2 ; X32-NEXT: jmp .LBB3_1
; X32-NEXT: .LBB3_2: # %atomicrmw.end ; X32-NEXT: .LBB3_2: # %atomicrmw.end
; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64+4, %edx
; X32-NEXT: movl sc64, %eax ; X32-NEXT: movl sc64, %eax
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jmp .LBB3_3 ; X32-NEXT: jmp .LBB3_3
; X32-NEXT: .LBB3_3: # %atomicrmw.start2 ; X32-NEXT: .LBB3_3: # %atomicrmw.start2
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: orl $1, %ebx ; X32-NEXT: orl $1, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: movl %edx, %ecx
; X32-NEXT: orl $1, %ecx ; X32-NEXT: orl $1, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB3_3 ; X32-NEXT: je .LBB3_4
; X32-NEXT: jmp .LBB3_4 ; X32-NEXT: jmp .LBB3_3
; X32-NEXT: .LBB3_4: # %atomicrmw.end1 ; X32-NEXT: .LBB3_4: # %atomicrmw.end1
; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64+4, %edx
; X32-NEXT: movl sc64, %eax ; X32-NEXT: movl sc64, %eax
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jmp .LBB3_5 ; X32-NEXT: jmp .LBB3_5
; X32-NEXT: .LBB3_5: # %atomicrmw.start8 ; X32-NEXT: .LBB3_5: # %atomicrmw.start8
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: orl %ecx, %ebx ; X32-NEXT: orl %ecx, %ebx
; X32-NEXT: movl %ebx, (%esp) # 4-byte Spill ; X32-NEXT: movl %ebx, (%esp) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: movl %edx, %ecx
; X32-NEXT: orl %esi, %ecx ; X32-NEXT: orl %esi, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB3_5 ; X32-NEXT: je .LBB3_6
; X32-NEXT: jmp .LBB3_6 ; X32-NEXT: jmp .LBB3_5
; X32-NEXT: .LBB3_6: # %atomicrmw.end7 ; X32-NEXT: .LBB3_6: # %atomicrmw.end7
; X32-NEXT: addl $52, %esp ; X32-NEXT: addl $52, %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: retl ; X32-NEXT: retl
%t1 = atomicrmw or i64* @sc64, i64 3 acquire %t1 = atomicrmw or i64* @sc64, i64 3 acquire
%t2 = atomicrmw or i64* @sc64, i64 4294967297 acquire %t2 = atomicrmw or i64* @sc64, i64 4294967297 acquire
%t3 = atomicrmw or i64* @sc64, i64 %t2 acquire %t3 = atomicrmw or i64* @sc64, i64 %t2 acquire
Show All 17 Lines
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: xorl $3, %ebx ; X32-NEXT: xorl $3, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %ecx, %edx ; X32-NEXT: movl %ecx, %edx
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB4_1 ; X32-NEXT: je .LBB4_2
; X32-NEXT: jmp .LBB4_2 ; X32-NEXT: jmp .LBB4_1
; X32-NEXT: .LBB4_2: # %atomicrmw.end ; X32-NEXT: .LBB4_2: # %atomicrmw.end
; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64+4, %edx
; X32-NEXT: movl sc64, %eax ; X32-NEXT: movl sc64, %eax
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jmp .LBB4_3 ; X32-NEXT: jmp .LBB4_3
; X32-NEXT: .LBB4_3: # %atomicrmw.start2 ; X32-NEXT: .LBB4_3: # %atomicrmw.start2
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: xorl $1, %ebx ; X32-NEXT: xorl $1, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: movl %edx, %ecx
; X32-NEXT: xorl $1, %ecx ; X32-NEXT: xorl $1, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB4_3 ; X32-NEXT: je .LBB4_4
; X32-NEXT: jmp .LBB4_4 ; X32-NEXT: jmp .LBB4_3
; X32-NEXT: .LBB4_4: # %atomicrmw.end1 ; X32-NEXT: .LBB4_4: # %atomicrmw.end1
; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64+4, %edx
; X32-NEXT: movl sc64, %eax ; X32-NEXT: movl sc64, %eax
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jmp .LBB4_5 ; X32-NEXT: jmp .LBB4_5
; X32-NEXT: .LBB4_5: # %atomicrmw.start8 ; X32-NEXT: .LBB4_5: # %atomicrmw.start8
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: movl %eax, %ebx
; X32-NEXT: xorl %ecx, %ebx ; X32-NEXT: xorl %ecx, %ebx
; X32-NEXT: movl %ebx, (%esp) # 4-byte Spill ; X32-NEXT: movl %ebx, (%esp) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: movl %edx, %ecx
; X32-NEXT: xorl %esi, %ecx ; X32-NEXT: xorl %esi, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB4_5 ; X32-NEXT: je .LBB4_6
; X32-NEXT: jmp .LBB4_6 ; X32-NEXT: jmp .LBB4_5
; X32-NEXT: .LBB4_6: # %atomicrmw.end7 ; X32-NEXT: .LBB4_6: # %atomicrmw.end7
; X32-NEXT: addl $52, %esp ; X32-NEXT: addl $52, %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: retl ; X32-NEXT: retl
%t1 = atomicrmw xor i64* @sc64, i64 3 acquire %t1 = atomicrmw xor i64* @sc64, i64 3 acquire
%t2 = atomicrmw xor i64* @sc64, i64 4294967297 acquire %t2 = atomicrmw xor i64* @sc64, i64 4294967297 acquire
%t3 = atomicrmw xor i64* @sc64, i64 %t2 acquire %t3 = atomicrmw xor i64* @sc64, i64 %t2 acquire
Show All 30 Lines
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: notl %ebx ; X32-NEXT: notl %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: notl %ecx ; X32-NEXT: notl %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB5_1 ; X32-NEXT: je .LBB5_2
; X32-NEXT: jmp .LBB5_2 ; X32-NEXT: jmp .LBB5_1
; X32-NEXT: .LBB5_2: # %atomicrmw.end ; X32-NEXT: .LBB5_2: # %atomicrmw.end
; X32-NEXT: addl $32, %esp ; X32-NEXT: addl $32, %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: popl %edi ; X32-NEXT: popl %edi
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: retl ; X32-NEXT: retl
%t1 = atomicrmw nand i64* @sc64, i64 %x acquire %t1 = atomicrmw nand i64* @sc64, i64 %x acquire
ret void ret void
Show All 28 Lines
; X32-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: cmovll %edx, %ecx ; X32-NEXT: cmovll %edx, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: cmovll %eax, %ebx ; X32-NEXT: cmovll %eax, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB6_1 ; X32-NEXT: je .LBB6_2
; X32-NEXT: jmp .LBB6_2 ; X32-NEXT: jmp .LBB6_1
; X32-NEXT: .LBB6_2: # %atomicrmw.end ; X32-NEXT: .LBB6_2: # %atomicrmw.end
; X32-NEXT: addl $32, %esp ; X32-NEXT: addl $32, %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: retl ; X32-NEXT: retl
%t1 = atomicrmw max i64* @sc64, i64 %x acquire %t1 = atomicrmw max i64* @sc64, i64 %x acquire
ret void ret void
} }
Show All 27 Lines
; X32-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: cmovgel %edx, %ecx ; X32-NEXT: cmovgel %edx, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: cmovgel %eax, %ebx ; X32-NEXT: cmovgel %eax, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB7_1 ; X32-NEXT: je .LBB7_2
; X32-NEXT: jmp .LBB7_2 ; X32-NEXT: jmp .LBB7_1
; X32-NEXT: .LBB7_2: # %atomicrmw.end ; X32-NEXT: .LBB7_2: # %atomicrmw.end
; X32-NEXT: addl $32, %esp ; X32-NEXT: addl $32, %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: retl ; X32-NEXT: retl
%t1 = atomicrmw min i64* @sc64, i64 %x acquire %t1 = atomicrmw min i64* @sc64, i64 %x acquire
ret void ret void
} }
Show All 27 Lines
; X32-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: cmovbl %edx, %ecx ; X32-NEXT: cmovbl %edx, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: cmovbl %eax, %ebx ; X32-NEXT: cmovbl %eax, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB8_1 ; X32-NEXT: je .LBB8_2
; X32-NEXT: jmp .LBB8_2 ; X32-NEXT: jmp .LBB8_1
; X32-NEXT: .LBB8_2: # %atomicrmw.end ; X32-NEXT: .LBB8_2: # %atomicrmw.end
; X32-NEXT: addl $32, %esp ; X32-NEXT: addl $32, %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: retl ; X32-NEXT: retl
%t1 = atomicrmw umax i64* @sc64, i64 %x acquire %t1 = atomicrmw umax i64* @sc64, i64 %x acquire
ret void ret void
} }
Show All 27 Lines
; X32-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: cmovael %edx, %ecx ; X32-NEXT: cmovael %edx, %ecx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: cmovael %eax, %ebx ; X32-NEXT: cmovael %eax, %ebx
; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB9_1 ; X32-NEXT: je .LBB9_2
; X32-NEXT: jmp .LBB9_2 ; X32-NEXT: jmp .LBB9_1
; X32-NEXT: .LBB9_2: # %atomicrmw.end ; X32-NEXT: .LBB9_2: # %atomicrmw.end
; X32-NEXT: addl $32, %esp ; X32-NEXT: addl $32, %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: retl ; X32-NEXT: retl
%t1 = atomicrmw umin i64* @sc64, i64 %x acquire %t1 = atomicrmw umin i64* @sc64, i64 %x acquire
ret void ret void
} }
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X32-NEXT: movl (%esp), %ecx # 4-byte Reload ; X32-NEXT: movl (%esp), %ecx # 4-byte Reload
; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: jne .LBB12_1 ; X32-NEXT: je .LBB12_2
; X32-NEXT: jmp .LBB12_2 ; X32-NEXT: jmp .LBB12_1
; X32-NEXT: .LBB12_2: # %atomicrmw.end ; X32-NEXT: .LBB12_2: # %atomicrmw.end
; X32-NEXT: addl $16, %esp ; X32-NEXT: addl $16, %esp
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: retl ; X32-NEXT: retl
%t1 = atomicrmw xchg i64* @sc64, i64 %x acquire %t1 = atomicrmw xchg i64* @sc64, i64 %x acquire
ret void ret void
} }

llvm/test/CodeGen/X86/avoid-sfb.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=x86-64 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=x86-64 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=x86-64 --x86-disable-avoid-SFB -verify-machineinstrs | FileCheck %s --check-prefix=DISABLED ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=x86-64 --x86-disable-avoid-SFB -verify-machineinstrs | FileCheck %s --check-prefix=DISABLED
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=core-avx2 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-AVX2 ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=core-avx2 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-AVX2
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=skx -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-AVX512 ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=skx -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-AVX512
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
%struct.S = type { i32, i32, i32, i32 } %struct.S = type { i32, i32, i32, i32 }
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define void @test_conditional_block(%struct.S* nocapture noalias %s1 , %struct.S* nocapture noalias %s2, i32 %x, %struct.S* nocapture noalias %s3, %struct.S* nocapture noalias readonly %s4) local_unnamed_addr #0 { define void @test_conditional_block(%struct.S* nocapture noalias %s1 , %struct.S* nocapture noalias %s2, i32 %x, %struct.S* nocapture noalias %s3, %struct.S* nocapture noalias readonly %s4) local_unnamed_addr #0 {
; CHECK-LABEL: test_conditional_block: ; CHECK-LABEL: test_conditional_block:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpl $18, %edx ; CHECK-NEXT: cmpl $17, %edx
; CHECK-NEXT: jl .LBB0_2 ; CHECK-NEXT: jle .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movl %edx, 4(%rdi) ; CHECK-NEXT: movl %edx, 4(%rdi)
; CHECK-NEXT: .LBB0_2: # %if.end ; CHECK-NEXT: .LBB0_2: # %if.end
; CHECK-NEXT: movups (%r8), %xmm0 ; CHECK-NEXT: movups (%r8), %xmm0
; CHECK-NEXT: movups %xmm0, (%rcx) ; CHECK-NEXT: movups %xmm0, (%rcx)
; CHECK-NEXT: movl (%rdi), %eax ; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: movl %eax, (%rsi) ; CHECK-NEXT: movl %eax, (%rsi)
; CHECK-NEXT: movl 4(%rdi), %eax ; CHECK-NEXT: movl 4(%rdi), %eax
; CHECK-NEXT: movl %eax, 4(%rsi) ; CHECK-NEXT: movl %eax, 4(%rsi)
; CHECK-NEXT: movq 8(%rdi), %rax ; CHECK-NEXT: movq 8(%rdi), %rax
; CHECK-NEXT: movq %rax, 8(%rsi) ; CHECK-NEXT: movq %rax, 8(%rsi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_conditional_block: ; DISABLED-LABEL: test_conditional_block:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: cmpl $18, %edx ; DISABLED-NEXT: cmpl $17, %edx
; DISABLED-NEXT: jl .LBB0_2 ; DISABLED-NEXT: jle .LBB0_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movl %edx, 4(%rdi) ; DISABLED-NEXT: movl %edx, 4(%rdi)
; DISABLED-NEXT: .LBB0_2: # %if.end ; DISABLED-NEXT: .LBB0_2: # %if.end
; DISABLED-NEXT: movups (%r8), %xmm0 ; DISABLED-NEXT: movups (%r8), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rcx) ; DISABLED-NEXT: movups %xmm0, (%rcx)
; DISABLED-NEXT: movups (%rdi), %xmm0 ; DISABLED-NEXT: movups (%rdi), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rsi) ; DISABLED-NEXT: movups %xmm0, (%rsi)
; DISABLED-NEXT: retq ; DISABLED-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_conditional_block: ; CHECK-AVX2-LABEL: test_conditional_block:
; CHECK-AVX2: # %bb.0: # %entry ; CHECK-AVX2: # %bb.0: # %entry
; CHECK-AVX2-NEXT: cmpl $18, %edx ; CHECK-AVX2-NEXT: cmpl $17, %edx
; CHECK-AVX2-NEXT: jl .LBB0_2 ; CHECK-AVX2-NEXT: jle .LBB0_2
; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: # %bb.1: # %if.then
; CHECK-AVX2-NEXT: movl %edx, 4(%rdi) ; CHECK-AVX2-NEXT: movl %edx, 4(%rdi)
; CHECK-AVX2-NEXT: .LBB0_2: # %if.end ; CHECK-AVX2-NEXT: .LBB0_2: # %if.end
; CHECK-AVX2-NEXT: vmovups (%r8), %xmm0 ; CHECK-AVX2-NEXT: vmovups (%r8), %xmm0
; CHECK-AVX2-NEXT: vmovups %xmm0, (%rcx) ; CHECK-AVX2-NEXT: vmovups %xmm0, (%rcx)
; CHECK-AVX2-NEXT: movl (%rdi), %eax ; CHECK-AVX2-NEXT: movl (%rdi), %eax
; CHECK-AVX2-NEXT: movl %eax, (%rsi) ; CHECK-AVX2-NEXT: movl %eax, (%rsi)
; CHECK-AVX2-NEXT: movl 4(%rdi), %eax ; CHECK-AVX2-NEXT: movl 4(%rdi), %eax
; CHECK-AVX2-NEXT: movl %eax, 4(%rsi) ; CHECK-AVX2-NEXT: movl %eax, 4(%rsi)
; CHECK-AVX2-NEXT: movq 8(%rdi), %rax ; CHECK-AVX2-NEXT: movq 8(%rdi), %rax
; CHECK-AVX2-NEXT: movq %rax, 8(%rsi) ; CHECK-AVX2-NEXT: movq %rax, 8(%rsi)
; CHECK-AVX2-NEXT: retq ; CHECK-AVX2-NEXT: retq
; ;
; CHECK-AVX512-LABEL: test_conditional_block: ; CHECK-AVX512-LABEL: test_conditional_block:
; CHECK-AVX512: # %bb.0: # %entry ; CHECK-AVX512: # %bb.0: # %entry
; CHECK-AVX512-NEXT: cmpl $18, %edx ; CHECK-AVX512-NEXT: cmpl $17, %edx
; CHECK-AVX512-NEXT: jl .LBB0_2 ; CHECK-AVX512-NEXT: jle .LBB0_2
; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: # %bb.1: # %if.then
; CHECK-AVX512-NEXT: movl %edx, 4(%rdi) ; CHECK-AVX512-NEXT: movl %edx, 4(%rdi)
; CHECK-AVX512-NEXT: .LBB0_2: # %if.end ; CHECK-AVX512-NEXT: .LBB0_2: # %if.end
; CHECK-AVX512-NEXT: vmovups (%r8), %xmm0 ; CHECK-AVX512-NEXT: vmovups (%r8), %xmm0
; CHECK-AVX512-NEXT: vmovups %xmm0, (%rcx) ; CHECK-AVX512-NEXT: vmovups %xmm0, (%rcx)
; CHECK-AVX512-NEXT: movl (%rdi), %eax ; CHECK-AVX512-NEXT: movl (%rdi), %eax
; CHECK-AVX512-NEXT: movl %eax, (%rsi) ; CHECK-AVX512-NEXT: movl %eax, (%rsi)
; CHECK-AVX512-NEXT: movl 4(%rdi), %eax ; CHECK-AVX512-NEXT: movl 4(%rdi), %eax
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Linesentry:
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 16, i32 4, i1 false) tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 16, i32 4, i1 false)
ret void ret void
} }
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define void @test_nondirect_br(%struct.S* nocapture noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 { define void @test_nondirect_br(%struct.S* nocapture noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
; CHECK-LABEL: test_nondirect_br: ; CHECK-LABEL: test_nondirect_br:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpl $18, %edx ; CHECK-NEXT: cmpl $17, %edx
; CHECK-NEXT: jl .LBB2_2 ; CHECK-NEXT: jle .LBB2_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movl %edx, 4(%rdi) ; CHECK-NEXT: movl %edx, 4(%rdi)
; CHECK-NEXT: .LBB2_2: # %if.end ; CHECK-NEXT: .LBB2_2: # %if.end
; CHECK-NEXT: cmpl $14, %r9d ; CHECK-NEXT: cmpl $13, %r9d
; CHECK-NEXT: jl .LBB2_4 ; CHECK-NEXT: jle .LBB2_4
; CHECK-NEXT: # %bb.3: # %if.then2 ; CHECK-NEXT: # %bb.3: # %if.then2
; CHECK-NEXT: movl %r9d, 12(%rdi) ; CHECK-NEXT: movl %r9d, 12(%rdi)
; CHECK-NEXT: .LBB2_4: # %if.end3 ; CHECK-NEXT: .LBB2_4: # %if.end3
; CHECK-NEXT: movups (%r8), %xmm0 ; CHECK-NEXT: movups (%r8), %xmm0
; CHECK-NEXT: movups %xmm0, (%rcx) ; CHECK-NEXT: movups %xmm0, (%rcx)
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq %rax, (%rsi) ; CHECK-NEXT: movq %rax, (%rsi)
; CHECK-NEXT: movl 8(%rdi), %eax ; CHECK-NEXT: movl 8(%rdi), %eax
; CHECK-NEXT: movl %eax, 8(%rsi) ; CHECK-NEXT: movl %eax, 8(%rsi)
; CHECK-NEXT: movl 12(%rdi), %eax ; CHECK-NEXT: movl 12(%rdi), %eax
; CHECK-NEXT: movl %eax, 12(%rsi) ; CHECK-NEXT: movl %eax, 12(%rsi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_nondirect_br: ; DISABLED-LABEL: test_nondirect_br:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: cmpl $18, %edx ; DISABLED-NEXT: cmpl $17, %edx
; DISABLED-NEXT: jl .LBB2_2 ; DISABLED-NEXT: jle .LBB2_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movl %edx, 4(%rdi) ; DISABLED-NEXT: movl %edx, 4(%rdi)
; DISABLED-NEXT: .LBB2_2: # %if.end ; DISABLED-NEXT: .LBB2_2: # %if.end
; DISABLED-NEXT: cmpl $14, %r9d ; DISABLED-NEXT: cmpl $13, %r9d
; DISABLED-NEXT: jl .LBB2_4 ; DISABLED-NEXT: jle .LBB2_4
; DISABLED-NEXT: # %bb.3: # %if.then2 ; DISABLED-NEXT: # %bb.3: # %if.then2
; DISABLED-NEXT: movl %r9d, 12(%rdi) ; DISABLED-NEXT: movl %r9d, 12(%rdi)
; DISABLED-NEXT: .LBB2_4: # %if.end3 ; DISABLED-NEXT: .LBB2_4: # %if.end3
; DISABLED-NEXT: movups (%r8), %xmm0 ; DISABLED-NEXT: movups (%r8), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rcx) ; DISABLED-NEXT: movups %xmm0, (%rcx)
; DISABLED-NEXT: movups (%rdi), %xmm0 ; DISABLED-NEXT: movups (%rdi), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rsi) ; DISABLED-NEXT: movups %xmm0, (%rsi)
; DISABLED-NEXT: retq ; DISABLED-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_nondirect_br: ; CHECK-AVX2-LABEL: test_nondirect_br:
; CHECK-AVX2: # %bb.0: # %entry ; CHECK-AVX2: # %bb.0: # %entry
; CHECK-AVX2-NEXT: cmpl $18, %edx ; CHECK-AVX2-NEXT: cmpl $17, %edx
; CHECK-AVX2-NEXT: jl .LBB2_2 ; CHECK-AVX2-NEXT: jle .LBB2_2
; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: # %bb.1: # %if.then
; CHECK-AVX2-NEXT: movl %edx, 4(%rdi) ; CHECK-AVX2-NEXT: movl %edx, 4(%rdi)
; CHECK-AVX2-NEXT: .LBB2_2: # %if.end ; CHECK-AVX2-NEXT: .LBB2_2: # %if.end
; CHECK-AVX2-NEXT: cmpl $14, %r9d ; CHECK-AVX2-NEXT: cmpl $13, %r9d
; CHECK-AVX2-NEXT: jl .LBB2_4 ; CHECK-AVX2-NEXT: jle .LBB2_4
; CHECK-AVX2-NEXT: # %bb.3: # %if.then2 ; CHECK-AVX2-NEXT: # %bb.3: # %if.then2
; CHECK-AVX2-NEXT: movl %r9d, 12(%rdi) ; CHECK-AVX2-NEXT: movl %r9d, 12(%rdi)
; CHECK-AVX2-NEXT: .LBB2_4: # %if.end3 ; CHECK-AVX2-NEXT: .LBB2_4: # %if.end3
; CHECK-AVX2-NEXT: vmovups (%r8), %xmm0 ; CHECK-AVX2-NEXT: vmovups (%r8), %xmm0
; CHECK-AVX2-NEXT: vmovups %xmm0, (%rcx) ; CHECK-AVX2-NEXT: vmovups %xmm0, (%rcx)
; CHECK-AVX2-NEXT: movq (%rdi), %rax ; CHECK-AVX2-NEXT: movq (%rdi), %rax
; CHECK-AVX2-NEXT: movq %rax, (%rsi) ; CHECK-AVX2-NEXT: movq %rax, (%rsi)
; CHECK-AVX2-NEXT: movl 8(%rdi), %eax ; CHECK-AVX2-NEXT: movl 8(%rdi), %eax
; CHECK-AVX2-NEXT: movl %eax, 8(%rsi) ; CHECK-AVX2-NEXT: movl %eax, 8(%rsi)
; CHECK-AVX2-NEXT: movl 12(%rdi), %eax ; CHECK-AVX2-NEXT: movl 12(%rdi), %eax
; CHECK-AVX2-NEXT: movl %eax, 12(%rsi) ; CHECK-AVX2-NEXT: movl %eax, 12(%rsi)
; CHECK-AVX2-NEXT: retq ; CHECK-AVX2-NEXT: retq
; ;
; CHECK-AVX512-LABEL: test_nondirect_br: ; CHECK-AVX512-LABEL: test_nondirect_br:
; CHECK-AVX512: # %bb.0: # %entry ; CHECK-AVX512: # %bb.0: # %entry
; CHECK-AVX512-NEXT: cmpl $18, %edx ; CHECK-AVX512-NEXT: cmpl $17, %edx
; CHECK-AVX512-NEXT: jl .LBB2_2 ; CHECK-AVX512-NEXT: jle .LBB2_2
; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: # %bb.1: # %if.then
; CHECK-AVX512-NEXT: movl %edx, 4(%rdi) ; CHECK-AVX512-NEXT: movl %edx, 4(%rdi)
; CHECK-AVX512-NEXT: .LBB2_2: # %if.end ; CHECK-AVX512-NEXT: .LBB2_2: # %if.end
; CHECK-AVX512-NEXT: cmpl $14, %r9d ; CHECK-AVX512-NEXT: cmpl $13, %r9d
; CHECK-AVX512-NEXT: jl .LBB2_4 ; CHECK-AVX512-NEXT: jle .LBB2_4
; CHECK-AVX512-NEXT: # %bb.3: # %if.then2 ; CHECK-AVX512-NEXT: # %bb.3: # %if.then2
; CHECK-AVX512-NEXT: movl %r9d, 12(%rdi) ; CHECK-AVX512-NEXT: movl %r9d, 12(%rdi)
; CHECK-AVX512-NEXT: .LBB2_4: # %if.end3 ; CHECK-AVX512-NEXT: .LBB2_4: # %if.end3
; CHECK-AVX512-NEXT: vmovups (%r8), %xmm0 ; CHECK-AVX512-NEXT: vmovups (%r8), %xmm0
; CHECK-AVX512-NEXT: vmovups %xmm0, (%rcx) ; CHECK-AVX512-NEXT: vmovups %xmm0, (%rcx)
; CHECK-AVX512-NEXT: movq (%rdi), %rax ; CHECK-AVX512-NEXT: movq (%rdi), %rax
; CHECK-AVX512-NEXT: movq %rax, (%rsi) ; CHECK-AVX512-NEXT: movq %rax, (%rsi)
; CHECK-AVX512-NEXT: movl 8(%rdi), %eax ; CHECK-AVX512-NEXT: movl 8(%rdi), %eax
Show All 29 Linesif.end3: ; preds = %if.then2, %if.end
ret void ret void
} }
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define void @test_2preds_block(%struct.S* nocapture noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 { define void @test_2preds_block(%struct.S* nocapture noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
; CHECK-LABEL: test_2preds_block: ; CHECK-LABEL: test_2preds_block:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %r9d, 12(%rdi) ; CHECK-NEXT: movl %r9d, 12(%rdi)
; CHECK-NEXT: cmpl $18, %edx ; CHECK-NEXT: cmpl $17, %edx
; CHECK-NEXT: jl .LBB3_2 ; CHECK-NEXT: jle .LBB3_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movl %edx, 4(%rdi) ; CHECK-NEXT: movl %edx, 4(%rdi)
; CHECK-NEXT: .LBB3_2: # %if.end ; CHECK-NEXT: .LBB3_2: # %if.end
; CHECK-NEXT: movups (%r8), %xmm0 ; CHECK-NEXT: movups (%r8), %xmm0
; CHECK-NEXT: movups %xmm0, (%rcx) ; CHECK-NEXT: movups %xmm0, (%rcx)
; CHECK-NEXT: movl (%rdi), %eax ; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: movl %eax, (%rsi) ; CHECK-NEXT: movl %eax, (%rsi)
; CHECK-NEXT: movl 4(%rdi), %eax ; CHECK-NEXT: movl 4(%rdi), %eax
; CHECK-NEXT: movl %eax, 4(%rsi) ; CHECK-NEXT: movl %eax, 4(%rsi)
; CHECK-NEXT: movl 8(%rdi), %eax ; CHECK-NEXT: movl 8(%rdi), %eax
; CHECK-NEXT: movl %eax, 8(%rsi) ; CHECK-NEXT: movl %eax, 8(%rsi)
; CHECK-NEXT: movl 12(%rdi), %eax ; CHECK-NEXT: movl 12(%rdi), %eax
; CHECK-NEXT: movl %eax, 12(%rsi) ; CHECK-NEXT: movl %eax, 12(%rsi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_2preds_block: ; DISABLED-LABEL: test_2preds_block:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: movl %r9d, 12(%rdi) ; DISABLED-NEXT: movl %r9d, 12(%rdi)
; DISABLED-NEXT: cmpl $18, %edx ; DISABLED-NEXT: cmpl $17, %edx
; DISABLED-NEXT: jl .LBB3_2 ; DISABLED-NEXT: jle .LBB3_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movl %edx, 4(%rdi) ; DISABLED-NEXT: movl %edx, 4(%rdi)
; DISABLED-NEXT: .LBB3_2: # %if.end ; DISABLED-NEXT: .LBB3_2: # %if.end
; DISABLED-NEXT: movups (%r8), %xmm0 ; DISABLED-NEXT: movups (%r8), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rcx) ; DISABLED-NEXT: movups %xmm0, (%rcx)
; DISABLED-NEXT: movups (%rdi), %xmm0 ; DISABLED-NEXT: movups (%rdi), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rsi) ; DISABLED-NEXT: movups %xmm0, (%rsi)
; DISABLED-NEXT: retq ; DISABLED-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_2preds_block: ; CHECK-AVX2-LABEL: test_2preds_block:
; CHECK-AVX2: # %bb.0: # %entry ; CHECK-AVX2: # %bb.0: # %entry
; CHECK-AVX2-NEXT: movl %r9d, 12(%rdi) ; CHECK-AVX2-NEXT: movl %r9d, 12(%rdi)
; CHECK-AVX2-NEXT: cmpl $18, %edx ; CHECK-AVX2-NEXT: cmpl $17, %edx
; CHECK-AVX2-NEXT: jl .LBB3_2 ; CHECK-AVX2-NEXT: jle .LBB3_2
; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: # %bb.1: # %if.then
; CHECK-AVX2-NEXT: movl %edx, 4(%rdi) ; CHECK-AVX2-NEXT: movl %edx, 4(%rdi)
; CHECK-AVX2-NEXT: .LBB3_2: # %if.end ; CHECK-AVX2-NEXT: .LBB3_2: # %if.end
; CHECK-AVX2-NEXT: vmovups (%r8), %xmm0 ; CHECK-AVX2-NEXT: vmovups (%r8), %xmm0
; CHECK-AVX2-NEXT: vmovups %xmm0, (%rcx) ; CHECK-AVX2-NEXT: vmovups %xmm0, (%rcx)
; CHECK-AVX2-NEXT: movl (%rdi), %eax ; CHECK-AVX2-NEXT: movl (%rdi), %eax
; CHECK-AVX2-NEXT: movl %eax, (%rsi) ; CHECK-AVX2-NEXT: movl %eax, (%rsi)
; CHECK-AVX2-NEXT: movl 4(%rdi), %eax ; CHECK-AVX2-NEXT: movl 4(%rdi), %eax
; CHECK-AVX2-NEXT: movl %eax, 4(%rsi) ; CHECK-AVX2-NEXT: movl %eax, 4(%rsi)
; CHECK-AVX2-NEXT: movl 8(%rdi), %eax ; CHECK-AVX2-NEXT: movl 8(%rdi), %eax
; CHECK-AVX2-NEXT: movl %eax, 8(%rsi) ; CHECK-AVX2-NEXT: movl %eax, 8(%rsi)
; CHECK-AVX2-NEXT: movl 12(%rdi), %eax ; CHECK-AVX2-NEXT: movl 12(%rdi), %eax
; CHECK-AVX2-NEXT: movl %eax, 12(%rsi) ; CHECK-AVX2-NEXT: movl %eax, 12(%rsi)
; CHECK-AVX2-NEXT: retq ; CHECK-AVX2-NEXT: retq
; ;
; CHECK-AVX512-LABEL: test_2preds_block: ; CHECK-AVX512-LABEL: test_2preds_block:
; CHECK-AVX512: # %bb.0: # %entry ; CHECK-AVX512: # %bb.0: # %entry
; CHECK-AVX512-NEXT: movl %r9d, 12(%rdi) ; CHECK-AVX512-NEXT: movl %r9d, 12(%rdi)
; CHECK-AVX512-NEXT: cmpl $18, %edx ; CHECK-AVX512-NEXT: cmpl $17, %edx
; CHECK-AVX512-NEXT: jl .LBB3_2 ; CHECK-AVX512-NEXT: jle .LBB3_2
; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: # %bb.1: # %if.then
; CHECK-AVX512-NEXT: movl %edx, 4(%rdi) ; CHECK-AVX512-NEXT: movl %edx, 4(%rdi)
; CHECK-AVX512-NEXT: .LBB3_2: # %if.end ; CHECK-AVX512-NEXT: .LBB3_2: # %if.end
; CHECK-AVX512-NEXT: vmovups (%r8), %xmm0 ; CHECK-AVX512-NEXT: vmovups (%r8), %xmm0
; CHECK-AVX512-NEXT: vmovups %xmm0, (%rcx) ; CHECK-AVX512-NEXT: vmovups %xmm0, (%rcx)
; CHECK-AVX512-NEXT: movl (%rdi), %eax ; CHECK-AVX512-NEXT: movl (%rdi), %eax
; CHECK-AVX512-NEXT: movl %eax, (%rsi) ; CHECK-AVX512-NEXT: movl %eax, (%rsi)
; CHECK-AVX512-NEXT: movl 4(%rdi), %eax ; CHECK-AVX512-NEXT: movl 4(%rdi), %eax
Show All 24 Linesif.end: ; preds = %if.then, %entry
ret void ret void
} }
%struct.S2 = type { i64, i64 } %struct.S2 = type { i64, i64 }
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define void @test_type64(%struct.S2* nocapture noalias %s1, %struct.S2* nocapture %s2, i32 %x, %struct.S2* nocapture %s3, %struct.S2* nocapture readonly %s4) local_unnamed_addr #0 { define void @test_type64(%struct.S2* nocapture noalias %s1, %struct.S2* nocapture %s2, i32 %x, %struct.S2* nocapture %s3, %struct.S2* nocapture readonly %s4) local_unnamed_addr #0 {
; CHECK-LABEL: test_type64: ; CHECK-LABEL: test_type64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpl $18, %edx ; CHECK-NEXT: cmpl $17, %edx
; CHECK-NEXT: jl .LBB4_2 ; CHECK-NEXT: jle .LBB4_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movslq %edx, %rax ; CHECK-NEXT: movslq %edx, %rax
; CHECK-NEXT: movq %rax, 8(%rdi) ; CHECK-NEXT: movq %rax, 8(%rdi)
; CHECK-NEXT: .LBB4_2: # %if.end ; CHECK-NEXT: .LBB4_2: # %if.end
; CHECK-NEXT: movups (%r8), %xmm0 ; CHECK-NEXT: movups (%r8), %xmm0
; CHECK-NEXT: movups %xmm0, (%rcx) ; CHECK-NEXT: movups %xmm0, (%rcx)
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq %rax, (%rsi) ; CHECK-NEXT: movq %rax, (%rsi)
; CHECK-NEXT: movq 8(%rdi), %rax ; CHECK-NEXT: movq 8(%rdi), %rax
; CHECK-NEXT: movq %rax, 8(%rsi) ; CHECK-NEXT: movq %rax, 8(%rsi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_type64: ; DISABLED-LABEL: test_type64:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: cmpl $18, %edx ; DISABLED-NEXT: cmpl $17, %edx
; DISABLED-NEXT: jl .LBB4_2 ; DISABLED-NEXT: jle .LBB4_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movslq %edx, %rax ; DISABLED-NEXT: movslq %edx, %rax
; DISABLED-NEXT: movq %rax, 8(%rdi) ; DISABLED-NEXT: movq %rax, 8(%rdi)
; DISABLED-NEXT: .LBB4_2: # %if.end ; DISABLED-NEXT: .LBB4_2: # %if.end
; DISABLED-NEXT: movups (%r8), %xmm0 ; DISABLED-NEXT: movups (%r8), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rcx) ; DISABLED-NEXT: movups %xmm0, (%rcx)
; DISABLED-NEXT: movups (%rdi), %xmm0 ; DISABLED-NEXT: movups (%rdi), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rsi) ; DISABLED-NEXT: movups %xmm0, (%rsi)
; DISABLED-NEXT: retq ; DISABLED-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_type64: ; CHECK-AVX2-LABEL: test_type64:
; CHECK-AVX2: # %bb.0: # %entry ; CHECK-AVX2: # %bb.0: # %entry
; CHECK-AVX2-NEXT: cmpl $18, %edx ; CHECK-AVX2-NEXT: cmpl $17, %edx
; CHECK-AVX2-NEXT: jl .LBB4_2 ; CHECK-AVX2-NEXT: jle .LBB4_2
; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: # %bb.1: # %if.then
; CHECK-AVX2-NEXT: movslq %edx, %rax ; CHECK-AVX2-NEXT: movslq %edx, %rax
; CHECK-AVX2-NEXT: movq %rax, 8(%rdi) ; CHECK-AVX2-NEXT: movq %rax, 8(%rdi)
; CHECK-AVX2-NEXT: .LBB4_2: # %if.end ; CHECK-AVX2-NEXT: .LBB4_2: # %if.end
; CHECK-AVX2-NEXT: vmovups (%r8), %xmm0 ; CHECK-AVX2-NEXT: vmovups (%r8), %xmm0
; CHECK-AVX2-NEXT: vmovups %xmm0, (%rcx) ; CHECK-AVX2-NEXT: vmovups %xmm0, (%rcx)
; CHECK-AVX2-NEXT: movq (%rdi), %rax ; CHECK-AVX2-NEXT: movq (%rdi), %rax
; CHECK-AVX2-NEXT: movq %rax, (%rsi) ; CHECK-AVX2-NEXT: movq %rax, (%rsi)
; CHECK-AVX2-NEXT: movq 8(%rdi), %rax ; CHECK-AVX2-NEXT: movq 8(%rdi), %rax
; CHECK-AVX2-NEXT: movq %rax, 8(%rsi) ; CHECK-AVX2-NEXT: movq %rax, 8(%rsi)
; CHECK-AVX2-NEXT: retq ; CHECK-AVX2-NEXT: retq
; ;
; CHECK-AVX512-LABEL: test_type64: ; CHECK-AVX512-LABEL: test_type64:
; CHECK-AVX512: # %bb.0: # %entry ; CHECK-AVX512: # %bb.0: # %entry
; CHECK-AVX512-NEXT: cmpl $18, %edx ; CHECK-AVX512-NEXT: cmpl $17, %edx
; CHECK-AVX512-NEXT: jl .LBB4_2 ; CHECK-AVX512-NEXT: jle .LBB4_2
; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: # %bb.1: # %if.then
; CHECK-AVX512-NEXT: movslq %edx, %rax ; CHECK-AVX512-NEXT: movslq %edx, %rax
; CHECK-AVX512-NEXT: movq %rax, 8(%rdi) ; CHECK-AVX512-NEXT: movq %rax, 8(%rdi)
; CHECK-AVX512-NEXT: .LBB4_2: # %if.end ; CHECK-AVX512-NEXT: .LBB4_2: # %if.end
; CHECK-AVX512-NEXT: vmovups (%r8), %xmm0 ; CHECK-AVX512-NEXT: vmovups (%r8), %xmm0
; CHECK-AVX512-NEXT: vmovups %xmm0, (%rcx) ; CHECK-AVX512-NEXT: vmovups %xmm0, (%rcx)
; CHECK-AVX512-NEXT: movq (%rdi), %rax ; CHECK-AVX512-NEXT: movq (%rdi), %rax
; CHECK-AVX512-NEXT: movq %rax, (%rsi) ; CHECK-AVX512-NEXT: movq %rax, (%rsi)
Show All 20 Linesif.end: ; preds = %if.then, %entry
ret void ret void
} }
%struct.S3 = type { i64, i8, i8, i16, i32 } %struct.S3 = type { i64, i8, i8, i16, i32 }
; Function Attrs: noinline nounwind uwtable ; Function Attrs: noinline nounwind uwtable
define void @test_mixed_type(%struct.S3* nocapture noalias %s1, %struct.S3* nocapture %s2, i32 %x, %struct.S3* nocapture readnone %s3, %struct.S3* nocapture readnone %s4) local_unnamed_addr #0 { define void @test_mixed_type(%struct.S3* nocapture noalias %s1, %struct.S3* nocapture %s2, i32 %x, %struct.S3* nocapture readnone %s3, %struct.S3* nocapture readnone %s4) local_unnamed_addr #0 {
; CHECK-LABEL: test_mixed_type: ; CHECK-LABEL: test_mixed_type:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpl $18, %edx ; CHECK-NEXT: cmpl $17, %edx
; CHECK-NEXT: jl .LBB5_2 ; CHECK-NEXT: jle .LBB5_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movslq %edx, %rax ; CHECK-NEXT: movslq %edx, %rax
; CHECK-NEXT: movq %rax, (%rdi) ; CHECK-NEXT: movq %rax, (%rdi)
; CHECK-NEXT: movb %dl, 8(%rdi) ; CHECK-NEXT: movb %dl, 8(%rdi)
; CHECK-NEXT: .LBB5_2: # %if.end ; CHECK-NEXT: .LBB5_2: # %if.end
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq %rax, (%rsi) ; CHECK-NEXT: movq %rax, (%rsi)
; CHECK-NEXT: movb 8(%rdi), %al ; CHECK-NEXT: movb 8(%rdi), %al
; CHECK-NEXT: movb %al, 8(%rsi) ; CHECK-NEXT: movb %al, 8(%rsi)
; CHECK-NEXT: movl 9(%rdi), %eax ; CHECK-NEXT: movl 9(%rdi), %eax
; CHECK-NEXT: movl %eax, 9(%rsi) ; CHECK-NEXT: movl %eax, 9(%rsi)
; CHECK-NEXT: movzwl 13(%rdi), %eax ; CHECK-NEXT: movzwl 13(%rdi), %eax
; CHECK-NEXT: movw %ax, 13(%rsi) ; CHECK-NEXT: movw %ax, 13(%rsi)
; CHECK-NEXT: movb 15(%rdi), %al ; CHECK-NEXT: movb 15(%rdi), %al
; CHECK-NEXT: movb %al, 15(%rsi) ; CHECK-NEXT: movb %al, 15(%rsi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_mixed_type: ; DISABLED-LABEL: test_mixed_type:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: cmpl $18, %edx ; DISABLED-NEXT: cmpl $17, %edx
; DISABLED-NEXT: jl .LBB5_2 ; DISABLED-NEXT: jle .LBB5_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movslq %edx, %rax ; DISABLED-NEXT: movslq %edx, %rax
; DISABLED-NEXT: movq %rax, (%rdi) ; DISABLED-NEXT: movq %rax, (%rdi)
; DISABLED-NEXT: movb %dl, 8(%rdi) ; DISABLED-NEXT: movb %dl, 8(%rdi)
; DISABLED-NEXT: .LBB5_2: # %if.end ; DISABLED-NEXT: .LBB5_2: # %if.end
; DISABLED-NEXT: movups (%rdi), %xmm0 ; DISABLED-NEXT: movups (%rdi), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rsi) ; DISABLED-NEXT: movups %xmm0, (%rsi)
; DISABLED-NEXT: retq ; DISABLED-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_mixed_type: ; CHECK-AVX2-LABEL: test_mixed_type:
; CHECK-AVX2: # %bb.0: # %entry ; CHECK-AVX2: # %bb.0: # %entry
; CHECK-AVX2-NEXT: cmpl $18, %edx ; CHECK-AVX2-NEXT: cmpl $17, %edx
; CHECK-AVX2-NEXT: jl .LBB5_2 ; CHECK-AVX2-NEXT: jle .LBB5_2
; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: # %bb.1: # %if.then
; CHECK-AVX2-NEXT: movslq %edx, %rax ; CHECK-AVX2-NEXT: movslq %edx, %rax
; CHECK-AVX2-NEXT: movq %rax, (%rdi) ; CHECK-AVX2-NEXT: movq %rax, (%rdi)
; CHECK-AVX2-NEXT: movb %dl, 8(%rdi) ; CHECK-AVX2-NEXT: movb %dl, 8(%rdi)
; CHECK-AVX2-NEXT: .LBB5_2: # %if.end ; CHECK-AVX2-NEXT: .LBB5_2: # %if.end
; CHECK-AVX2-NEXT: movq (%rdi), %rax ; CHECK-AVX2-NEXT: movq (%rdi), %rax
; CHECK-AVX2-NEXT: movq %rax, (%rsi) ; CHECK-AVX2-NEXT: movq %rax, (%rsi)
; CHECK-AVX2-NEXT: movb 8(%rdi), %al ; CHECK-AVX2-NEXT: movb 8(%rdi), %al
; CHECK-AVX2-NEXT: movb %al, 8(%rsi) ; CHECK-AVX2-NEXT: movb %al, 8(%rsi)
; CHECK-AVX2-NEXT: movl 9(%rdi), %eax ; CHECK-AVX2-NEXT: movl 9(%rdi), %eax
; CHECK-AVX2-NEXT: movl %eax, 9(%rsi) ; CHECK-AVX2-NEXT: movl %eax, 9(%rsi)
; CHECK-AVX2-NEXT: movzwl 13(%rdi), %eax ; CHECK-AVX2-NEXT: movzwl 13(%rdi), %eax
; CHECK-AVX2-NEXT: movw %ax, 13(%rsi) ; CHECK-AVX2-NEXT: movw %ax, 13(%rsi)
; CHECK-AVX2-NEXT: movb 15(%rdi), %al ; CHECK-AVX2-NEXT: movb 15(%rdi), %al
; CHECK-AVX2-NEXT: movb %al, 15(%rsi) ; CHECK-AVX2-NEXT: movb %al, 15(%rsi)
; CHECK-AVX2-NEXT: retq ; CHECK-AVX2-NEXT: retq
; ;
; CHECK-AVX512-LABEL: test_mixed_type: ; CHECK-AVX512-LABEL: test_mixed_type:
; CHECK-AVX512: # %bb.0: # %entry ; CHECK-AVX512: # %bb.0: # %entry
; CHECK-AVX512-NEXT: cmpl $18, %edx ; CHECK-AVX512-NEXT: cmpl $17, %edx
; CHECK-AVX512-NEXT: jl .LBB5_2 ; CHECK-AVX512-NEXT: jle .LBB5_2
; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: # %bb.1: # %if.then
; CHECK-AVX512-NEXT: movslq %edx, %rax ; CHECK-AVX512-NEXT: movslq %edx, %rax
; CHECK-AVX512-NEXT: movq %rax, (%rdi) ; CHECK-AVX512-NEXT: movq %rax, (%rdi)
; CHECK-AVX512-NEXT: movb %dl, 8(%rdi) ; CHECK-AVX512-NEXT: movb %dl, 8(%rdi)
; CHECK-AVX512-NEXT: .LBB5_2: # %if.end ; CHECK-AVX512-NEXT: .LBB5_2: # %if.end
; CHECK-AVX512-NEXT: movq (%rdi), %rax ; CHECK-AVX512-NEXT: movq (%rdi), %rax
; CHECK-AVX512-NEXT: movq %rax, (%rsi) ; CHECK-AVX512-NEXT: movq %rax, (%rsi)
; CHECK-AVX512-NEXT: movb 8(%rdi), %al ; CHECK-AVX512-NEXT: movb 8(%rdi), %al
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
%struct.S5 = type { i16, i16, i16, i16, i16, i16, i16, i16 } %struct.S5 = type { i16, i16, i16, i16, i16, i16, i16, i16 }
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define void @test_type16(%struct.S5* nocapture noalias %s1, %struct.S5* nocapture %s2, i32 %x, %struct.S5* nocapture %s3, %struct.S5* nocapture readonly %s4) local_unnamed_addr #0 { define void @test_type16(%struct.S5* nocapture noalias %s1, %struct.S5* nocapture %s2, i32 %x, %struct.S5* nocapture %s3, %struct.S5* nocapture readonly %s4) local_unnamed_addr #0 {
; CHECK-LABEL: test_type16: ; CHECK-LABEL: test_type16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpl $18, %edx ; CHECK-NEXT: cmpl $17, %edx
; CHECK-NEXT: jl .LBB7_2 ; CHECK-NEXT: jle .LBB7_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movw %dx, 2(%rdi) ; CHECK-NEXT: movw %dx, 2(%rdi)
; CHECK-NEXT: .LBB7_2: # %if.end ; CHECK-NEXT: .LBB7_2: # %if.end
; CHECK-NEXT: movups (%r8), %xmm0 ; CHECK-NEXT: movups (%r8), %xmm0
; CHECK-NEXT: movups %xmm0, (%rcx) ; CHECK-NEXT: movups %xmm0, (%rcx)
; CHECK-NEXT: movzwl (%rdi), %eax ; CHECK-NEXT: movzwl (%rdi), %eax
; CHECK-NEXT: movw %ax, (%rsi) ; CHECK-NEXT: movw %ax, (%rsi)
; CHECK-NEXT: movzwl 2(%rdi), %eax ; CHECK-NEXT: movzwl 2(%rdi), %eax
; CHECK-NEXT: movw %ax, 2(%rsi) ; CHECK-NEXT: movw %ax, 2(%rsi)
; CHECK-NEXT: movq 4(%rdi), %rax ; CHECK-NEXT: movq 4(%rdi), %rax
; CHECK-NEXT: movq %rax, 4(%rsi) ; CHECK-NEXT: movq %rax, 4(%rsi)
; CHECK-NEXT: movl 12(%rdi), %eax ; CHECK-NEXT: movl 12(%rdi), %eax
; CHECK-NEXT: movl %eax, 12(%rsi) ; CHECK-NEXT: movl %eax, 12(%rsi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_type16: ; DISABLED-LABEL: test_type16:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: cmpl $18, %edx ; DISABLED-NEXT: cmpl $17, %edx
; DISABLED-NEXT: jl .LBB7_2 ; DISABLED-NEXT: jle .LBB7_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movw %dx, 2(%rdi) ; DISABLED-NEXT: movw %dx, 2(%rdi)
; DISABLED-NEXT: .LBB7_2: # %if.end ; DISABLED-NEXT: .LBB7_2: # %if.end
; DISABLED-NEXT: movups (%r8), %xmm0 ; DISABLED-NEXT: movups (%r8), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rcx) ; DISABLED-NEXT: movups %xmm0, (%rcx)
; DISABLED-NEXT: movups (%rdi), %xmm0 ; DISABLED-NEXT: movups (%rdi), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rsi) ; DISABLED-NEXT: movups %xmm0, (%rsi)
; DISABLED-NEXT: retq ; DISABLED-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_type16: ; CHECK-AVX2-LABEL: test_type16:
; CHECK-AVX2: # %bb.0: # %entry ; CHECK-AVX2: # %bb.0: # %entry
; CHECK-AVX2-NEXT: cmpl $18, %edx ; CHECK-AVX2-NEXT: cmpl $17, %edx
; CHECK-AVX2-NEXT: jl .LBB7_2 ; CHECK-AVX2-NEXT: jle .LBB7_2
; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: # %bb.1: # %if.then
; CHECK-AVX2-NEXT: movw %dx, 2(%rdi) ; CHECK-AVX2-NEXT: movw %dx, 2(%rdi)
; CHECK-AVX2-NEXT: .LBB7_2: # %if.end ; CHECK-AVX2-NEXT: .LBB7_2: # %if.end
; CHECK-AVX2-NEXT: vmovups (%r8), %xmm0 ; CHECK-AVX2-NEXT: vmovups (%r8), %xmm0
; CHECK-AVX2-NEXT: vmovups %xmm0, (%rcx) ; CHECK-AVX2-NEXT: vmovups %xmm0, (%rcx)
; CHECK-AVX2-NEXT: movzwl (%rdi), %eax ; CHECK-AVX2-NEXT: movzwl (%rdi), %eax
; CHECK-AVX2-NEXT: movw %ax, (%rsi) ; CHECK-AVX2-NEXT: movw %ax, (%rsi)
; CHECK-AVX2-NEXT: movzwl 2(%rdi), %eax ; CHECK-AVX2-NEXT: movzwl 2(%rdi), %eax
; CHECK-AVX2-NEXT: movw %ax, 2(%rsi) ; CHECK-AVX2-NEXT: movw %ax, 2(%rsi)
; CHECK-AVX2-NEXT: movq 4(%rdi), %rax ; CHECK-AVX2-NEXT: movq 4(%rdi), %rax
; CHECK-AVX2-NEXT: movq %rax, 4(%rsi) ; CHECK-AVX2-NEXT: movq %rax, 4(%rsi)
; CHECK-AVX2-NEXT: movl 12(%rdi), %eax ; CHECK-AVX2-NEXT: movl 12(%rdi), %eax
; CHECK-AVX2-NEXT: movl %eax, 12(%rsi) ; CHECK-AVX2-NEXT: movl %eax, 12(%rsi)
; CHECK-AVX2-NEXT: retq ; CHECK-AVX2-NEXT: retq
; ;
; CHECK-AVX512-LABEL: test_type16: ; CHECK-AVX512-LABEL: test_type16:
; CHECK-AVX512: # %bb.0: # %entry ; CHECK-AVX512: # %bb.0: # %entry
; CHECK-AVX512-NEXT: cmpl $18, %edx ; CHECK-AVX512-NEXT: cmpl $17, %edx
; CHECK-AVX512-NEXT: jl .LBB7_2 ; CHECK-AVX512-NEXT: jle .LBB7_2
; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: # %bb.1: # %if.then
; CHECK-AVX512-NEXT: movw %dx, 2(%rdi) ; CHECK-AVX512-NEXT: movw %dx, 2(%rdi)
; CHECK-AVX512-NEXT: .LBB7_2: # %if.end ; CHECK-AVX512-NEXT: .LBB7_2: # %if.end
; CHECK-AVX512-NEXT: vmovups (%r8), %xmm0 ; CHECK-AVX512-NEXT: vmovups (%r8), %xmm0
; CHECK-AVX512-NEXT: vmovups %xmm0, (%rcx) ; CHECK-AVX512-NEXT: vmovups %xmm0, (%rcx)
; CHECK-AVX512-NEXT: movzwl (%rdi), %eax ; CHECK-AVX512-NEXT: movzwl (%rdi), %eax
; CHECK-AVX512-NEXT: movw %ax, (%rsi) ; CHECK-AVX512-NEXT: movw %ax, (%rsi)
; CHECK-AVX512-NEXT: movzwl 2(%rdi), %eax ; CHECK-AVX512-NEXT: movzwl 2(%rdi), %eax
▲ Show 20 Lines • Show All 139 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .cfi_offset %rbp, -16 ; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %r8, %r15 ; CHECK-NEXT: movq %r8, %r15
; CHECK-NEXT: movq %rcx, %r14 ; CHECK-NEXT: movq %rcx, %r14
; CHECK-NEXT: movl %edx, %ebp ; CHECK-NEXT: movl %edx, %ebp
; CHECK-NEXT: movq %rsi, %r12 ; CHECK-NEXT: movq %rsi, %r12
; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl %r9d, 12(%rdi) ; CHECK-NEXT: movl %r9d, 12(%rdi)
; CHECK-NEXT: callq bar@PLT ; CHECK-NEXT: callq bar@PLT
; CHECK-NEXT: cmpl $18, %ebp ; CHECK-NEXT: cmpl $17, %ebp
; CHECK-NEXT: jl .LBB9_2 ; CHECK-NEXT: jle .LBB9_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movl %ebp, 4(%rbx) ; CHECK-NEXT: movl %ebp, 4(%rbx)
; CHECK-NEXT: movq %rbx, %rdi ; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: callq bar@PLT ; CHECK-NEXT: callq bar@PLT
; CHECK-NEXT: .LBB9_2: # %if.end ; CHECK-NEXT: .LBB9_2: # %if.end
; CHECK-NEXT: movups (%r15), %xmm0 ; CHECK-NEXT: movups (%r15), %xmm0
; CHECK-NEXT: movups %xmm0, (%r14) ; CHECK-NEXT: movups %xmm0, (%r14)
; CHECK-NEXT: movups (%rbx), %xmm0 ; CHECK-NEXT: movups (%rbx), %xmm0
Show All 29 Lines
; DISABLED-NEXT: .cfi_offset %rbp, -16 ; DISABLED-NEXT: .cfi_offset %rbp, -16
; DISABLED-NEXT: movq %r8, %r15 ; DISABLED-NEXT: movq %r8, %r15
; DISABLED-NEXT: movq %rcx, %r14 ; DISABLED-NEXT: movq %rcx, %r14
; DISABLED-NEXT: movl %edx, %ebp ; DISABLED-NEXT: movl %edx, %ebp
; DISABLED-NEXT: movq %rsi, %r12 ; DISABLED-NEXT: movq %rsi, %r12
; DISABLED-NEXT: movq %rdi, %rbx ; DISABLED-NEXT: movq %rdi, %rbx
; DISABLED-NEXT: movl %r9d, 12(%rdi) ; DISABLED-NEXT: movl %r9d, 12(%rdi)
; DISABLED-NEXT: callq bar@PLT ; DISABLED-NEXT: callq bar@PLT
; DISABLED-NEXT: cmpl $18, %ebp ; DISABLED-NEXT: cmpl $17, %ebp
; DISABLED-NEXT: jl .LBB9_2 ; DISABLED-NEXT: jle .LBB9_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movl %ebp, 4(%rbx) ; DISABLED-NEXT: movl %ebp, 4(%rbx)
; DISABLED-NEXT: movq %rbx, %rdi ; DISABLED-NEXT: movq %rbx, %rdi
; DISABLED-NEXT: callq bar@PLT ; DISABLED-NEXT: callq bar@PLT
; DISABLED-NEXT: .LBB9_2: # %if.end ; DISABLED-NEXT: .LBB9_2: # %if.end
; DISABLED-NEXT: movups (%r15), %xmm0 ; DISABLED-NEXT: movups (%r15), %xmm0
; DISABLED-NEXT: movups %xmm0, (%r14) ; DISABLED-NEXT: movups %xmm0, (%r14)
; DISABLED-NEXT: movups (%rbx), %xmm0 ; DISABLED-NEXT: movups (%rbx), %xmm0
Show All 29 Lines
; CHECK-AVX2-NEXT: .cfi_offset %rbp, -16 ; CHECK-AVX2-NEXT: .cfi_offset %rbp, -16
; CHECK-AVX2-NEXT: movq %r8, %r15 ; CHECK-AVX2-NEXT: movq %r8, %r15
; CHECK-AVX2-NEXT: movq %rcx, %r14 ; CHECK-AVX2-NEXT: movq %rcx, %r14
; CHECK-AVX2-NEXT: movl %edx, %ebp ; CHECK-AVX2-NEXT: movl %edx, %ebp
; CHECK-AVX2-NEXT: movq %rsi, %r12 ; CHECK-AVX2-NEXT: movq %rsi, %r12
; CHECK-AVX2-NEXT: movq %rdi, %rbx ; CHECK-AVX2-NEXT: movq %rdi, %rbx
; CHECK-AVX2-NEXT: movl %r9d, 12(%rdi) ; CHECK-AVX2-NEXT: movl %r9d, 12(%rdi)
; CHECK-AVX2-NEXT: callq bar@PLT ; CHECK-AVX2-NEXT: callq bar@PLT
; CHECK-AVX2-NEXT: cmpl $18, %ebp ; CHECK-AVX2-NEXT: cmpl $17, %ebp
; CHECK-AVX2-NEXT: jl .LBB9_2 ; CHECK-AVX2-NEXT: jle .LBB9_2
; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: # %bb.1: # %if.then
; CHECK-AVX2-NEXT: movl %ebp, 4(%rbx) ; CHECK-AVX2-NEXT: movl %ebp, 4(%rbx)
; CHECK-AVX2-NEXT: movq %rbx, %rdi ; CHECK-AVX2-NEXT: movq %rbx, %rdi
; CHECK-AVX2-NEXT: callq bar@PLT ; CHECK-AVX2-NEXT: callq bar@PLT
; CHECK-AVX2-NEXT: .LBB9_2: # %if.end ; CHECK-AVX2-NEXT: .LBB9_2: # %if.end
; CHECK-AVX2-NEXT: vmovups (%r15), %xmm0 ; CHECK-AVX2-NEXT: vmovups (%r15), %xmm0
; CHECK-AVX2-NEXT: vmovups %xmm0, (%r14) ; CHECK-AVX2-NEXT: vmovups %xmm0, (%r14)
; CHECK-AVX2-NEXT: vmovups (%rbx), %xmm0 ; CHECK-AVX2-NEXT: vmovups (%rbx), %xmm0
Show All 29 Lines
; CHECK-AVX512-NEXT: .cfi_offset %rbp, -16 ; CHECK-AVX512-NEXT: .cfi_offset %rbp, -16
; CHECK-AVX512-NEXT: movq %r8, %r15 ; CHECK-AVX512-NEXT: movq %r8, %r15
; CHECK-AVX512-NEXT: movq %rcx, %r14 ; CHECK-AVX512-NEXT: movq %rcx, %r14
; CHECK-AVX512-NEXT: movl %edx, %ebp ; CHECK-AVX512-NEXT: movl %edx, %ebp
; CHECK-AVX512-NEXT: movq %rsi, %r12 ; CHECK-AVX512-NEXT: movq %rsi, %r12
; CHECK-AVX512-NEXT: movq %rdi, %rbx ; CHECK-AVX512-NEXT: movq %rdi, %rbx
; CHECK-AVX512-NEXT: movl %r9d, 12(%rdi) ; CHECK-AVX512-NEXT: movl %r9d, 12(%rdi)
; CHECK-AVX512-NEXT: callq bar@PLT ; CHECK-AVX512-NEXT: callq bar@PLT
; CHECK-AVX512-NEXT: cmpl $18, %ebp ; CHECK-AVX512-NEXT: cmpl $17, %ebp
; CHECK-AVX512-NEXT: jl .LBB9_2 ; CHECK-AVX512-NEXT: jle .LBB9_2
; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: # %bb.1: # %if.then
; CHECK-AVX512-NEXT: movl %ebp, 4(%rbx) ; CHECK-AVX512-NEXT: movl %ebp, 4(%rbx)
; CHECK-AVX512-NEXT: movq %rbx, %rdi ; CHECK-AVX512-NEXT: movq %rbx, %rdi
; CHECK-AVX512-NEXT: callq bar@PLT ; CHECK-AVX512-NEXT: callq bar@PLT
; CHECK-AVX512-NEXT: .LBB9_2: # %if.end ; CHECK-AVX512-NEXT: .LBB9_2: # %if.end
; CHECK-AVX512-NEXT: vmovups (%r15), %xmm0 ; CHECK-AVX512-NEXT: vmovups (%r15), %xmm0
; CHECK-AVX512-NEXT: vmovups %xmm0, (%r14) ; CHECK-AVX512-NEXT: vmovups %xmm0, (%r14)
; CHECK-AVX512-NEXT: vmovups (%rbx), %xmm0 ; CHECK-AVX512-NEXT: vmovups (%rbx), %xmm0
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .cfi_offset %r12, -32 ; CHECK-NEXT: .cfi_offset %r12, -32
; CHECK-NEXT: .cfi_offset %r14, -24 ; CHECK-NEXT: .cfi_offset %r14, -24
; CHECK-NEXT: .cfi_offset %r15, -16 ; CHECK-NEXT: .cfi_offset %r15, -16
; CHECK-NEXT: movq %r8, %r12 ; CHECK-NEXT: movq %r8, %r12
; CHECK-NEXT: movq %rcx, %r15 ; CHECK-NEXT: movq %rcx, %r15
; CHECK-NEXT: movq %rsi, %r14 ; CHECK-NEXT: movq %rsi, %r14
; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl %r9d, 12(%rdi) ; CHECK-NEXT: movl %r9d, 12(%rdi)
; CHECK-NEXT: cmpl $18, %edx ; CHECK-NEXT: cmpl $17, %edx
; CHECK-NEXT: jl .LBB10_2 ; CHECK-NEXT: jle .LBB10_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movl %edx, 4(%rbx) ; CHECK-NEXT: movl %edx, 4(%rbx)
; CHECK-NEXT: movq %rbx, %rdi ; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: callq bar@PLT ; CHECK-NEXT: callq bar@PLT
; CHECK-NEXT: .LBB10_2: # %if.end ; CHECK-NEXT: .LBB10_2: # %if.end
; CHECK-NEXT: movups (%r12), %xmm0 ; CHECK-NEXT: movups (%r12), %xmm0
; CHECK-NEXT: movups %xmm0, (%r15) ; CHECK-NEXT: movups %xmm0, (%r15)
; CHECK-NEXT: movq (%rbx), %rax ; CHECK-NEXT: movq (%rbx), %rax
Show All 30 Lines
; DISABLED-NEXT: .cfi_offset %r12, -32 ; DISABLED-NEXT: .cfi_offset %r12, -32
; DISABLED-NEXT: .cfi_offset %r14, -24 ; DISABLED-NEXT: .cfi_offset %r14, -24
; DISABLED-NEXT: .cfi_offset %r15, -16 ; DISABLED-NEXT: .cfi_offset %r15, -16
; DISABLED-NEXT: movq %r8, %r15 ; DISABLED-NEXT: movq %r8, %r15
; DISABLED-NEXT: movq %rcx, %r14 ; DISABLED-NEXT: movq %rcx, %r14
; DISABLED-NEXT: movq %rsi, %r12 ; DISABLED-NEXT: movq %rsi, %r12
; DISABLED-NEXT: movq %rdi, %rbx ; DISABLED-NEXT: movq %rdi, %rbx
; DISABLED-NEXT: movl %r9d, 12(%rdi) ; DISABLED-NEXT: movl %r9d, 12(%rdi)
; DISABLED-NEXT: cmpl $18, %edx ; DISABLED-NEXT: cmpl $17, %edx
; DISABLED-NEXT: jl .LBB10_2 ; DISABLED-NEXT: jle .LBB10_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movl %edx, 4(%rbx) ; DISABLED-NEXT: movl %edx, 4(%rbx)
; DISABLED-NEXT: movq %rbx, %rdi ; DISABLED-NEXT: movq %rbx, %rdi
; DISABLED-NEXT: callq bar@PLT ; DISABLED-NEXT: callq bar@PLT
; DISABLED-NEXT: .LBB10_2: # %if.end ; DISABLED-NEXT: .LBB10_2: # %if.end
; DISABLED-NEXT: movups (%r15), %xmm0 ; DISABLED-NEXT: movups (%r15), %xmm0
; DISABLED-NEXT: movups %xmm0, (%r14) ; DISABLED-NEXT: movups %xmm0, (%r14)
; DISABLED-NEXT: movups (%rbx), %xmm0 ; DISABLED-NEXT: movups (%rbx), %xmm0
Show All 26 Lines
; CHECK-AVX2-NEXT: .cfi_offset %r12, -32 ; CHECK-AVX2-NEXT: .cfi_offset %r12, -32
; CHECK-AVX2-NEXT: .cfi_offset %r14, -24 ; CHECK-AVX2-NEXT: .cfi_offset %r14, -24
; CHECK-AVX2-NEXT: .cfi_offset %r15, -16 ; CHECK-AVX2-NEXT: .cfi_offset %r15, -16
; CHECK-AVX2-NEXT: movq %r8, %r12 ; CHECK-AVX2-NEXT: movq %r8, %r12
; CHECK-AVX2-NEXT: movq %rcx, %r15 ; CHECK-AVX2-NEXT: movq %rcx, %r15
; CHECK-AVX2-NEXT: movq %rsi, %r14 ; CHECK-AVX2-NEXT: movq %rsi, %r14
; CHECK-AVX2-NEXT: movq %rdi, %rbx ; CHECK-AVX2-NEXT: movq %rdi, %rbx
; CHECK-AVX2-NEXT: movl %r9d, 12(%rdi) ; CHECK-AVX2-NEXT: movl %r9d, 12(%rdi)
; CHECK-AVX2-NEXT: cmpl $18, %edx ; CHECK-AVX2-NEXT: cmpl $17, %edx
; CHECK-AVX2-NEXT: jl .LBB10_2 ; CHECK-AVX2-NEXT: jle .LBB10_2
; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: # %bb.1: # %if.then
; CHECK-AVX2-NEXT: movl %edx, 4(%rbx) ; CHECK-AVX2-NEXT: movl %edx, 4(%rbx)
; CHECK-AVX2-NEXT: movq %rbx, %rdi ; CHECK-AVX2-NEXT: movq %rbx, %rdi
; CHECK-AVX2-NEXT: callq bar@PLT ; CHECK-AVX2-NEXT: callq bar@PLT
; CHECK-AVX2-NEXT: .LBB10_2: # %if.end ; CHECK-AVX2-NEXT: .LBB10_2: # %if.end
; CHECK-AVX2-NEXT: vmovups (%r12), %xmm0 ; CHECK-AVX2-NEXT: vmovups (%r12), %xmm0
; CHECK-AVX2-NEXT: vmovups %xmm0, (%r15) ; CHECK-AVX2-NEXT: vmovups %xmm0, (%r15)
; CHECK-AVX2-NEXT: movq (%rbx), %rax ; CHECK-AVX2-NEXT: movq (%rbx), %rax
Show All 30 Lines
; CHECK-AVX512-NEXT: .cfi_offset %r12, -32 ; CHECK-AVX512-NEXT: .cfi_offset %r12, -32
; CHECK-AVX512-NEXT: .cfi_offset %r14, -24 ; CHECK-AVX512-NEXT: .cfi_offset %r14, -24
; CHECK-AVX512-NEXT: .cfi_offset %r15, -16 ; CHECK-AVX512-NEXT: .cfi_offset %r15, -16
; CHECK-AVX512-NEXT: movq %r8, %r12 ; CHECK-AVX512-NEXT: movq %r8, %r12
; CHECK-AVX512-NEXT: movq %rcx, %r15 ; CHECK-AVX512-NEXT: movq %rcx, %r15
; CHECK-AVX512-NEXT: movq %rsi, %r14 ; CHECK-AVX512-NEXT: movq %rsi, %r14
; CHECK-AVX512-NEXT: movq %rdi, %rbx ; CHECK-AVX512-NEXT: movq %rdi, %rbx
; CHECK-AVX512-NEXT: movl %r9d, 12(%rdi) ; CHECK-AVX512-NEXT: movl %r9d, 12(%rdi)
; CHECK-AVX512-NEXT: cmpl $18, %edx ; CHECK-AVX512-NEXT: cmpl $17, %edx
; CHECK-AVX512-NEXT: jl .LBB10_2 ; CHECK-AVX512-NEXT: jle .LBB10_2
; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: # %bb.1: # %if.then
; CHECK-AVX512-NEXT: movl %edx, 4(%rbx) ; CHECK-AVX512-NEXT: movl %edx, 4(%rbx)
; CHECK-AVX512-NEXT: movq %rbx, %rdi ; CHECK-AVX512-NEXT: movq %rbx, %rdi
; CHECK-AVX512-NEXT: callq bar@PLT ; CHECK-AVX512-NEXT: callq bar@PLT
; CHECK-AVX512-NEXT: .LBB10_2: # %if.end ; CHECK-AVX512-NEXT: .LBB10_2: # %if.end
; CHECK-AVX512-NEXT: vmovups (%r12), %xmm0 ; CHECK-AVX512-NEXT: vmovups (%r12), %xmm0
; CHECK-AVX512-NEXT: vmovups %xmm0, (%r15) ; CHECK-AVX512-NEXT: vmovups %xmm0, (%r15)
; CHECK-AVX512-NEXT: movq (%rbx), %rax ; CHECK-AVX512-NEXT: movq (%rbx), %rax
Show All 40 Lines
%struct.S7 = type { float, float, float , float, float, float, float, float } %struct.S7 = type { float, float, float , float, float, float, float, float }
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define void @test_conditional_block_float(%struct.S7* nocapture noalias %s1, %struct.S7* nocapture %s2, i32 %x, %struct.S7* nocapture %s3, %struct.S7* nocapture readonly %s4, float %y) local_unnamed_addr #0 { define void @test_conditional_block_float(%struct.S7* nocapture noalias %s1, %struct.S7* nocapture %s2, i32 %x, %struct.S7* nocapture %s3, %struct.S7* nocapture readonly %s4, float %y) local_unnamed_addr #0 {
; CHECK-LABEL: test_conditional_block_float: ; CHECK-LABEL: test_conditional_block_float:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpl $18, %edx ; CHECK-NEXT: cmpl $17, %edx
; CHECK-NEXT: jl .LBB11_2 ; CHECK-NEXT: jle .LBB11_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000 ; CHECK-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000
; CHECK-NEXT: .LBB11_2: # %if.end ; CHECK-NEXT: .LBB11_2: # %if.end
; CHECK-NEXT: movups (%r8), %xmm0 ; CHECK-NEXT: movups (%r8), %xmm0
; CHECK-NEXT: movups 16(%r8), %xmm1 ; CHECK-NEXT: movups 16(%r8), %xmm1
; CHECK-NEXT: movups %xmm1, 16(%rcx) ; CHECK-NEXT: movups %xmm1, 16(%rcx)
; CHECK-NEXT: movups %xmm0, (%rcx) ; CHECK-NEXT: movups %xmm0, (%rcx)
; CHECK-NEXT: movl (%rdi), %eax ; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: movl 4(%rdi), %ecx ; CHECK-NEXT: movl 4(%rdi), %ecx
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: movups 16(%rdi), %xmm0 ; CHECK-NEXT: movups 16(%rdi), %xmm0
; CHECK-NEXT: movups %xmm0, 16(%rsi) ; CHECK-NEXT: movups %xmm0, 16(%rsi)
; CHECK-NEXT: movl %eax, (%rsi) ; CHECK-NEXT: movl %eax, (%rsi)
; CHECK-NEXT: movl %ecx, 4(%rsi) ; CHECK-NEXT: movl %ecx, 4(%rsi)
; CHECK-NEXT: movq %rdx, 8(%rsi) ; CHECK-NEXT: movq %rdx, 8(%rsi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_conditional_block_float: ; DISABLED-LABEL: test_conditional_block_float:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: cmpl $18, %edx ; DISABLED-NEXT: cmpl $17, %edx
; DISABLED-NEXT: jl .LBB11_2 ; DISABLED-NEXT: jle .LBB11_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000 ; DISABLED-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000
; DISABLED-NEXT: .LBB11_2: # %if.end ; DISABLED-NEXT: .LBB11_2: # %if.end
; DISABLED-NEXT: movups (%r8), %xmm0 ; DISABLED-NEXT: movups (%r8), %xmm0
; DISABLED-NEXT: movups 16(%r8), %xmm1 ; DISABLED-NEXT: movups 16(%r8), %xmm1
; DISABLED-NEXT: movups %xmm1, 16(%rcx) ; DISABLED-NEXT: movups %xmm1, 16(%rcx)
; DISABLED-NEXT: movups %xmm0, (%rcx) ; DISABLED-NEXT: movups %xmm0, (%rcx)
; DISABLED-NEXT: movups (%rdi), %xmm0 ; DISABLED-NEXT: movups (%rdi), %xmm0
; DISABLED-NEXT: movups 16(%rdi), %xmm1 ; DISABLED-NEXT: movups 16(%rdi), %xmm1
; DISABLED-NEXT: movups %xmm1, 16(%rsi) ; DISABLED-NEXT: movups %xmm1, 16(%rsi)
; DISABLED-NEXT: movups %xmm0, (%rsi) ; DISABLED-NEXT: movups %xmm0, (%rsi)
; DISABLED-NEXT: retq ; DISABLED-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_conditional_block_float: ; CHECK-AVX2-LABEL: test_conditional_block_float:
; CHECK-AVX2: # %bb.0: # %entry ; CHECK-AVX2: # %bb.0: # %entry
; CHECK-AVX2-NEXT: cmpl $18, %edx ; CHECK-AVX2-NEXT: cmpl $17, %edx
; CHECK-AVX2-NEXT: jl .LBB11_2 ; CHECK-AVX2-NEXT: jle .LBB11_2
; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: # %bb.1: # %if.then
; CHECK-AVX2-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000 ; CHECK-AVX2-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000
; CHECK-AVX2-NEXT: .LBB11_2: # %if.end ; CHECK-AVX2-NEXT: .LBB11_2: # %if.end
; CHECK-AVX2-NEXT: vmovups (%r8), %ymm0 ; CHECK-AVX2-NEXT: vmovups (%r8), %ymm0
; CHECK-AVX2-NEXT: vmovups %ymm0, (%rcx) ; CHECK-AVX2-NEXT: vmovups %ymm0, (%rcx)
; CHECK-AVX2-NEXT: movl (%rdi), %eax ; CHECK-AVX2-NEXT: movl (%rdi), %eax
; CHECK-AVX2-NEXT: movl %eax, (%rsi) ; CHECK-AVX2-NEXT: movl %eax, (%rsi)
; CHECK-AVX2-NEXT: movl 4(%rdi), %eax ; CHECK-AVX2-NEXT: movl 4(%rdi), %eax
; CHECK-AVX2-NEXT: movl %eax, 4(%rsi) ; CHECK-AVX2-NEXT: movl %eax, 4(%rsi)
; CHECK-AVX2-NEXT: vmovups 8(%rdi), %xmm0 ; CHECK-AVX2-NEXT: vmovups 8(%rdi), %xmm0
; CHECK-AVX2-NEXT: vmovups %xmm0, 8(%rsi) ; CHECK-AVX2-NEXT: vmovups %xmm0, 8(%rsi)
; CHECK-AVX2-NEXT: movq 24(%rdi), %rax ; CHECK-AVX2-NEXT: movq 24(%rdi), %rax
; CHECK-AVX2-NEXT: movq %rax, 24(%rsi) ; CHECK-AVX2-NEXT: movq %rax, 24(%rsi)
; CHECK-AVX2-NEXT: vzeroupper ; CHECK-AVX2-NEXT: vzeroupper
; CHECK-AVX2-NEXT: retq ; CHECK-AVX2-NEXT: retq
; ;
; CHECK-AVX512-LABEL: test_conditional_block_float: ; CHECK-AVX512-LABEL: test_conditional_block_float:
; CHECK-AVX512: # %bb.0: # %entry ; CHECK-AVX512: # %bb.0: # %entry
; CHECK-AVX512-NEXT: cmpl $18, %edx ; CHECK-AVX512-NEXT: cmpl $17, %edx
; CHECK-AVX512-NEXT: jl .LBB11_2 ; CHECK-AVX512-NEXT: jle .LBB11_2
; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: # %bb.1: # %if.then
; CHECK-AVX512-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000 ; CHECK-AVX512-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000
; CHECK-AVX512-NEXT: .LBB11_2: # %if.end ; CHECK-AVX512-NEXT: .LBB11_2: # %if.end
; CHECK-AVX512-NEXT: vmovups (%r8), %ymm0 ; CHECK-AVX512-NEXT: vmovups (%r8), %ymm0
; CHECK-AVX512-NEXT: vmovups %ymm0, (%rcx) ; CHECK-AVX512-NEXT: vmovups %ymm0, (%rcx)
; CHECK-AVX512-NEXT: movl (%rdi), %eax ; CHECK-AVX512-NEXT: movl (%rdi), %eax
; CHECK-AVX512-NEXT: movl %eax, (%rsi) ; CHECK-AVX512-NEXT: movl %eax, (%rsi)
; CHECK-AVX512-NEXT: movl 4(%rdi), %eax ; CHECK-AVX512-NEXT: movl 4(%rdi), %eax
Show All 24 Lines
} }
%struct.S8 = type { i64, i64, i64, i64, i64, i64 } %struct.S8 = type { i64, i64, i64, i64, i64, i64 }
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define void @test_conditional_block_ymm(%struct.S8* nocapture noalias %s1, %struct.S8* nocapture %s2, i32 %x, %struct.S8* nocapture %s3, %struct.S8* nocapture readonly %s4) local_unnamed_addr #0 { define void @test_conditional_block_ymm(%struct.S8* nocapture noalias %s1, %struct.S8* nocapture %s2, i32 %x, %struct.S8* nocapture %s3, %struct.S8* nocapture readonly %s4) local_unnamed_addr #0 {
; CHECK-LABEL: test_conditional_block_ymm: ; CHECK-LABEL: test_conditional_block_ymm:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpl $18, %edx ; CHECK-NEXT: cmpl $17, %edx
; CHECK-NEXT: jl .LBB12_2 ; CHECK-NEXT: jle .LBB12_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movq $1, 8(%rdi) ; CHECK-NEXT: movq $1, 8(%rdi)
; CHECK-NEXT: .LBB12_2: # %if.end ; CHECK-NEXT: .LBB12_2: # %if.end
; CHECK-NEXT: movups (%r8), %xmm0 ; CHECK-NEXT: movups (%r8), %xmm0
; CHECK-NEXT: movups 16(%r8), %xmm1 ; CHECK-NEXT: movups 16(%r8), %xmm1
; CHECK-NEXT: movups %xmm1, 16(%rcx) ; CHECK-NEXT: movups %xmm1, 16(%rcx)
; CHECK-NEXT: movups %xmm0, (%rcx) ; CHECK-NEXT: movups %xmm0, (%rcx)
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rcx ; CHECK-NEXT: movq 8(%rdi), %rcx
; CHECK-NEXT: movups 16(%rdi), %xmm0 ; CHECK-NEXT: movups 16(%rdi), %xmm0
; CHECK-NEXT: movups %xmm0, 16(%rsi) ; CHECK-NEXT: movups %xmm0, 16(%rsi)
; CHECK-NEXT: movq %rax, (%rsi) ; CHECK-NEXT: movq %rax, (%rsi)
; CHECK-NEXT: movq %rcx, 8(%rsi) ; CHECK-NEXT: movq %rcx, 8(%rsi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_conditional_block_ymm: ; DISABLED-LABEL: test_conditional_block_ymm:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: cmpl $18, %edx ; DISABLED-NEXT: cmpl $17, %edx
; DISABLED-NEXT: jl .LBB12_2 ; DISABLED-NEXT: jle .LBB12_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movq $1, 8(%rdi) ; DISABLED-NEXT: movq $1, 8(%rdi)
; DISABLED-NEXT: .LBB12_2: # %if.end ; DISABLED-NEXT: .LBB12_2: # %if.end
; DISABLED-NEXT: movups (%r8), %xmm0 ; DISABLED-NEXT: movups (%r8), %xmm0
; DISABLED-NEXT: movups 16(%r8), %xmm1 ; DISABLED-NEXT: movups 16(%r8), %xmm1
; DISABLED-NEXT: movups %xmm1, 16(%rcx) ; DISABLED-NEXT: movups %xmm1, 16(%rcx)
; DISABLED-NEXT: movups %xmm0, (%rcx) ; DISABLED-NEXT: movups %xmm0, (%rcx)
; DISABLED-NEXT: movups (%rdi), %xmm0 ; DISABLED-NEXT: movups (%rdi), %xmm0
; DISABLED-NEXT: movups 16(%rdi), %xmm1 ; DISABLED-NEXT: movups 16(%rdi), %xmm1
; DISABLED-NEXT: movups %xmm1, 16(%rsi) ; DISABLED-NEXT: movups %xmm1, 16(%rsi)
; DISABLED-NEXT: movups %xmm0, (%rsi) ; DISABLED-NEXT: movups %xmm0, (%rsi)
; DISABLED-NEXT: retq ; DISABLED-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_conditional_block_ymm: ; CHECK-AVX2-LABEL: test_conditional_block_ymm:
; CHECK-AVX2: # %bb.0: # %entry ; CHECK-AVX2: # %bb.0: # %entry
; CHECK-AVX2-NEXT: cmpl $18, %edx ; CHECK-AVX2-NEXT: cmpl $17, %edx
; CHECK-AVX2-NEXT: jl .LBB12_2 ; CHECK-AVX2-NEXT: jle .LBB12_2
; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: # %bb.1: # %if.then
; CHECK-AVX2-NEXT: movq $1, 8(%rdi) ; CHECK-AVX2-NEXT: movq $1, 8(%rdi)
; CHECK-AVX2-NEXT: .LBB12_2: # %if.end ; CHECK-AVX2-NEXT: .LBB12_2: # %if.end
; CHECK-AVX2-NEXT: vmovups (%r8), %ymm0 ; CHECK-AVX2-NEXT: vmovups (%r8), %ymm0
; CHECK-AVX2-NEXT: vmovups %ymm0, (%rcx) ; CHECK-AVX2-NEXT: vmovups %ymm0, (%rcx)
; CHECK-AVX2-NEXT: movq (%rdi), %rax ; CHECK-AVX2-NEXT: movq (%rdi), %rax
; CHECK-AVX2-NEXT: movq %rax, (%rsi) ; CHECK-AVX2-NEXT: movq %rax, (%rsi)
; CHECK-AVX2-NEXT: movq 8(%rdi), %rax ; CHECK-AVX2-NEXT: movq 8(%rdi), %rax
; CHECK-AVX2-NEXT: movq %rax, 8(%rsi) ; CHECK-AVX2-NEXT: movq %rax, 8(%rsi)
; CHECK-AVX2-NEXT: vmovups 16(%rdi), %xmm0 ; CHECK-AVX2-NEXT: vmovups 16(%rdi), %xmm0
; CHECK-AVX2-NEXT: vmovups %xmm0, 16(%rsi) ; CHECK-AVX2-NEXT: vmovups %xmm0, 16(%rsi)
; CHECK-AVX2-NEXT: vzeroupper ; CHECK-AVX2-NEXT: vzeroupper
; CHECK-AVX2-NEXT: retq ; CHECK-AVX2-NEXT: retq
; ;
; CHECK-AVX512-LABEL: test_conditional_block_ymm: ; CHECK-AVX512-LABEL: test_conditional_block_ymm:
; CHECK-AVX512: # %bb.0: # %entry ; CHECK-AVX512: # %bb.0: # %entry
; CHECK-AVX512-NEXT: cmpl $18, %edx ; CHECK-AVX512-NEXT: cmpl $17, %edx
; CHECK-AVX512-NEXT: jl .LBB12_2 ; CHECK-AVX512-NEXT: jle .LBB12_2
; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: # %bb.1: # %if.then
; CHECK-AVX512-NEXT: movq $1, 8(%rdi) ; CHECK-AVX512-NEXT: movq $1, 8(%rdi)
; CHECK-AVX512-NEXT: .LBB12_2: # %if.end ; CHECK-AVX512-NEXT: .LBB12_2: # %if.end
; CHECK-AVX512-NEXT: vmovups (%r8), %ymm0 ; CHECK-AVX512-NEXT: vmovups (%r8), %ymm0
; CHECK-AVX512-NEXT: vmovups %ymm0, (%rcx) ; CHECK-AVX512-NEXT: vmovups %ymm0, (%rcx)
; CHECK-AVX512-NEXT: movq (%rdi), %rax ; CHECK-AVX512-NEXT: movq (%rdi), %rax
; CHECK-AVX512-NEXT: movq %rax, (%rsi) ; CHECK-AVX512-NEXT: movq %rax, (%rsi)
; CHECK-AVX512-NEXT: movq 8(%rdi), %rax ; CHECK-AVX512-NEXT: movq 8(%rdi), %rax
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llvm/test/CodeGen/X86/avx-cmp.ll

Show All 20 Lines; CHECK-NEXT: retq
ret <4 x i64> %s ret <4 x i64> %s
} }
declare void @scale() nounwind declare void @scale() nounwind
define void @render(double %a0) nounwind { define void @render(double %a0) nounwind {
; CHECK-LABEL: render: ; CHECK-LABEL: render:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: vmovsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB2_6 ; CHECK-NEXT: je .LBB2_6
; CHECK-NEXT: # %bb.1: # %for.cond5.preheader ; CHECK-NEXT: # %bb.1: # %for.cond5.preheader
; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: movb $1, %bpl
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB2_2: # %for.cond5 ; CHECK-NEXT: .LBB2_2: # %for.cond5
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: testb %bl, %bl ; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: jne .LBB2_2 ; CHECK-NEXT: je .LBB2_2
; CHECK-NEXT: # %bb.3: # %for.cond5 ; CHECK-NEXT: # %bb.3: # %for.cond5
; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1
; CHECK-NEXT: testb %bpl, %bpl ; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: jne .LBB2_2 ; CHECK-NEXT: je .LBB2_2
; CHECK-NEXT: # %bb.4: # %for.body33.preheader ; CHECK-NEXT: # %bb.4: # %for.body33.preheader
; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1
; CHECK-NEXT: vmovsd (%rsp), %xmm0 # 8-byte Reload ; CHECK-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: jne .LBB2_5 ; CHECK-NEXT: jne .LBB2_5
; CHECK-NEXT: jnp .LBB2_2 ; CHECK-NEXT: jnp .LBB2_2
; CHECK-NEXT: .LBB2_5: # %if.then ; CHECK-NEXT: .LBB2_5: # %if.then
; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1
; CHECK-NEXT: callq scale@PLT ; CHECK-NEXT: callq scale@PLT
; CHECK-NEXT: jmp .LBB2_2 ; CHECK-NEXT: jmp .LBB2_2
; CHECK-NEXT: .LBB2_6: # %for.end52 ; CHECK-NEXT: .LBB2_6: # %for.end52
; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
br i1 undef, label %for.cond5, label %for.end52 br i1 undef, label %for.cond5, label %for.end52
for.cond5: for.cond5:
%or.cond = and i1 undef, false %or.cond = and i1 undef, false
br i1 %or.cond, label %for.body33, label %for.cond5 br i1 %or.cond, label %for.body33, label %for.cond5
▲ Show 20 Lines • Show All 156 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/avx-load-store.ll

Show First 20 Lines • Show All 209 Lines • ▼ Show 20 Lines
declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x i32>, <8 x float>) nounwind declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x i32>, <8 x float>) nounwind
define void @f_f() nounwind { define void @f_f() nounwind {
; CHECK-LABEL: f_f: ; CHECK-LABEL: f_f:
; CHECK: # %bb.0: # %allocas ; CHECK: # %bb.0: # %allocas
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB9_2 ; CHECK-NEXT: je .LBB9_2
; CHECK-NEXT: # %bb.1: # %cif_mask_all ; CHECK-NEXT: # %bb.1: # %cif_mask_all
; CHECK-NEXT: .LBB9_2: # %cif_mask_mixed ; CHECK-NEXT: .LBB9_2: # %cif_mask_mixed
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB9_4 ; CHECK-NEXT: je .LBB9_4
; CHECK-NEXT: # %bb.3: # %cif_mixed_test_all ; CHECK-NEXT: # %bb.3: # %cif_mixed_test_all
; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,0,0,0] ; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,0,0,0]
; CHECK-NEXT: vmaskmovps %ymm0, %ymm0, (%rax) ; CHECK-NEXT: vmaskmovps %ymm0, %ymm0, (%rax)
; CHECK-NEXT: .LBB9_4: # %cif_mixed_test_any_check ; CHECK-NEXT: .LBB9_4: # %cif_mixed_test_any_check
; ;
; CHECK_O0-LABEL: f_f: ; CHECK_O0-LABEL: f_f:
; CHECK_O0: # %bb.0: # %allocas ; CHECK_O0: # %bb.0: # %allocas
; CHECK_O0-NEXT: # implicit-def: $al ; CHECK_O0-NEXT: # implicit-def: $al
▲ Show 20 Lines • Show All 127 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll

Show First 20 Lines • Show All 3,780 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB108_1: # %bb1 ; CHECK-NEXT: .LBB108_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu (%rdi,%rax,4), %xmm1 ; CHECK-NEXT: vmovdqu (%rdi,%rax,4), %xmm1
; CHECK-NEXT: vpcmpltd %xmm0, %xmm1, %k1 ; CHECK-NEXT: vpcmpltd %xmm0, %xmm1, %k1
; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1} ; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,4) ; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,4)
; CHECK-NEXT: addq $4, %rax ; CHECK-NEXT: addq $4, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF ; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400
; CHECK-NEXT: jg .LBB108_1 ; CHECK-NEXT: jge .LBB108_1
; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: # %bb.2: # %bb10
; CHECK-NEXT: retq ; CHECK-NEXT: retq
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
%tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp
Show All 19 Lines
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB109_1: # %bb1 ; CHECK-NEXT: .LBB109_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu (%rdi,%rax,4), %ymm1 ; CHECK-NEXT: vmovdqu (%rdi,%rax,4), %ymm1
; CHECK-NEXT: vpcmpltd %ymm0, %ymm1, %k1 ; CHECK-NEXT: vpcmpltd %ymm0, %ymm1, %k1
; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1} ; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1}
; CHECK-NEXT: vmovdqu %ymm1, (%rdi,%rax,4) ; CHECK-NEXT: vmovdqu %ymm1, (%rdi,%rax,4)
; CHECK-NEXT: addq $8, %rax ; CHECK-NEXT: addq $8, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF ; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400
; CHECK-NEXT: jg .LBB109_1 ; CHECK-NEXT: jge .LBB109_1
; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: # %bb.2: # %bb10
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
Show All 20 Lines
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB110_1: # %bb1 ; CHECK-NEXT: .LBB110_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu64 (%rdi,%rax,4), %zmm1 ; CHECK-NEXT: vmovdqu64 (%rdi,%rax,4), %zmm1
; CHECK-NEXT: vpcmpltd %zmm0, %zmm1, %k1 ; CHECK-NEXT: vpcmpltd %zmm0, %zmm1, %k1
; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1} ; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1}
; CHECK-NEXT: vmovdqu64 %zmm1, (%rdi,%rax,4) ; CHECK-NEXT: vmovdqu64 %zmm1, (%rdi,%rax,4)
; CHECK-NEXT: addq $16, %rax ; CHECK-NEXT: addq $16, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF ; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400
; CHECK-NEXT: jg .LBB110_1 ; CHECK-NEXT: jge .LBB110_1
; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: # %bb.2: # %bb10
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
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; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB111_1: # %bb1 ; CHECK-NEXT: .LBB111_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu (%rdi,%rax,8), %xmm1 ; CHECK-NEXT: vmovdqu (%rdi,%rax,8), %xmm1
; CHECK-NEXT: vpcmpltq %xmm0, %xmm1, %k1 ; CHECK-NEXT: vpcmpltq %xmm0, %xmm1, %k1
; CHECK-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1} ; CHECK-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,8) ; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,8)
; CHECK-NEXT: addq $2, %rax ; CHECK-NEXT: addq $2, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF ; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400
; CHECK-NEXT: jg .LBB111_1 ; CHECK-NEXT: jge .LBB111_1
; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: # %bb.2: # %bb10
; CHECK-NEXT: retq ; CHECK-NEXT: retq
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
%tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp
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; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB112_1: # %bb1 ; CHECK-NEXT: .LBB112_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu (%rdi,%rax,8), %ymm1 ; CHECK-NEXT: vmovdqu (%rdi,%rax,8), %ymm1
; CHECK-NEXT: vpcmpltq %ymm0, %ymm1, %k1 ; CHECK-NEXT: vpcmpltq %ymm0, %ymm1, %k1
; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1} ; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1}
; CHECK-NEXT: vmovdqu %ymm1, (%rdi,%rax,8) ; CHECK-NEXT: vmovdqu %ymm1, (%rdi,%rax,8)
; CHECK-NEXT: addq $4, %rax ; CHECK-NEXT: addq $4, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF ; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400
; CHECK-NEXT: jg .LBB112_1 ; CHECK-NEXT: jge .LBB112_1
; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: # %bb.2: # %bb10
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
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; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB113_1: # %bb1 ; CHECK-NEXT: .LBB113_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu64 (%rdi,%rax,8), %zmm1 ; CHECK-NEXT: vmovdqu64 (%rdi,%rax,8), %zmm1
; CHECK-NEXT: vpcmpltq %zmm0, %zmm1, %k1 ; CHECK-NEXT: vpcmpltq %zmm0, %zmm1, %k1
; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1} ; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1}
; CHECK-NEXT: vmovdqu64 %zmm1, (%rdi,%rax,8) ; CHECK-NEXT: vmovdqu64 %zmm1, (%rdi,%rax,8)
; CHECK-NEXT: addq $8, %rax ; CHECK-NEXT: addq $8, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF ; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400
; CHECK-NEXT: jg .LBB113_1 ; CHECK-NEXT: jge .LBB113_1
; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: # %bb.2: # %bb10
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
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; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB114_1: # %bb1 ; CHECK-NEXT: .LBB114_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu (%rdi,%rax,4), %xmm1 ; CHECK-NEXT: vmovdqu (%rdi,%rax,4), %xmm1
; CHECK-NEXT: vpcmpltud %xmm0, %xmm1, %k1 ; CHECK-NEXT: vpcmpltud %xmm0, %xmm1, %k1
; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1} ; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,4) ; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,4)
; CHECK-NEXT: addq $4, %rax ; CHECK-NEXT: addq $4, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF ; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400
; CHECK-NEXT: ja .LBB114_1 ; CHECK-NEXT: jae .LBB114_1
; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: # %bb.2: # %bb10
; CHECK-NEXT: retq ; CHECK-NEXT: retq
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
%tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp
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; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB115_1: # %bb1 ; CHECK-NEXT: .LBB115_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu (%rdi,%rax,4), %ymm1 ; CHECK-NEXT: vmovdqu (%rdi,%rax,4), %ymm1
; CHECK-NEXT: vpcmpltud %ymm0, %ymm1, %k1 ; CHECK-NEXT: vpcmpltud %ymm0, %ymm1, %k1
; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1} ; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1}
; CHECK-NEXT: vmovdqu %ymm1, (%rdi,%rax,4) ; CHECK-NEXT: vmovdqu %ymm1, (%rdi,%rax,4)
; CHECK-NEXT: addq $8, %rax ; CHECK-NEXT: addq $8, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF ; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400
; CHECK-NEXT: ja .LBB115_1 ; CHECK-NEXT: jae .LBB115_1
; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: # %bb.2: # %bb10
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
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; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB116_1: # %bb1 ; CHECK-NEXT: .LBB116_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu64 (%rdi,%rax,4), %zmm1 ; CHECK-NEXT: vmovdqu64 (%rdi,%rax,4), %zmm1
; CHECK-NEXT: vpcmpltud %zmm0, %zmm1, %k1 ; CHECK-NEXT: vpcmpltud %zmm0, %zmm1, %k1
; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1} ; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1}
; CHECK-NEXT: vmovdqu64 %zmm1, (%rdi,%rax,4) ; CHECK-NEXT: vmovdqu64 %zmm1, (%rdi,%rax,4)
; CHECK-NEXT: addq $16, %rax ; CHECK-NEXT: addq $16, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF ; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400
; CHECK-NEXT: ja .LBB116_1 ; CHECK-NEXT: jae .LBB116_1
; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: # %bb.2: # %bb10
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
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; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB117_1: # %bb1 ; CHECK-NEXT: .LBB117_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu (%rdi,%rax,8), %xmm1 ; CHECK-NEXT: vmovdqu (%rdi,%rax,8), %xmm1
; CHECK-NEXT: vpcmpltuq %xmm0, %xmm1, %k1 ; CHECK-NEXT: vpcmpltuq %xmm0, %xmm1, %k1
; CHECK-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1} ; CHECK-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,8) ; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,8)
; CHECK-NEXT: addq $2, %rax ; CHECK-NEXT: addq $2, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF ; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400
; CHECK-NEXT: ja .LBB117_1 ; CHECK-NEXT: jae .LBB117_1
; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: # %bb.2: # %bb10
; CHECK-NEXT: retq ; CHECK-NEXT: retq
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
%tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp
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; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB118_1: # %bb1 ; CHECK-NEXT: .LBB118_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu (%rdi,%rax,8), %ymm1 ; CHECK-NEXT: vmovdqu (%rdi,%rax,8), %ymm1
; CHECK-NEXT: vpcmpltuq %ymm0, %ymm1, %k1 ; CHECK-NEXT: vpcmpltuq %ymm0, %ymm1, %k1
; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1} ; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1}
; CHECK-NEXT: vmovdqu %ymm1, (%rdi,%rax,8) ; CHECK-NEXT: vmovdqu %ymm1, (%rdi,%rax,8)
; CHECK-NEXT: addq $4, %rax ; CHECK-NEXT: addq $4, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF ; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400
; CHECK-NEXT: ja .LBB118_1 ; CHECK-NEXT: jae .LBB118_1
; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: # %bb.2: # %bb10
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
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; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB119_1: # %bb1 ; CHECK-NEXT: .LBB119_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu64 (%rdi,%rax,8), %zmm1 ; CHECK-NEXT: vmovdqu64 (%rdi,%rax,8), %zmm1
; CHECK-NEXT: vpcmpltuq %zmm0, %zmm1, %k1 ; CHECK-NEXT: vpcmpltuq %zmm0, %zmm1, %k1
; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1} ; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1}
; CHECK-NEXT: vmovdqu64 %zmm1, (%rdi,%rax,8) ; CHECK-NEXT: vmovdqu64 %zmm1, (%rdi,%rax,8)
; CHECK-NEXT: addq $8, %rax ; CHECK-NEXT: addq $8, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF ; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400
; CHECK-NEXT: ja .LBB119_1 ; CHECK-NEXT: jae .LBB119_1
; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: # %bb.2: # %bb10
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
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llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll

Show All 22 Lines
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_5 ; CHECK-NEXT: jne .LBB0_5
; CHECK-NEXT: # %bb.1: # %bb5 ; CHECK-NEXT: # %bb.1: # %bb5
; CHECK-NEXT: movq %rsi, %r12 ; CHECK-NEXT: movq %rsi, %r12
; CHECK-NEXT: movslq %edi, %rbp ; CHECK-NEXT: movslq %edi, %rbp
; CHECK-NEXT: leaq (,%rbp,8), %rax ; CHECK-NEXT: leaq (,%rbp,8), %rax
; CHECK-NEXT: leaq global(%rax,%rax,2), %r14 ; CHECK-NEXT: leaq global(%rax,%rax,2), %r14
; CHECK-NEXT: leaq global+4(%rax,%rax,2), %r15 ; CHECK-NEXT: leaq global+4(%rax,%rax,2), %r15
; CHECK-NEXT: xorl %r13d, %r13d ; CHECK-NEXT: movb $1, %r13b
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_2: # %bb8 ; CHECK-NEXT: .LBB0_2: # %bb8
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: callq bar@PLT ; CHECK-NEXT: callq bar@PLT
; CHECK-NEXT: movq %rax, %rbx ; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: movq %rax, %rdi ; CHECK-NEXT: movq %rax, %rdi
; CHECK-NEXT: callq *%r12 ; CHECK-NEXT: callq *%r12
; CHECK-NEXT: movq %r14, %rdi ; CHECK-NEXT: movq %r14, %rdi
; CHECK-NEXT: callq hoge@PLT ; CHECK-NEXT: callq hoge@PLT
; CHECK-NEXT: movq %r15, %rdi ; CHECK-NEXT: movq %r15, %rdi
; CHECK-NEXT: callq hoge@PLT ; CHECK-NEXT: callq hoge@PLT
; CHECK-NEXT: testb %r13b, %r13b ; CHECK-NEXT: testb %r13b, %r13b
; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.3: # %bb15 ; CHECK-NEXT: # %bb.3: # %bb15
; CHECK-NEXT: leaq (%rbp,%rbp,2), %rax ; CHECK-NEXT: leaq (%rbp,%rbp,2), %rax
; CHECK-NEXT: movq %rbx, global+16(,%rax,8) ; CHECK-NEXT: movq %rbx, global+16(,%rax,8)
; CHECK-NEXT: movabsq $-2305847407260205056, %rbx # imm = 0xDFFFFC0000000000 ; CHECK-NEXT: movabsq $-2305847407260205056, %rbx # imm = 0xDFFFFC0000000000
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.4: # %bb17 ; CHECK-NEXT: # %bb.4: # %bb17
; CHECK-NEXT: callq widget@PLT ; CHECK-NEXT: callq widget@PLT
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llvm/test/CodeGen/X86/cmp-bool.ll

Show All 19 Lines
if.end: if.end:
ret void ret void
} }
define void @bool_ne(i1 zeroext %a, i1 zeroext %b, void ()* nocapture %c) nounwind { define void @bool_ne(i1 zeroext %a, i1 zeroext %b, void ()* nocapture %c) nounwind {
; CHECK-LABEL: bool_ne: ; CHECK-LABEL: bool_ne:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb %sil, %dil ; CHECK-NEXT: xorl %esi, %edi
; CHECK-NEXT: je .LBB1_1 ; CHECK-NEXT: je .LBB1_1
; CHECK-NEXT: # %bb.2: # %if.then ; CHECK-NEXT: # %bb.2: # %if.then
; CHECK-NEXT: jmpq *%rdx # TAILCALL ; CHECK-NEXT: jmpq *%rdx # TAILCALL
; CHECK-NEXT: .LBB1_1: # %if.end ; CHECK-NEXT: .LBB1_1: # %if.end
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%cmp = xor i1 %a, %b %cmp = xor i1 %a, %b
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: if.then:
tail call void %c() #1 tail call void %c() #1
br label %if.end br label %if.end
if.end: if.end:
ret void ret void
} }

llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll

Show All 29 Lines
; 32-GOOD-RA-NEXT: pushl %esi ; 32-GOOD-RA-NEXT: pushl %esi
; 32-GOOD-RA-NEXT: pushl %eax ; 32-GOOD-RA-NEXT: pushl %eax
; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %eax ; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %eax
; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %edx ; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %edx
; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %ebx ; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %ebx
; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %ecx ; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %ecx
; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %esi ; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %esi
; 32-GOOD-RA-NEXT: lock cmpxchg8b (%esi) ; 32-GOOD-RA-NEXT: lock cmpxchg8b (%esi)
; 32-GOOD-RA-NEXT: setne %bl ; 32-GOOD-RA-NEXT: sete %bl
; 32-GOOD-RA-NEXT: subl $8, %esp ; 32-GOOD-RA-NEXT: subl $8, %esp
; 32-GOOD-RA-NEXT: pushl %edx ; 32-GOOD-RA-NEXT: pushl %edx
; 32-GOOD-RA-NEXT: pushl %eax ; 32-GOOD-RA-NEXT: pushl %eax
; 32-GOOD-RA-NEXT: calll bar@PLT ; 32-GOOD-RA-NEXT: calll bar@PLT
; 32-GOOD-RA-NEXT: addl $16, %esp ; 32-GOOD-RA-NEXT: addl $16, %esp
; 32-GOOD-RA-NEXT: testb %bl, %bl ; 32-GOOD-RA-NEXT: testb %bl, %bl
; 32-GOOD-RA-NEXT: jne .LBB0_3 ; 32-GOOD-RA-NEXT: je .LBB0_3
; 32-GOOD-RA-NEXT: # %bb.1: # %t ; 32-GOOD-RA-NEXT: # %bb.1: # %t
; 32-GOOD-RA-NEXT: movl $42, %eax ; 32-GOOD-RA-NEXT: movl $42, %eax
; 32-GOOD-RA-NEXT: jmp .LBB0_2 ; 32-GOOD-RA-NEXT: jmp .LBB0_2
; 32-GOOD-RA-NEXT: .LBB0_3: # %f ; 32-GOOD-RA-NEXT: .LBB0_3: # %f
; 32-GOOD-RA-NEXT: xorl %eax, %eax ; 32-GOOD-RA-NEXT: xorl %eax, %eax
; 32-GOOD-RA-NEXT: .LBB0_2: # %t ; 32-GOOD-RA-NEXT: .LBB0_2: # %t
; 32-GOOD-RA-NEXT: xorl %edx, %edx ; 32-GOOD-RA-NEXT: xorl %edx, %edx
; 32-GOOD-RA-NEXT: addl $4, %esp ; 32-GOOD-RA-NEXT: addl $4, %esp
; 32-GOOD-RA-NEXT: popl %esi ; 32-GOOD-RA-NEXT: popl %esi
; 32-GOOD-RA-NEXT: popl %ebx ; 32-GOOD-RA-NEXT: popl %ebx
; 32-GOOD-RA-NEXT: retl ; 32-GOOD-RA-NEXT: retl
; ;
; 32-FAST-RA-LABEL: test_intervening_call: ; 32-FAST-RA-LABEL: test_intervening_call:
; 32-FAST-RA: # %bb.0: # %entry ; 32-FAST-RA: # %bb.0: # %entry
; 32-FAST-RA-NEXT: pushl %ebx ; 32-FAST-RA-NEXT: pushl %ebx
; 32-FAST-RA-NEXT: pushl %esi ; 32-FAST-RA-NEXT: pushl %esi
; 32-FAST-RA-NEXT: pushl %eax ; 32-FAST-RA-NEXT: pushl %eax
; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %esi ; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %esi
; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %ebx ; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %ebx
; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %ecx ; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %ecx
; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %eax ; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %eax
; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %edx ; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %edx
; 32-FAST-RA-NEXT: lock cmpxchg8b (%esi) ; 32-FAST-RA-NEXT: lock cmpxchg8b (%esi)
; 32-FAST-RA-NEXT: setne %bl ; 32-FAST-RA-NEXT: sete %bl
; 32-FAST-RA-NEXT: subl $8, %esp ; 32-FAST-RA-NEXT: subl $8, %esp
; 32-FAST-RA-NEXT: pushl %edx ; 32-FAST-RA-NEXT: pushl %edx
; 32-FAST-RA-NEXT: pushl %eax ; 32-FAST-RA-NEXT: pushl %eax
; 32-FAST-RA-NEXT: calll bar@PLT ; 32-FAST-RA-NEXT: calll bar@PLT
; 32-FAST-RA-NEXT: addl $16, %esp ; 32-FAST-RA-NEXT: addl $16, %esp
; 32-FAST-RA-NEXT: testb %bl, %bl ; 32-FAST-RA-NEXT: testb %bl, %bl
; 32-FAST-RA-NEXT: jne .LBB0_3 ; 32-FAST-RA-NEXT: je .LBB0_3
; 32-FAST-RA-NEXT: # %bb.1: # %t ; 32-FAST-RA-NEXT: # %bb.1: # %t
; 32-FAST-RA-NEXT: movl $42, %eax ; 32-FAST-RA-NEXT: movl $42, %eax
; 32-FAST-RA-NEXT: jmp .LBB0_2 ; 32-FAST-RA-NEXT: jmp .LBB0_2
; 32-FAST-RA-NEXT: .LBB0_3: # %f ; 32-FAST-RA-NEXT: .LBB0_3: # %f
; 32-FAST-RA-NEXT: xorl %eax, %eax ; 32-FAST-RA-NEXT: xorl %eax, %eax
; 32-FAST-RA-NEXT: .LBB0_2: # %t ; 32-FAST-RA-NEXT: .LBB0_2: # %t
; 32-FAST-RA-NEXT: xorl %edx, %edx ; 32-FAST-RA-NEXT: xorl %edx, %edx
; 32-FAST-RA-NEXT: addl $4, %esp ; 32-FAST-RA-NEXT: addl $4, %esp
; 32-FAST-RA-NEXT: popl %esi ; 32-FAST-RA-NEXT: popl %esi
; 32-FAST-RA-NEXT: popl %ebx ; 32-FAST-RA-NEXT: popl %ebx
; 32-FAST-RA-NEXT: retl ; 32-FAST-RA-NEXT: retl
; ;
; 64-ALL-LABEL: test_intervening_call: ; 64-ALL-LABEL: test_intervening_call:
; 64-ALL: # %bb.0: # %entry ; 64-ALL: # %bb.0: # %entry
; 64-ALL-NEXT: pushq %rbx ; 64-ALL-NEXT: pushq %rbx
; 64-ALL-NEXT: movq %rsi, %rax ; 64-ALL-NEXT: movq %rsi, %rax
; 64-ALL-NEXT: lock cmpxchgq %rdx, (%rdi) ; 64-ALL-NEXT: lock cmpxchgq %rdx, (%rdi)
; 64-ALL-NEXT: setne %bl ; 64-ALL-NEXT: sete %bl
; 64-ALL-NEXT: movq %rax, %rdi ; 64-ALL-NEXT: movq %rax, %rdi
; 64-ALL-NEXT: callq bar@PLT ; 64-ALL-NEXT: callq bar@PLT
; 64-ALL-NEXT: testb %bl, %bl ; 64-ALL-NEXT: testb %bl, %bl
; 64-ALL-NEXT: jne .LBB0_2 ; 64-ALL-NEXT: je .LBB0_2
; 64-ALL-NEXT: # %bb.1: # %t ; 64-ALL-NEXT: # %bb.1: # %t
; 64-ALL-NEXT: movl $42, %eax ; 64-ALL-NEXT: movl $42, %eax
; 64-ALL-NEXT: popq %rbx ; 64-ALL-NEXT: popq %rbx
; 64-ALL-NEXT: retq ; 64-ALL-NEXT: retq
; 64-ALL-NEXT: .LBB0_2: # %f ; 64-ALL-NEXT: .LBB0_2: # %f
; 64-ALL-NEXT: xorl %eax, %eax ; 64-ALL-NEXT: xorl %eax, %eax
; 64-ALL-NEXT: popq %rbx ; 64-ALL-NEXT: popq %rbx
; 64-ALL-NEXT: retq ; 64-ALL-NEXT: retq
▲ Show 20 Lines • Show All 173 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/copy-eflags.ll

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; Preserve increment flags across a call. ; Preserve increment flags across a call.
define dso_local i32 @test2(i32* %ptr) nounwind { define dso_local i32 @test2(i32* %ptr) nounwind {
; X32-LABEL: test2: ; X32-LABEL: test2:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebx
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: incl (%eax) ; X32-NEXT: incl (%eax)
; X32-NEXT: setne %bl ; X32-NEXT: sete %bl
; X32-NEXT: pushl $42 ; X32-NEXT: pushl $42
; X32-NEXT: calll external ; X32-NEXT: calll external
; X32-NEXT: addl $4, %esp ; X32-NEXT: addl $4, %esp
; X32-NEXT: testb %bl, %bl ; X32-NEXT: testb %bl, %bl
; X32-NEXT: jne .LBB1_2 ; X32-NEXT: je .LBB1_2
; X32-NEXT: # %bb.1: # %then ; X32-NEXT: # %bb.1: # %then
; X32-NEXT: movl $64, %eax ; X32-NEXT: movl $64, %eax
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: retl ; X32-NEXT: retl
; X32-NEXT: .LBB1_2: # %else ; X32-NEXT: .LBB1_2: # %else
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: xorl %eax, %eax
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test2: ; X64-LABEL: test2:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rbx ; X64-NEXT: pushq %rbx
; X64-NEXT: incl (%rdi) ; X64-NEXT: incl (%rdi)
; X64-NEXT: setne %bl ; X64-NEXT: sete %bl
; X64-NEXT: movl $42, %edi ; X64-NEXT: movl $42, %edi
; X64-NEXT: callq external ; X64-NEXT: callq external
; X64-NEXT: testb %bl, %bl ; X64-NEXT: testb %bl, %bl
; X64-NEXT: jne .LBB1_2 ; X64-NEXT: je .LBB1_2
; X64-NEXT: # %bb.1: # %then ; X64-NEXT: # %bb.1: # %then
; X64-NEXT: movl $64, %eax ; X64-NEXT: movl $64, %eax
; X64-NEXT: popq %rbx ; X64-NEXT: popq %rbx
; X64-NEXT: retq ; X64-NEXT: retq
; X64-NEXT: .LBB1_2: # %else ; X64-NEXT: .LBB1_2: # %else
; X64-NEXT: xorl %eax, %eax ; X64-NEXT: xorl %eax, %eax
; X64-NEXT: popq %rbx ; X64-NEXT: popq %rbx
; X64-NEXT: retq ; X64-NEXT: retq
Show All 20 Lines
; use volatile stores similar to test1 to force the save and restore of ; use volatile stores similar to test1 to force the save and restore of
; a condition without calling another function. We then set up subsequent calls ; a condition without calling another function. We then set up subsequent calls
; in tail position. ; in tail position.
define dso_local void @test_tail_call(i32* %ptr) nounwind optsize { define dso_local void @test_tail_call(i32* %ptr) nounwind optsize {
; X32-LABEL: test_tail_call: ; X32-LABEL: test_tail_call:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: incl (%eax) ; X32-NEXT: incl (%eax)
; X32-NEXT: setne %al ; X32-NEXT: sete %al
; X32-NEXT: incb a ; X32-NEXT: incb a
; X32-NEXT: sete d ; X32-NEXT: sete d
; X32-NEXT: testb %al, %al ; X32-NEXT: testb %al, %al
; X32-NEXT: jne external_b # TAILCALL ; X32-NEXT: je external_b # TAILCALL
; X32-NEXT: # %bb.1: # %then ; X32-NEXT: # %bb.1: # %then
; X32-NEXT: jmp external_a # TAILCALL ; X32-NEXT: jmp external_a # TAILCALL
; ;
; X64-LABEL: test_tail_call: ; X64-LABEL: test_tail_call:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: incl (%rdi) ; X64-NEXT: incl (%rdi)
; X64-NEXT: setne %al ; X64-NEXT: sete %al
; X64-NEXT: incb a(%rip) ; X64-NEXT: incb a(%rip)
; X64-NEXT: sete d(%rip) ; X64-NEXT: sete d(%rip)
; X64-NEXT: testb %al, %al ; X64-NEXT: testb %al, %al
; X64-NEXT: jne external_b # TAILCALL ; X64-NEXT: je external_b # TAILCALL
; X64-NEXT: # %bb.1: # %then ; X64-NEXT: # %bb.1: # %then
; X64-NEXT: jmp external_a # TAILCALL ; X64-NEXT: jmp external_a # TAILCALL
entry: entry:
%val = load i32, i32* %ptr %val = load i32, i32* %ptr
%inc = add i32 %val, 1 %inc = add i32 %val, 1
store i32 %inc, i32* %ptr store i32 %inc, i32* %ptr
%cmp = icmp eq i32 %inc, 0 %cmp = icmp eq i32 %inc, 0
%aval = load volatile i8, i8* @a %aval = load volatile i8, i8* @a
▲ Show 20 Lines • Show All 162 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/cse-cmp.ll

  • This file was added.
; RUN: llc -o - %s | FileCheck %s
;
; We should see 1 cmp instruction used to produce the flags for both
; conditional jumps. This currently happens by means of Machine CSE
; but requires instruction selection to actually select the exact same
; comparison twice.
define i32 @foo(i32 %arg) {
; CHECK-LABEL: foo:
; CHECK: cmpl $1, %edi
; CHECK-NOT: cmpl
%i1 = icmp eq i32 %arg, 1
br i1 %i1, label %bb5, label %bb2
bb2:
%i3 = icmp sgt i32 %arg, 1
br i1 %i3, label %bb3, label %bb4
bb3:
call void @f0()
br label %return
bb4:
call void @f1()
br label %return
bb5:
call void @f2()
br label %return
return:
%v = phi i32 [0, %bb3], [11, %bb4], [22, %bb5]
ret i32 %v
}
declare void @f0()
declare void @f1()
declare void @f2()

llvm/test/CodeGen/X86/fp128-cast.ll

Show First 20 Lines • Show All 1,248 Lines • ▼ Show 20 Linesentry:
%add = add i128 %or, 3 %add = add i128 %or, 3
%0 = bitcast i128 %add to fp128 %0 = bitcast i128 %add to fp128
ret fp128 %0 ret fp128 %0
} }
define fp128 @TestTruncCopysign(fp128 %x, i32 %n) nounwind { define fp128 @TestTruncCopysign(fp128 %x, i32 %n) nounwind {
; X64-SSE-LABEL: TestTruncCopysign: ; X64-SSE-LABEL: TestTruncCopysign:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: cmpl $50001, %edi # imm = 0xC351 ; X64-SSE-NEXT: cmpl $50000, %edi # imm = 0xC350
; X64-SSE-NEXT: jl .LBB26_2 ; X64-SSE-NEXT: jle .LBB26_2
; X64-SSE-NEXT: # %bb.1: # %if.then ; X64-SSE-NEXT: # %bb.1: # %if.then
; X64-SSE-NEXT: pushq %rax ; X64-SSE-NEXT: pushq %rax
; X64-SSE-NEXT: callq __trunctfdf2@PLT ; X64-SSE-NEXT: callq __trunctfdf2@PLT
; X64-SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; X64-SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; X64-SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: callq __extenddftf2@PLT ; X64-SSE-NEXT: callq __extenddftf2@PLT
; X64-SSE-NEXT: addq $8, %rsp ; X64-SSE-NEXT: addq $8, %rsp
; X64-SSE-NEXT: .LBB26_2: # %cleanup ; X64-SSE-NEXT: .LBB26_2: # %cleanup
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X32-LABEL: TestTruncCopysign: ; X32-LABEL: TestTruncCopysign:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: pushl %edi ; X32-NEXT: pushl %edi
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: subl $36, %esp ; X32-NEXT: subl $36, %esp
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %edi ; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx ; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: cmpl $50001, {{[0-9]+}}(%esp) # imm = 0xC351 ; X32-NEXT: cmpl $50000, {{[0-9]+}}(%esp) # imm = 0xC350
; X32-NEXT: jl .LBB26_4 ; X32-NEXT: jle .LBB26_4
; X32-NEXT: # %bb.1: # %if.then ; X32-NEXT: # %bb.1: # %if.then
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: pushl %ecx ; X32-NEXT: pushl %ecx
; X32-NEXT: pushl %edi ; X32-NEXT: pushl %edi
; X32-NEXT: pushl %edx ; X32-NEXT: pushl %edx
; X32-NEXT: calll __trunctfdf2 ; X32-NEXT: calll __trunctfdf2
; X32-NEXT: addl $16, %esp ; X32-NEXT: addl $16, %esp
; X32-NEXT: fstpl {{[0-9]+}}(%esp) ; X32-NEXT: fstpl {{[0-9]+}}(%esp)
Show All 24 Lines
; X32-NEXT: movl %esi, %eax ; X32-NEXT: movl %esi, %eax
; X32-NEXT: addl $36, %esp ; X32-NEXT: addl $36, %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: popl %edi ; X32-NEXT: popl %edi
; X32-NEXT: retl $4 ; X32-NEXT: retl $4
; ;
; X64-AVX-LABEL: TestTruncCopysign: ; X64-AVX-LABEL: TestTruncCopysign:
; X64-AVX: # %bb.0: # %entry ; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: cmpl $50001, %edi # imm = 0xC351 ; X64-AVX-NEXT: cmpl $50000, %edi # imm = 0xC350
; X64-AVX-NEXT: jl .LBB26_2 ; X64-AVX-NEXT: jle .LBB26_2
; X64-AVX-NEXT: # %bb.1: # %if.then ; X64-AVX-NEXT: # %bb.1: # %if.then
; X64-AVX-NEXT: pushq %rax ; X64-AVX-NEXT: pushq %rax
; X64-AVX-NEXT: callq __trunctfdf2@PLT ; X64-AVX-NEXT: callq __trunctfdf2@PLT
; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vmovddup {{.*#+}} xmm1 = [+Inf,+Inf] ; X64-AVX-NEXT: vmovddup {{.*#+}} xmm1 = [+Inf,+Inf]
; X64-AVX-NEXT: # xmm1 = mem[0,0] ; X64-AVX-NEXT: # xmm1 = mem[0,0]
; X64-AVX-NEXT: vorps %xmm0, %xmm1, %xmm0 ; X64-AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
; X64-AVX-NEXT: callq __extenddftf2@PLT ; X64-AVX-NEXT: callq __extenddftf2@PLT
▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/fp128-select.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; SSE: # %bb.0: # %BB0 ; SSE: # %bb.0: # %BB0
; SSE-NEXT: pushq %rbx ; SSE-NEXT: pushq %rbx
; SSE-NEXT: .cfi_def_cfa_offset 16 ; SSE-NEXT: .cfi_def_cfa_offset 16
; SSE-NEXT: subq $32, %rsp ; SSE-NEXT: subq $32, %rsp
; SSE-NEXT: .cfi_def_cfa_offset 48 ; SSE-NEXT: .cfi_def_cfa_offset 48
; SSE-NEXT: .cfi_offset %rbx, -16 ; SSE-NEXT: .cfi_offset %rbx, -16
; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; SSE-NEXT: callq __netf2@PLT ; SSE-NEXT: callq __eqtf2@PLT
; SSE-NEXT: movl %eax, %ebx ; SSE-NEXT: movl %eax, %ebx
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; SSE-NEXT: callq __eqtf2@PLT ; SSE-NEXT: callq __eqtf2@PLT
; SSE-NEXT: testl %eax, %eax ; SSE-NEXT: testl %eax, %eax
; SSE-NEXT: je .LBB1_1 ; SSE-NEXT: je .LBB1_1
; SSE-NEXT: # %bb.2: # %BB0 ; SSE-NEXT: # %bb.2: # %BB0
; SSE-NEXT: xorps %xmm1, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
Show All 10 Lines
; SSE-NEXT: addq $32, %rsp ; SSE-NEXT: addq $32, %rsp
; SSE-NEXT: .cfi_def_cfa_offset 16 ; SSE-NEXT: .cfi_def_cfa_offset 16
; SSE-NEXT: popq %rbx ; SSE-NEXT: popq %rbx
; SSE-NEXT: .cfi_def_cfa_offset 8 ; SSE-NEXT: .cfi_def_cfa_offset 8
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; NOSSE-LABEL: test_select_cc: ; NOSSE-LABEL: test_select_cc:
; NOSSE: # %bb.0: # %BB0 ; NOSSE: # %bb.0: # %BB0
; NOSSE-NEXT: pushq %rbp ; NOSSE-NEXT: pushq %r14
; NOSSE-NEXT: .cfi_def_cfa_offset 16 ; NOSSE-NEXT: .cfi_def_cfa_offset 16
; NOSSE-NEXT: pushq %r15 ; NOSSE-NEXT: pushq %rbx
; NOSSE-NEXT: .cfi_def_cfa_offset 24 ; NOSSE-NEXT: .cfi_def_cfa_offset 24
; NOSSE-NEXT: pushq %r14 ; NOSSE-NEXT: pushq %rax
; NOSSE-NEXT: .cfi_def_cfa_offset 32 ; NOSSE-NEXT: .cfi_def_cfa_offset 32
; NOSSE-NEXT: pushq %r12 ; NOSSE-NEXT: .cfi_offset %rbx, -24
; NOSSE-NEXT: .cfi_def_cfa_offset 40 ; NOSSE-NEXT: .cfi_offset %r14, -16
; NOSSE-NEXT: pushq %rbx
; NOSSE-NEXT: .cfi_def_cfa_offset 48
; NOSSE-NEXT: .cfi_offset %rbx, -48
; NOSSE-NEXT: .cfi_offset %r12, -40
; NOSSE-NEXT: .cfi_offset %r14, -32
; NOSSE-NEXT: .cfi_offset %r15, -24
; NOSSE-NEXT: .cfi_offset %rbp, -16
; NOSSE-NEXT: movq %rcx, %r12
; NOSSE-NEXT: movq %rdx, %rbx
; NOSSE-NEXT: movq %rsi, %r14 ; NOSSE-NEXT: movq %rsi, %r14
; NOSSE-NEXT: movq %rdi, %r15 ; NOSSE-NEXT: movq %rdi, %rbx
; NOSSE-NEXT: callq __netf2@PLT
; NOSSE-NEXT: movl %eax, %ebp
; NOSSE-NEXT: movq %r15, %rdi
; NOSSE-NEXT: movq %r14, %rsi
; NOSSE-NEXT: movq %rbx, %rdx
; NOSSE-NEXT: movq %r12, %rcx
; NOSSE-NEXT: callq __eqtf2@PLT ; NOSSE-NEXT: callq __eqtf2@PLT
; NOSSE-NEXT: movl %eax, %ecx ; NOSSE-NEXT: movl %eax, %ecx
; NOSSE-NEXT: xorl %eax, %eax ; NOSSE-NEXT: xorl %eax, %eax
; NOSSE-NEXT: testl %ecx, %ecx ; NOSSE-NEXT: testl %ecx, %ecx
; NOSSE-NEXT: movabsq $4611404543450677248, %rdx # imm = 0x3FFF000000000000 ; NOSSE-NEXT: movabsq $4611404543450677248, %rdx # imm = 0x3FFF000000000000
; NOSSE-NEXT: cmovneq %rax, %rdx ; NOSSE-NEXT: cmovneq %rax, %rdx
; NOSSE-NEXT: testl %ebp, %ebp
; NOSSE-NEXT: je .LBB1_2 ; NOSSE-NEXT: je .LBB1_2
; NOSSE-NEXT: # %bb.1: ; NOSSE-NEXT: # %bb.1:
; NOSSE-NEXT: movq %r15, %rax ; NOSSE-NEXT: movq %rbx, %rax
; NOSSE-NEXT: movq %r14, %rdx ; NOSSE-NEXT: movq %r14, %rdx
; NOSSE-NEXT: .LBB1_2: # %BB2 ; NOSSE-NEXT: .LBB1_2: # %BB2
; NOSSE-NEXT: popq %rbx ; NOSSE-NEXT: addq $8, %rsp
; NOSSE-NEXT: .cfi_def_cfa_offset 40
; NOSSE-NEXT: popq %r12
; NOSSE-NEXT: .cfi_def_cfa_offset 32
; NOSSE-NEXT: popq %r14
; NOSSE-NEXT: .cfi_def_cfa_offset 24 ; NOSSE-NEXT: .cfi_def_cfa_offset 24
; NOSSE-NEXT: popq %r15 ; NOSSE-NEXT: popq %rbx
; NOSSE-NEXT: .cfi_def_cfa_offset 16 ; NOSSE-NEXT: .cfi_def_cfa_offset 16
; NOSSE-NEXT: popq %rbp ; NOSSE-NEXT: popq %r14
; NOSSE-NEXT: .cfi_def_cfa_offset 8 ; NOSSE-NEXT: .cfi_def_cfa_offset 8
; NOSSE-NEXT: retq ; NOSSE-NEXT: retq
BB0: BB0:
%a = fcmp oeq fp128 %0, %1 %a = fcmp oeq fp128 %0, %1
%b = uitofp i1 %a to fp128 %b = uitofp i1 %a to fp128
br i1 %a, label %BB1, label %BB2 br i1 %a, label %BB1, label %BB2
BB1: BB1:
br label %BB2 br label %BB2
BB2: BB2:
%c = phi fp128 [ %0, %BB0 ], [ %b, %BB1 ] %c = phi fp128 [ %0, %BB0 ], [ %b, %BB1 ]
ret fp128 %c ret fp128 %c
} }

llvm/test/CodeGen/X86/jump_sign.ll

Show First 20 Lines • Show All 212 Lines • ▼ Show 20 Lines
} }
; PR://13046 ; PR://13046
define void @func_o() nounwind uwtable { define void @func_o() nounwind uwtable {
; CHECK-LABEL: func_o: ; CHECK-LABEL: func_o:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je .LBB12_1 ; CHECK-NEXT: jne .LBB12_1
; CHECK-NEXT: # %bb.2: # %if.end.i ; CHECK-NEXT: # %bb.2: # %if.end.i
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB12_5 ; CHECK-NEXT: je .LBB12_5
; CHECK-NEXT: # %bb.3: # %sw.bb ; CHECK-NEXT: # %bb.3: # %sw.bb
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB12_8 ; CHECK-NEXT: jne .LBB12_8
; CHECK-NEXT: # %bb.4: # %if.end29 ; CHECK-NEXT: # %bb.4: # %if.end29
; CHECK-NEXT: movzwl (%eax), %eax ; CHECK-NEXT: movzwl (%eax), %eax
; CHECK-NEXT: imull $-13107, %eax, %eax # imm = 0xCCCD ; CHECK-NEXT: imull $-13107, %eax, %eax # imm = 0xCCCD
; CHECK-NEXT: rorw %ax ; CHECK-NEXT: rorw %ax
; CHECK-NEXT: movzwl %ax, %eax ; CHECK-NEXT: movzwl %ax, %eax
; CHECK-NEXT: cmpl $6554, %eax # imm = 0x199A ; CHECK-NEXT: cmpl $6554, %eax # imm = 0x199A
; CHECK-NEXT: jae .LBB12_5 ; CHECK-NEXT: jae .LBB12_5
; CHECK-NEXT: .LBB12_8: # %if.then44 ; CHECK-NEXT: .LBB12_8: # %if.then44
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je .LBB12_9 ; CHECK-NEXT: jne .LBB12_9
; CHECK-NEXT: # %bb.10: # %if.else.i104 ; CHECK-NEXT: # %bb.10: # %if.else.i104
; CHECK-NEXT: retl ; CHECK-NEXT: retl
; CHECK-NEXT: .LBB12_5: # %sw.default ; CHECK-NEXT: .LBB12_5: # %sw.default
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB12_7 ; CHECK-NEXT: je .LBB12_7
; CHECK-NEXT: # %bb.6: # %if.then.i96 ; CHECK-NEXT: # %bb.6: # %if.then.i96
; CHECK-NEXT: .LBB12_1: # %if.then.i ; CHECK-NEXT: .LBB12_1: # %if.then.i
; CHECK-NEXT: .LBB12_9: # %if.then.i103 ; CHECK-NEXT: .LBB12_9: # %if.then.i103
; CHECK-NEXT: .LBB12_7: # %if.else.i97 ; CHECK-NEXT: .LBB12_7: # %if.else.i97
entry: entry:
%0 = load i16, i16* undef, align 2 %0 = load i16, i16* undef, align 2
br i1 undef, label %if.then.i, label %if.end.i br i1 undef, label %if.then.i, label %if.end.i
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llvm/test/CodeGen/X86/lea.ll

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; ISel the add of -4 with a neg and use an lea for the rest of the ; ISel the add of -4 with a neg and use an lea for the rest of the
; arithmetic. ; arithmetic.
define i32 @test2(i32 %x_offs) nounwind readnone { define i32 @test2(i32 %x_offs) nounwind readnone {
; LINUX-LABEL: test2: ; LINUX-LABEL: test2:
; LINUX: # %bb.0: # %entry ; LINUX: # %bb.0: # %entry
; LINUX-NEXT: # kill: def $edi killed $edi def $rdi ; LINUX-NEXT: # kill: def $edi killed $edi def $rdi
; LINUX-NEXT: cmpl $5, %edi ; LINUX-NEXT: cmpl $4, %edi
; LINUX-NEXT: jl .LBB1_2 ; LINUX-NEXT: jle .LBB1_2
; LINUX-NEXT: # %bb.1: # %bb.nph ; LINUX-NEXT: # %bb.1: # %bb.nph
; LINUX-NEXT: leal -5(%rdi), %eax ; LINUX-NEXT: leal -5(%rdi), %eax
; LINUX-NEXT: andl $-4, %eax ; LINUX-NEXT: andl $-4, %eax
; LINUX-NEXT: negl %eax ; LINUX-NEXT: negl %eax
; LINUX-NEXT: leal -4(%rdi,%rax), %eax ; LINUX-NEXT: leal -4(%rdi,%rax), %eax
; LINUX-NEXT: retq ; LINUX-NEXT: retq
; LINUX-NEXT: .LBB1_2: # %bb2 ; LINUX-NEXT: .LBB1_2: # %bb2
; LINUX-NEXT: movl %edi, %eax ; LINUX-NEXT: movl %edi, %eax
; LINUX-NEXT: retq ; LINUX-NEXT: retq
; ;
; WIN-LABEL: test2: ; WIN-LABEL: test2:
; WIN: # %bb.0: # %entry ; WIN: # %bb.0: # %entry
; WIN-NEXT: # kill: def $ecx killed $ecx def $rcx ; WIN-NEXT: # kill: def $ecx killed $ecx def $rcx
; WIN-NEXT: cmpl $5, %ecx ; WIN-NEXT: cmpl $4, %ecx
; WIN-NEXT: jl .LBB1_2 ; WIN-NEXT: jle .LBB1_2
; WIN-NEXT: # %bb.1: # %bb.nph ; WIN-NEXT: # %bb.1: # %bb.nph
; WIN-NEXT: leal -5(%rcx), %eax ; WIN-NEXT: leal -5(%rcx), %eax
; WIN-NEXT: andl $-4, %eax ; WIN-NEXT: andl $-4, %eax
; WIN-NEXT: negl %eax ; WIN-NEXT: negl %eax
; WIN-NEXT: leal -4(%rcx,%rax), %eax ; WIN-NEXT: leal -4(%rcx,%rax), %eax
; WIN-NEXT: retq ; WIN-NEXT: retq
; WIN-NEXT: .LBB1_2: # %bb2 ; WIN-NEXT: .LBB1_2: # %bb2
; WIN-NEXT: movl %ecx, %eax ; WIN-NEXT: movl %ecx, %eax
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llvm/test/CodeGen/X86/legalize-shift-64.ll

Show First 20 Lines • Show All 137 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .cfi_offset %ebp, -8 ; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl %esp, %ebp ; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: .cfi_def_cfa_register %ebp ; CHECK-NEXT: .cfi_def_cfa_register %ebp
; CHECK-NEXT: andl $-8, %esp ; CHECK-NEXT: andl $-8, %esp
; CHECK-NEXT: subl $16, %esp ; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: movl $1, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $1, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB5_3 ; CHECK-NEXT: je .LBB5_3
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: jmp .LBB5_2 ; CHECK-NEXT: jmp .LBB5_2
; CHECK-NEXT: .LBB5_3: # %if.end ; CHECK-NEXT: .LBB5_3: # %if.end
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: .LBB5_2: # %if.then ; CHECK-NEXT: .LBB5_2: # %if.then
; CHECK-NEXT: movl %ebp, %esp ; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp ; CHECK-NEXT: popl %ebp
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llvm/test/CodeGen/X86/loop-blocks.ll

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; CHECK: .LBB2_1: ; CHECK: .LBB2_1:
; CHECK-NEXT: callq body ; CHECK-NEXT: callq body
; CHECK-NEXT: callq get ; CHECK-NEXT: callq get
; CHECK-NEXT: cmpl $2, %eax ; CHECK-NEXT: cmpl $2, %eax
; CHECK-NEXT: jge .LBB2_2 ; CHECK-NEXT: jge .LBB2_2
; CHECK-NEXT: callq bar99 ; CHECK-NEXT: callq bar99
; CHECK-NEXT: callq get ; CHECK-NEXT: callq get
; CHECK-NEXT: cmpl $2999, %eax ; CHECK-NEXT: cmpl $3000, %eax
; CHECK-NEXT: jg .LBB2_6 ; CHECK-NEXT: jge .LBB2_6
; CHECK-NEXT: callq block_a_true_func ; CHECK-NEXT: callq block_a_true_func
; CHECK-NEXT: callq block_a_merge_func ; CHECK-NEXT: callq block_a_merge_func
; CHECK-NEXT: jmp .LBB2_1 ; CHECK-NEXT: jmp .LBB2_1
; CHECK-NEXT: align ; CHECK-NEXT: align
; CHECK-NEXT: .LBB2_6: ; CHECK-NEXT: .LBB2_6:
; CHECK-NEXT: callq block_a_false_func ; CHECK-NEXT: callq block_a_false_func
; CHECK-NEXT: callq block_a_merge_func ; CHECK-NEXT: callq block_a_merge_func
; CHECK-NEXT: jmp .LBB2_1 ; CHECK-NEXT: jmp .LBB2_1
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llvm/test/CodeGen/X86/lvi-hardening-gadget-graph.ll

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; CHECK: digraph "Speculative gadgets for \"test\" function" { ; CHECK: digraph "Speculative gadgets for \"test\" function" {
; CHECK-NEXT: label="Speculative gadgets for \"test\" function"; ; CHECK-NEXT: label="Speculative gadgets for \"test\" function";
; CHECK: Node0x{{[0-9a-f]+}} [shape=record,color = green,label="{LFENCE\n}"]; ; CHECK: Node0x{{[0-9a-f]+}} [shape=record,color = green,label="{LFENCE\n}"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 0]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 0];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $eax = MOV32rm %stack.4.i, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.i)\n}"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $eax = MOV32rm %stack.4.i, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.i)\n}"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[color = red, style = "dashed"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[color = red, style = "dashed"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{JCC_1 %bb.6, 13, implicit killed $eflags\n}"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{JCC_1 %bb.2, 12, implicit killed $eflags\n}"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{CMP32rm killed renamable $eax, %stack.2.secret_size.addr, 1, $noreg, 0, $noreg, implicit-def $eflags :: (dereferenceable load (s32) from %ir.secret_size.addr)\n}"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{CMP32rm killed renamable $eax, %stack.2.secret_size.addr, 1, $noreg, 0, $noreg, implicit-def $eflags :: (dereferenceable load (s32) from %ir.secret_size.addr)\n}"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[color = red, style = "dashed"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[color = red, style = "dashed"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $eax = MOV32rm %stack.4.i, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.i)\n}"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $eax = MOV32rm %stack.4.i, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.i)\n}"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[color = red, style = "dashed"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[color = red, style = "dashed"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{JCC_1 %bb.4, 5, implicit killed $eflags\n}"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{JCC_1 %bb.3, 4, implicit killed $eflags\n}"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $rax = MOV64rm %stack.1.secret.addr, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.secret.addr)\n}"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $rax = MOV64rm %stack.1.secret.addr, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.secret.addr)\n}"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[color = red, style = "dashed"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[color = red, style = "dashed"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $eax = MOV32rm killed renamable $rax, 4, killed renamable $rcx, 0, $noreg :: (load (s32) from %ir.arrayidx)\n}"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $eax = MOV32rm killed renamable $rax, 4, killed renamable $rcx, 0, $noreg :: (load (s32) from %ir.arrayidx)\n}"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $rcx = MOVSX64rm32 %stack.3.ret_val, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.ret_val)\n}"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $rcx = MOVSX64rm32 %stack.3.ret_val, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.ret_val)\n}"];
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llvm/test/CodeGen/X86/machine-cse.ll

Show All 10 Lines
; CHECK-LABEL: t: ; CHECK-LABEL: t:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: shlq $9, %rax ; CHECK-NEXT: shlq $9, %rax
; CHECK-NEXT: leaq (%rax,%rax,4), %rdi ; CHECK-NEXT: leaq (%rax,%rax,4), %rdi
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: callq bar@PLT ; CHECK-NEXT: callq bar@PLT
; CHECK-NEXT: .LBB0_2: # %bb2 ; CHECK-NEXT: .LBB0_2: # %bb2
; CHECK-NEXT: callq foo@PLT ; CHECK-NEXT: callq foo@PLT
entry: entry:
%0 = zext i32 %base to i64 %0 = zext i32 %base to i64
%1 = getelementptr inbounds %struct.s2, %struct.s2* null, i64 %0 %1 = getelementptr inbounds %struct.s2, %struct.s2* null, i64 %0
br i1 undef, label %bb1, label %bb2 br i1 undef, label %bb1, label %bb2
Show All 20 Lines
declare void @printf(...) nounwind declare void @printf(...) nounwind
define void @commute(i32 %test_case, i32 %scale) nounwind ssp { define void @commute(i32 %test_case, i32 %scale) nounwind ssp {
; CHECK-LABEL: commute: ; CHECK-LABEL: commute:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi ; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi ; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-NEXT: leal -1(%rdi), %eax ; CHECK-NEXT: leal -1(%rdi), %eax
; CHECK-NEXT: cmpl $2, %eax ; CHECK-NEXT: cmpl $3, %eax
; CHECK-NEXT: ja .LBB1_4 ; CHECK-NEXT: jae .LBB1_4
; CHECK-NEXT: # %bb.1: # %sw.bb ; CHECK-NEXT: # %bb.1: # %sw.bb
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB1_4 ; CHECK-NEXT: je .LBB1_4
; CHECK-NEXT: # %bb.2: # %if.end34 ; CHECK-NEXT: # %bb.2: # %if.end34
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: imull %edi, %esi ; CHECK-NEXT: imull %edi, %esi
; CHECK-NEXT: leal (%rsi,%rsi,2), %esi ; CHECK-NEXT: leal (%rsi,%rsi,2), %esi
; CHECK-NEXT: # kill: def $edi killed $edi killed $rdi ; CHECK-NEXT: # kill: def $edi killed $edi killed $rdi
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: callq printf@PLT ; CHECK-NEXT: callq printf@PLT
; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: addq $8, %rsp
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llvm/test/CodeGen/X86/masked_compressstore.ll

Show First 20 Lines • Show All 1,286 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9 ; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE2-NEXT: pcmpeqd %xmm8, %xmm9 ; SSE2-NEXT: pcmpeqd %xmm8, %xmm9
; SSE2-NEXT: pcmpeqd {{[0-9]+}}(%rsp), %xmm8 ; SSE2-NEXT: pcmpeqd {{[0-9]+}}(%rsp), %xmm8
; SSE2-NEXT: packssdw %xmm9, %xmm8 ; SSE2-NEXT: packssdw %xmm9, %xmm8
; SSE2-NEXT: packsswb %xmm10, %xmm8 ; SSE2-NEXT: packsswb %xmm10, %xmm8
; SSE2-NEXT: pmovmskb %xmm8, %eax ; SSE2-NEXT: pmovmskb %xmm8, %eax
; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: shll $16, %eax
; SSE2-NEXT: orl %ecx, %eax ; SSE2-NEXT: orl %ecx, %eax
; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: testb $1, %cl
; SSE2-NEXT: jne LBB6_1 ; SSE2-NEXT: jne LBB6_1
; SSE2-NEXT: ## %bb.2: ## %else ; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB6_3 ; SSE2-NEXT: jne LBB6_3
; SSE2-NEXT: LBB6_4: ## %else2 ; SSE2-NEXT: LBB6_4: ## %else2
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne LBB6_5 ; SSE2-NEXT: jne LBB6_5
; SSE2-NEXT: LBB6_6: ## %else5 ; SSE2-NEXT: LBB6_6: ## %else5
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; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9 ; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE42-NEXT: pcmpeqd %xmm8, %xmm9 ; SSE42-NEXT: pcmpeqd %xmm8, %xmm9
; SSE42-NEXT: pcmpeqd {{[0-9]+}}(%rsp), %xmm8 ; SSE42-NEXT: pcmpeqd {{[0-9]+}}(%rsp), %xmm8
; SSE42-NEXT: packssdw %xmm9, %xmm8 ; SSE42-NEXT: packssdw %xmm9, %xmm8
; SSE42-NEXT: packsswb %xmm10, %xmm8 ; SSE42-NEXT: packsswb %xmm10, %xmm8
; SSE42-NEXT: pmovmskb %xmm8, %eax ; SSE42-NEXT: pmovmskb %xmm8, %eax
; SSE42-NEXT: shll $16, %eax ; SSE42-NEXT: shll $16, %eax
; SSE42-NEXT: orl %ecx, %eax ; SSE42-NEXT: orl %ecx, %eax
; SSE42-NEXT: testb $1, %al ; SSE42-NEXT: testb $1, %cl
; SSE42-NEXT: jne LBB6_1 ; SSE42-NEXT: jne LBB6_1
; SSE42-NEXT: ## %bb.2: ## %else ; SSE42-NEXT: ## %bb.2: ## %else
; SSE42-NEXT: testb $2, %al ; SSE42-NEXT: testb $2, %al
; SSE42-NEXT: jne LBB6_3 ; SSE42-NEXT: jne LBB6_3
; SSE42-NEXT: LBB6_4: ## %else2 ; SSE42-NEXT: LBB6_4: ## %else2
; SSE42-NEXT: testb $4, %al ; SSE42-NEXT: testb $4, %al
; SSE42-NEXT: jne LBB6_5 ; SSE42-NEXT: jne LBB6_5
; SSE42-NEXT: LBB6_6: ## %else5 ; SSE42-NEXT: LBB6_6: ## %else5
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; AVX1-NEXT: vextractf128 $1, %ymm6, %xmm5 ; AVX1-NEXT: vextractf128 $1, %ymm6, %xmm5
; AVX1-NEXT: vpcmpeqd %xmm5, %xmm9, %xmm5 ; AVX1-NEXT: vpcmpeqd %xmm5, %xmm9, %xmm5
; AVX1-NEXT: vpcmpeqd %xmm6, %xmm9, %xmm6 ; AVX1-NEXT: vpcmpeqd %xmm6, %xmm9, %xmm6
; AVX1-NEXT: vpackssdw %xmm5, %xmm6, %xmm5 ; AVX1-NEXT: vpackssdw %xmm5, %xmm6, %xmm5
; AVX1-NEXT: vpacksswb %xmm4, %xmm5, %xmm4 ; AVX1-NEXT: vpacksswb %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vpmovmskb %xmm4, %eax ; AVX1-NEXT: vpmovmskb %xmm4, %eax
; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: shll $16, %eax
; AVX1-NEXT: orl %ecx, %eax ; AVX1-NEXT: orl %ecx, %eax
; AVX1-NEXT: testb $1, %al ; AVX1-NEXT: testb $1, %cl
; AVX1-NEXT: jne LBB6_1 ; AVX1-NEXT: jne LBB6_1
; AVX1-NEXT: ## %bb.2: ## %else ; AVX1-NEXT: ## %bb.2: ## %else
; AVX1-NEXT: testb $2, %al ; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: jne LBB6_3 ; AVX1-NEXT: jne LBB6_3
; AVX1-NEXT: LBB6_4: ## %else2 ; AVX1-NEXT: LBB6_4: ## %else2
; AVX1-NEXT: testb $4, %al ; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: jne LBB6_5 ; AVX1-NEXT: jne LBB6_5
; AVX1-NEXT: LBB6_6: ## %else5 ; AVX1-NEXT: LBB6_6: ## %else5
▲ Show 20 Lines • Show All 2,534 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/masked_expandload.ll

Show First 20 Lines • Show All 1,383 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9 ; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE2-NEXT: pcmpeqd %xmm8, %xmm9 ; SSE2-NEXT: pcmpeqd %xmm8, %xmm9
; SSE2-NEXT: pcmpeqd {{[0-9]+}}(%rsp), %xmm8 ; SSE2-NEXT: pcmpeqd {{[0-9]+}}(%rsp), %xmm8
; SSE2-NEXT: packssdw %xmm9, %xmm8 ; SSE2-NEXT: packssdw %xmm9, %xmm8
; SSE2-NEXT: packsswb %xmm10, %xmm8 ; SSE2-NEXT: packsswb %xmm10, %xmm8
; SSE2-NEXT: pmovmskb %xmm8, %ecx ; SSE2-NEXT: pmovmskb %xmm8, %ecx
; SSE2-NEXT: shll $16, %ecx ; SSE2-NEXT: shll $16, %ecx
; SSE2-NEXT: orl %edx, %ecx ; SSE2-NEXT: orl %edx, %ecx
; SSE2-NEXT: testb $1, %cl ; SSE2-NEXT: testb $1, %dl
; SSE2-NEXT: jne LBB8_1 ; SSE2-NEXT: jne LBB8_1
; SSE2-NEXT: ## %bb.2: ## %else ; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %cl ; SSE2-NEXT: testb $2, %cl
; SSE2-NEXT: jne LBB8_3 ; SSE2-NEXT: jne LBB8_3
; SSE2-NEXT: LBB8_4: ## %else2 ; SSE2-NEXT: LBB8_4: ## %else2
; SSE2-NEXT: testb $4, %cl ; SSE2-NEXT: testb $4, %cl
; SSE2-NEXT: jne LBB8_5 ; SSE2-NEXT: jne LBB8_5
; SSE2-NEXT: LBB8_6: ## %else6 ; SSE2-NEXT: LBB8_6: ## %else6
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; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9 ; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE42-NEXT: pcmpeqd %xmm8, %xmm9 ; SSE42-NEXT: pcmpeqd %xmm8, %xmm9
; SSE42-NEXT: pcmpeqd {{[0-9]+}}(%rsp), %xmm8 ; SSE42-NEXT: pcmpeqd {{[0-9]+}}(%rsp), %xmm8
; SSE42-NEXT: packssdw %xmm9, %xmm8 ; SSE42-NEXT: packssdw %xmm9, %xmm8
; SSE42-NEXT: packsswb %xmm10, %xmm8 ; SSE42-NEXT: packsswb %xmm10, %xmm8
; SSE42-NEXT: pmovmskb %xmm8, %ecx ; SSE42-NEXT: pmovmskb %xmm8, %ecx
; SSE42-NEXT: shll $16, %ecx ; SSE42-NEXT: shll $16, %ecx
; SSE42-NEXT: orl %edx, %ecx ; SSE42-NEXT: orl %edx, %ecx
; SSE42-NEXT: testb $1, %cl ; SSE42-NEXT: testb $1, %dl
; SSE42-NEXT: jne LBB8_1 ; SSE42-NEXT: jne LBB8_1
; SSE42-NEXT: ## %bb.2: ## %else ; SSE42-NEXT: ## %bb.2: ## %else
; SSE42-NEXT: testb $2, %cl ; SSE42-NEXT: testb $2, %cl
; SSE42-NEXT: jne LBB8_3 ; SSE42-NEXT: jne LBB8_3
; SSE42-NEXT: LBB8_4: ## %else2 ; SSE42-NEXT: LBB8_4: ## %else2
; SSE42-NEXT: testb $4, %cl ; SSE42-NEXT: testb $4, %cl
; SSE42-NEXT: jne LBB8_5 ; SSE42-NEXT: jne LBB8_5
; SSE42-NEXT: LBB8_6: ## %else6 ; SSE42-NEXT: LBB8_6: ## %else6
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; AVX1-NEXT: vextractf128 $1, %ymm6, %xmm5 ; AVX1-NEXT: vextractf128 $1, %ymm6, %xmm5
; AVX1-NEXT: vpcmpeqd %xmm5, %xmm9, %xmm5 ; AVX1-NEXT: vpcmpeqd %xmm5, %xmm9, %xmm5
; AVX1-NEXT: vpcmpeqd %xmm6, %xmm9, %xmm6 ; AVX1-NEXT: vpcmpeqd %xmm6, %xmm9, %xmm6
; AVX1-NEXT: vpackssdw %xmm5, %xmm6, %xmm5 ; AVX1-NEXT: vpackssdw %xmm5, %xmm6, %xmm5
; AVX1-NEXT: vpacksswb %xmm4, %xmm5, %xmm4 ; AVX1-NEXT: vpacksswb %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vpmovmskb %xmm4, %eax ; AVX1-NEXT: vpmovmskb %xmm4, %eax
; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: shll $16, %eax
; AVX1-NEXT: orl %ecx, %eax ; AVX1-NEXT: orl %ecx, %eax
; AVX1-NEXT: testb $1, %al ; AVX1-NEXT: testb $1, %cl
; AVX1-NEXT: jne LBB8_1 ; AVX1-NEXT: jne LBB8_1
; AVX1-NEXT: ## %bb.2: ## %else ; AVX1-NEXT: ## %bb.2: ## %else
; AVX1-NEXT: testb $2, %al ; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: jne LBB8_3 ; AVX1-NEXT: jne LBB8_3
; AVX1-NEXT: LBB8_4: ## %else2 ; AVX1-NEXT: LBB8_4: ## %else2
; AVX1-NEXT: testb $4, %al ; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: jne LBB8_5 ; AVX1-NEXT: jne LBB8_5
; AVX1-NEXT: LBB8_6: ## %else6 ; AVX1-NEXT: LBB8_6: ## %else6
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llvm/test/CodeGen/X86/masked_load.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,526 Lines • ▼ Show 20 Lines
define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, <32 x i8>* %addr, <32 x i8> %dst) { define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, <32 x i8>* %addr, <32 x i8> %dst) {
; SSE2-LABEL: load_v32i8_v32i8: ; SSE2-LABEL: load_v32i8_v32i8:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: pmovmskb %xmm0, %ecx ; SSE2-NEXT: pmovmskb %xmm0, %ecx
; SSE2-NEXT: pmovmskb %xmm1, %eax ; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: shll $16, %eax
; SSE2-NEXT: orl %ecx, %eax ; SSE2-NEXT: orl %ecx, %eax
; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: testb $1, %cl
; SSE2-NEXT: jne LBB24_1 ; SSE2-NEXT: jne LBB24_1
; SSE2-NEXT: ## %bb.2: ## %else ; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB24_3 ; SSE2-NEXT: jne LBB24_3
; SSE2-NEXT: LBB24_4: ## %else2 ; SSE2-NEXT: LBB24_4: ## %else2
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne LBB24_5 ; SSE2-NEXT: jne LBB24_5
; SSE2-NEXT: LBB24_6: ## %else5 ; SSE2-NEXT: LBB24_6: ## %else5
▲ Show 20 Lines • Show All 402 Lines • ▼ Show 20 Lines
; SSE2-NEXT: jmp LBB24_64 ; SSE2-NEXT: jmp LBB24_64
; ;
; SSE42-LABEL: load_v32i8_v32i8: ; SSE42-LABEL: load_v32i8_v32i8:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: pmovmskb %xmm0, %ecx ; SSE42-NEXT: pmovmskb %xmm0, %ecx
; SSE42-NEXT: pmovmskb %xmm1, %eax ; SSE42-NEXT: pmovmskb %xmm1, %eax
; SSE42-NEXT: shll $16, %eax ; SSE42-NEXT: shll $16, %eax
; SSE42-NEXT: orl %ecx, %eax ; SSE42-NEXT: orl %ecx, %eax
; SSE42-NEXT: testb $1, %al ; SSE42-NEXT: testb $1, %cl
; SSE42-NEXT: jne LBB24_1 ; SSE42-NEXT: jne LBB24_1
; SSE42-NEXT: ## %bb.2: ## %else ; SSE42-NEXT: ## %bb.2: ## %else
; SSE42-NEXT: testb $2, %al ; SSE42-NEXT: testb $2, %al
; SSE42-NEXT: jne LBB24_3 ; SSE42-NEXT: jne LBB24_3
; SSE42-NEXT: LBB24_4: ## %else2 ; SSE42-NEXT: LBB24_4: ## %else2
; SSE42-NEXT: testb $4, %al ; SSE42-NEXT: testb $4, %al
; SSE42-NEXT: jne LBB24_5 ; SSE42-NEXT: jne LBB24_5
; SSE42-NEXT: LBB24_6: ## %else5 ; SSE42-NEXT: LBB24_6: ## %else5
▲ Show 20 Lines • Show All 217 Lines • ▼ Show 20 Lines
; ;
; AVX1-LABEL: load_v32i8_v32i8: ; AVX1-LABEL: load_v32i8_v32i8:
; AVX1: ## %bb.0: ; AVX1: ## %bb.0:
; AVX1-NEXT: vpmovmskb %xmm0, %ecx ; AVX1-NEXT: vpmovmskb %xmm0, %ecx
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax ; AVX1-NEXT: vpmovmskb %xmm0, %eax
; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: shll $16, %eax
; AVX1-NEXT: orl %ecx, %eax ; AVX1-NEXT: orl %ecx, %eax
; AVX1-NEXT: testb $1, %al ; AVX1-NEXT: testb $1, %cl
; AVX1-NEXT: jne LBB24_1 ; AVX1-NEXT: jne LBB24_1
; AVX1-NEXT: ## %bb.2: ## %else ; AVX1-NEXT: ## %bb.2: ## %else
; AVX1-NEXT: testb $2, %al ; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: jne LBB24_3 ; AVX1-NEXT: jne LBB24_3
; AVX1-NEXT: LBB24_4: ## %else2 ; AVX1-NEXT: LBB24_4: ## %else2
; AVX1-NEXT: testb $4, %al ; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: jne LBB24_5 ; AVX1-NEXT: jne LBB24_5
; AVX1-NEXT: LBB24_6: ## %else5 ; AVX1-NEXT: LBB24_6: ## %else5
▲ Show 20 Lines • Show All 2,164 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/masked_store.ll

Show First 20 Lines • Show All 3,244 Lines • ▼ Show 20 Lines
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: pcmpeqb %xmm4, %xmm0 ; SSE2-NEXT: pcmpeqb %xmm4, %xmm0
; SSE2-NEXT: pmovmskb %xmm0, %ecx ; SSE2-NEXT: pmovmskb %xmm0, %ecx
; SSE2-NEXT: pcmpeqb %xmm4, %xmm1 ; SSE2-NEXT: pcmpeqb %xmm4, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax ; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: shll $16, %eax
; SSE2-NEXT: orl %ecx, %eax ; SSE2-NEXT: orl %ecx, %eax
; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: testb $1, %cl
; SSE2-NEXT: movd %xmm2, %ecx ; SSE2-NEXT: movd %xmm2, %ecx
; SSE2-NEXT: jne LBB16_1 ; SSE2-NEXT: jne LBB16_1
; SSE2-NEXT: ## %bb.2: ## %else ; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB16_3 ; SSE2-NEXT: jne LBB16_3
; SSE2-NEXT: LBB16_4: ## %else2 ; SSE2-NEXT: LBB16_4: ## %else2
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne LBB16_5 ; SSE2-NEXT: jne LBB16_5
▲ Show 20 Lines • Show All 191 Lines • ▼ Show 20 Lines
; SSE4: ## %bb.0: ; SSE4: ## %bb.0:
; SSE4-NEXT: pxor %xmm4, %xmm4 ; SSE4-NEXT: pxor %xmm4, %xmm4
; SSE4-NEXT: pcmpeqb %xmm4, %xmm0 ; SSE4-NEXT: pcmpeqb %xmm4, %xmm0
; SSE4-NEXT: pmovmskb %xmm0, %ecx ; SSE4-NEXT: pmovmskb %xmm0, %ecx
; SSE4-NEXT: pcmpeqb %xmm4, %xmm1 ; SSE4-NEXT: pcmpeqb %xmm4, %xmm1
; SSE4-NEXT: pmovmskb %xmm1, %eax ; SSE4-NEXT: pmovmskb %xmm1, %eax
; SSE4-NEXT: shll $16, %eax ; SSE4-NEXT: shll $16, %eax
; SSE4-NEXT: orl %ecx, %eax ; SSE4-NEXT: orl %ecx, %eax
; SSE4-NEXT: testb $1, %al ; SSE4-NEXT: testb $1, %cl
; SSE4-NEXT: jne LBB16_1 ; SSE4-NEXT: jne LBB16_1
; SSE4-NEXT: ## %bb.2: ## %else ; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB16_3 ; SSE4-NEXT: jne LBB16_3
; SSE4-NEXT: LBB16_4: ## %else2 ; SSE4-NEXT: LBB16_4: ## %else2
; SSE4-NEXT: testb $4, %al ; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne LBB16_5 ; SSE4-NEXT: jne LBB16_5
; SSE4-NEXT: LBB16_6: ## %else4 ; SSE4-NEXT: LBB16_6: ## %else4
▲ Show 20 Lines • Show All 218 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm3 ; AVX1-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm3
; AVX1-NEXT: vpmovmskb %xmm3, %ecx ; AVX1-NEXT: vpmovmskb %xmm3, %ecx
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax ; AVX1-NEXT: vpmovmskb %xmm0, %eax
; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: shll $16, %eax
; AVX1-NEXT: orl %ecx, %eax ; AVX1-NEXT: orl %ecx, %eax
; AVX1-NEXT: testb $1, %al ; AVX1-NEXT: testb $1, %cl
; AVX1-NEXT: jne LBB16_1 ; AVX1-NEXT: jne LBB16_1
; AVX1-NEXT: ## %bb.2: ## %else ; AVX1-NEXT: ## %bb.2: ## %else
; AVX1-NEXT: testb $2, %al ; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: jne LBB16_3 ; AVX1-NEXT: jne LBB16_3
; AVX1-NEXT: LBB16_4: ## %else2 ; AVX1-NEXT: LBB16_4: ## %else2
; AVX1-NEXT: testb $4, %al ; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: jne LBB16_5 ; AVX1-NEXT: jne LBB16_5
; AVX1-NEXT: LBB16_6: ## %else4 ; AVX1-NEXT: LBB16_6: ## %else4
▲ Show 20 Lines • Show All 1,878 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/masked_store_trunc.ll

Show First 20 Lines • Show All 4,431 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pcmpeqb %xmm7, %xmm4 ; SSE2-NEXT: pcmpeqb %xmm7, %xmm4
; SSE2-NEXT: pmovmskb %xmm4, %ecx ; SSE2-NEXT: pmovmskb %xmm4, %ecx
; SSE2-NEXT: xorl $65535, %ecx # imm = 0xFFFF ; SSE2-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; SSE2-NEXT: pcmpeqb %xmm7, %xmm5 ; SSE2-NEXT: pcmpeqb %xmm7, %xmm5
; SSE2-NEXT: pmovmskb %xmm5, %eax ; SSE2-NEXT: pmovmskb %xmm5, %eax
; SSE2-NEXT: notl %eax ; SSE2-NEXT: notl %eax
; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: shll $16, %eax
; SSE2-NEXT: orl %ecx, %eax ; SSE2-NEXT: orl %ecx, %eax
; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: testb $1, %cl
; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movd %xmm0, %ecx
; SSE2-NEXT: jne .LBB15_1 ; SSE2-NEXT: jne .LBB15_1
; SSE2-NEXT: # %bb.2: # %else ; SSE2-NEXT: # %bb.2: # %else
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne .LBB15_3 ; SSE2-NEXT: jne .LBB15_3
; SSE2-NEXT: .LBB15_4: # %else2 ; SSE2-NEXT: .LBB15_4: # %else2
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne .LBB15_5 ; SSE2-NEXT: jne .LBB15_5
▲ Show 20 Lines • Show All 200 Lines • ▼ Show 20 Lines
; SSE4-NEXT: pcmpeqb %xmm7, %xmm4 ; SSE4-NEXT: pcmpeqb %xmm7, %xmm4
; SSE4-NEXT: pmovmskb %xmm4, %ecx ; SSE4-NEXT: pmovmskb %xmm4, %ecx
; SSE4-NEXT: xorl $65535, %ecx # imm = 0xFFFF ; SSE4-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; SSE4-NEXT: pcmpeqb %xmm7, %xmm5 ; SSE4-NEXT: pcmpeqb %xmm7, %xmm5
; SSE4-NEXT: pmovmskb %xmm5, %eax ; SSE4-NEXT: pmovmskb %xmm5, %eax
; SSE4-NEXT: notl %eax ; SSE4-NEXT: notl %eax
; SSE4-NEXT: shll $16, %eax ; SSE4-NEXT: shll $16, %eax
; SSE4-NEXT: orl %ecx, %eax ; SSE4-NEXT: orl %ecx, %eax
; SSE4-NEXT: testb $1, %al ; SSE4-NEXT: testb $1, %cl
; SSE4-NEXT: jne .LBB15_1 ; SSE4-NEXT: jne .LBB15_1
; SSE4-NEXT: # %bb.2: # %else ; SSE4-NEXT: # %bb.2: # %else
; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne .LBB15_3 ; SSE4-NEXT: jne .LBB15_3
; SSE4-NEXT: .LBB15_4: # %else2 ; SSE4-NEXT: .LBB15_4: # %else2
; SSE4-NEXT: testb $4, %al ; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne .LBB15_5 ; SSE4-NEXT: jne .LBB15_5
; SSE4-NEXT: .LBB15_6: # %else4 ; SSE4-NEXT: .LBB15_6: # %else4
▲ Show 20 Lines • Show All 228 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpmovmskb %xmm3, %ecx ; AVX1-NEXT: vpmovmskb %xmm3, %ecx
; AVX1-NEXT: xorl $65535, %ecx # imm = 0xFFFF ; AVX1-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vpcmpeqb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpmovmskb %xmm1, %eax ; AVX1-NEXT: vpmovmskb %xmm1, %eax
; AVX1-NEXT: notl %eax ; AVX1-NEXT: notl %eax
; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: shll $16, %eax
; AVX1-NEXT: orl %ecx, %eax ; AVX1-NEXT: orl %ecx, %eax
; AVX1-NEXT: testb $1, %al ; AVX1-NEXT: testb $1, %cl
; AVX1-NEXT: jne .LBB15_1 ; AVX1-NEXT: jne .LBB15_1
; AVX1-NEXT: # %bb.2: # %else ; AVX1-NEXT: # %bb.2: # %else
; AVX1-NEXT: testb $2, %al ; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: jne .LBB15_3 ; AVX1-NEXT: jne .LBB15_3
; AVX1-NEXT: .LBB15_4: # %else2 ; AVX1-NEXT: .LBB15_4: # %else2
; AVX1-NEXT: testb $4, %al ; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: jne .LBB15_5 ; AVX1-NEXT: jne .LBB15_5
; AVX1-NEXT: .LBB15_6: # %else4 ; AVX1-NEXT: .LBB15_6: # %else4
▲ Show 20 Lines • Show All 1,648 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,412 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pcmpeqb %xmm6, %xmm4 ; SSE2-NEXT: pcmpeqb %xmm6, %xmm4
; SSE2-NEXT: pmovmskb %xmm4, %ecx ; SSE2-NEXT: pmovmskb %xmm4, %ecx
; SSE2-NEXT: xorl $65535, %ecx # imm = 0xFFFF ; SSE2-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; SSE2-NEXT: pcmpeqb %xmm6, %xmm5 ; SSE2-NEXT: pcmpeqb %xmm6, %xmm5
; SSE2-NEXT: pmovmskb %xmm5, %eax ; SSE2-NEXT: pmovmskb %xmm5, %eax
; SSE2-NEXT: notl %eax ; SSE2-NEXT: notl %eax
; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: shll $16, %eax
; SSE2-NEXT: orl %ecx, %eax ; SSE2-NEXT: orl %ecx, %eax
; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: testb $1, %cl
; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movd %xmm0, %ecx
; SSE2-NEXT: jne .LBB15_1 ; SSE2-NEXT: jne .LBB15_1
; SSE2-NEXT: # %bb.2: # %else ; SSE2-NEXT: # %bb.2: # %else
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne .LBB15_3 ; SSE2-NEXT: jne .LBB15_3
; SSE2-NEXT: .LBB15_4: # %else2 ; SSE2-NEXT: .LBB15_4: # %else2
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne .LBB15_5 ; SSE2-NEXT: jne .LBB15_5
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; SSE4-NEXT: pcmpeqb %xmm6, %xmm4 ; SSE4-NEXT: pcmpeqb %xmm6, %xmm4
; SSE4-NEXT: pmovmskb %xmm4, %ecx ; SSE4-NEXT: pmovmskb %xmm4, %ecx
; SSE4-NEXT: xorl $65535, %ecx # imm = 0xFFFF ; SSE4-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; SSE4-NEXT: pcmpeqb %xmm6, %xmm5 ; SSE4-NEXT: pcmpeqb %xmm6, %xmm5
; SSE4-NEXT: pmovmskb %xmm5, %eax ; SSE4-NEXT: pmovmskb %xmm5, %eax
; SSE4-NEXT: notl %eax ; SSE4-NEXT: notl %eax
; SSE4-NEXT: shll $16, %eax ; SSE4-NEXT: shll $16, %eax
; SSE4-NEXT: orl %ecx, %eax ; SSE4-NEXT: orl %ecx, %eax
; SSE4-NEXT: testb $1, %al ; SSE4-NEXT: testb $1, %cl
; SSE4-NEXT: jne .LBB15_1 ; SSE4-NEXT: jne .LBB15_1
; SSE4-NEXT: # %bb.2: # %else ; SSE4-NEXT: # %bb.2: # %else
; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne .LBB15_3 ; SSE4-NEXT: jne .LBB15_3
; SSE4-NEXT: .LBB15_4: # %else2 ; SSE4-NEXT: .LBB15_4: # %else2
; SSE4-NEXT: testb $4, %al ; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne .LBB15_5 ; SSE4-NEXT: jne .LBB15_5
; SSE4-NEXT: .LBB15_6: # %else4 ; SSE4-NEXT: .LBB15_6: # %else4
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; AVX1-NEXT: vpmovmskb %xmm3, %ecx ; AVX1-NEXT: vpmovmskb %xmm3, %ecx
; AVX1-NEXT: xorl $65535, %ecx # imm = 0xFFFF ; AVX1-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vpcmpeqb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpmovmskb %xmm1, %eax ; AVX1-NEXT: vpmovmskb %xmm1, %eax
; AVX1-NEXT: notl %eax ; AVX1-NEXT: notl %eax
; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: shll $16, %eax
; AVX1-NEXT: orl %ecx, %eax ; AVX1-NEXT: orl %ecx, %eax
; AVX1-NEXT: testb $1, %al ; AVX1-NEXT: testb $1, %cl
; AVX1-NEXT: jne .LBB15_1 ; AVX1-NEXT: jne .LBB15_1
; AVX1-NEXT: # %bb.2: # %else ; AVX1-NEXT: # %bb.2: # %else
; AVX1-NEXT: testb $2, %al ; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: jne .LBB15_3 ; AVX1-NEXT: jne .LBB15_3
; AVX1-NEXT: .LBB15_4: # %else2 ; AVX1-NEXT: .LBB15_4: # %else2
; AVX1-NEXT: testb $4, %al ; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: jne .LBB15_5 ; AVX1-NEXT: jne .LBB15_5
; AVX1-NEXT: .LBB15_6: # %else4 ; AVX1-NEXT: .LBB15_6: # %else4
▲ Show 20 Lines • Show All 1,653 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/masked_store_trunc_usat.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,198 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pcmpeqb %xmm7, %xmm4 ; SSE2-NEXT: pcmpeqb %xmm7, %xmm4
; SSE2-NEXT: pmovmskb %xmm4, %ecx ; SSE2-NEXT: pmovmskb %xmm4, %ecx
; SSE2-NEXT: xorl $65535, %ecx # imm = 0xFFFF ; SSE2-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; SSE2-NEXT: pcmpeqb %xmm7, %xmm5 ; SSE2-NEXT: pcmpeqb %xmm7, %xmm5
; SSE2-NEXT: pmovmskb %xmm5, %eax ; SSE2-NEXT: pmovmskb %xmm5, %eax
; SSE2-NEXT: notl %eax ; SSE2-NEXT: notl %eax
; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: shll $16, %eax
; SSE2-NEXT: orl %ecx, %eax ; SSE2-NEXT: orl %ecx, %eax
; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: testb $1, %cl
; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movd %xmm0, %ecx
; SSE2-NEXT: jne .LBB15_1 ; SSE2-NEXT: jne .LBB15_1
; SSE2-NEXT: # %bb.2: # %else ; SSE2-NEXT: # %bb.2: # %else
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne .LBB15_3 ; SSE2-NEXT: jne .LBB15_3
; SSE2-NEXT: .LBB15_4: # %else2 ; SSE2-NEXT: .LBB15_4: # %else2
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne .LBB15_5 ; SSE2-NEXT: jne .LBB15_5
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; SSE4-NEXT: pcmpeqb %xmm7, %xmm4 ; SSE4-NEXT: pcmpeqb %xmm7, %xmm4
; SSE4-NEXT: pmovmskb %xmm4, %ecx ; SSE4-NEXT: pmovmskb %xmm4, %ecx
; SSE4-NEXT: xorl $65535, %ecx # imm = 0xFFFF ; SSE4-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; SSE4-NEXT: pcmpeqb %xmm7, %xmm5 ; SSE4-NEXT: pcmpeqb %xmm7, %xmm5
; SSE4-NEXT: pmovmskb %xmm5, %eax ; SSE4-NEXT: pmovmskb %xmm5, %eax
; SSE4-NEXT: notl %eax ; SSE4-NEXT: notl %eax
; SSE4-NEXT: shll $16, %eax ; SSE4-NEXT: shll $16, %eax
; SSE4-NEXT: orl %ecx, %eax ; SSE4-NEXT: orl %ecx, %eax
; SSE4-NEXT: testb $1, %al ; SSE4-NEXT: testb $1, %cl
; SSE4-NEXT: jne .LBB15_1 ; SSE4-NEXT: jne .LBB15_1
; SSE4-NEXT: # %bb.2: # %else ; SSE4-NEXT: # %bb.2: # %else
; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne .LBB15_3 ; SSE4-NEXT: jne .LBB15_3
; SSE4-NEXT: .LBB15_4: # %else2 ; SSE4-NEXT: .LBB15_4: # %else2
; SSE4-NEXT: testb $4, %al ; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne .LBB15_5 ; SSE4-NEXT: jne .LBB15_5
; SSE4-NEXT: .LBB15_6: # %else4 ; SSE4-NEXT: .LBB15_6: # %else4
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; AVX1-NEXT: vpmovmskb %xmm3, %ecx ; AVX1-NEXT: vpmovmskb %xmm3, %ecx
; AVX1-NEXT: xorl $65535, %ecx # imm = 0xFFFF ; AVX1-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vpcmpeqb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpmovmskb %xmm1, %eax ; AVX1-NEXT: vpmovmskb %xmm1, %eax
; AVX1-NEXT: notl %eax ; AVX1-NEXT: notl %eax
; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: shll $16, %eax
; AVX1-NEXT: orl %ecx, %eax ; AVX1-NEXT: orl %ecx, %eax
; AVX1-NEXT: testb $1, %al ; AVX1-NEXT: testb $1, %cl
; AVX1-NEXT: jne .LBB15_1 ; AVX1-NEXT: jne .LBB15_1
; AVX1-NEXT: # %bb.2: # %else ; AVX1-NEXT: # %bb.2: # %else
; AVX1-NEXT: testb $2, %al ; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: jne .LBB15_3 ; AVX1-NEXT: jne .LBB15_3
; AVX1-NEXT: .LBB15_4: # %else2 ; AVX1-NEXT: .LBB15_4: # %else2
; AVX1-NEXT: testb $4, %al ; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: jne .LBB15_5 ; AVX1-NEXT: jne .LBB15_5
; AVX1-NEXT: .LBB15_6: # %else4 ; AVX1-NEXT: .LBB15_6: # %else4
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llvm/test/CodeGen/X86/musttail-varargs.ll

Show First 20 Lines • Show All 321 Lines • ▼ Show 20 Lines
%struct.Foo = type { i1, i8*, i8* } %struct.Foo = type { i1, i8*, i8* }
@g = external dso_local global i32 @g = external dso_local global i32
define void @h_thunk(%struct.Foo* %this, ...) { define void @h_thunk(%struct.Foo* %this, ...) {
; LINUX-LABEL: h_thunk: ; LINUX-LABEL: h_thunk:
; LINUX: # %bb.0: ; LINUX: # %bb.0:
; LINUX-NEXT: cmpb $1, (%rdi) ; LINUX-NEXT: cmpb $0, (%rdi)
; LINUX-NEXT: jne .LBB2_2 ; LINUX-NEXT: je .LBB2_2
; LINUX-NEXT: # %bb.1: # %then ; LINUX-NEXT: # %bb.1: # %then
; LINUX-NEXT: movq 8(%rdi), %r11 ; LINUX-NEXT: movq 8(%rdi), %r11
; LINUX-NEXT: jmpq *%r11 # TAILCALL ; LINUX-NEXT: jmpq *%r11 # TAILCALL
; LINUX-NEXT: .LBB2_2: # %else ; LINUX-NEXT: .LBB2_2: # %else
; LINUX-NEXT: movq 16(%rdi), %r11 ; LINUX-NEXT: movq 16(%rdi), %r11
; LINUX-NEXT: movl $42, g(%rip) ; LINUX-NEXT: movl $42, g(%rip)
; LINUX-NEXT: jmpq *%r11 # TAILCALL ; LINUX-NEXT: jmpq *%r11 # TAILCALL
; ;
; LINUX-X32-LABEL: h_thunk: ; LINUX-X32-LABEL: h_thunk:
; LINUX-X32: # %bb.0: ; LINUX-X32: # %bb.0:
; LINUX-X32-NEXT: cmpb $1, (%edi) ; LINUX-X32-NEXT: cmpb $0, (%edi)
; LINUX-X32-NEXT: jne .LBB2_2 ; LINUX-X32-NEXT: je .LBB2_2
; LINUX-X32-NEXT: # %bb.1: # %then ; LINUX-X32-NEXT: # %bb.1: # %then
; LINUX-X32-NEXT: movl 4(%edi), %r11d ; LINUX-X32-NEXT: movl 4(%edi), %r11d
; LINUX-X32-NEXT: movl %edi, %edi ; LINUX-X32-NEXT: movl %edi, %edi
; LINUX-X32-NEXT: jmpq *%r11 # TAILCALL ; LINUX-X32-NEXT: jmpq *%r11 # TAILCALL
; LINUX-X32-NEXT: .LBB2_2: # %else ; LINUX-X32-NEXT: .LBB2_2: # %else
; LINUX-X32-NEXT: movl 8(%edi), %r11d ; LINUX-X32-NEXT: movl 8(%edi), %r11d
; LINUX-X32-NEXT: movl $42, g(%rip) ; LINUX-X32-NEXT: movl $42, g(%rip)
; LINUX-X32-NEXT: movl %edi, %edi ; LINUX-X32-NEXT: movl %edi, %edi
; LINUX-X32-NEXT: jmpq *%r11 # TAILCALL ; LINUX-X32-NEXT: jmpq *%r11 # TAILCALL
; ;
; WINDOWS-LABEL: h_thunk: ; WINDOWS-LABEL: h_thunk:
; WINDOWS: # %bb.0: ; WINDOWS: # %bb.0:
; WINDOWS-NEXT: cmpb $1, (%rcx) ; WINDOWS-NEXT: cmpb $0, (%rcx)
; WINDOWS-NEXT: jne .LBB2_2 ; WINDOWS-NEXT: je .LBB2_2
; WINDOWS-NEXT: # %bb.1: # %then ; WINDOWS-NEXT: # %bb.1: # %then
; WINDOWS-NEXT: movq 8(%rcx), %rax ; WINDOWS-NEXT: movq 8(%rcx), %rax
; WINDOWS-NEXT: rex64 jmpq *%rax # TAILCALL ; WINDOWS-NEXT: rex64 jmpq *%rax # TAILCALL
; WINDOWS-NEXT: .LBB2_2: # %else ; WINDOWS-NEXT: .LBB2_2: # %else
; WINDOWS-NEXT: movq 16(%rcx), %rax ; WINDOWS-NEXT: movq 16(%rcx), %rax
; WINDOWS-NEXT: movl $42, g(%rip) ; WINDOWS-NEXT: movl $42, g(%rip)
; WINDOWS-NEXT: rex64 jmpq *%rax # TAILCALL ; WINDOWS-NEXT: rex64 jmpq *%rax # TAILCALL
; ;
; X86-LABEL: h_thunk: ; X86-LABEL: h_thunk:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: cmpb $1, (%eax) ; X86-NEXT: cmpb $0, (%eax)
; X86-NEXT: jne LBB2_2 ; X86-NEXT: je LBB2_2
; X86-NEXT: # %bb.1: # %then ; X86-NEXT: # %bb.1: # %then
; X86-NEXT: movl 4(%eax), %ecx ; X86-NEXT: movl 4(%eax), %ecx
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: jmpl *%ecx # TAILCALL ; X86-NEXT: jmpl *%ecx # TAILCALL
; X86-NEXT: LBB2_2: # %else ; X86-NEXT: LBB2_2: # %else
; X86-NEXT: movl 8(%eax), %ecx ; X86-NEXT: movl 8(%eax), %ecx
; X86-NEXT: movl $42, _g ; X86-NEXT: movl $42, _g
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
Show All 20 Lines

llvm/test/CodeGen/X86/nobt.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; This tests some cases where BT must not be generated. See also bt.ll. ; This tests some cases where BT must not be generated. See also bt.ll.
; Fixes 20040709-[12].c in gcc testsuite. ; Fixes 20040709-[12].c in gcc testsuite.
define void @test2(i32 %x, i32 %n) nounwind { define void @test2(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: # %bb.1: # %bb
; CHECK-NEXT: calll foo@PLT ; CHECK-NEXT: calll foo@PLT
; CHECK-NEXT: .LBB0_2: # %UnifiedReturnBlock ; CHECK-NEXT: .LBB0_2: # %UnifiedReturnBlock
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%tmp1 = and i32 %x, 1 %tmp1 = and i32 %x, 1
%tmp2 = urem i32 %tmp1, 15 %tmp2 = urem i32 %tmp1, 15
%tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1] %tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1]
%tmp4 = icmp eq i32 %tmp3, %tmp2 ; <i1> [#uses=1] %tmp4 = icmp eq i32 %tmp3, %tmp2 ; <i1> [#uses=1]
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: ; preds = %entry bb: ; preds = %entry
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: ; preds = %entry UnifiedReturnBlock: ; preds = %entry
ret void ret void
} }
define void @test3(i32 %x, i32 %n) nounwind { define void @test3(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB1_2 ; CHECK-NEXT: je .LBB1_2
; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: # %bb.1: # %bb
; CHECK-NEXT: calll foo@PLT ; CHECK-NEXT: calll foo@PLT
; CHECK-NEXT: .LBB1_2: # %UnifiedReturnBlock ; CHECK-NEXT: .LBB1_2: # %UnifiedReturnBlock
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%tmp1 = and i32 %x, 1 %tmp1 = and i32 %x, 1
%tmp2 = urem i32 %tmp1, 15 %tmp2 = urem i32 %tmp1, 15
%tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1] %tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1]
%tmp4 = icmp eq i32 %tmp2, %tmp3 ; <i1> [#uses=1] %tmp4 = icmp eq i32 %tmp2, %tmp3 ; <i1> [#uses=1]
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: ; preds = %entry bb: ; preds = %entry
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: ; preds = %entry UnifiedReturnBlock: ; preds = %entry
ret void ret void
} }
define void @test4(i32 %x, i32 %n) nounwind { define void @test4(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: test4: ; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB2_2 ; CHECK-NEXT: je .LBB2_2
; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: # %bb.1: # %bb
; CHECK-NEXT: calll foo@PLT ; CHECK-NEXT: calll foo@PLT
; CHECK-NEXT: .LBB2_2: # %UnifiedReturnBlock ; CHECK-NEXT: .LBB2_2: # %UnifiedReturnBlock
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%tmp1 = and i32 %x, 1 %tmp1 = and i32 %x, 1
%tmp2 = urem i32 %tmp1, 15 %tmp2 = urem i32 %tmp1, 15
%tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1] %tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1]
%tmp4 = icmp ne i32 %tmp2, %tmp3 ; <i1> [#uses=1] %tmp4 = icmp ne i32 %tmp2, %tmp3 ; <i1> [#uses=1]
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: ; preds = %entry bb: ; preds = %entry
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: ; preds = %entry UnifiedReturnBlock: ; preds = %entry
ret void ret void
} }
define void @test5(i32 %x, i32 %n) nounwind { define void @test5(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB3_2 ; CHECK-NEXT: je .LBB3_2
; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: # %bb.1: # %bb
; CHECK-NEXT: calll foo@PLT ; CHECK-NEXT: calll foo@PLT
; CHECK-NEXT: .LBB3_2: # %UnifiedReturnBlock ; CHECK-NEXT: .LBB3_2: # %UnifiedReturnBlock
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%tmp1 = and i32 %x, 1 %tmp1 = and i32 %x, 1
%tmp2 = urem i32 %tmp1, 15 %tmp2 = urem i32 %tmp1, 15
%tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1] %tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1]
Show All 12 Lines

llvm/test/CodeGen/X86/optimize-max-0.ll

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ## in Loop: Header=BB0_4 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB0_4 Depth=1
; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: jmp LBB0_4 ; CHECK-NEXT: jmp LBB0_4
; CHECK-NEXT: LBB0_12: ## %bb18.loopexit ; CHECK-NEXT: LBB0_12: ## %bb18.loopexit
; CHECK-NEXT: movl (%esp), %eax ## 4-byte Reload ; CHECK-NEXT: movl (%esp), %eax ## 4-byte Reload
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload ; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload
; CHECK-NEXT: addl %ecx, %eax ; CHECK-NEXT: addl %ecx, %eax
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill ; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: cmpl $1, %edi ; CHECK-NEXT: cmpl $2, %edi
; CHECK-NEXT: jle LBB0_13 ; CHECK-NEXT: jl LBB0_13
; CHECK-NEXT: ## %bb.7: ## %bb.nph5 ; CHECK-NEXT: ## %bb.7: ## %bb.nph5
; CHECK-NEXT: cmpl $2, %ebp ; CHECK-NEXT: cmpl $2, %ebp
; CHECK-NEXT: jl LBB0_13 ; CHECK-NEXT: jl LBB0_13
; CHECK-NEXT: ## %bb.8: ## %bb.nph5.split ; CHECK-NEXT: ## %bb.8: ## %bb.nph5.split
; CHECK-NEXT: movl %ebp, %edx ; CHECK-NEXT: movl %ebp, %edx
; CHECK-NEXT: shrl $31, %edx ; CHECK-NEXT: shrl $31, %edx
; CHECK-NEXT: addl %ebp, %edx ; CHECK-NEXT: addl %ebp, %edx
; CHECK-NEXT: sarl %edx ; CHECK-NEXT: sarl %edx
▲ Show 20 Lines • Show All 417 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ## in Loop: Header=BB1_4 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB1_4 Depth=1
; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: jmp LBB1_4 ; CHECK-NEXT: jmp LBB1_4
; CHECK-NEXT: LBB1_12: ## %bb18.loopexit ; CHECK-NEXT: LBB1_12: ## %bb18.loopexit
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax ## 4-byte Reload ; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax ## 4-byte Reload
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload ; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload
; CHECK-NEXT: addl %ecx, %eax ; CHECK-NEXT: addl %ecx, %eax
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill ; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: cmpl $1, %ebp ; CHECK-NEXT: cmpl $2, %ebp
; CHECK-NEXT: jbe LBB1_13 ; CHECK-NEXT: jb LBB1_13
; CHECK-NEXT: ## %bb.7: ## %bb.nph5 ; CHECK-NEXT: ## %bb.7: ## %bb.nph5
; CHECK-NEXT: cmpl $2, %edi ; CHECK-NEXT: cmpl $2, %edi
; CHECK-NEXT: jb LBB1_13 ; CHECK-NEXT: jb LBB1_13
; CHECK-NEXT: ## %bb.8: ## %bb.nph5.split ; CHECK-NEXT: ## %bb.8: ## %bb.nph5.split
; CHECK-NEXT: movl %edi, %ebp ; CHECK-NEXT: movl %edi, %ebp
; CHECK-NEXT: shrl %ebp ; CHECK-NEXT: shrl %ebp
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: shrl %eax ; CHECK-NEXT: shrl %eax
▲ Show 20 Lines • Show All 372 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/or-branch.ll

Show All 12 Lines
; JUMP2-NEXT: # %bb.2: # %UnifiedReturnBlock ; JUMP2-NEXT: # %bb.2: # %UnifiedReturnBlock
; JUMP2-NEXT: retl ; JUMP2-NEXT: retl
; JUMP2-NEXT: .LBB0_3: # %cond_true ; JUMP2-NEXT: .LBB0_3: # %cond_true
; JUMP2-NEXT: jmp bar@PLT # TAILCALL ; JUMP2-NEXT: jmp bar@PLT # TAILCALL
; ;
; JUMP1-LABEL: foo: ; JUMP1-LABEL: foo:
; JUMP1: # %bb.0: # %entry ; JUMP1: # %bb.0: # %entry
; JUMP1-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; JUMP1-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; JUMP1-NEXT: setne %al ; JUMP1-NEXT: sete %al
; JUMP1-NEXT: cmpl $5, {{[0-9]+}}(%esp) ; JUMP1-NEXT: cmpl $5, {{[0-9]+}}(%esp)
; JUMP1-NEXT: setge %cl ; JUMP1-NEXT: setl %cl
; JUMP1-NEXT: testb %al, %cl ; JUMP1-NEXT: orb %al, %cl
; JUMP1-NEXT: jne .LBB0_1 ; JUMP1-NEXT: je .LBB0_1
; JUMP1-NEXT: # %bb.2: # %cond_true ; JUMP1-NEXT: # %bb.2: # %cond_true
; JUMP1-NEXT: jmp bar@PLT # TAILCALL ; JUMP1-NEXT: jmp bar@PLT # TAILCALL
; JUMP1-NEXT: .LBB0_1: # %UnifiedReturnBlock ; JUMP1-NEXT: .LBB0_1: # %UnifiedReturnBlock
; JUMP1-NEXT: retl ; JUMP1-NEXT: retl
entry: entry:
%tmp1 = icmp eq i32 %X, 0 %tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5 %tmp3 = icmp slt i32 %Y, 5
%tmp4 = or i1 %tmp3, %tmp1 %tmp4 = or i1 %tmp3, %tmp1
Show All 9 Lines
; If the branch is unpredictable, don't add another branch ; If the branch is unpredictable, don't add another branch
; regardless of whether they are expensive or not. ; regardless of whether they are expensive or not.
define void @unpredictable(i32 %X, i32 %Y, i32 %Z) nounwind { define void @unpredictable(i32 %X, i32 %Y, i32 %Z) nounwind {
; JUMP2-LABEL: unpredictable: ; JUMP2-LABEL: unpredictable:
; JUMP2: # %bb.0: # %entry ; JUMP2: # %bb.0: # %entry
; JUMP2-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; JUMP2-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; JUMP2-NEXT: setne %al ; JUMP2-NEXT: sete %al
; JUMP2-NEXT: cmpl $5, {{[0-9]+}}(%esp) ; JUMP2-NEXT: cmpl $5, {{[0-9]+}}(%esp)
; JUMP2-NEXT: setge %cl ; JUMP2-NEXT: setl %cl
; JUMP2-NEXT: testb %al, %cl ; JUMP2-NEXT: orb %al, %cl
; JUMP2-NEXT: jne .LBB1_1 ; JUMP2-NEXT: je .LBB1_1
; JUMP2-NEXT: # %bb.2: # %cond_true ; JUMP2-NEXT: # %bb.2: # %cond_true
; JUMP2-NEXT: jmp bar@PLT # TAILCALL ; JUMP2-NEXT: jmp bar@PLT # TAILCALL
; JUMP2-NEXT: .LBB1_1: # %UnifiedReturnBlock ; JUMP2-NEXT: .LBB1_1: # %UnifiedReturnBlock
; JUMP2-NEXT: retl ; JUMP2-NEXT: retl
; ;
; JUMP1-LABEL: unpredictable: ; JUMP1-LABEL: unpredictable:
; JUMP1: # %bb.0: # %entry ; JUMP1: # %bb.0: # %entry
; JUMP1-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; JUMP1-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; JUMP1-NEXT: setne %al ; JUMP1-NEXT: sete %al
; JUMP1-NEXT: cmpl $5, {{[0-9]+}}(%esp) ; JUMP1-NEXT: cmpl $5, {{[0-9]+}}(%esp)
; JUMP1-NEXT: setge %cl ; JUMP1-NEXT: setl %cl
; JUMP1-NEXT: testb %al, %cl ; JUMP1-NEXT: orb %al, %cl
; JUMP1-NEXT: jne .LBB1_1 ; JUMP1-NEXT: je .LBB1_1
; JUMP1-NEXT: # %bb.2: # %cond_true ; JUMP1-NEXT: # %bb.2: # %cond_true
; JUMP1-NEXT: jmp bar@PLT # TAILCALL ; JUMP1-NEXT: jmp bar@PLT # TAILCALL
; JUMP1-NEXT: .LBB1_1: # %UnifiedReturnBlock ; JUMP1-NEXT: .LBB1_1: # %UnifiedReturnBlock
; JUMP1-NEXT: retl ; JUMP1-NEXT: retl
entry: entry:
%tmp1 = icmp eq i32 %X, 0 %tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5 %tmp3 = icmp slt i32 %Y, 5
%tmp4 = or i1 %tmp3, %tmp1 %tmp4 = or i1 %tmp3, %tmp1
Show All 14 Lines

llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll

Show First 20 Lines • Show All 209 Lines • ▼ Show 20 Lines
; CHECK32-NEXT: pushl %esi ; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: pushl %eax ; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ebx ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ebx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: lock cmpxchg8b (%esi) ; CHECK32-NEXT: lock cmpxchg8b (%esi)
; CHECK32-NEXT: setne %bl ; CHECK32-NEXT: sete %bl
; CHECK32-NEXT: subl $8, %esp ; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: pushl %edx ; CHECK32-NEXT: pushl %edx
; CHECK32-NEXT: pushl %eax ; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: calll bar@PLT ; CHECK32-NEXT: calll bar@PLT
; CHECK32-NEXT: addl $16, %esp ; CHECK32-NEXT: addl $16, %esp
; CHECK32-NEXT: testb %bl, %bl ; CHECK32-NEXT: testb %bl, %bl
; CHECK32-NEXT: jne .LBB4_3 ; CHECK32-NEXT: je .LBB4_3
; CHECK32-NEXT: # %bb.1: # %t ; CHECK32-NEXT: # %bb.1: # %t
; CHECK32-NEXT: movl $42, %eax ; CHECK32-NEXT: movl $42, %eax
; CHECK32-NEXT: jmp .LBB4_2 ; CHECK32-NEXT: jmp .LBB4_2
; CHECK32-NEXT: .LBB4_3: # %f ; CHECK32-NEXT: .LBB4_3: # %f
; CHECK32-NEXT: xorl %eax, %eax ; CHECK32-NEXT: xorl %eax, %eax
; CHECK32-NEXT: .LBB4_2: # %t ; CHECK32-NEXT: .LBB4_2: # %t
; CHECK32-NEXT: xorl %edx, %edx ; CHECK32-NEXT: xorl %edx, %edx
; CHECK32-NEXT: addl $4, %esp ; CHECK32-NEXT: addl $4, %esp
; CHECK32-NEXT: popl %esi ; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: popl %ebx ; CHECK32-NEXT: popl %ebx
; CHECK32-NEXT: retl ; CHECK32-NEXT: retl
; ;
; CHECK64-LABEL: test_intervening_call: ; CHECK64-LABEL: test_intervening_call:
; CHECK64: # %bb.0: # %entry ; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: pushq %rbx ; CHECK64-NEXT: pushq %rbx
; CHECK64-NEXT: movq %rsi, %rax ; CHECK64-NEXT: movq %rsi, %rax
; CHECK64-NEXT: lock cmpxchgq %rdx, (%rdi) ; CHECK64-NEXT: lock cmpxchgq %rdx, (%rdi)
; CHECK64-NEXT: setne %bl ; CHECK64-NEXT: sete %bl
; CHECK64-NEXT: movq %rax, %rdi ; CHECK64-NEXT: movq %rax, %rdi
; CHECK64-NEXT: callq bar@PLT ; CHECK64-NEXT: callq bar@PLT
; CHECK64-NEXT: testb %bl, %bl ; CHECK64-NEXT: testb %bl, %bl
; CHECK64-NEXT: jne .LBB4_2 ; CHECK64-NEXT: je .LBB4_2
; CHECK64-NEXT: # %bb.1: # %t ; CHECK64-NEXT: # %bb.1: # %t
; CHECK64-NEXT: movl $42, %eax ; CHECK64-NEXT: movl $42, %eax
; CHECK64-NEXT: popq %rbx ; CHECK64-NEXT: popq %rbx
; CHECK64-NEXT: retq ; CHECK64-NEXT: retq
; CHECK64-NEXT: .LBB4_2: # %f ; CHECK64-NEXT: .LBB4_2: # %f
; CHECK64-NEXT: xorl %eax, %eax ; CHECK64-NEXT: xorl %eax, %eax
; CHECK64-NEXT: popq %rbx ; CHECK64-NEXT: popq %rbx
; CHECK64-NEXT: retq ; CHECK64-NEXT: retq
Show All 23 Lines
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ebp ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ebp
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ebx ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ebx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: lock cmpxchg8b (%esi) ; CHECK32-NEXT: lock cmpxchg8b (%esi)
; CHECK32-NEXT: setne {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill ; CHECK32-NEXT: sete {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl %ebp, %edx ; CHECK32-NEXT: movl %ebp, %edx
; CHECK32-NEXT: movl %edi, %ecx ; CHECK32-NEXT: movl %edi, %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ebx ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ebx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: lock cmpxchg8b (%esi) ; CHECK32-NEXT: lock cmpxchg8b (%esi)
; CHECK32-NEXT: sete %al ; CHECK32-NEXT: sete %al
; CHECK32-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; CHECK32-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
; CHECK32-NEXT: jne .LBB5_4 ; CHECK32-NEXT: je .LBB5_4
; CHECK32-NEXT: # %bb.1: # %entry ; CHECK32-NEXT: # %bb.1: # %entry
; CHECK32-NEXT: testb %al, %al ; CHECK32-NEXT: testb %al, %al
; CHECK32-NEXT: je .LBB5_4 ; CHECK32-NEXT: je .LBB5_4
; CHECK32-NEXT: # %bb.2: # %t ; CHECK32-NEXT: # %bb.2: # %t
; CHECK32-NEXT: movl $42, %eax ; CHECK32-NEXT: movl $42, %eax
; CHECK32-NEXT: jmp .LBB5_3 ; CHECK32-NEXT: jmp .LBB5_3
; CHECK32-NEXT: .LBB5_4: # %f ; CHECK32-NEXT: .LBB5_4: # %f
; CHECK32-NEXT: xorl %eax, %eax ; CHECK32-NEXT: xorl %eax, %eax
; CHECK32-NEXT: .LBB5_3: # %t ; CHECK32-NEXT: .LBB5_3: # %t
; CHECK32-NEXT: xorl %edx, %edx ; CHECK32-NEXT: xorl %edx, %edx
; CHECK32-NEXT: addl $4, %esp ; CHECK32-NEXT: addl $4, %esp
; CHECK32-NEXT: popl %esi ; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: popl %edi ; CHECK32-NEXT: popl %edi
; CHECK32-NEXT: popl %ebx ; CHECK32-NEXT: popl %ebx
; CHECK32-NEXT: popl %ebp ; CHECK32-NEXT: popl %ebp
; CHECK32-NEXT: retl ; CHECK32-NEXT: retl
; ;
; CHECK64-LABEL: test_two_live_flags: ; CHECK64-LABEL: test_two_live_flags:
; CHECK64: # %bb.0: # %entry ; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: movq %rsi, %rax ; CHECK64-NEXT: movq %rsi, %rax
; CHECK64-NEXT: lock cmpxchgq %rdx, (%rdi) ; CHECK64-NEXT: lock cmpxchgq %rdx, (%rdi)
; CHECK64-NEXT: setne %dl ; CHECK64-NEXT: sete %dl
; CHECK64-NEXT: movq %r8, %rax ; CHECK64-NEXT: movq %r8, %rax
; CHECK64-NEXT: lock cmpxchgq %r9, (%rcx) ; CHECK64-NEXT: lock cmpxchgq %r9, (%rcx)
; CHECK64-NEXT: sete %al ; CHECK64-NEXT: sete %al
; CHECK64-NEXT: testb %dl, %dl ; CHECK64-NEXT: testb %dl, %dl
; CHECK64-NEXT: jne .LBB5_3 ; CHECK64-NEXT: je .LBB5_3
; CHECK64-NEXT: # %bb.1: # %entry ; CHECK64-NEXT: # %bb.1: # %entry
; CHECK64-NEXT: testb %al, %al ; CHECK64-NEXT: testb %al, %al
; CHECK64-NEXT: je .LBB5_3 ; CHECK64-NEXT: je .LBB5_3
; CHECK64-NEXT: # %bb.2: # %t ; CHECK64-NEXT: # %bb.2: # %t
; CHECK64-NEXT: movl $42, %eax ; CHECK64-NEXT: movl $42, %eax
; CHECK64-NEXT: retq ; CHECK64-NEXT: retq
; CHECK64-NEXT: .LBB5_3: # %f ; CHECK64-NEXT: .LBB5_3: # %f
; CHECK64-NEXT: xorl %eax, %eax ; CHECK64-NEXT: xorl %eax, %eax
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/pr29170.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
target triple = "i386-unknown-linux-gnu" target triple = "i386-unknown-linux-gnu"
@b = global i16 0, align 4 @b = global i16 0, align 4
define i32 @main() { define i32 @main() {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_3 ; CHECK-NEXT: je .LBB0_3
; CHECK-NEXT: # %bb.1: # %go ; CHECK-NEXT: # %bb.1: # %go
; CHECK-NEXT: movl $-1, %ecx ; CHECK-NEXT: movl $-1, %ecx
; CHECK-NEXT: movsbl b, %edx ; CHECK-NEXT: movsbl b, %edx
; CHECK-NEXT: notl %ecx ; CHECK-NEXT: notl %ecx
; CHECK-NEXT: movzwl %dx, %edx ; CHECK-NEXT: movzwl %dx, %edx
; CHECK-NEXT: cmpl $-1, %edx ; CHECK-NEXT: cmpl $-1, %edx
; CHECK-NEXT: sbbl %ecx, %eax ; CHECK-NEXT: sbbl %ecx, %eax
; CHECK-NEXT: jge .LBB0_3 ; CHECK-NEXT: jge .LBB0_3
; CHECK-NEXT: # %bb.2: # %if.then ; CHECK-NEXT: # %bb.2: # %if.then
; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_3: # %if.else ; CHECK-NEXT: .LBB0_3: # %if.else
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%true = icmp eq i32 0, 0
%const = bitcast i64 -4294967296 to i64 %const = bitcast i64 -4294967296 to i64
br i1 %true, label %go, label %if.else br i1 undef, label %go, label %if.else
go: go:
%b = load i16, i16* @b, align 4 %b = load i16, i16* @b, align 4
%sext = shl i16 %b, 8 %sext = shl i16 %b, 8
%conv = ashr i16 %sext, 8 %conv = ashr i16 %sext, 8
%neg4 = xor i64 %const, -1 %neg4 = xor i64 %const, -1
%conv5 = zext i16 %conv to i64 %conv5 = zext i16 %conv to i64
%cmp = icmp slt i64 %conv5, %neg4 %cmp = icmp slt i64 %conv5, %neg4
Show All 9 Lines

llvm/test/CodeGen/X86/pr36602.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
define i32 @fn2() { define i32 @fn2() {
; CHECK-LABEL: fn2: ; CHECK-LABEL: fn2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_2: # %bb2 ; CHECK-NEXT: .LBB0_2: # %bb2
; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%_tmp10 = icmp eq i8 0, 0 %_tmp10 = icmp eq i8 0, 0
%_tmp13 = icmp slt i8 undef, 1 %_tmp13 = icmp slt i8 undef, 1
Show All 12 Lines

llvm/test/CodeGen/X86/pr38217.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
@_ZL11DIGIT_TABLE = dso_local constant [201 x i8] c"00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899\00", align 16 @_ZL11DIGIT_TABLE = dso_local constant [201 x i8] c"00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899\00", align 16
define dso_local void @_Z12d2s_bufferedmPc(i64, i8* nocapture) { define dso_local void @_Z12d2s_bufferedmPc(i64, i8* nocapture) {
; CHECK-LABEL: _Z12d2s_bufferedmPc: ; CHECK-LABEL: _Z12d2s_bufferedmPc:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpq $10000, %rdi # imm = 0x2710 ; CHECK-NEXT: cmpq $9999, %rdi # imm = 0x270F
; CHECK-NEXT: jb .LBB0_3 ; CHECK-NEXT: jbe .LBB0_3
; CHECK-NEXT: # %bb.1: # %.preheader ; CHECK-NEXT: # %bb.1: # %.preheader
; CHECK-NEXT: movq %rdi, %r9 ; CHECK-NEXT: movq %rdi, %r9
; CHECK-NEXT: xorl %r10d, %r10d ; CHECK-NEXT: xorl %r10d, %r10d
; CHECK-NEXT: movabsq $3777893186295716171, %r8 # imm = 0x346DC5D63886594B ; CHECK-NEXT: movabsq $3777893186295716171, %r8 # imm = 0x346DC5D63886594B
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_2: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: .LBB0_2: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movq %r9, %rax ; CHECK-NEXT: movq %r9, %rax
; CHECK-NEXT: mulq %r8 ; CHECK-NEXT: mulq %r8
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/pr38795.ll

Show All 39 Lines
; CHECK-NEXT: # =>This Loop Header: Depth=1 ; CHECK-NEXT: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB0_20 Depth 2 ; CHECK-NEXT: # Child Loop BB0_20 Depth 2
; CHECK-NEXT: cmpb $8, %dl ; CHECK-NEXT: cmpb $8, %dl
; CHECK-NEXT: movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill ; CHECK-NEXT: movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
; CHECK-NEXT: ja .LBB0_3 ; CHECK-NEXT: ja .LBB0_3
; CHECK-NEXT: # %bb.2: # %for.cond ; CHECK-NEXT: # %bb.2: # %for.cond
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: testb %bl, %bl ; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: je .LBB0_3 ; CHECK-NEXT: jne .LBB0_3
; CHECK-NEXT: # %bb.4: # %if.end ; CHECK-NEXT: # %bb.4: # %if.end
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: cltd ; CHECK-NEXT: cltd
; CHECK-NEXT: idivl a ; CHECK-NEXT: idivl a
; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dl # 1-byte Reload ; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dl # 1-byte Reload
; CHECK-NEXT: movb %cl, %dh ; CHECK-NEXT: movb %cl, %dh
; CHECK-NEXT: movl $0, h ; CHECK-NEXT: movl $0, h
; CHECK-NEXT: cmpb $8, %dl ; CHECK-NEXT: cmpb $9, %dl
; CHECK-NEXT: jg .LBB0_8 ; CHECK-NEXT: jge .LBB0_8
; CHECK-NEXT: # %bb.5: # %if.then13 ; CHECK-NEXT: # %bb.5: # %if.then13
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: movl %eax, %esi ; CHECK-NEXT: movl %eax, %esi
; CHECK-NEXT: movl $.str, (%esp) ; CHECK-NEXT: movl $.str, (%esp)
; CHECK-NEXT: movb %dh, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill ; CHECK-NEXT: movb %dh, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
; CHECK-NEXT: calll printf ; CHECK-NEXT: calll printf
; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dh # 1-byte Reload ; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dh # 1-byte Reload
; CHECK-NEXT: testb %bl, %bl ; CHECK-NEXT: testb %bl, %bl
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; CHECK-NEXT: # implicit-def: $eax ; CHECK-NEXT: # implicit-def: $eax
; CHECK-NEXT: .LBB0_6: # %for.cond35 ; CHECK-NEXT: .LBB0_6: # %for.cond35
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: testl %edi, %edi ; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: je .LBB0_7 ; CHECK-NEXT: je .LBB0_7
; CHECK-NEXT: .LBB0_11: # %af ; CHECK-NEXT: .LBB0_11: # %af
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: testb %bl, %bl ; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: jne .LBB0_12 ; CHECK-NEXT: je .LBB0_12
; CHECK-NEXT: .LBB0_17: # %if.end39 ; CHECK-NEXT: .LBB0_17: # %if.end39
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: testl %eax, %eax ; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: je .LBB0_19 ; CHECK-NEXT: je .LBB0_19
; CHECK-NEXT: # %bb.18: # %if.then41 ; CHECK-NEXT: # %bb.18: # %if.then41
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $fn, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $fn, {{[0-9]+}}(%esp)
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; CHECK-NEXT: jne .LBB0_20 ; CHECK-NEXT: jne .LBB0_20
; CHECK-NEXT: # %bb.21: # %for.cond47 ; CHECK-NEXT: # %bb.21: # %for.cond47
; CHECK-NEXT: # in Loop: Header=BB0_20 Depth=2 ; CHECK-NEXT: # in Loop: Header=BB0_20 Depth=2
; CHECK-NEXT: testb %bl, %bl ; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: jne .LBB0_20 ; CHECK-NEXT: jne .LBB0_20
; CHECK-NEXT: .LBB0_9: # %ae ; CHECK-NEXT: .LBB0_9: # %ae
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: testb %bl, %bl ; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: jne .LBB0_10 ; CHECK-NEXT: je .LBB0_10
; CHECK-NEXT: # %bb.13: # %if.end26 ; CHECK-NEXT: # %bb.13: # %if.end26
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testb %dl, %dl ; CHECK-NEXT: testb %dl, %dl
; CHECK-NEXT: je .LBB0_16 ; CHECK-NEXT: je .LBB0_16
; CHECK-NEXT: # %bb.14: # %if.end26 ; CHECK-NEXT: # %bb.14: # %if.end26
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: testl %ebp, %ebp ; CHECK-NEXT: testl %ebp, %ebp
; CHECK-NEXT: jne .LBB0_16 ; CHECK-NEXT: jne .LBB0_16
; CHECK-NEXT: # %bb.15: # %if.then31 ; CHECK-NEXT: # %bb.15: # %if.then31
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %ebp, %ebp ; CHECK-NEXT: xorl %ebp, %ebp
; CHECK-NEXT: jmp .LBB0_16 ; CHECK-NEXT: jmp .LBB0_16
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_10: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: .LBB0_10: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: # implicit-def: $eax ; CHECK-NEXT: # implicit-def: $eax
; CHECK-NEXT: testb %bl, %bl ; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: je .LBB0_17 ; CHECK-NEXT: jne .LBB0_17
; CHECK-NEXT: .LBB0_12: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: .LBB0_12: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: # implicit-def: $edi ; CHECK-NEXT: # implicit-def: $edi
; CHECK-NEXT: # implicit-def: $cl ; CHECK-NEXT: # implicit-def: $cl
; CHECK-NEXT: # kill: killed $cl ; CHECK-NEXT: # kill: killed $cl
; CHECK-NEXT: # implicit-def: $dl ; CHECK-NEXT: # implicit-def: $dl
; CHECK-NEXT: # implicit-def: $ebp ; CHECK-NEXT: # implicit-def: $ebp
; CHECK-NEXT: testl %edi, %edi ; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: jne .LBB0_11 ; CHECK-NEXT: jne .LBB0_11
▲ Show 20 Lines • Show All 106 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/pr46585.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s
@global = external local_unnamed_addr global i8 @global = external local_unnamed_addr global i8
@global.1 = external local_unnamed_addr global i64 @global.1 = external local_unnamed_addr global i64
define void @spam() local_unnamed_addr { define void @spam() local_unnamed_addr {
; CHECK-LABEL: spam: ; CHECK-LABEL: spam:
; CHECK: ## %bb.0: ## %bb ; CHECK: ## %bb.0: ## %bb
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je LBB0_2 ; CHECK-NEXT: jne LBB0_2
; CHECK-NEXT: ## %bb.1: ## %bb9 ; CHECK-NEXT: ## %bb.1: ## %bb9
; CHECK-NEXT: movq _global.1@GOTPCREL(%rip), %rax ; CHECK-NEXT: movq _global.1@GOTPCREL(%rip), %rax
; CHECK-NEXT: movq $1, (%rax) ; CHECK-NEXT: movq $1, (%rax)
; CHECK-NEXT: LBB0_2: ## %bb8 ; CHECK-NEXT: LBB0_2: ## %bb8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
bb: bb:
%tmp = load i8, i8* @global, align 1 %tmp = load i8, i8* @global, align 1
%tmp1 = and i8 %tmp, 1 %tmp1 = and i8 %tmp, 1
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llvm/test/CodeGen/X86/pr46827.ll

Show All 14 Lines
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $eflags ; CHECK: liveins: $eflags
; CHECK: XABORT_DEF implicit-def $eax ; CHECK: XABORT_DEF implicit-def $eax
; CHECK: %4:gr32 = COPY $eax ; CHECK: %4:gr32 = COPY $eax
; CHECK: bb.5.bb107: ; CHECK: bb.5.bb107:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $eflags ; CHECK: liveins: $eflags
; CHECK: %2:gr32 = PHI %3, %bb.3, %4, %bb.4 ; CHECK: %2:gr32 = PHI %3, %bb.3, %4, %bb.4
; CHECK: JCC_1 %bb.2, 5, implicit $eflags ; CHECK: JCC_1 %bb.1, 4, implicit $eflags
; CHECK: JMP_1 %bb.1 ; CHECK: JMP_1 %bb.2
declare i32 @llvm.x86.xbegin() #0 declare i32 @llvm.x86.xbegin() #0
define void @wobble.12(i32 %tmp116) { define void @wobble.12(i32 %tmp116) {
bb107: ; preds = %bb42 bb107: ; preds = %bb42
%tmp117 = icmp eq i32 %tmp116, 1 %tmp117 = icmp eq i32 %tmp116, 1
%tmp127 = tail call i32 @llvm.x86.xbegin() #0 %tmp127 = tail call i32 @llvm.x86.xbegin() #0
br i1 %tmp117, label %bb129, label %bb250 br i1 %tmp117, label %bb129, label %bb250
bb129: ; preds = %bb107 bb129: ; preds = %bb107
unreachable unreachable
bb250: ; preds = %bb107 bb250: ; preds = %bb107
unreachable unreachable
} }

llvm/test/CodeGen/X86/pr50254.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
@d.e = external dso_local unnamed_addr global i32, align 4 @d.e = external dso_local unnamed_addr global i32, align 4
define void @PR50254() { define void @PR50254() {
; X86-LABEL: PR50254: ; X86-LABEL: PR50254:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: movswl d.e, %eax ; X86-NEXT: movswl d.e, %eax
; X86-NEXT: xorl %ecx, %ecx ; X86-NEXT: xorl %ecx, %ecx
; X86-NEXT: testb %cl, %cl ; X86-NEXT: testb %cl, %cl
; X86-NEXT: jne .LBB0_2 ; X86-NEXT: je .LBB0_2
; X86-NEXT: # %bb.1: # %for.end ; X86-NEXT: # %bb.1: # %for.end
; X86-NEXT: movw %ax, d.e ; X86-NEXT: movw %ax, d.e
; X86-NEXT: .LBB0_2: # %for.body.1 ; X86-NEXT: .LBB0_2: # %for.body.1
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: PR50254: ; X64-LABEL: PR50254:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: movswq d.e(%rip), %rax ; X64-NEXT: movswq d.e(%rip), %rax
; X64-NEXT: xorl %ecx, %ecx ; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: testb %cl, %cl ; X64-NEXT: testb %cl, %cl
; X64-NEXT: jne .LBB0_2 ; X64-NEXT: je .LBB0_2
; X64-NEXT: # %bb.1: # %for.end ; X64-NEXT: # %bb.1: # %for.end
; X64-NEXT: movw %ax, d.e(%rip) ; X64-NEXT: movw %ax, d.e(%rip)
; X64-NEXT: .LBB0_2: # %for.body.1 ; X64-NEXT: .LBB0_2: # %for.body.1
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%load = load i16, i16* bitcast (i32* @d.e to i16*), align 4 %load = load i16, i16* bitcast (i32* @d.e to i16*), align 4
%xor1 = xor i16 %load, 0 %xor1 = xor i16 %load, 0
%xor2 = xor i64 undef, 3821908120 %xor2 = xor i64 undef, 3821908120
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llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll

Show All 36 Lines
; CHECK-NEXT: .cfi_offset %r14, -32 ; CHECK-NEXT: .cfi_offset %r14, -32
; CHECK-NEXT: .cfi_offset %r15, -24 ; CHECK-NEXT: .cfi_offset %r15, -24
; CHECK-NEXT: .cfi_offset %rbp, -16 ; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: testq $-3, %rdx ; CHECK-NEXT: testq $-3, %rdx
; CHECK-NEXT: jne LBB0_4 ; CHECK-NEXT: jne LBB0_4
; CHECK-NEXT: ## %bb.1: ## %if.end ; CHECK-NEXT: ## %bb.1: ## %if.end
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne LBB0_5 ; CHECK-NEXT: je LBB0_5
; CHECK-NEXT: ## %bb.2: ## %if.then4 ; CHECK-NEXT: ## %bb.2: ## %if.then4
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je LBB0_55 ; CHECK-NEXT: je LBB0_55
; CHECK-NEXT: ## %bb.3: ## %SyTime.exit ; CHECK-NEXT: ## %bb.3: ## %SyTime.exit
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je LBB0_55 ; CHECK-NEXT: je LBB0_55
Show All 34 Lines
; CHECK-NEXT: movl $0, (%rax) ; CHECK-NEXT: movl $0, (%rax)
; CHECK-NEXT: testb %cl, %cl ; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: jne LBB0_9 ; CHECK-NEXT: jne LBB0_9
; CHECK-NEXT: ## %bb.10: ## %do.end ; CHECK-NEXT: ## %bb.10: ## %do.end
; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill ; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
; CHECK-NEXT: movq %rbp, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill ; CHECK-NEXT: movq %rbp, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
; CHECK-NEXT: xorl %r12d, %r12d ; CHECK-NEXT: xorl %r12d, %r12d
; CHECK-NEXT: testb %r12b, %r12b ; CHECK-NEXT: testb %r12b, %r12b
; CHECK-NEXT: jne LBB0_11 ; CHECK-NEXT: je LBB0_11
; CHECK-NEXT: ## %bb.12: ## %while.body200.preheader ; CHECK-NEXT: ## %bb.12: ## %while.body200.preheader
; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: leaq LJTI0_0(%rip), %rdx ; CHECK-NEXT: leaq LJTI0_0(%rip), %rdx
; CHECK-NEXT: leaq LJTI0_1(%rip), %r13 ; CHECK-NEXT: leaq LJTI0_1(%rip), %r13
; CHECK-NEXT: movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill ; CHECK-NEXT: movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill
; CHECK-NEXT: xorl %r14d, %r14d ; CHECK-NEXT: xorl %r14d, %r14d
; CHECK-NEXT: jmp LBB0_13 ; CHECK-NEXT: jmp LBB0_13
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: ## implicit-def: $rax ; CHECK-NEXT: ## implicit-def: $rax
; CHECK-NEXT: jmp LBB0_29 ; CHECK-NEXT: jmp LBB0_29
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_32: ## %do.body479.backedge ; CHECK-NEXT: LBB0_32: ## %do.body479.backedge
; CHECK-NEXT: ## in Loop: Header=BB0_29 Depth=2 ; CHECK-NEXT: ## in Loop: Header=BB0_29 Depth=2
; CHECK-NEXT: leaq 1(%rbp), %rax ; CHECK-NEXT: leaq 1(%rbp), %rax
; CHECK-NEXT: testb %bl, %bl ; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: je LBB0_33 ; CHECK-NEXT: jne LBB0_33
; CHECK-NEXT: LBB0_29: ## %land.rhs485 ; CHECK-NEXT: LBB0_29: ## %land.rhs485
; CHECK-NEXT: ## Parent Loop BB0_13 Depth=1 ; CHECK-NEXT: ## Parent Loop BB0_13 Depth=1
; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: js LBB0_55 ; CHECK-NEXT: js LBB0_55
; CHECK-NEXT: ## %bb.30: ## %cond.true.i.i2780 ; CHECK-NEXT: ## %bb.30: ## %cond.true.i.i2780
; CHECK-NEXT: ## in Loop: Header=BB0_29 Depth=2 ; CHECK-NEXT: ## in Loop: Header=BB0_29 Depth=2
; CHECK-NEXT: movq %rax, %rbp ; CHECK-NEXT: movq %rax, %rbp
; CHECK-NEXT: testb %bl, %bl ; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: jne LBB0_32 ; CHECK-NEXT: jne LBB0_32
; CHECK-NEXT: ## %bb.31: ## %lor.rhs500 ; CHECK-NEXT: ## %bb.31: ## %lor.rhs500
; CHECK-NEXT: ## in Loop: Header=BB0_29 Depth=2 ; CHECK-NEXT: ## in Loop: Header=BB0_29 Depth=2
; CHECK-NEXT: movl $256, %esi ## imm = 0x100 ; CHECK-NEXT: movl $256, %esi ## imm = 0x100
; CHECK-NEXT: callq ___maskrune ; CHECK-NEXT: callq ___maskrune
; CHECK-NEXT: testb %bl, %bl ; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: jne LBB0_32 ; CHECK-NEXT: je LBB0_32
; CHECK-NEXT: jmp LBB0_34 ; CHECK-NEXT: jmp LBB0_34
; CHECK-NEXT: LBB0_45: ## %sw.bb1134 ; CHECK-NEXT: LBB0_45: ## %sw.bb1134
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rcx ; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rcx
; CHECK-NEXT: cmpq %rax, %rcx ; CHECK-NEXT: cmpq %rax, %rcx
; CHECK-NEXT: jb LBB0_55 ; CHECK-NEXT: jb LBB0_55
; CHECK-NEXT: ## %bb.46: ## in Loop: Header=BB0_13 Depth=1 ; CHECK-NEXT: ## %bb.46: ## in Loop: Header=BB0_13 Depth=1
Show All 33 Lines
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: movq _SyFgets.yank@GOTPCREL(%rip), %rax ; CHECK-NEXT: movq _SyFgets.yank@GOTPCREL(%rip), %rax
; CHECK-NEXT: movb $0, (%rax) ; CHECK-NEXT: movb $0, (%rax)
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_38: ## %for.cond534 ; CHECK-NEXT: LBB0_38: ## %for.cond534
; CHECK-NEXT: ## Parent Loop BB0_13 Depth=1 ; CHECK-NEXT: ## Parent Loop BB0_13 Depth=1
; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2
; CHECK-NEXT: testb %bl, %bl ; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: jne LBB0_38 ; CHECK-NEXT: je LBB0_38
; CHECK-NEXT: ## %bb.39: ## %for.cond542.preheader ; CHECK-NEXT: ## %bb.39: ## %for.cond542.preheader
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: testb %bl, %bl ; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: movb $0, (%rbp) ; CHECK-NEXT: movb $0, (%rbp)
; CHECK-NEXT: movl %r12d, %r14d ; CHECK-NEXT: movl %r12d, %r14d
; CHECK-NEXT: leaq LJTI0_0(%rip), %rdx ; CHECK-NEXT: leaq LJTI0_0(%rip), %rdx
; CHECK-NEXT: jmp LBB0_21 ; CHECK-NEXT: jmp LBB0_21
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movl $512, %eax ## imm = 0x200 ; CHECK-NEXT: movl $512, %eax ## imm = 0x200
; CHECK-NEXT: cmpq %rax, %rax ; CHECK-NEXT: cmpq %rax, %rax
; CHECK-NEXT: jae LBB0_55 ; CHECK-NEXT: jae LBB0_55
; CHECK-NEXT: ## %bb.51: ## %for.body1664.lr.ph ; CHECK-NEXT: ## %bb.51: ## %for.body1664.lr.ph
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx ## 8-byte Reload ; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx ## 8-byte Reload
; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ebp ## 4-byte Reload ; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ebp ## 4-byte Reload
; CHECK-NEXT: jne LBB0_54 ; CHECK-NEXT: je LBB0_54
; CHECK-NEXT: ## %bb.52: ## %while.body1679.preheader ; CHECK-NEXT: ## %bb.52: ## %while.body1679.preheader
; CHECK-NEXT: incl %ebp ; CHECK-NEXT: incl %ebp
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_53: ## %while.body1679 ; CHECK-NEXT: LBB0_53: ## %while.body1679
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movq (%rbx), %rdi ; CHECK-NEXT: movq (%rbx), %rdi
; CHECK-NEXT: callq _fileno ; CHECK-NEXT: callq _fileno
; CHECK-NEXT: movslq %ebp, %rax ; CHECK-NEXT: movslq %ebp, %rax
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llvm/test/CodeGen/X86/reverse_branches.ll

Show All 38 Lines
; CHECK-NEXT: jmp LBB0_1 ; CHECK-NEXT: jmp LBB0_1
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_6: ## %for.inc9 ; CHECK-NEXT: LBB0_6: ## %for.inc9
; CHECK-NEXT: ## in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: incl %r12d ; CHECK-NEXT: incl %r12d
; CHECK-NEXT: LBB0_1: ## %for.cond ; CHECK-NEXT: LBB0_1: ## %for.cond
; CHECK-NEXT: ## =>This Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Loop Header: Depth=1
; CHECK-NEXT: ## Child Loop BB0_3 Depth 2 ; CHECK-NEXT: ## Child Loop BB0_3 Depth 2
; CHECK-NEXT: cmpl $999, %r12d ## imm = 0x3E7 ; CHECK-NEXT: cmpl $1000, %r12d ## imm = 0x3E8
; CHECK-NEXT: jg LBB0_7 ; CHECK-NEXT: jge LBB0_7
; CHECK-NEXT: ## %bb.2: ## %for.cond1.preheader ; CHECK-NEXT: ## %bb.2: ## %for.cond1.preheader
; CHECK-NEXT: ## in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: movl $-1, %ebp ; CHECK-NEXT: movl $-1, %ebp
; CHECK-NEXT: movq %r15, %rdi ; CHECK-NEXT: movq %r15, %rdi
; CHECK-NEXT: movq %r14, %rbx ; CHECK-NEXT: movq %r14, %rbx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_3: ## %for.cond1 ; CHECK-NEXT: LBB0_3: ## %for.cond1
; CHECK-NEXT: ## Parent Loop BB0_1 Depth=1 ; CHECK-NEXT: ## Parent Loop BB0_1 Depth=1
; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2
; CHECK-NEXT: incl %ebp ; CHECK-NEXT: incl %ebp
; CHECK-NEXT: cmpl $999, %ebp ## imm = 0x3E7 ; CHECK-NEXT: cmpl $1000, %ebp ## imm = 0x3E8
; CHECK-NEXT: jg LBB0_6 ; CHECK-NEXT: jge LBB0_6
; CHECK-NEXT: ## %bb.4: ## %for.body3 ; CHECK-NEXT: ## %bb.4: ## %for.body3
; CHECK-NEXT: ## in Loop: Header=BB0_3 Depth=2 ; CHECK-NEXT: ## in Loop: Header=BB0_3 Depth=2
; CHECK-NEXT: addq $1002, %rbx ## imm = 0x3EA ; CHECK-NEXT: addq $1002, %rbx ## imm = 0x3EA
; CHECK-NEXT: leaq 1001(%rdi), %r13 ; CHECK-NEXT: leaq 1001(%rdi), %r13
; CHECK-NEXT: movl $1000, %edx ## imm = 0x3E8 ; CHECK-NEXT: movl $1000, %edx ## imm = 0x3E8
; CHECK-NEXT: movl $120, %esi ; CHECK-NEXT: movl $120, %esi
; CHECK-NEXT: callq _memchr ; CHECK-NEXT: callq _memchr
; CHECK-NEXT: cmpq %rax, %rbx ; CHECK-NEXT: cmpq %rax, %rbx
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; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_15: ## %for.inc38 ; CHECK-NEXT: LBB0_15: ## %for.inc38
; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1
; CHECK-NEXT: incl %eax ; CHECK-NEXT: incl %eax
; CHECK-NEXT: LBB0_8: ## %for.cond14 ; CHECK-NEXT: LBB0_8: ## %for.cond14
; CHECK-NEXT: ## =>This Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Loop Header: Depth=1
; CHECK-NEXT: ## Child Loop BB0_10 Depth 2 ; CHECK-NEXT: ## Child Loop BB0_10 Depth 2
; CHECK-NEXT: ## Child Loop BB0_12 Depth 3 ; CHECK-NEXT: ## Child Loop BB0_12 Depth 3
; CHECK-NEXT: cmpl $999, %eax ## imm = 0x3E7 ; CHECK-NEXT: cmpl $1000, %eax ## imm = 0x3E8
; CHECK-NEXT: jg LBB0_16 ; CHECK-NEXT: jge LBB0_16
; CHECK-NEXT: ## %bb.9: ## %for.cond18.preheader ; CHECK-NEXT: ## %bb.9: ## %for.cond18.preheader
; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1 ; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1
; CHECK-NEXT: movq %rcx, %rdx ; CHECK-NEXT: movq %rcx, %rdx
; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: jmp LBB0_10 ; CHECK-NEXT: jmp LBB0_10
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_14: ## %exit ; CHECK-NEXT: LBB0_14: ## %exit
; CHECK-NEXT: ## in Loop: Header=BB0_10 Depth=2 ; CHECK-NEXT: ## in Loop: Header=BB0_10 Depth=2
; CHECK-NEXT: addq %rsi, %rbp ; CHECK-NEXT: addq %rsi, %rbp
; CHECK-NEXT: incq %rdi ; CHECK-NEXT: incq %rdi
; CHECK-NEXT: decq %rsi ; CHECK-NEXT: decq %rsi
; CHECK-NEXT: addq $1001, %rdx ## imm = 0x3E9 ; CHECK-NEXT: addq $1001, %rdx ## imm = 0x3E9
; CHECK-NEXT: cmpq $-1000, %rbp ## imm = 0xFC18 ; CHECK-NEXT: cmpq $-1000, %rbp ## imm = 0xFC18
; CHECK-NEXT: jne LBB0_5 ; CHECK-NEXT: jne LBB0_5
; CHECK-NEXT: LBB0_10: ## %for.cond18 ; CHECK-NEXT: LBB0_10: ## %for.cond18
; CHECK-NEXT: ## Parent Loop BB0_8 Depth=1 ; CHECK-NEXT: ## Parent Loop BB0_8 Depth=1
; CHECK-NEXT: ## => This Loop Header: Depth=2 ; CHECK-NEXT: ## => This Loop Header: Depth=2
; CHECK-NEXT: ## Child Loop BB0_12 Depth 3 ; CHECK-NEXT: ## Child Loop BB0_12 Depth 3
; CHECK-NEXT: cmpl $999, %edi ## imm = 0x3E7 ; CHECK-NEXT: cmpl $1000, %edi ## imm = 0x3E8
; CHECK-NEXT: jg LBB0_15 ; CHECK-NEXT: jge LBB0_15
; CHECK-NEXT: ## %bb.11: ## %for.body20 ; CHECK-NEXT: ## %bb.11: ## %for.body20
; CHECK-NEXT: ## in Loop: Header=BB0_10 Depth=2 ; CHECK-NEXT: ## in Loop: Header=BB0_10 Depth=2
; CHECK-NEXT: movq $-1000, %rbp ## imm = 0xFC18 ; CHECK-NEXT: movq $-1000, %rbp ## imm = 0xFC18
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_12: ## %do.body.i ; CHECK-NEXT: LBB0_12: ## %do.body.i
; CHECK-NEXT: ## Parent Loop BB0_8 Depth=1 ; CHECK-NEXT: ## Parent Loop BB0_8 Depth=1
; CHECK-NEXT: ## Parent Loop BB0_10 Depth=2 ; CHECK-NEXT: ## Parent Loop BB0_10 Depth=2
; CHECK-NEXT: ## => This Inner Loop Header: Depth=3 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=3
▲ Show 20 Lines • Show All 118 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/select.ll

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; GENERIC-LABEL: test2: ; GENERIC-LABEL: test2:
; GENERIC: ## %bb.0: ## %entry ; GENERIC: ## %bb.0: ## %entry
; GENERIC-NEXT: pushq %rax ; GENERIC-NEXT: pushq %rax
; GENERIC-NEXT: callq _return_false ; GENERIC-NEXT: callq _return_false
; GENERIC-NEXT: xorl %ecx, %ecx ; GENERIC-NEXT: xorl %ecx, %ecx
; GENERIC-NEXT: testb $1, %al ; GENERIC-NEXT: testb $1, %al
; GENERIC-NEXT: movl $-3840, %eax ## imm = 0xF100 ; GENERIC-NEXT: movl $-3840, %eax ## imm = 0xF100
; GENERIC-NEXT: cmovnel %ecx, %eax ; GENERIC-NEXT: cmovnel %ecx, %eax
; GENERIC-NEXT: cmpl $32768, %eax ## imm = 0x8000 ; GENERIC-NEXT: cmpl $32767, %eax ## imm = 0x7FFF
; GENERIC-NEXT: jge LBB1_1 ; GENERIC-NEXT: jg LBB1_1
; GENERIC-NEXT: ## %bb.2: ## %bb91 ; GENERIC-NEXT: ## %bb.2: ## %bb91
; GENERIC-NEXT: xorl %eax, %eax ; GENERIC-NEXT: xorl %eax, %eax
; GENERIC-NEXT: popq %rcx ; GENERIC-NEXT: popq %rcx
; GENERIC-NEXT: retq ; GENERIC-NEXT: retq
; GENERIC-NEXT: LBB1_1: ## %bb90 ; GENERIC-NEXT: LBB1_1: ## %bb90
; GENERIC-NEXT: ud2 ; GENERIC-NEXT: ud2
; ;
; ATOM-LABEL: test2: ; ATOM-LABEL: test2:
; ATOM: ## %bb.0: ## %entry ; ATOM: ## %bb.0: ## %entry
; ATOM-NEXT: pushq %rax ; ATOM-NEXT: pushq %rax
; ATOM-NEXT: callq _return_false ; ATOM-NEXT: callq _return_false
; ATOM-NEXT: xorl %ecx, %ecx ; ATOM-NEXT: xorl %ecx, %ecx
; ATOM-NEXT: movl $-3840, %edx ## imm = 0xF100 ; ATOM-NEXT: movl $-3840, %edx ## imm = 0xF100
; ATOM-NEXT: testb $1, %al ; ATOM-NEXT: testb $1, %al
; ATOM-NEXT: cmovnel %ecx, %edx ; ATOM-NEXT: cmovnel %ecx, %edx
; ATOM-NEXT: cmpl $32768, %edx ## imm = 0x8000 ; ATOM-NEXT: cmpl $32767, %edx ## imm = 0x7FFF
; ATOM-NEXT: jge LBB1_1 ; ATOM-NEXT: jg LBB1_1
; ATOM-NEXT: ## %bb.2: ## %bb91 ; ATOM-NEXT: ## %bb.2: ## %bb91
; ATOM-NEXT: xorl %eax, %eax ; ATOM-NEXT: xorl %eax, %eax
; ATOM-NEXT: popq %rcx ; ATOM-NEXT: popq %rcx
; ATOM-NEXT: retq ; ATOM-NEXT: retq
; ATOM-NEXT: LBB1_1: ## %bb90 ; ATOM-NEXT: LBB1_1: ## %bb90
; ATOM-NEXT: ud2 ; ATOM-NEXT: ud2
; ;
; ATHLON-LABEL: test2: ; ATHLON-LABEL: test2:
; ATHLON: ## %bb.0: ## %entry ; ATHLON: ## %bb.0: ## %entry
; ATHLON-NEXT: subl $12, %esp ; ATHLON-NEXT: subl $12, %esp
; ATHLON-NEXT: calll _return_false ; ATHLON-NEXT: calll _return_false
; ATHLON-NEXT: xorl %ecx, %ecx ; ATHLON-NEXT: xorl %ecx, %ecx
; ATHLON-NEXT: testb $1, %al ; ATHLON-NEXT: testb $1, %al
; ATHLON-NEXT: movl $-3840, %eax ## imm = 0xF100 ; ATHLON-NEXT: movl $-3840, %eax ## imm = 0xF100
; ATHLON-NEXT: cmovnel %ecx, %eax ; ATHLON-NEXT: cmovnel %ecx, %eax
; ATHLON-NEXT: cmpl $32768, %eax ## imm = 0x8000 ; ATHLON-NEXT: cmpl $32767, %eax ## imm = 0x7FFF
; ATHLON-NEXT: jge LBB1_1 ; ATHLON-NEXT: jg LBB1_1
; ATHLON-NEXT: ## %bb.2: ## %bb91 ; ATHLON-NEXT: ## %bb.2: ## %bb91
; ATHLON-NEXT: xorl %eax, %eax ; ATHLON-NEXT: xorl %eax, %eax
; ATHLON-NEXT: addl $12, %esp ; ATHLON-NEXT: addl $12, %esp
; ATHLON-NEXT: retl ; ATHLON-NEXT: retl
; ATHLON-NEXT: LBB1_1: ## %bb90 ; ATHLON-NEXT: LBB1_1: ## %bb90
; ATHLON-NEXT: ud2 ; ATHLON-NEXT: ud2
; ;
; MCU-LABEL: test2: ; MCU-LABEL: test2:
; MCU: # %bb.0: # %entry ; MCU: # %bb.0: # %entry
; MCU-NEXT: calll return_false@PLT ; MCU-NEXT: calll return_false@PLT
; MCU-NEXT: xorl %ecx, %ecx ; MCU-NEXT: xorl %ecx, %ecx
; MCU-NEXT: testb $1, %al ; MCU-NEXT: testb $1, %al
; MCU-NEXT: jne .LBB1_2 ; MCU-NEXT: jne .LBB1_2
; MCU-NEXT: # %bb.1: # %entry ; MCU-NEXT: # %bb.1: # %entry
; MCU-NEXT: movl $-3840, %ecx # imm = 0xF100 ; MCU-NEXT: movl $-3840, %ecx # imm = 0xF100
; MCU-NEXT: .LBB1_2: # %entry ; MCU-NEXT: .LBB1_2: # %entry
; MCU-NEXT: cmpl $32768, %ecx # imm = 0x8000 ; MCU-NEXT: cmpl $32767, %ecx # imm = 0x7FFF
; MCU-NEXT: jge .LBB1_3 ; MCU-NEXT: jg .LBB1_3
; MCU-NEXT: # %bb.4: # %bb91 ; MCU-NEXT: # %bb.4: # %bb91
; MCU-NEXT: xorl %eax, %eax ; MCU-NEXT: xorl %eax, %eax
; MCU-NEXT: retl ; MCU-NEXT: retl
; MCU-NEXT: .LBB1_3: # %bb90 ; MCU-NEXT: .LBB1_3: # %bb90
entry: entry:
%tmp73 = tail call i1 @return_false() %tmp73 = tail call i1 @return_false()
%g.0 = select i1 %tmp73, i16 0, i16 -480 %g.0 = select i1 %tmp73, i16 0, i16 -480
%tmp7778 = sext i16 %g.0 to i32 %tmp7778 = sext i16 %g.0 to i32
▲ Show 20 Lines • Show All 1,571 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/setcc-freeze.ll

Show All 20 LinesA:
ret i32 10 ret i32 10
B: B:
ret i32 20 ret i32 20
} }
define i32 @f_false(i16* %p) { define i32 @f_false(i16* %p) {
; CHECK-LABEL: f_false: ; CHECK-LABEL: f_false:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB1_2 ; CHECK-NEXT: je .LBB1_2
; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: # %bb.1: # %A
; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: movl $10, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: .LBB1_2: # %B ; CHECK-NEXT: .LBB1_2: # %B
; CHECK-NEXT: movl $20, %eax ; CHECK-NEXT: movl $20, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%v = load i16, i16* %p, align 2 %v = load i16, i16* %p, align 2
%and = and i16 %v, 2048 %and = and i16 %v, 2048
%cond = icmp ult i16 %and, 0 %cond = icmp ult i16 %and, 0
%cond.fr = freeze i1 %cond %cond.fr = freeze i1 %cond
br i1 %cond.fr, label %A, label %B br i1 %cond.fr, label %A, label %B
A: A:
ret i32 10 ret i32 10
B: B:
ret i32 20 ret i32 20
} }
define i32 @f_false2(i16* %p) { define i32 @f_false2(i16* %p) {
; CHECK-LABEL: f_false2: ; CHECK-LABEL: f_false2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB2_2 ; CHECK-NEXT: je .LBB2_2
; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: # %bb.1: # %A
; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: movl $10, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: .LBB2_2: # %B ; CHECK-NEXT: .LBB2_2: # %B
; CHECK-NEXT: movl $20, %eax ; CHECK-NEXT: movl $20, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%v = load i16, i16* %p, align 2 %v = load i16, i16* %p, align 2
%and = and i16 %v, 2048 %and = and i16 %v, 2048
%cond = icmp ult i16 65535, %and %cond = icmp ult i16 65535, %and
%cond.fr = freeze i1 %cond %cond.fr = freeze i1 %cond
br i1 %cond.fr, label %A, label %B br i1 %cond.fr, label %A, label %B
A: A:
ret i32 10 ret i32 10
B: B:
ret i32 20 ret i32 20
} }
define i32 @f_false3(i16* %p) { define i32 @f_false3(i16* %p) {
; CHECK-LABEL: f_false3: ; CHECK-LABEL: f_false3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB3_2 ; CHECK-NEXT: je .LBB3_2
; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: # %bb.1: # %A
; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: movl $10, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: .LBB3_2: # %B ; CHECK-NEXT: .LBB3_2: # %B
; CHECK-NEXT: movl $20, %eax ; CHECK-NEXT: movl $20, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%v = load i16, i16* %p, align 2 %v = load i16, i16* %p, align 2
%and = and i16 %v, 2048 %and = and i16 %v, 2048
%cond = icmp slt i16 32767, %and %cond = icmp slt i16 32767, %and
%cond.fr = freeze i1 %cond %cond.fr = freeze i1 %cond
br i1 %cond.fr, label %A, label %B br i1 %cond.fr, label %A, label %B
A: A:
ret i32 10 ret i32 10
B: B:
ret i32 20 ret i32 20
} }
define i32 @f_false4(i16* %p) { define i32 @f_false4(i16* %p) {
; CHECK-LABEL: f_false4: ; CHECK-LABEL: f_false4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB4_2 ; CHECK-NEXT: je .LBB4_2
; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: # %bb.1: # %A
; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: movl $10, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: .LBB4_2: # %B ; CHECK-NEXT: .LBB4_2: # %B
; CHECK-NEXT: movl $20, %eax ; CHECK-NEXT: movl $20, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%v = load i16, i16* %p, align 2 %v = load i16, i16* %p, align 2
%and = and i16 %v, 2048 %and = and i16 %v, 2048
%cond = icmp sgt i16 %and, 32767 %cond = icmp sgt i16 %and, 32767
%cond.fr = freeze i1 %cond %cond.fr = freeze i1 %cond
br i1 %cond.fr, label %A, label %B br i1 %cond.fr, label %A, label %B
A: A:
ret i32 10 ret i32 10
B: B:
ret i32 20 ret i32 20
} }
define i32 @f_true(i16* %p) { define i32 @f_true(i16* %p) {
; CHECK-LABEL: f_true: ; CHECK-LABEL: f_true:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB5_2 ; CHECK-NEXT: je .LBB5_2
; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: # %bb.1: # %A
; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: movl $10, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: .LBB5_2: # %B ; CHECK-NEXT: .LBB5_2: # %B
; CHECK-NEXT: movl $20, %eax ; CHECK-NEXT: movl $20, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%v = load i16, i16* %p, align 2 %v = load i16, i16* %p, align 2
%and = and i16 %v, 2048 %and = and i16 %v, 2048
%cond = icmp sge i16 %and, -32768 %cond = icmp sge i16 %and, -32768
%cond.fr = freeze i1 %cond %cond.fr = freeze i1 %cond
br i1 %cond.fr, label %A, label %B br i1 %cond.fr, label %A, label %B
A: A:
ret i32 10 ret i32 10
B: B:
ret i32 20 ret i32 20
} }
define i32 @f_true2(i16* %p) { define i32 @f_true2(i16* %p) {
; CHECK-LABEL: f_true2: ; CHECK-LABEL: f_true2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB6_2 ; CHECK-NEXT: je .LBB6_2
; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: # %bb.1: # %A
; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: movl $10, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: .LBB6_2: # %B ; CHECK-NEXT: .LBB6_2: # %B
; CHECK-NEXT: movl $20, %eax ; CHECK-NEXT: movl $20, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%v = load i16, i16* %p, align 2 %v = load i16, i16* %p, align 2
%and = and i16 %v, 2048 %and = and i16 %v, 2048
%cond = icmp uge i16 %and, 0 %cond = icmp uge i16 %and, 0
%cond.fr = freeze i1 %cond %cond.fr = freeze i1 %cond
br i1 %cond.fr, label %A, label %B br i1 %cond.fr, label %A, label %B
A: A:
ret i32 10 ret i32 10
B: B:
ret i32 20 ret i32 20
} }
define i32 @f_true3(i16* %p) { define i32 @f_true3(i16* %p) {
; CHECK-LABEL: f_true3: ; CHECK-LABEL: f_true3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB7_2 ; CHECK-NEXT: je .LBB7_2
; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: # %bb.1: # %A
; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: movl $10, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: .LBB7_2: # %B ; CHECK-NEXT: .LBB7_2: # %B
; CHECK-NEXT: movl $20, %eax ; CHECK-NEXT: movl $20, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%v = load i16, i16* %p, align 2 %v = load i16, i16* %p, align 2
%and = and i16 %v, 2048 %and = and i16 %v, 2048
%cond = icmp ule i16 0, %and %cond = icmp ule i16 0, %and
%cond.fr = freeze i1 %cond %cond.fr = freeze i1 %cond
br i1 %cond.fr, label %A, label %B br i1 %cond.fr, label %A, label %B
A: A:
ret i32 10 ret i32 10
B: B:
ret i32 20 ret i32 20
} }
define i32 @f_true4(i16* %p) { define i32 @f_true4(i16* %p) {
; CHECK-LABEL: f_true4: ; CHECK-LABEL: f_true4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB8_2 ; CHECK-NEXT: je .LBB8_2
; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: # %bb.1: # %A
; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: movl $10, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: .LBB8_2: # %B ; CHECK-NEXT: .LBB8_2: # %B
; CHECK-NEXT: movl $20, %eax ; CHECK-NEXT: movl $20, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%v = load i16, i16* %p, align 2 %v = load i16, i16* %p, align 2
%and = and i16 %v, 2048 %and = and i16 %v, 2048
%cond = icmp ule i16 %and, 65535 %cond = icmp ule i16 %and, 65535
%cond.fr = freeze i1 %cond %cond.fr = freeze i1 %cond
br i1 %cond.fr, label %A, label %B br i1 %cond.fr, label %A, label %B
A: A:
ret i32 10 ret i32 10
B: B:
ret i32 20 ret i32 20
} }

llvm/test/CodeGen/X86/shrink-compare-pgso.ll

Show First 20 Lines • Show All 279 Lines • ▼ Show 20 Lines
if.end: if.end:
ret void ret void
} }
define dso_local void @test_sext_i8_icmp_255(i8 %x) nounwind !prof !14 { define dso_local void @test_sext_i8_icmp_255(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_255: ; CHECK-LABEL: test_sext_i8_icmp_255:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je bar # TAILCALL ; CHECK-NEXT: jne bar # TAILCALL
; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%sext = sext i8 %x to i32 %sext = sext i8 %x to i32
%cmp = icmp eq i32 %sext, 255 %cmp = icmp eq i32 %sext, 255
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: if.then:
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llvm/test/CodeGen/X86/shrink-compare.ll

Show First 20 Lines • Show All 279 Lines • ▼ Show 20 Lines
if.end: if.end:
ret void ret void
} }
define dso_local void @test_sext_i8_icmp_255(i8 %x) nounwind minsize { define dso_local void @test_sext_i8_icmp_255(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_255: ; CHECK-LABEL: test_sext_i8_icmp_255:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je bar # TAILCALL ; CHECK-NEXT: jne bar # TAILCALL
; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%sext = sext i8 %x to i32 %sext = sext i8 %x to i32
%cmp = icmp eq i32 %sext, 255 %cmp = icmp eq i32 %sext, 255
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: if.then:
tail call void @bar() nounwind tail call void @bar() nounwind
br label %if.end br label %if.end
if.end: if.end:
ret void ret void
} }

llvm/test/CodeGen/X86/sibcall.ll

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
} }
define dso_local i32 @t6(i32 %x) nounwind ssp { define dso_local i32 @t6(i32 %x) nounwind ssp {
; X86-LABEL: t6: ; X86-LABEL: t6:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: subl $12, %esp ; X86-NEXT: subl $12, %esp
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: cmpl $9, %eax ; X86-NEXT: cmpl $10, %eax
; X86-NEXT: jg .LBB6_2 ; X86-NEXT: jge .LBB6_2
; X86-NEXT: # %bb.1: # %bb ; X86-NEXT: # %bb.1: # %bb
; X86-NEXT: decl %eax ; X86-NEXT: decl %eax
; X86-NEXT: movl %eax, (%esp) ; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: calll t6 ; X86-NEXT: calll t6
; X86-NEXT: addl $12, %esp ; X86-NEXT: addl $12, %esp
; X86-NEXT: retl ; X86-NEXT: retl
; X86-NEXT: .LBB6_2: # %bb1 ; X86-NEXT: .LBB6_2: # %bb1
; X86-NEXT: addl $12, %esp ; X86-NEXT: addl $12, %esp
; X86-NEXT: jmp bar # TAILCALL ; X86-NEXT: jmp bar # TAILCALL
; ;
; X64-LABEL: t6: ; X64-LABEL: t6:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: cmpl $9, %edi ; X64-NEXT: cmpl $10, %edi
; X64-NEXT: jg .LBB6_2 ; X64-NEXT: jge .LBB6_2
; X64-NEXT: # %bb.1: # %bb ; X64-NEXT: # %bb.1: # %bb
; X64-NEXT: decl %edi ; X64-NEXT: decl %edi
; X64-NEXT: jmp t6 # TAILCALL ; X64-NEXT: jmp t6 # TAILCALL
; X64-NEXT: .LBB6_2: # %bb1 ; X64-NEXT: .LBB6_2: # %bb1
; X64-NEXT: jmp bar # TAILCALL ; X64-NEXT: jmp bar # TAILCALL
; ;
; X32-LABEL: t6: ; X32-LABEL: t6:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: cmpl $9, %edi ; X32-NEXT: cmpl $10, %edi
; X32-NEXT: jg .LBB6_2 ; X32-NEXT: jge .LBB6_2
; X32-NEXT: # %bb.1: # %bb ; X32-NEXT: # %bb.1: # %bb
; X32-NEXT: decl %edi ; X32-NEXT: decl %edi
; X32-NEXT: jmp t6 # TAILCALL ; X32-NEXT: jmp t6 # TAILCALL
; X32-NEXT: .LBB6_2: # %bb1 ; X32-NEXT: .LBB6_2: # %bb1
; X32-NEXT: jmp bar # TAILCALL ; X32-NEXT: jmp bar # TAILCALL
%t0 = icmp slt i32 %x, 10 %t0 = icmp slt i32 %x, 10
br i1 %t0, label %bb, label %bb1 br i1 %t0, label %bb, label %bb1
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, (%esp) ; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: calll t22_f_sret@PLT ; X86-NEXT: calll t22_f_sret@PLT
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: t22_non_sret_to_sret: ; X64-LABEL: t22_non_sret_to_sret:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: jmp t22_f_sret@PLT # TAILCALL ; X64-NEXT: jmp t22_f_sret@PLT # TAILCALL
; ;
; X32-LABEL: t22_non_sret_to_sret: ; X32-LABEL: t22_non_sret_to_sret:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: jmp t22_f_sret@PLT # TAILCALL ; X32-NEXT: jmp t22_f_sret@PLT # TAILCALL
tail call ccc void @t22_f_sret(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind tail call ccc void @t22_f_sret(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind
ret void ret void
} }
declare dso_local fastcc void @t21_f_sret(%struct.foo* noalias sret(%struct.foo)) nounwind declare dso_local fastcc void @t21_f_sret(%struct.foo* noalias sret(%struct.foo)) nounwind
declare dso_local fastcc void @t21_f_sret2(%struct.foo* noalias sret(%struct.foo), %struct.foo* noalias) nounwind declare dso_local fastcc void @t21_f_sret2(%struct.foo* noalias sret(%struct.foo), %struct.foo* noalias) nounwind
declare dso_local fastcc void @t21_f_non_sret(%struct.foo*) nounwind declare dso_local fastcc void @t21_f_non_sret(%struct.foo*) nounwind
declare ccc void @t22_f_sret(%struct.foo* noalias sret(%struct.foo)) nounwind declare ccc void @t22_f_sret(%struct.foo* noalias sret(%struct.foo)) nounwind
declare ccc void @f_sret(%struct.foo* noalias sret(%struct.foo), i32, i32) nounwind declare ccc void @f_sret(%struct.foo* noalias sret(%struct.foo), i32, i32) nounwind

llvm/test/CodeGen/X86/slow-incdec.ll

Show First 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
declare void @external_b() declare void @external_b()
declare {i8, i1} @llvm.uadd.with.overflow.i8(i8, i8) declare {i8, i1} @llvm.uadd.with.overflow.i8(i8, i8)
define void @test_tail_call(i32* %ptr) nounwind { define void @test_tail_call(i32* %ptr) nounwind {
; INCDEC-LABEL: test_tail_call: ; INCDEC-LABEL: test_tail_call:
; INCDEC: # %bb.0: # %entry ; INCDEC: # %bb.0: # %entry
; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax ; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
; INCDEC-NEXT: incl (%eax) ; INCDEC-NEXT: incl (%eax)
; INCDEC-NEXT: setne %al ; INCDEC-NEXT: sete %al
; INCDEC-NEXT: incb a ; INCDEC-NEXT: incb a
; INCDEC-NEXT: sete d ; INCDEC-NEXT: sete d
; INCDEC-NEXT: testb %al, %al ; INCDEC-NEXT: testb %al, %al
; INCDEC-NEXT: jne .LBB7_2 ; INCDEC-NEXT: je .LBB7_2
; INCDEC-NEXT: # %bb.1: # %then ; INCDEC-NEXT: # %bb.1: # %then
; INCDEC-NEXT: jmp external_a@PLT # TAILCALL ; INCDEC-NEXT: jmp external_a@PLT # TAILCALL
; INCDEC-NEXT: .LBB7_2: # %else ; INCDEC-NEXT: .LBB7_2: # %else
; INCDEC-NEXT: jmp external_b@PLT # TAILCALL ; INCDEC-NEXT: jmp external_b@PLT # TAILCALL
; ;
; ADD-LABEL: test_tail_call: ; ADD-LABEL: test_tail_call:
; ADD: # %bb.0: # %entry ; ADD: # %bb.0: # %entry
; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax ; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
; ADD-NEXT: addl $1, (%eax) ; ADD-NEXT: addl $1, (%eax)
; ADD-NEXT: setne %al ; ADD-NEXT: sete %al
; ADD-NEXT: addb $1, a ; ADD-NEXT: addb $1, a
; ADD-NEXT: sete d ; ADD-NEXT: sete d
; ADD-NEXT: testb %al, %al ; ADD-NEXT: testb %al, %al
; ADD-NEXT: jne .LBB7_2 ; ADD-NEXT: je .LBB7_2
; ADD-NEXT: # %bb.1: # %then ; ADD-NEXT: # %bb.1: # %then
; ADD-NEXT: jmp external_a@PLT # TAILCALL ; ADD-NEXT: jmp external_a@PLT # TAILCALL
; ADD-NEXT: .LBB7_2: # %else ; ADD-NEXT: .LBB7_2: # %else
; ADD-NEXT: jmp external_b@PLT # TAILCALL ; ADD-NEXT: jmp external_b@PLT # TAILCALL
entry: entry:
%val = load i32, i32* %ptr %val = load i32, i32* %ptr
%add_ov = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %val, i32 1) %add_ov = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %val, i32 1)
%inc = extractvalue { i32, i1 } %add_ov, 0 %inc = extractvalue { i32, i1 } %add_ov, 0
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llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression.ll

Show All 36 Lines
define dso_local i32 @_Z3barPi(i32* %p) { define dso_local i32 @_Z3barPi(i32* %p) {
; CHECK-LABEL: _Z3barPi: ; CHECK-LABEL: _Z3barPi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfence ; CHECK-NEXT: lfence
; CHECK-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: lfence ; CHECK-NEXT: lfence
; CHECK-NEXT: movl $4, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movl $4, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: lfence ; CHECK-NEXT: lfence
; CHECK-NEXT: cmpl $3, (%rdi) ; CHECK-NEXT: cmpl $4, (%rdi)
; CHECK-NEXT: lfence ; CHECK-NEXT: lfence
; CHECK-NEXT: jg .LBB1_2 ; CHECK-NEXT: jge .LBB1_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: lfence ; CHECK-NEXT: lfence
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: lfence ; CHECK-NEXT: lfence
; CHECK-NEXT: movslq (%rax), %rax ; CHECK-NEXT: movslq (%rax), %rax
; CHECK-NEXT: lfence ; CHECK-NEXT: lfence
; CHECK-NEXT: movl -24(%rsp,%rax,4), %eax ; CHECK-NEXT: movl -24(%rsp,%rax,4), %eax
; CHECK-NEXT: lfence ; CHECK-NEXT: lfence
; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: lfence ; CHECK-NEXT: lfence
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax ; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: .LBB1_2: # %if.else ; CHECK-NEXT: .LBB1_2: # %if.else
; CHECK-NEXT: lfence ; CHECK-NEXT: lfence
; CHECK-NEXT: movl $-1, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movl $-1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: lfence ; CHECK-NEXT: lfence
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax ; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; X86-ONE-LFENCE-LABEL: _Z3barPi: ; X86-ONE-LFENCE-LABEL: _Z3barPi:
; X86-ONE-LFENCE: # %bb.0: # %entry ; X86-ONE-LFENCE: # %bb.0: # %entry
; X86-ONE-LFENCE-NEXT: lfence ; X86-ONE-LFENCE-NEXT: lfence
; X86-ONE-LFENCE-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) ; X86-ONE-LFENCE-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
; X86-ONE-LFENCE-NEXT: movl $4, -{{[0-9]+}}(%rsp) ; X86-ONE-LFENCE-NEXT: movl $4, -{{[0-9]+}}(%rsp)
; X86-ONE-LFENCE-NEXT: cmpl $3, (%rdi) ; X86-ONE-LFENCE-NEXT: cmpl $4, (%rdi)
; X86-ONE-LFENCE-NEXT: jg .LBB1_2 ; X86-ONE-LFENCE-NEXT: jge .LBB1_2
; X86-ONE-LFENCE-NEXT: # %bb.1: # %if.then ; X86-ONE-LFENCE-NEXT: # %bb.1: # %if.then
; X86-ONE-LFENCE-NEXT: lfence ; X86-ONE-LFENCE-NEXT: lfence
; X86-ONE-LFENCE-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; X86-ONE-LFENCE-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; X86-ONE-LFENCE-NEXT: movslq (%rax), %rax ; X86-ONE-LFENCE-NEXT: movslq (%rax), %rax
; X86-ONE-LFENCE-NEXT: movl -24(%rsp,%rax,4), %eax ; X86-ONE-LFENCE-NEXT: movl -24(%rsp,%rax,4), %eax
; X86-ONE-LFENCE-NEXT: movl %eax, -{{[0-9]+}}(%rsp) ; X86-ONE-LFENCE-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
; X86-ONE-LFENCE-NEXT: movl -{{[0-9]+}}(%rsp), %eax ; X86-ONE-LFENCE-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; X86-ONE-LFENCE-NEXT: retq ; X86-ONE-LFENCE-NEXT: retq
; X86-ONE-LFENCE-NEXT: .LBB1_2: # %if.else ; X86-ONE-LFENCE-NEXT: .LBB1_2: # %if.else
; X86-ONE-LFENCE-NEXT: lfence ; X86-ONE-LFENCE-NEXT: lfence
; X86-ONE-LFENCE-NEXT: movl $-1, -{{[0-9]+}}(%rsp) ; X86-ONE-LFENCE-NEXT: movl $-1, -{{[0-9]+}}(%rsp)
; X86-ONE-LFENCE-NEXT: movl -{{[0-9]+}}(%rsp), %eax ; X86-ONE-LFENCE-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; X86-ONE-LFENCE-NEXT: retq ; X86-ONE-LFENCE-NEXT: retq
; ;
; X86-OMIT-BR-LABEL: _Z3barPi: ; X86-OMIT-BR-LABEL: _Z3barPi:
; X86-OMIT-BR: # %bb.0: # %entry ; X86-OMIT-BR: # %bb.0: # %entry
; X86-OMIT-BR-NEXT: lfence ; X86-OMIT-BR-NEXT: lfence
; X86-OMIT-BR-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) ; X86-OMIT-BR-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
; X86-OMIT-BR-NEXT: lfence ; X86-OMIT-BR-NEXT: lfence
; X86-OMIT-BR-NEXT: movl $4, -{{[0-9]+}}(%rsp) ; X86-OMIT-BR-NEXT: movl $4, -{{[0-9]+}}(%rsp)
; X86-OMIT-BR-NEXT: lfence ; X86-OMIT-BR-NEXT: lfence
; X86-OMIT-BR-NEXT: cmpl $3, (%rdi) ; X86-OMIT-BR-NEXT: cmpl $4, (%rdi)
; X86-OMIT-BR-NEXT: jg .LBB1_2 ; X86-OMIT-BR-NEXT: jge .LBB1_2
; X86-OMIT-BR-NEXT: # %bb.1: # %if.then ; X86-OMIT-BR-NEXT: # %bb.1: # %if.then
; X86-OMIT-BR-NEXT: lfence ; X86-OMIT-BR-NEXT: lfence
; X86-OMIT-BR-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; X86-OMIT-BR-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; X86-OMIT-BR-NEXT: lfence ; X86-OMIT-BR-NEXT: lfence
; X86-OMIT-BR-NEXT: movslq (%rax), %rax ; X86-OMIT-BR-NEXT: movslq (%rax), %rax
; X86-OMIT-BR-NEXT: lfence ; X86-OMIT-BR-NEXT: lfence
; X86-OMIT-BR-NEXT: movl -24(%rsp,%rax,4), %eax ; X86-OMIT-BR-NEXT: movl -24(%rsp,%rax,4), %eax
; X86-OMIT-BR-NEXT: lfence ; X86-OMIT-BR-NEXT: lfence
Show All 10 Lines
; ;
; X86-NON-CONST-LABEL: _Z3barPi: ; X86-NON-CONST-LABEL: _Z3barPi:
; X86-NON-CONST: # %bb.0: # %entry ; X86-NON-CONST: # %bb.0: # %entry
; X86-NON-CONST-NEXT: lfence ; X86-NON-CONST-NEXT: lfence
; X86-NON-CONST-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) ; X86-NON-CONST-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
; X86-NON-CONST-NEXT: lfence ; X86-NON-CONST-NEXT: lfence
; X86-NON-CONST-NEXT: movl $4, -{{[0-9]+}}(%rsp) ; X86-NON-CONST-NEXT: movl $4, -{{[0-9]+}}(%rsp)
; X86-NON-CONST-NEXT: lfence ; X86-NON-CONST-NEXT: lfence
; X86-NON-CONST-NEXT: cmpl $3, (%rdi) ; X86-NON-CONST-NEXT: cmpl $4, (%rdi)
; X86-NON-CONST-NEXT: lfence ; X86-NON-CONST-NEXT: lfence
; X86-NON-CONST-NEXT: jg .LBB1_2 ; X86-NON-CONST-NEXT: jge .LBB1_2
; X86-NON-CONST-NEXT: # %bb.1: # %if.then ; X86-NON-CONST-NEXT: # %bb.1: # %if.then
; X86-NON-CONST-NEXT: lfence ; X86-NON-CONST-NEXT: lfence
; X86-NON-CONST-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; X86-NON-CONST-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; X86-NON-CONST-NEXT: lfence ; X86-NON-CONST-NEXT: lfence
; X86-NON-CONST-NEXT: movslq (%rax), %rax ; X86-NON-CONST-NEXT: movslq (%rax), %rax
; X86-NON-CONST-NEXT: lfence ; X86-NON-CONST-NEXT: lfence
; X86-NON-CONST-NEXT: movl -24(%rsp,%rax,4), %eax ; X86-NON-CONST-NEXT: movl -24(%rsp,%rax,4), %eax
; X86-NON-CONST-NEXT: lfence ; X86-NON-CONST-NEXT: lfence
▲ Show 20 Lines • Show All 167 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll

Show First 20 Lines • Show All 622 Lines • ▼ Show 20 Lines
; X64-PIC-NEXT: orq %rcx, %rsp ; X64-PIC-NEXT: orq %rcx, %rsp
; X64-PIC-NEXT: retq ; X64-PIC-NEXT: retq
; ;
; X64-RETPOLINE-LABEL: test_switch_jumptable: ; X64-RETPOLINE-LABEL: test_switch_jumptable:
; X64-RETPOLINE: # %bb.0: # %entry ; X64-RETPOLINE: # %bb.0: # %entry
; X64-RETPOLINE-NEXT: movq %rsp, %rcx ; X64-RETPOLINE-NEXT: movq %rsp, %rcx
; X64-RETPOLINE-NEXT: movq $-1, %rax ; X64-RETPOLINE-NEXT: movq $-1, %rax
; X64-RETPOLINE-NEXT: sarq $63, %rcx ; X64-RETPOLINE-NEXT: sarq $63, %rcx
; X64-RETPOLINE-NEXT: cmpl $1, %edi ; X64-RETPOLINE-NEXT: cmpl $2, %edi
; X64-RETPOLINE-NEXT: jg .LBB7_4 ; X64-RETPOLINE-NEXT: jge .LBB7_4
; X64-RETPOLINE-NEXT: # %bb.1: # %entry ; X64-RETPOLINE-NEXT: # %bb.1: # %entry
; X64-RETPOLINE-NEXT: cmovgq %rax, %rcx ; X64-RETPOLINE-NEXT: cmovgeq %rax, %rcx
; X64-RETPOLINE-NEXT: testl %edi, %edi ; X64-RETPOLINE-NEXT: testl %edi, %edi
; X64-RETPOLINE-NEXT: je .LBB7_7 ; X64-RETPOLINE-NEXT: je .LBB7_7
; X64-RETPOLINE-NEXT: # %bb.2: # %entry ; X64-RETPOLINE-NEXT: # %bb.2: # %entry
; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx ; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx
; X64-RETPOLINE-NEXT: cmpl $1, %edi ; X64-RETPOLINE-NEXT: cmpl $1, %edi
; X64-RETPOLINE-NEXT: jne .LBB7_6 ; X64-RETPOLINE-NEXT: jne .LBB7_6
; X64-RETPOLINE-NEXT: # %bb.3: # %bb2 ; X64-RETPOLINE-NEXT: # %bb.3: # %bb2
; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx ; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx
; X64-RETPOLINE-NEXT: shlq $47, %rcx ; X64-RETPOLINE-NEXT: shlq $47, %rcx
; X64-RETPOLINE-NEXT: movl $13, %eax ; X64-RETPOLINE-NEXT: movl $13, %eax
; X64-RETPOLINE-NEXT: orq %rcx, %rsp ; X64-RETPOLINE-NEXT: orq %rcx, %rsp
; X64-RETPOLINE-NEXT: retq ; X64-RETPOLINE-NEXT: retq
; X64-RETPOLINE-NEXT: .LBB7_4: # %entry ; X64-RETPOLINE-NEXT: .LBB7_4: # %entry
; X64-RETPOLINE-NEXT: cmovleq %rax, %rcx ; X64-RETPOLINE-NEXT: cmovlq %rax, %rcx
; X64-RETPOLINE-NEXT: cmpl $2, %edi
; X64-RETPOLINE-NEXT: je .LBB7_8 ; X64-RETPOLINE-NEXT: je .LBB7_8
; X64-RETPOLINE-NEXT: # %bb.5: # %entry ; X64-RETPOLINE-NEXT: # %bb.5: # %entry
; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx ; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx
; X64-RETPOLINE-NEXT: cmpl $3, %edi ; X64-RETPOLINE-NEXT: cmpl $3, %edi
; X64-RETPOLINE-NEXT: jne .LBB7_6 ; X64-RETPOLINE-NEXT: jne .LBB7_6
; X64-RETPOLINE-NEXT: # %bb.9: # %bb5 ; X64-RETPOLINE-NEXT: # %bb.9: # %bb5
; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx ; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx
; X64-RETPOLINE-NEXT: shlq $47, %rcx ; X64-RETPOLINE-NEXT: shlq $47, %rcx
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; X64-PIC-NEXT: retq ; X64-PIC-NEXT: retq
; ;
; X64-RETPOLINE-LABEL: test_switch_jumptable_fallthrough: ; X64-RETPOLINE-LABEL: test_switch_jumptable_fallthrough:
; X64-RETPOLINE: # %bb.0: # %entry ; X64-RETPOLINE: # %bb.0: # %entry
; X64-RETPOLINE-NEXT: movq %rsp, %r9 ; X64-RETPOLINE-NEXT: movq %rsp, %r9
; X64-RETPOLINE-NEXT: movq $-1, %r10 ; X64-RETPOLINE-NEXT: movq $-1, %r10
; X64-RETPOLINE-NEXT: sarq $63, %r9 ; X64-RETPOLINE-NEXT: sarq $63, %r9
; X64-RETPOLINE-NEXT: xorl %eax, %eax ; X64-RETPOLINE-NEXT: xorl %eax, %eax
; X64-RETPOLINE-NEXT: cmpl $1, %edi ; X64-RETPOLINE-NEXT: cmpl $2, %edi
; X64-RETPOLINE-NEXT: jg .LBB8_5 ; X64-RETPOLINE-NEXT: jge .LBB8_5
; X64-RETPOLINE-NEXT: # %bb.1: # %entry ; X64-RETPOLINE-NEXT: # %bb.1: # %entry
; X64-RETPOLINE-NEXT: cmovgq %r10, %r9 ; X64-RETPOLINE-NEXT: cmovgeq %r10, %r9
; X64-RETPOLINE-NEXT: testl %edi, %edi ; X64-RETPOLINE-NEXT: testl %edi, %edi
; X64-RETPOLINE-NEXT: je .LBB8_2 ; X64-RETPOLINE-NEXT: je .LBB8_2
; X64-RETPOLINE-NEXT: # %bb.3: # %entry ; X64-RETPOLINE-NEXT: # %bb.3: # %entry
; X64-RETPOLINE-NEXT: cmoveq %r10, %r9 ; X64-RETPOLINE-NEXT: cmoveq %r10, %r9
; X64-RETPOLINE-NEXT: cmpl $1, %edi ; X64-RETPOLINE-NEXT: cmpl $1, %edi
; X64-RETPOLINE-NEXT: jne .LBB8_8 ; X64-RETPOLINE-NEXT: jne .LBB8_8
; X64-RETPOLINE-NEXT: # %bb.4: ; X64-RETPOLINE-NEXT: # %bb.4:
; X64-RETPOLINE-NEXT: cmovneq %r10, %r9 ; X64-RETPOLINE-NEXT: cmovneq %r10, %r9
; X64-RETPOLINE-NEXT: jmp .LBB8_10 ; X64-RETPOLINE-NEXT: jmp .LBB8_10
; X64-RETPOLINE-NEXT: .LBB8_5: # %entry ; X64-RETPOLINE-NEXT: .LBB8_5: # %entry
; X64-RETPOLINE-NEXT: cmovleq %r10, %r9 ; X64-RETPOLINE-NEXT: cmovlq %r10, %r9
; X64-RETPOLINE-NEXT: cmpl $2, %edi
; X64-RETPOLINE-NEXT: je .LBB8_6 ; X64-RETPOLINE-NEXT: je .LBB8_6
; X64-RETPOLINE-NEXT: # %bb.7: # %entry ; X64-RETPOLINE-NEXT: # %bb.7: # %entry
; X64-RETPOLINE-NEXT: cmoveq %r10, %r9 ; X64-RETPOLINE-NEXT: cmoveq %r10, %r9
; X64-RETPOLINE-NEXT: cmpl $3, %edi ; X64-RETPOLINE-NEXT: cmpl $3, %edi
; X64-RETPOLINE-NEXT: jne .LBB8_8 ; X64-RETPOLINE-NEXT: jne .LBB8_8
; X64-RETPOLINE-NEXT: # %bb.13: ; X64-RETPOLINE-NEXT: # %bb.13:
; X64-RETPOLINE-NEXT: cmovneq %r10, %r9 ; X64-RETPOLINE-NEXT: cmovneq %r10, %r9
; X64-RETPOLINE-NEXT: jmp .LBB8_12 ; X64-RETPOLINE-NEXT: jmp .LBB8_12
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llvm/test/CodeGen/X86/statepoint-ra.ll

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;CHECK: STATEPOINT 2882400000, 0, 0, target-flags(x86-plt) @blam, 2, 9, 2, 0, 2, 59, 2, 0, 2, 1, 2, 0, 2, 0, 2, 0, 2, 26, 2, 0, 2, 0, 1, 8, %stack.0, 0, 2, 4, %62, 2, 7, 2, 0, 2, 4, %58, 2, 7, 2, 0, 2, 4, %6, 2, 7, 2, 0, 2, 4, %53, 2, 7, 2, 0, 2, 4, %45, 2, 7, 2, 0, 2, 4, %41, 2, 7, 2, 0, 2, 4, %10, 2, 7, 2, 0, 2, 4, %49, 2, 7, 2, 0, 2, 4, %71, 2, 7, 2, 0, 2, 4, %66, 2, 7, 2, 0, 2, 4, %14, 2, 7, 2, 0, 2, 4, %76, 2, 7, 2, 0, 2, 7, 2, 0, 2, 1, 1, 8, %stack.0, 0, 2, 0, 2, 1, 0, 0, csr_64_mostregs, implicit-def $rsp, implicit-def $ssp :: (volatile load store (s64) on %stack.0) ;CHECK: STATEPOINT 2882400000, 0, 0, target-flags(x86-plt) @blam, 2, 9, 2, 0, 2, 59, 2, 0, 2, 1, 2, 0, 2, 0, 2, 0, 2, 26, 2, 0, 2, 0, 1, 8, %stack.0, 0, 2, 4, %62, 2, 7, 2, 0, 2, 4, %58, 2, 7, 2, 0, 2, 4, %6, 2, 7, 2, 0, 2, 4, %53, 2, 7, 2, 0, 2, 4, %45, 2, 7, 2, 0, 2, 4, %41, 2, 7, 2, 0, 2, 4, %10, 2, 7, 2, 0, 2, 4, %49, 2, 7, 2, 0, 2, 4, %71, 2, 7, 2, 0, 2, 4, %66, 2, 7, 2, 0, 2, 4, %14, 2, 7, 2, 0, 2, 4, %76, 2, 7, 2, 0, 2, 7, 2, 0, 2, 1, 1, 8, %stack.0, 0, 2, 0, 2, 1, 0, 0, csr_64_mostregs, implicit-def $rsp, implicit-def $ssp :: (volatile load store (s64) on %stack.0)
;CHECK: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp ;CHECK: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
;CHECK: %17:gr32 = MOV32r0 implicit-def dead $eflags ;CHECK: %17:gr32 = MOV32r0 implicit-def dead $eflags
;CHECK: TEST8rr %17.sub_8bit, %17.sub_8bit, implicit-def $eflags ;CHECK: TEST8rr %17.sub_8bit, %17.sub_8bit, implicit-def $eflags
;CHECK: MOVSDmr %stack.1, 1, $noreg, 0, $noreg, %41 :: (store (s64) into %stack.1) ;CHECK: MOVSDmr %stack.1, 1, $noreg, 0, $noreg, %41 :: (store (s64) into %stack.1)
;CHECK: MOVSDmr %stack.2, 1, $noreg, 0, $noreg, %45 :: (store (s64) into %stack.2) ;CHECK: MOVSDmr %stack.2, 1, $noreg, 0, $noreg, %45 :: (store (s64) into %stack.2)
;CHECK: MOVSDmr %stack.5, 1, $noreg, 0, $noreg, %58 :: (store (s64) into %stack.5) ;CHECK: MOVSDmr %stack.5, 1, $noreg, 0, $noreg, %58 :: (store (s64) into %stack.5)
;CHECK: MOVSDmr %stack.6, 1, $noreg, 0, $noreg, %62 :: (store (s64) into %stack.6) ;CHECK: MOVSDmr %stack.6, 1, $noreg, 0, $noreg, %62 :: (store (s64) into %stack.6)
;CHECK: JCC_1 %bb.2, 4, implicit killed $eflags ;CHECK: JCC_1 %bb.2, 5, implicit killed $eflags
;CHECK: bb.1: ;CHECK: bb.1:
;CHECK: successors: %bb.3(0x80000000) ;CHECK: successors: %bb.3(0x80000000)
;CHECK: %54:fr64 = MOVSDrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load (s64) from constant-pool) ;CHECK: %54:fr64 = MOVSDrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load (s64) from constant-pool)
;CHECK: MOVSDmr %stack.3, 1, $noreg, 0, $noreg, %54 :: (store (s64) into %stack.3) ;CHECK: MOVSDmr %stack.3, 1, $noreg, 0, $noreg, %54 :: (store (s64) into %stack.3)
;CHECK: MOVSDmr %stack.4, 1, $noreg, 0, $noreg, %54 :: (store (s64) into %stack.4) ;CHECK: MOVSDmr %stack.4, 1, $noreg, 0, $noreg, %54 :: (store (s64) into %stack.4)
;CHECK: MOVSDmr %stack.7, 1, $noreg, 0, $noreg, %54 :: (store (s64) into %stack.7) ;CHECK: MOVSDmr %stack.7, 1, $noreg, 0, $noreg, %54 :: (store (s64) into %stack.7)
;CHECK: JMP_1 %bb.3 ;CHECK: JMP_1 %bb.3
;CHECK: bb.2.bb13: ;CHECK: bb.2.bb13:
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llvm/test/CodeGen/X86/statepoint-vreg-details.ll

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; CHECK-VREG-NEXT: %0:gr64 = COPY $rdi ; CHECK-VREG-NEXT: %0:gr64 = COPY $rdi
; CHECK-VREG-NEXT: %4:gr8 = COPY %1.sub_8bit ; CHECK-VREG-NEXT: %4:gr8 = COPY %1.sub_8bit
; CHECK-VREG-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp ; CHECK-VREG-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK-VREG-NEXT: %2:gr64 = STATEPOINT 0, 0, 0, @return_i1, 2, 0, 2, 0, 2, 0, 2, 1, %0(tied-def 0), 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp, implicit-def $al ; CHECK-VREG-NEXT: %2:gr64 = STATEPOINT 0, 0, 0, @return_i1, 2, 0, 2, 0, 2, 0, 2, 1, %0(tied-def 0), 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp, implicit-def $al
; CHECK-VREG-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp ; CHECK-VREG-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK-VREG-NEXT: %5:gr8 = COPY $al ; CHECK-VREG-NEXT: %5:gr8 = COPY $al
; CHECK-VREG-NEXT: %3:gr8 = COPY %5 ; CHECK-VREG-NEXT: %3:gr8 = COPY %5
; CHECK-VREG-NEXT: TEST8ri killed %4, 1, implicit-def $eflags ; CHECK-VREG-NEXT: TEST8ri killed %4, 1, implicit-def $eflags
; CHECK-VREG-NEXT: JCC_1 %bb.2, 4, implicit $eflags ; CHECK-VREG-NEXT: JCC_1 %bb.1, 5, implicit $eflags
; CHECK-VREG-NEXT: JMP_1 %bb.1 ; CHECK-VREG-NEXT: JMP_1 %bb.2
; CHECK-VREG: bb.1.left: ; CHECK-VREG: bb.1.left:
; CHECK-VREG-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp ; CHECK-VREG-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK-VREG-NEXT: $rdi = COPY %2 ; CHECK-VREG-NEXT: $rdi = COPY %2
; CHECK-VREG-NEXT: CALL64pcrel32 @consume, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp ; CHECK-VREG-NEXT: CALL64pcrel32 @consume, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp
; CHECK-VREG-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp ; CHECK-VREG-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK-VREG-NEXT: $al = COPY %3 ; CHECK-VREG-NEXT: $al = COPY %3
; CHECK-VREG-NEXT: RET 0, $al ; CHECK-VREG-NEXT: RET 0, $al
; CHECK-VREG: bb.2.right: ; CHECK-VREG: bb.2.right:
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llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll

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define i64 addrspace(1)* @test_invoke_same_val(i1 %cond, i64 addrspace(1)* %val1, i64 addrspace(1)* %val2, i64 addrspace(1)* %val3) define i64 addrspace(1)* @test_invoke_same_val(i1 %cond, i64 addrspace(1)* %val1, i64 addrspace(1)* %val2, i64 addrspace(1)* %val3)
; CHECK-LABEL: name: test_invoke_same_val ; CHECK-LABEL: name: test_invoke_same_val
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: renamable $rbx = COPY $rcx ; CHECK: renamable $rbx = COPY $rcx
; CHECK: renamable $rbp = COPY $rdx ; CHECK: renamable $rbp = COPY $rdx
; CHECK: renamable $r14d = COPY $edi ; CHECK: renamable $r14d = COPY $edi
; CHECK: TEST8ri renamable $r14b, 1, implicit-def $eflags ; CHECK: TEST8ri renamable $r14b, 1, implicit-def $eflags
; CHECK: JCC_1 %bb.3, 4, implicit killed $eflags ; CHECK: JCC_1 %bb.1, 5, implicit killed $eflags
; CHECK: JMP_1 %bb.1 ; CHECK: JMP_1 %bb.3
; CHECK: bb.1.left: ; CHECK: bb.1.left:
; CHECK: MOV64mr %stack.0, 1, $noreg, 0, $noreg, renamable $rsi :: (store (s64) into %stack.0) ; CHECK: MOV64mr %stack.0, 1, $noreg, 0, $noreg, renamable $rsi :: (store (s64) into %stack.0)
; CHECK: $rdi = COPY killed renamable $rsi ; CHECK: $rdi = COPY killed renamable $rsi
; CHECK: renamable $rbp = STATEPOINT 0, 0, 1, @some_call, $rdi, 2, 0, 2, 0, 2, 0, 2, 2, killed renamable $rbp(tied-def 0), 1, 8, %stack.0, 0, 2, 0, 2, 2, 0, 0, 1, 1, csr_64, implicit-def $rsp, implicit-def $ssp :: (volatile load store (s64) on %stack.0) ; CHECK: renamable $rbp = STATEPOINT 0, 0, 1, @some_call, $rdi, 2, 0, 2, 0, 2, 0, 2, 2, killed renamable $rbp(tied-def 0), 1, 8, %stack.0, 0, 2, 0, 2, 2, 0, 0, 1, 1, csr_64, implicit-def $rsp, implicit-def $ssp :: (volatile load store (s64) on %stack.0)
; CHECK: JMP_1 %bb.2 ; CHECK: JMP_1 %bb.2
; CHECK: bb.2.left.relocs: ; CHECK: bb.2.left.relocs:
; CHECK: renamable $rbx = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %stack.0) ; CHECK: renamable $rbx = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %stack.0)
; CHECK: JMP_1 %bb.5 ; CHECK: JMP_1 %bb.5
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llvm/test/CodeGen/X86/switch-bt.ll

Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
sw.default: sw.default:
store i32 7, i32* %y store i32 7, i32* %y
br label %sw.epilog br label %sw.epilog
sw.epilog: sw.epilog:
ret void ret void
; The balanced binary switch here would start with a comparison against 39, but ; The balanced binary switch here would start with a comparison against 39, but
; it is currently starting with 29 because of the density-sum heuristic. ; it is currently starting with 29 because of the density-sum heuristic.
; CHECK: cmpl $39 ; CHECK: cmpl $40
; CHECK: jg ; CHECK: jge
; CHECK: cmpl $10 ; CHECK: cmpl $10
; CHECK: je ; CHECK: je
; CHECK: cmpl $20 ; CHECK: cmpl $20
; CHECK: je ; CHECK: je
; CHECK: cmpl $30 ; CHECK: cmpl $30
; CHECK: jne ; CHECK: jne
; CHECK: cmpl $40 ; CHECK: .LBB{{.*}}
; CHECK: je ; CHECK: je
; CHECK: cmpl $50 ; CHECK: cmpl $50
; CHECK: je ; CHECK: je
; CHECK: cmpl $60 ; CHECK: cmpl $60
; CHECK: jne ; CHECK: jne
} }
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llvm/test/CodeGen/X86/switch-density.ll

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bb0: tail call void @g(i32 0) br label %return bb0: tail call void @g(i32 0) br label %return
bb1: tail call void @g(i32 1) br label %return bb1: tail call void @g(i32 1) br label %return
bb2: tail call void @g(i32 1) br label %return bb2: tail call void @g(i32 1) br label %return
return: ret void return: ret void
; Should pivot around 400 for two subtrees with two jump tables each. ; Should pivot around 400 for two subtrees with two jump tables each.
; CHECK-LABEL: sparse ; CHECK-LABEL: sparse
; CHECK-NOT: cmpl ; CHECK-NOT: cmpl
; CHECK: cmpl $399 ; CHECK: cmpl $400
; CHECK: cmpl $100 ; CHECK: cmpl $100
; CHECK: cmpl $300 ; CHECK: cmpl $300
; CHECK: cmpl $400
; CHECK: cmpl $500 ; CHECK: cmpl $500
} }
define void @med(i32 %x) { define void @med(i32 %x) {
entry: entry:
switch i32 %x, label %return [ switch i32 %x, label %return [
i32 30, label %bb0 i32 30, label %bb0
i32 10, label %bb1 i32 10, label %bb1
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; Lowered as a jump table when sparse, and branches when dense. ; Lowered as a jump table when sparse, and branches when dense.
; CHECK-LABEL: med ; CHECK-LABEL: med
; SPARSE: addl $-10 ; SPARSE: addl $-10
; SPARSE: cmpl $40 ; SPARSE: cmpl $40
; SPARSE: ja ; SPARSE: ja
; SPARSE: jmpq *.LJTI ; SPARSE: jmpq *.LJTI
; DENSE-NOT: cmpl ; DENSE-NOT: cmpl
; DENSE: cmpl $29 ; DENSE: cmpl $30
; DENSE-DAG: cmpl $10 ; DENSE-DAG: cmpl $10
; DENSE-DAG: cmpl $20 ; DENSE-DAG: cmpl $20
; DENSE-DAG: cmpl $30 ; DENSE-DAG: cmpl $30
; DENSE-DAG: cmpl $40 ; DENSE-DAG: cmpl $40
; DENSE-DAG: cmpl $50 ; DENSE-DAG: cmpl $50
; DENSE: retq ; DENSE: retq
} }
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bb0: tail call void @g(i32 0) br label %return bb0: tail call void @g(i32 0) br label %return
bb1: tail call void @g(i32 1) br label %return bb1: tail call void @g(i32 1) br label %return
bb2: tail call void @g(i32 1) br label %return bb2: tail call void @g(i32 1) br label %return
bb3: tail call void @g(i32 2) br label %return bb3: tail call void @g(i32 2) br label %return
return: ret void return: ret void
; Lowered as branches. ; Lowered as branches.
; CHECK-LABEL: dense_optsize ; CHECK-LABEL: dense_optsize
; CHECK: cmpl $11 ; CHECK: cmpl $12
; CHECK: cmpl $20 ; CHECK: cmpl $20
; CHECK: cmpl $16 ; CHECK: cmpl $16
; CHECK: cmpl $12 ; CHECK: cmpl $12
; CHECK: cmpl $4 ; CHECK: cmpl $4
; CHECK: cmpl $8 ; CHECK: cmpl $8
; CHECK: retq ; CHECK: retq
} }
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bb0: tail call void @g(i32 0) br label %return bb0: tail call void @g(i32 0) br label %return
bb1: tail call void @g(i32 1) br label %return bb1: tail call void @g(i32 1) br label %return
bb2: tail call void @g(i32 1) br label %return bb2: tail call void @g(i32 1) br label %return
bb3: tail call void @g(i32 2) br label %return bb3: tail call void @g(i32 2) br label %return
return: ret void return: ret void
; Lowered as branches. ; Lowered as branches.
; CHECK-LABEL: dense_pgso ; CHECK-LABEL: dense_pgso
; CHECK: cmpl $11 ; CHECK: cmpl $12
; CHECK: cmpl $20 ; CHECK: cmpl $20
; CHECK: cmpl $16 ; CHECK: cmpl $16
; CHECK: cmpl $12 ; CHECK: cmpl $12
; CHECK: cmpl $4 ; CHECK: cmpl $4
; CHECK: cmpl $8 ; CHECK: cmpl $8
; CHECK: retq ; CHECK: retq
} }
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llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll

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; CHECK: successors: %[[PEELED_CASE_LABEL:.*]](0x5999999a), %[[PEELED_SWITCH_LABEL:.*]](0x26666666) ; CHECK: successors: %[[PEELED_CASE_LABEL:.*]](0x5999999a), %[[PEELED_SWITCH_LABEL:.*]](0x26666666)
; CHECK: %[[VAL:[0-9]+]]:gr32 = COPY $edi ; CHECK: %[[VAL:[0-9]+]]:gr32 = COPY $edi
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18568, implicit-def $eflags ; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18568, implicit-def $eflags
; CHECK: JCC_1 %[[PEELED_CASE_LABEL]], 4, implicit $eflags ; CHECK: JCC_1 %[[PEELED_CASE_LABEL]], 4, implicit $eflags
; CHECK: JMP_1 %[[PEELED_SWITCH_LABEL]] ; CHECK: JMP_1 %[[PEELED_SWITCH_LABEL]]
; CHECK: [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}: ; CHECK: [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[BB1_LABEL:.*]](0x0206d3a0), %[[BB2_LABEL:.*]](0x7df92c60) ; CHECK: successors: %[[BB1_LABEL:.*]](0x0206d3a0), %[[BB2_LABEL:.*]](0x7df92c60)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18311, implicit-def $eflags ; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18312, implicit-def $eflags
; CHECK: JCC_1 %[[BB2_LABEL]], 15, implicit $eflags ; CHECK: JCC_1 %[[BB1_LABEL]], 12, implicit $eflags
; CHECK: JMP_1 %[[BB1_LABEL]] ; CHECK: JMP_1 %[[BB2_LABEL]]
; CHECK: [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}: ; CHECK: [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[CASE2_LABEL:.*]](0x35e50d5b), %[[BB3_LABEL:.*]](0x4a1af2a5) ; CHECK: successors: %[[CASE2_LABEL:.*]](0x35e50d5b), %[[BB3_LABEL:.*]](0x4a1af2a5)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], -8826, implicit-def $eflags ; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], -8826, implicit-def $eflags
; CHECK: JCC_1 %[[CASE2_LABEL]], 4, implicit $eflags ; CHECK: JCC_1 %[[CASE2_LABEL]], 4, implicit $eflags
; CHECK: JMP_1 %[[BB3_LABEL]] ; CHECK: JMP_1 %[[BB3_LABEL]]
; CHECK: [[BB3_LABEL]] ; CHECK: [[BB3_LABEL]]
; CHECK: successors: %[[CASE5_LABEL:.*]](0x45d173c8), %[[BB4_LABEL:.*]](0x3a2e8c38) ; CHECK: successors: %[[CASE5_LABEL:.*]](0x45d173c8), %[[BB4_LABEL:.*]](0x3a2e8c38)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 129, implicit-def $eflags ; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 129, implicit-def $eflags
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; CHECK: successors: %[[PEELED_CASE_LABEL:.*]](0x59999999), %[[PEELED_SWITCH_LABEL:.*]](0x26666667) ; CHECK: successors: %[[PEELED_CASE_LABEL:.*]](0x59999999), %[[PEELED_SWITCH_LABEL:.*]](0x26666667)
; CHECK: %[[VAL:[0-9]+]]:gr32 = COPY $edi ; CHECK: %[[VAL:[0-9]+]]:gr32 = COPY $edi
; CHECK: %{{[0-9]+}}:gr32 = ADD32ri8 %{{[0-9]+}}, -85, implicit-def dead $eflags ; CHECK: %{{[0-9]+}}:gr32 = ADD32ri8 %{{[0-9]+}}, -85, implicit-def dead $eflags
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %{{[0-9]+}}, 2, implicit-def $eflags ; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %{{[0-9]+}}, 2, implicit-def $eflags
; CHECK: JCC_1 %[[PEELED_CASE_LABEL]], 2, implicit $eflags ; CHECK: JCC_1 %[[PEELED_CASE_LABEL]], 2, implicit $eflags
; CHECK: JMP_1 %[[PEELED_SWITCH_LABEL]] ; CHECK: JMP_1 %[[PEELED_SWITCH_LABEL]]
; CHECK: [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}: ; CHECK: [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[BB1_LABEL:.*]](0x0088888a), %[[BB2_LABEL:.*]](0x7f777776) ; CHECK: successors: %[[BB1_LABEL:.*]](0x0088888a), %[[BB2_LABEL:.*]](0x7f777776)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 4, implicit-def $eflags ; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 5, implicit-def $eflags
; CHECK: JCC_1 %[[BB2_LABEL]], 15, implicit $eflags ; CHECK: JCC_1 %[[BB1_LABEL]], 12, implicit $eflags
; CHECK: JMP_1 %[[BB1_LABEL]] ; CHECK: JMP_1 %[[BB2_LABEL]]
; CHECK: [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}: ; CHECK: [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[CASE4_LABEL:.*]](0x7f775a4f), %[[BB3_LABEL:.*]](0x0088a5b1) ; CHECK: successors: %[[CASE4_LABEL:.*]](0x7f775a4f), %[[BB3_LABEL:.*]](0x0088a5b1)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 1, implicit-def $eflags ; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 1, implicit-def $eflags
; CHECK: JCC_1 %[[CASE4_LABEL]], 4, implicit $eflags ; CHECK: JCC_1 %[[CASE4_LABEL]], 4, implicit $eflags
; CHECK: JMP_1 %[[BB3_LABEL]] ; CHECK: JMP_1 %[[BB3_LABEL]]
; CHECK: [[BB3_LABEL]].{{[a-zA-Z0-9.]+}}: ; CHECK: [[BB3_LABEL]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[CASE1_LABEL:.*]](0x66666666), %[[DEFAULT_BB_LABEL:.*]](0x1999999a) ; CHECK: successors: %[[CASE1_LABEL:.*]](0x66666666), %[[DEFAULT_BB_LABEL:.*]](0x1999999a)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], -40, implicit-def $eflags ; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], -40, implicit-def $eflags
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llvm/test/CodeGen/X86/switch.ll

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; Should be lowered to two range checks. ; Should be lowered to two range checks.
; CHECK-LABEL: simple_ranges ; CHECK-LABEL: simple_ranges
; CHECK: leal -100 ; CHECK: leal -100
; CHECK: cmpl $4 ; CHECK: cmpl $4
; CHECK: jb ; CHECK: jb
; CHECK: cmpl $3 ; CHECK: cmpl $4
; CHECK: ja ; CHECK: jae
; We do this even at -O0, because it's cheap and makes codegen faster. ; We do this even at -O0, because it's cheap and makes codegen faster.
; NOOPT-LABEL: simple_ranges ; NOOPT-LABEL: simple_ranges
; NOOPT: subl $4 ; NOOPT: subl $4
; NOOPT: jb ; NOOPT: jb
; NOOPT: addl $-100 ; NOOPT: addl $-100
; NOOPT: subl $4 ; NOOPT: subl $4
; NOOPT: jb ; NOOPT: jb
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] ]
bb0: tail call void @g(i32 0) br label %return bb0: tail call void @g(i32 0) br label %return
bb1: tail call void @g(i32 1) br label %return bb1: tail call void @g(i32 1) br label %return
return: ret void return: ret void
; Should pivot around 400 for two subtrees of equal size. ; Should pivot around 400 for two subtrees of equal size.
; CHECK-LABEL: optimal_pivot1 ; CHECK-LABEL: optimal_pivot1
; CHECK-NOT: cmpl ; CHECK-NOT: cmpl
; CHECK: cmpl $399 ; CHECK: cmpl $400
} }
define void @optimal_pivot2(i32 %x) { define void @optimal_pivot2(i32 %x) {
entry: entry:
switch i32 %x, label %return [ switch i32 %x, label %return [
i32 100, label %bb0 i32 101, label %bb1 i32 102, label %bb2 i32 103, label %bb3 i32 100, label %bb0 i32 101, label %bb1 i32 102, label %bb2 i32 103, label %bb3
i32 200, label %bb0 i32 201, label %bb1 i32 202, label %bb2 i32 203, label %bb3 i32 200, label %bb0 i32 201, label %bb1 i32 202, label %bb2 i32 203, label %bb3
i32 300, label %bb0 i32 301, label %bb1 i32 302, label %bb2 i32 303, label %bb3 i32 300, label %bb0 i32 301, label %bb1 i32 302, label %bb2 i32 303, label %bb3
i32 400, label %bb0 i32 401, label %bb1 i32 402, label %bb2 i32 403, label %bb3 i32 400, label %bb0 i32 401, label %bb1 i32 402, label %bb2 i32 403, label %bb3
] ]
bb0: tail call void @g(i32 0) br label %return bb0: tail call void @g(i32 0) br label %return
bb1: tail call void @g(i32 1) br label %return bb1: tail call void @g(i32 1) br label %return
bb2: tail call void @g(i32 2) br label %return bb2: tail call void @g(i32 2) br label %return
bb3: tail call void @g(i32 3) br label %return bb3: tail call void @g(i32 3) br label %return
return: ret void return: ret void
; Should pivot around 300 for two subtrees with two jump tables each. ; Should pivot around 300 for two subtrees with two jump tables each.
; CHECK-LABEL: optimal_pivot2 ; CHECK-LABEL: optimal_pivot2
; CHECK-NOT: cmpl ; CHECK-NOT: cmpl
; CHECK: cmpl $299 ; CHECK: cmpl $300
; CHECK: jmpq *.LJTI ; CHECK: jmpq *.LJTI
; CHECK: jmpq *.LJTI ; CHECK: jmpq *.LJTI
; CHECK: jmpq *.LJTI ; CHECK: jmpq *.LJTI
; CHECK: jmpq *.LJTI ; CHECK: jmpq *.LJTI
} }
define void @optimal_jump_table1(i32 %x) { define void @optimal_jump_table1(i32 %x) {
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bb3: tail call void @g(i32 3) br label %return bb3: tail call void @g(i32 3) br label %return
bb4: tail call void @g(i32 4) br label %return bb4: tail call void @g(i32 4) br label %return
bb5: tail call void @g(i32 5) br label %return bb5: tail call void @g(i32 5) br label %return
return: ret void return: ret void
; Make sure to pick a pivot in the middle also with zero-weight cases. ; Make sure to pick a pivot in the middle also with zero-weight cases.
; CHECK-LABEL: zero_weight_tree ; CHECK-LABEL: zero_weight_tree
; CHECK-NOT: cmpl ; CHECK-NOT: cmpl
; CHECK: cmpl $29 ; CHECK: cmpl $30
} }
!3 = !{!"branch_weights", i32 1, i32 10, i32 0, i32 0, i32 0, i32 0, i32 10} !3 = !{!"branch_weights", i32 1, i32 10, i32 0, i32 0, i32 0, i32 0, i32 10}
define void @left_leaning_weight_balanced_tree(i32 %x) { define void @left_leaning_weight_balanced_tree(i32 %x) {
entry: entry:
switch i32 %x, label %return [ switch i32 %x, label %return [
Show All 18 Lines
; Without branch probabilities, the pivot would be 40, since that would yield ; Without branch probabilities, the pivot would be 40, since that would yield
; equal-sized sub-trees. When taking weights into account, case 70 becomes the ; equal-sized sub-trees. When taking weights into account, case 70 becomes the
; pivot. Since there is room for 3 cases in a leaf, cases 50 and 60 are also ; pivot. Since there is room for 3 cases in a leaf, cases 50 and 60 are also
; included in the right-hand side because that doesn't reduce their rank. ; included in the right-hand side because that doesn't reduce their rank.
; CHECK-LABEL: left_leaning_weight_balanced_tree ; CHECK-LABEL: left_leaning_weight_balanced_tree
; CHECK-NOT: cmpl ; CHECK-NOT: cmpl
; CHECK: cmpl $49 ; CHECK: cmpl $50
} }
!4 = !{!"branch_weights", i32 1, i32 10, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1000} !4 = !{!"branch_weights", i32 1, i32 10, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1000}
define void @left_leaning_weight_balanced_tree2(i32 %x) { define void @left_leaning_weight_balanced_tree2(i32 %x) {
entry: entry:
switch i32 %x, label %return [ switch i32 %x, label %return [
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return: ret void return: ret void
; Same as the previous test, except case 50 has higher rank to the left than it ; Same as the previous test, except case 50 has higher rank to the left than it
; would have on the right. Case 60 would have the same rank on both sides, so is ; would have on the right. Case 60 would have the same rank on both sides, so is
; moved into the leaf. ; moved into the leaf.
; CHECK-LABEL: left_leaning_weight_balanced_tree2 ; CHECK-LABEL: left_leaning_weight_balanced_tree2
; CHECK-NOT: cmpl ; CHECK-NOT: cmpl
; CHECK: cmpl $59 ; CHECK: cmpl $60
} }
!5 = !{!"branch_weights", i32 1, i32 10, i32 1, i32 1, i32 1, i32 1, i32 90, i32 70, i32 1000} !5 = !{!"branch_weights", i32 1, i32 10, i32 1, i32 1, i32 1, i32 1, i32 90, i32 70, i32 1000}
define void @right_leaning_weight_balanced_tree(i32 %x) { define void @right_leaning_weight_balanced_tree(i32 %x) {
entry: entry:
switch i32 %x, label %return [ switch i32 %x, label %return [
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bb6: tail call void @g(i32 6) br label %return bb6: tail call void @g(i32 6) br label %return
bb7: tail call void @g(i32 7) br label %return bb7: tail call void @g(i32 7) br label %return
return: ret void return: ret void
; Analogous to left_leaning_weight_balanced_tree. ; Analogous to left_leaning_weight_balanced_tree.
; CHECK-LABEL: right_leaning_weight_balanced_tree ; CHECK-LABEL: right_leaning_weight_balanced_tree
; CHECK-NOT: cmpl ; CHECK-NOT: cmpl
; CHECK: cmpl $19 ; CHECK: cmpl $20
} }
!6 = !{!"branch_weights", i32 1, i32 1000, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 10} !6 = !{!"branch_weights", i32 1, i32 1000, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 10}
define void @jump_table_affects_balance(i32 %x) { define void @jump_table_affects_balance(i32 %x) {
entry: entry:
switch i32 %x, label %return [ switch i32 %x, label %return [
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bb3: tail call void @g(i32 3) br label %return bb3: tail call void @g(i32 3) br label %return
return: ret void return: ret void
; CHECK-LABEL: jump_table_affects_balance ; CHECK-LABEL: jump_table_affects_balance
; If the tree were balanced based on number of clusters, {0-3,100} would go on ; If the tree were balanced based on number of clusters, {0-3,100} would go on
; the left and {200,300} on the right. However, the jump table weights as much ; the left and {200,300} on the right. However, the jump table weights as much
; as its components, so 100 is selected as the pivot. ; as its components, so 100 is selected as the pivot.
; CHECK-NOT: cmpl ; CHECK-NOT: cmpl
; CHECK: cmpl $99 ; CHECK: cmpl $100
} }
define void @pr23738(i4 %x) { define void @pr23738(i4 %x) {
entry: entry:
switch i4 %x, label %bb0 [ switch i4 %x, label %bb0 [
i4 0, label %bb1 i4 0, label %bb1
i4 1, label %bb1 i4 1, label %bb1
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llvm/test/CodeGen/X86/tail-dup-asm-goto.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=x86_64-linux -stop-after=early-tailduplication < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-linux -stop-after=early-tailduplication < %s | FileCheck %s
; Ensure that we don't duplicate a block with an "INLINEASM_BR" instruction ; Ensure that we don't duplicate a block with an "INLINEASM_BR" instruction
; during code gen. ; during code gen.
declare dso_local void @foo() declare dso_local void @foo()
define i8* @test1(i8** %arg1, i8* %arg2) { define i8* @test1(i8** %arg1, i8* %arg2) {
; CHECK-LABEL: name: test1 ; CHECK-LABEL: name: test1
; CHECK: bb.0.bb: ; CHECK: bb.0.bb:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000) ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $rdi, $rsi ; CHECK: liveins: $rdi, $rsi
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.arg1) ; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.arg1)
; CHECK: [[SUB64rr:%[0-9]+]]:gr64 = SUB64rr [[MOV64rm]], [[COPY]], implicit-def $eflags ; CHECK: [[SUB64rr:%[0-9]+]]:gr64 = SUB64rr [[MOV64rm]], [[COPY]], implicit-def $eflags
; CHECK: JCC_1 %bb.2, 4, implicit $eflags ; CHECK: JCC_1 %bb.1, 5, implicit $eflags
; CHECK: JMP_1 %bb.1 ; CHECK: JMP_1 %bb.2
; CHECK: bb.1.bb100: ; CHECK: bb.1.bb100:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: MOV64mi32 [[COPY1]], 1, $noreg, 0, $noreg, 0 :: (store (s64) into %ir.arg1) ; CHECK: MOV64mi32 [[COPY1]], 1, $noreg, 0, $noreg, 0 :: (store (s64) into %ir.arg1)
; CHECK: JMP_1 %bb.3 ; CHECK: JMP_1 %bb.3
; CHECK: bb.2.bb106: ; CHECK: bb.2.bb106:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp ; CHECK: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK: CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp ; CHECK: CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp
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llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; CHECK-NEXT: pushq %r14 ; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %r13 ; CHECK-NEXT: pushq %r13
; CHECK-NEXT: pushq %r12 ; CHECK-NEXT: pushq %r12
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movl $1, %ebx ; CHECK-NEXT: movl $1, %ebx
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB1_27 ; CHECK-NEXT: je .LBB1_27
; CHECK-NEXT: # %bb.1: # %if.end19 ; CHECK-NEXT: # %bb.1: # %if.end19
; CHECK-NEXT: movl %esi, %r13d ; CHECK-NEXT: movl %esi, %r13d
; CHECK-NEXT: movq %rdi, %r12 ; CHECK-NEXT: movq %rdi, %r12
; CHECK-NEXT: movl (%rax), %ebp ; CHECK-NEXT: movl (%rax), %ebp
; CHECK-NEXT: leal (,%rbp,4), %r14d ; CHECK-NEXT: leal (,%rbp,4), %r14d
; CHECK-NEXT: movl %r14d, %r15d ; CHECK-NEXT: movl %r14d, %r15d
; CHECK-NEXT: movl $1, %esi ; CHECK-NEXT: movl $1, %esi
; CHECK-NEXT: movq %r15, %rdi ; CHECK-NEXT: movq %r15, %rdi
Show All 10 Lines
; CHECK-NEXT: jne .LBB1_26 ; CHECK-NEXT: jne .LBB1_26
; CHECK-NEXT: # %bb.4: # %if.end19 ; CHECK-NEXT: # %bb.4: # %if.end19
; CHECK-NEXT: cmpq %r12, %rbx ; CHECK-NEXT: cmpq %r12, %rbx
; CHECK-NEXT: jb .LBB1_26 ; CHECK-NEXT: jb .LBB1_26
; CHECK-NEXT: # %bb.5: # %if.end50 ; CHECK-NEXT: # %bb.5: # %if.end50
; CHECK-NEXT: movq %rbx, %rdi ; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: movq %r15, %rdx ; CHECK-NEXT: movq %r15, %rdx
; CHECK-NEXT: callq memcpy@PLT ; CHECK-NEXT: callq memcpy@PLT
; CHECK-NEXT: cmpl $4, %r14d ; CHECK-NEXT: cmpl $3, %r14d
; CHECK-NEXT: jb .LBB1_29 ; CHECK-NEXT: jbe .LBB1_29
; CHECK-NEXT: # %bb.6: # %shared_preheader ; CHECK-NEXT: # %bb.6: # %shared_preheader
; CHECK-NEXT: movb $32, %dl ; CHECK-NEXT: movb $32, %dl
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: # implicit-def: $rcx ; CHECK-NEXT: # implicit-def: $rcx
; CHECK-NEXT: jmp .LBB1_9 ; CHECK-NEXT: jmp .LBB1_9
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB1_7: # %merge_predecessor_split ; CHECK-NEXT: .LBB1_7: # %merge_predecessor_split
; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1
Show All 17 Lines
; CHECK-NEXT: testq %rbx, %rbx ; CHECK-NEXT: testq %rbx, %rbx
; CHECK-NEXT: jne .LBB1_28 ; CHECK-NEXT: jne .LBB1_28
; CHECK-NEXT: # %bb.11: # %inner_loop_body ; CHECK-NEXT: # %bb.11: # %inner_loop_body
; CHECK-NEXT: # in Loop: Header=BB1_10 Depth=2 ; CHECK-NEXT: # in Loop: Header=BB1_10 Depth=2
; CHECK-NEXT: testl %eax, %eax ; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: jns .LBB1_10 ; CHECK-NEXT: jns .LBB1_10
; CHECK-NEXT: # %bb.12: # %if.end96.i ; CHECK-NEXT: # %bb.12: # %if.end96.i
; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1
; CHECK-NEXT: cmpl $3, %ebp ; CHECK-NEXT: cmpl $2, %ebp
; CHECK-NEXT: jae .LBB1_23 ; CHECK-NEXT: ja .LBB1_23
; CHECK-NEXT: # %bb.13: # %if.end287.i ; CHECK-NEXT: # %bb.13: # %if.end287.i
; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1
; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: cmpl $1, %ebp ; CHECK-NEXT: cmpl $1, %ebp
; CHECK-NEXT: setne %dl ; CHECK-NEXT: setne %dl
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB1_17 ; CHECK-NEXT: je .LBB1_17
; CHECK-NEXT: # %bb.14: # %if.end308.i ; CHECK-NEXT: # %bb.14: # %if.end308.i
; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je .LBB1_7 ; CHECK-NEXT: je .LBB1_7
; CHECK-NEXT: # %bb.15: # %if.end335.i ; CHECK-NEXT: # %bb.15: # %if.end335.i
; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1
; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: testb %dl, %dl ; CHECK-NEXT: testb %dl, %dl
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llvm/test/CodeGen/X86/tail-opts.ll

Show First 20 Lines • Show All 241 Lines • ▼ Show 20 Lines
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB3_9 ; CHECK-NEXT: jne .LBB3_9
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: movb 0, %bl ; CHECK-NEXT: movb 0, %bl
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB3_8 ; CHECK-NEXT: je .LBB3_8
; CHECK-NEXT: # %bb.2: # %bb.i ; CHECK-NEXT: # %bb.2: # %bb.i
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je .LBB3_8 ; CHECK-NEXT: je .LBB3_8
; CHECK-NEXT: # %bb.3: # %lvalue_p.exit ; CHECK-NEXT: # %bb.3: # %lvalue_p.exit
; CHECK-NEXT: movq 0, %rax ; CHECK-NEXT: movq 0, %rax
; CHECK-NEXT: movzbl (%rax), %ecx ; CHECK-NEXT: movzbl (%rax), %ecx
; CHECK-NEXT: testl %ecx, %ecx ; CHECK-NEXT: testl %ecx, %ecx
▲ Show 20 Lines • Show All 672 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll

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define void @vector_variable_shift_left_loop(i32* nocapture %arr, i8* nocapture readonly %control, i32 %count, i32 %amt0, i32 %amt1) nounwind { define void @vector_variable_shift_left_loop(i32* nocapture %arr, i8* nocapture readonly %control, i32 %count, i32 %amt0, i32 %amt1) nounwind {
; SSE-LABEL: vector_variable_shift_left_loop: ; SSE-LABEL: vector_variable_shift_left_loop:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
; SSE-NEXT: testl %edx, %edx ; SSE-NEXT: testl %edx, %edx
; SSE-NEXT: jle .LBB0_9 ; SSE-NEXT: jle .LBB0_9
; SSE-NEXT: # %bb.1: # %for.body.preheader ; SSE-NEXT: # %bb.1: # %for.body.preheader
; SSE-NEXT: movl %ecx, %r9d ; SSE-NEXT: movl %ecx, %r9d
; SSE-NEXT: movl %edx, %eax ; SSE-NEXT: movl %edx, %eax
; SSE-NEXT: cmpl $31, %edx ; SSE-NEXT: cmpl $32, %edx
; SSE-NEXT: ja .LBB0_3 ; SSE-NEXT: jae .LBB0_3
; SSE-NEXT: # %bb.2: ; SSE-NEXT: # %bb.2:
; SSE-NEXT: xorl %edx, %edx ; SSE-NEXT: xorl %edx, %edx
; SSE-NEXT: jmp .LBB0_6 ; SSE-NEXT: jmp .LBB0_6
; SSE-NEXT: .LBB0_3: # %vector.ph ; SSE-NEXT: .LBB0_3: # %vector.ph
; SSE-NEXT: movl %eax, %edx ; SSE-NEXT: movl %eax, %edx
; SSE-NEXT: andl $-32, %edx ; SSE-NEXT: andl $-32, %edx
; SSE-NEXT: movd %r9d, %xmm0 ; SSE-NEXT: movd %r9d, %xmm0
; SSE-NEXT: movd %r8d, %xmm2 ; SSE-NEXT: movd %r8d, %xmm2
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; ;
; AVX1-LABEL: vector_variable_shift_left_loop: ; AVX1-LABEL: vector_variable_shift_left_loop:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: testl %edx, %edx ; AVX1-NEXT: testl %edx, %edx
; AVX1-NEXT: jle .LBB0_9 ; AVX1-NEXT: jle .LBB0_9
; AVX1-NEXT: # %bb.1: # %for.body.preheader ; AVX1-NEXT: # %bb.1: # %for.body.preheader
; AVX1-NEXT: movl %ecx, %r9d ; AVX1-NEXT: movl %ecx, %r9d
; AVX1-NEXT: movl %edx, %eax ; AVX1-NEXT: movl %edx, %eax
; AVX1-NEXT: cmpl $31, %edx ; AVX1-NEXT: cmpl $32, %edx
; AVX1-NEXT: ja .LBB0_3 ; AVX1-NEXT: jae .LBB0_3
; AVX1-NEXT: # %bb.2: ; AVX1-NEXT: # %bb.2:
; AVX1-NEXT: xorl %edx, %edx ; AVX1-NEXT: xorl %edx, %edx
; AVX1-NEXT: jmp .LBB0_6 ; AVX1-NEXT: jmp .LBB0_6
; AVX1-NEXT: .LBB0_3: # %vector.ph ; AVX1-NEXT: .LBB0_3: # %vector.ph
; AVX1-NEXT: movl %eax, %edx ; AVX1-NEXT: movl %eax, %edx
; AVX1-NEXT: andl $-32, %edx ; AVX1-NEXT: andl $-32, %edx
; AVX1-NEXT: vmovd %r9d, %xmm0 ; AVX1-NEXT: vmovd %r9d, %xmm0
; AVX1-NEXT: vmovd %r8d, %xmm1 ; AVX1-NEXT: vmovd %r8d, %xmm1
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; ;
; AVX2-LABEL: vector_variable_shift_left_loop: ; AVX2-LABEL: vector_variable_shift_left_loop:
; AVX2: # %bb.0: # %entry ; AVX2: # %bb.0: # %entry
; AVX2-NEXT: testl %edx, %edx ; AVX2-NEXT: testl %edx, %edx
; AVX2-NEXT: jle .LBB0_9 ; AVX2-NEXT: jle .LBB0_9
; AVX2-NEXT: # %bb.1: # %for.body.preheader ; AVX2-NEXT: # %bb.1: # %for.body.preheader
; AVX2-NEXT: movl %ecx, %r9d ; AVX2-NEXT: movl %ecx, %r9d
; AVX2-NEXT: movl %edx, %eax ; AVX2-NEXT: movl %edx, %eax
; AVX2-NEXT: cmpl $31, %edx ; AVX2-NEXT: cmpl $32, %edx
; AVX2-NEXT: ja .LBB0_3 ; AVX2-NEXT: jae .LBB0_3
; AVX2-NEXT: # %bb.2: ; AVX2-NEXT: # %bb.2:
; AVX2-NEXT: xorl %edx, %edx ; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: jmp .LBB0_6 ; AVX2-NEXT: jmp .LBB0_6
; AVX2-NEXT: .LBB0_3: # %vector.ph ; AVX2-NEXT: .LBB0_3: # %vector.ph
; AVX2-NEXT: movl %eax, %edx ; AVX2-NEXT: movl %eax, %edx
; AVX2-NEXT: andl $-32, %edx ; AVX2-NEXT: andl $-32, %edx
; AVX2-NEXT: vmovd %r9d, %xmm0 ; AVX2-NEXT: vmovd %r9d, %xmm0
; AVX2-NEXT: vpbroadcastd %xmm0, %ymm0 ; AVX2-NEXT: vpbroadcastd %xmm0, %ymm0
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; ;
; XOP-LABEL: vector_variable_shift_left_loop: ; XOP-LABEL: vector_variable_shift_left_loop:
; XOP: # %bb.0: # %entry ; XOP: # %bb.0: # %entry
; XOP-NEXT: testl %edx, %edx ; XOP-NEXT: testl %edx, %edx
; XOP-NEXT: jle .LBB0_9 ; XOP-NEXT: jle .LBB0_9
; XOP-NEXT: # %bb.1: # %for.body.preheader ; XOP-NEXT: # %bb.1: # %for.body.preheader
; XOP-NEXT: movl %ecx, %r9d ; XOP-NEXT: movl %ecx, %r9d
; XOP-NEXT: movl %edx, %eax ; XOP-NEXT: movl %edx, %eax
; XOP-NEXT: cmpl $31, %edx ; XOP-NEXT: cmpl $32, %edx
; XOP-NEXT: ja .LBB0_3 ; XOP-NEXT: jae .LBB0_3
; XOP-NEXT: # %bb.2: ; XOP-NEXT: # %bb.2:
; XOP-NEXT: xorl %edx, %edx ; XOP-NEXT: xorl %edx, %edx
; XOP-NEXT: jmp .LBB0_6 ; XOP-NEXT: jmp .LBB0_6
; XOP-NEXT: .LBB0_3: # %vector.ph ; XOP-NEXT: .LBB0_3: # %vector.ph
; XOP-NEXT: movl %eax, %edx ; XOP-NEXT: movl %eax, %edx
; XOP-NEXT: andl $-32, %edx ; XOP-NEXT: andl $-32, %edx
; XOP-NEXT: vmovd %r9d, %xmm0 ; XOP-NEXT: vmovd %r9d, %xmm0
; XOP-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] ; XOP-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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llvm/test/CodeGen/X86/widen_cast-1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=i686-unknown-unknown -mattr=+sse4.2 < %s | FileCheck %s ; RUN: llc -mtriple=i686-unknown-unknown -mattr=+sse4.2 < %s | FileCheck %s
; RUN: llc -mtriple=i686-unknown-unknown -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s ; RUN: llc -mtriple=i686-unknown-unknown -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s
; Scheduler causes produce a different instruction order ; Scheduler causes produce a different instruction order
; bitcast a v4i16 to v2i32 ; bitcast a v4i16 to v2i32
define void @convert(<2 x i32>* %dst, <4 x i16>* %src) nounwind { define void @convert(<2 x i32>* %dst, <4 x i16>* %src) nounwind {
; CHECK-LABEL: convert: ; CHECK-LABEL: convert:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %eax ; CHECK-NEXT: pushl %eax
; CHECK-NEXT: movl $0, (%esp) ; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-NEXT: cmpl $3, (%esp) ; CHECK-NEXT: cmpl $4, (%esp)
; CHECK-NEXT: jg .LBB0_3 ; CHECK-NEXT: jge .LBB0_3
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_2: # %forbody ; CHECK-NEXT: .LBB0_2: # %forbody
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl (%esp), %eax ; CHECK-NEXT: movl (%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: movq {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: psubw %xmm0, %xmm1 ; CHECK-NEXT: psubw %xmm0, %xmm1
; CHECK-NEXT: movq %xmm1, (%ecx,%eax,8) ; CHECK-NEXT: movq %xmm1, (%ecx,%eax,8)
; CHECK-NEXT: incl (%esp) ; CHECK-NEXT: incl (%esp)
; CHECK-NEXT: cmpl $3, (%esp) ; CHECK-NEXT: cmpl $4, (%esp)
; CHECK-NEXT: jle .LBB0_2 ; CHECK-NEXT: jl .LBB0_2
; CHECK-NEXT: .LBB0_3: # %afterfor ; CHECK-NEXT: .LBB0_3: # %afterfor
; CHECK-NEXT: popl %eax ; CHECK-NEXT: popl %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
; ;
; ATOM-LABEL: convert: ; ATOM-LABEL: convert:
; ATOM: # %bb.0: # %entry ; ATOM: # %bb.0: # %entry
; ATOM-NEXT: pushl %eax ; ATOM-NEXT: pushl %eax
; ATOM-NEXT: pcmpeqd %xmm0, %xmm0 ; ATOM-NEXT: pcmpeqd %xmm0, %xmm0
; ATOM-NEXT: movl $0, (%esp) ; ATOM-NEXT: movl $0, (%esp)
; ATOM-NEXT: cmpl $3, (%esp) ; ATOM-NEXT: cmpl $4, (%esp)
; ATOM-NEXT: jg .LBB0_3 ; ATOM-NEXT: jge .LBB0_3
; ATOM-NEXT: .p2align 4, 0x90 ; ATOM-NEXT: .p2align 4, 0x90
; ATOM-NEXT: .LBB0_2: # %forbody ; ATOM-NEXT: .LBB0_2: # %forbody
; ATOM-NEXT: # =>This Inner Loop Header: Depth=1 ; ATOM-NEXT: # =>This Inner Loop Header: Depth=1
; ATOM-NEXT: movl (%esp), %eax ; ATOM-NEXT: movl (%esp), %eax
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %ecx ; ATOM-NEXT: movl {{[0-9]+}}(%esp), %ecx
; ATOM-NEXT: movq {{.*#+}} xmm1 = mem[0],zero ; ATOM-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %ecx ; ATOM-NEXT: movl {{[0-9]+}}(%esp), %ecx
; ATOM-NEXT: psubw %xmm0, %xmm1 ; ATOM-NEXT: psubw %xmm0, %xmm1
; ATOM-NEXT: movq %xmm1, (%ecx,%eax,8) ; ATOM-NEXT: movq %xmm1, (%ecx,%eax,8)
; ATOM-NEXT: incl (%esp) ; ATOM-NEXT: incl (%esp)
; ATOM-NEXT: cmpl $3, (%esp) ; ATOM-NEXT: cmpl $4, (%esp)
; ATOM-NEXT: jle .LBB0_2 ; ATOM-NEXT: jl .LBB0_2
; ATOM-NEXT: .LBB0_3: # %afterfor ; ATOM-NEXT: .LBB0_3: # %afterfor
; ATOM-NEXT: popl %eax ; ATOM-NEXT: popl %eax
; ATOM-NEXT: retl ; ATOM-NEXT: retl
entry: entry:
%dst.addr = alloca <2 x i32>* %dst.addr = alloca <2 x i32>*
%src.addr = alloca <4 x i16>* %src.addr = alloca <4 x i16>*
%i = alloca i32, align 4 %i = alloca i32, align 4
store <2 x i32>* %dst, <2 x i32>** %dst.addr store <2 x i32>* %dst, <2 x i32>** %dst.addr
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llvm/test/CodeGen/X86/widen_cast-2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.2 | FileCheck %s ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.2 | FileCheck %s
; bitcast v14i16 to v7i32 ; bitcast v14i16 to v7i32
define void @convert(<7 x i32>* %dst, <14 x i16>* %src) nounwind { define void @convert(<7 x i32>* %dst, <14 x i16>* %src) nounwind {
; CHECK-LABEL: convert: ; CHECK-LABEL: convert:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %eax ; CHECK-NEXT: pushl %eax
; CHECK-NEXT: movl $0, (%esp) ; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-NEXT: cmpl $3, (%esp) ; CHECK-NEXT: cmpl $4, (%esp)
; CHECK-NEXT: jg .LBB0_3 ; CHECK-NEXT: jge .LBB0_3
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_2: # %forbody ; CHECK-NEXT: .LBB0_2: # %forbody
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl (%esp), %eax ; CHECK-NEXT: movl (%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: shll $5, %eax ; CHECK-NEXT: shll $5, %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: movdqa (%edx,%eax), %xmm1 ; CHECK-NEXT: movdqa (%edx,%eax), %xmm1
; CHECK-NEXT: movdqa 16(%edx,%eax), %xmm2 ; CHECK-NEXT: movdqa 16(%edx,%eax), %xmm2
; CHECK-NEXT: psubw %xmm0, %xmm2 ; CHECK-NEXT: psubw %xmm0, %xmm2
; CHECK-NEXT: psubw %xmm0, %xmm1 ; CHECK-NEXT: psubw %xmm0, %xmm1
; CHECK-NEXT: movdqa %xmm1, (%ecx,%eax) ; CHECK-NEXT: movdqa %xmm1, (%ecx,%eax)
; CHECK-NEXT: movd %xmm2, 16(%ecx,%eax) ; CHECK-NEXT: movd %xmm2, 16(%ecx,%eax)
; CHECK-NEXT: pextrd $1, %xmm2, 20(%ecx,%eax) ; CHECK-NEXT: pextrd $1, %xmm2, 20(%ecx,%eax)
; CHECK-NEXT: pextrd $2, %xmm2, 24(%ecx,%eax) ; CHECK-NEXT: pextrd $2, %xmm2, 24(%ecx,%eax)
; CHECK-NEXT: incl (%esp) ; CHECK-NEXT: incl (%esp)
; CHECK-NEXT: cmpl $3, (%esp) ; CHECK-NEXT: cmpl $4, (%esp)
; CHECK-NEXT: jle .LBB0_2 ; CHECK-NEXT: jl .LBB0_2
; CHECK-NEXT: .LBB0_3: # %afterfor ; CHECK-NEXT: .LBB0_3: # %afterfor
; CHECK-NEXT: popl %eax ; CHECK-NEXT: popl %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%dst.addr = alloca <7 x i32>* %dst.addr = alloca <7 x i32>*
%src.addr = alloca <14 x i16>* %src.addr = alloca <14 x i16>*
%i = alloca i32, align 4 %i = alloca i32, align 4
store <7 x i32>* %dst, <7 x i32>** %dst.addr store <7 x i32>* %dst, <7 x i32>** %dst.addr
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llvm/test/CodeGen/X86/x32-va_start.ll

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; SSE-NEXT: .LBB0_5: # %entry ; SSE-NEXT: .LBB0_5: # %entry
; SSE-NEXT: leal -{{[0-9]+}}(%rsp), %eax ; SSE-NEXT: leal -{{[0-9]+}}(%rsp), %eax
; SSE-NEXT: movl %eax, -{{[0-9]+}}(%esp) ; SSE-NEXT: movl %eax, -{{[0-9]+}}(%esp)
; SSE-NEXT: leal {{[0-9]+}}(%rsp), %eax ; SSE-NEXT: leal {{[0-9]+}}(%rsp), %eax
; SSE-NEXT: movl %eax, -{{[0-9]+}}(%esp) ; SSE-NEXT: movl %eax, -{{[0-9]+}}(%esp)
; SSE-NEXT: movabsq $274877906952, %rax # imm = 0x4000000008 ; SSE-NEXT: movabsq $274877906952, %rax # imm = 0x4000000008
; SSE-NEXT: movq %rax, -{{[0-9]+}}(%esp) ; SSE-NEXT: movq %rax, -{{[0-9]+}}(%esp)
; SSE-NEXT: movl $8, %ecx ; SSE-NEXT: movl $8, %ecx
; SSE-NEXT: cmpl $40, %ecx ; SSE-NEXT: cmpl $41, %ecx
; SSE-NEXT: ja .LBB0_2 ; SSE-NEXT: jae .LBB0_2
; SSE-NEXT: # %bb.1: # %vaarg.in_reg ; SSE-NEXT: # %bb.1: # %vaarg.in_reg
; SSE-NEXT: movl -{{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl -{{[0-9]+}}(%esp), %eax
; SSE-NEXT: addl %ecx, %eax ; SSE-NEXT: addl %ecx, %eax
; SSE-NEXT: addl $8, %ecx ; SSE-NEXT: addl $8, %ecx
; SSE-NEXT: movl %ecx, -{{[0-9]+}}(%esp) ; SSE-NEXT: movl %ecx, -{{[0-9]+}}(%esp)
; SSE-NEXT: jmp .LBB0_3 ; SSE-NEXT: jmp .LBB0_3
; SSE-NEXT: .LBB0_2: # %vaarg.in_mem ; SSE-NEXT: .LBB0_2: # %vaarg.in_mem
; SSE-NEXT: movl -{{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl -{{[0-9]+}}(%esp), %eax
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; NOSSE-NEXT: movq %r9, -{{[0-9]+}}(%esp) ; NOSSE-NEXT: movq %r9, -{{[0-9]+}}(%esp)
; NOSSE-NEXT: leal -{{[0-9]+}}(%rsp), %eax ; NOSSE-NEXT: leal -{{[0-9]+}}(%rsp), %eax
; NOSSE-NEXT: movl %eax, -{{[0-9]+}}(%esp) ; NOSSE-NEXT: movl %eax, -{{[0-9]+}}(%esp)
; NOSSE-NEXT: leal {{[0-9]+}}(%rsp), %eax ; NOSSE-NEXT: leal {{[0-9]+}}(%rsp), %eax
; NOSSE-NEXT: movl %eax, -{{[0-9]+}}(%esp) ; NOSSE-NEXT: movl %eax, -{{[0-9]+}}(%esp)
; NOSSE-NEXT: movabsq $206158430216, %rax # imm = 0x3000000008 ; NOSSE-NEXT: movabsq $206158430216, %rax # imm = 0x3000000008
; NOSSE-NEXT: movq %rax, -{{[0-9]+}}(%esp) ; NOSSE-NEXT: movq %rax, -{{[0-9]+}}(%esp)
; NOSSE-NEXT: movl $8, %ecx ; NOSSE-NEXT: movl $8, %ecx
; NOSSE-NEXT: cmpl $40, %ecx ; NOSSE-NEXT: cmpl $41, %ecx
; NOSSE-NEXT: ja .LBB0_2 ; NOSSE-NEXT: jae .LBB0_2
; NOSSE-NEXT: # %bb.1: # %vaarg.in_reg ; NOSSE-NEXT: # %bb.1: # %vaarg.in_reg
; NOSSE-NEXT: movl -{{[0-9]+}}(%esp), %eax ; NOSSE-NEXT: movl -{{[0-9]+}}(%esp), %eax
; NOSSE-NEXT: addl %ecx, %eax ; NOSSE-NEXT: addl %ecx, %eax
; NOSSE-NEXT: addl $8, %ecx ; NOSSE-NEXT: addl $8, %ecx
; NOSSE-NEXT: movl %ecx, -{{[0-9]+}}(%esp) ; NOSSE-NEXT: movl %ecx, -{{[0-9]+}}(%esp)
; NOSSE-NEXT: movl (%eax), %eax ; NOSSE-NEXT: movl (%eax), %eax
; NOSSE-NEXT: retq ; NOSSE-NEXT: retq
; NOSSE-NEXT: .LBB0_2: # %vaarg.in_mem ; NOSSE-NEXT: .LBB0_2: # %vaarg.in_mem
; NOSSE-NEXT: movl -{{[0-9]+}}(%esp), %eax ; NOSSE-NEXT: movl -{{[0-9]+}}(%esp), %eax
; NOSSE-NEXT: leal 8(%rax), %ecx ; NOSSE-NEXT: leal 8(%rax), %ecx
; NOSSE-NEXT: movl %ecx, -{{[0-9]+}}(%esp) ; NOSSE-NEXT: movl %ecx, -{{[0-9]+}}(%esp)
; NOSSE-NEXT: movl (%eax), %eax ; NOSSE-NEXT: movl (%eax), %eax
; NOSSE-NEXT: retq ; NOSSE-NEXT: retq
; ;
; 32BITABI-LABEL: foo: ; 32BITABI-LABEL: foo:
; 32BITABI: # %bb.0: # %entry ; 32BITABI: # %bb.0: # %entry
; 32BITABI-NEXT: subl $28, %esp ; 32BITABI-NEXT: subl $28, %esp
; 32BITABI-NEXT: leal {{[0-9]+}}(%esp), %ecx ; 32BITABI-NEXT: leal {{[0-9]+}}(%esp), %ecx
; 32BITABI-NEXT: movl %ecx, (%esp) ; 32BITABI-NEXT: movl %ecx, (%esp)
; 32BITABI-NEXT: cmpl $40, %ecx ; 32BITABI-NEXT: cmpl $41, %ecx
; 32BITABI-NEXT: ja .LBB0_2 ; 32BITABI-NEXT: jae .LBB0_2
; 32BITABI-NEXT: # %bb.1: # %vaarg.in_reg ; 32BITABI-NEXT: # %bb.1: # %vaarg.in_reg
; 32BITABI-NEXT: movl {{[0-9]+}}(%esp), %eax ; 32BITABI-NEXT: movl {{[0-9]+}}(%esp), %eax
; 32BITABI-NEXT: addl %ecx, %eax ; 32BITABI-NEXT: addl %ecx, %eax
; 32BITABI-NEXT: addl $8, %ecx ; 32BITABI-NEXT: addl $8, %ecx
; 32BITABI-NEXT: movl %ecx, (%esp) ; 32BITABI-NEXT: movl %ecx, (%esp)
; 32BITABI-NEXT: jmp .LBB0_3 ; 32BITABI-NEXT: jmp .LBB0_3
; 32BITABI-NEXT: .LBB0_2: # %vaarg.in_mem ; 32BITABI-NEXT: .LBB0_2: # %vaarg.in_mem
; 32BITABI-NEXT: movl {{[0-9]+}}(%esp), %eax ; 32BITABI-NEXT: movl {{[0-9]+}}(%esp), %eax
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llvm/test/CodeGen/X86/x86-repmov-copy-eflags.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
target triple = "i686-pc-windows-msvc18.0.0" target triple = "i686-pc-windows-msvc18.0.0"
%struct.T = type { i64, [3 x i32] } %struct.T = type { i64, [3 x i32] }
; Function Attrs: nounwind optsize ; Function Attrs: nounwind optsize
define void @f(i8* %p, i8* %q, i32* inalloca(i32) nocapture %unused) #0 { define void @f(i8* %p, i8* %q, i32* inalloca(i32) nocapture %unused) #0 {
; CHECK-LABEL: f:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: andl $-8, %esp
; CHECK-NEXT: subl $40, %esp
; CHECK-NEXT: movl 8(%ebp), %edi
; CHECK-NEXT: movl 12(%ebp), %esi
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: movl $6, %ecx
; CHECK-NEXT: rep;movsl (%esi), %es:(%edi)
; CHECK-NEXT: leal {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: LBB0_1: # %while.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: decl (%esp)
; CHECK-NEXT: sete %bl
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: calll _g
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: je LBB0_1
; CHECK-NEXT: # %bb.2: # %while.end
; CHECK-NEXT: leal -12(%ebp), %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: popl %ebx
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
entry: entry:
%g = alloca %struct.T, align 8 %g = alloca %struct.T, align 8
%r = alloca i32, align 8 %r = alloca i32, align 8
store i32 0, i32* %r, align 4 store i32 0, i32* %r, align 4
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %p, i8* align 8 %q, i32 24, i1 false) call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %p, i8* align 8 %q, i32 24, i1 false)
br label %while.body br label %while.body
while.body: ; preds = %while.body, %entry while.body: ; preds = %while.body, %entry
%load = load i32, i32* %r, align 4 %load = load i32, i32* %r, align 4
%dec = add nsw i32 %load, -1 %dec = add nsw i32 %load, -1
store i32 %dec, i32* %r, align 4 store i32 %dec, i32* %r, align 4
call void @g(%struct.T* %g) call void @g(%struct.T* %g)
%tobool = icmp eq i32 %dec, 0 %tobool = icmp eq i32 %dec, 0
br i1 %tobool, label %while.end, label %while.body br i1 %tobool, label %while.end, label %while.body
while.end: ; preds = %while.body while.end: ; preds = %while.body
ret void ret void
} }
define void @f_pgso(i8* %p, i8* %q, i32* inalloca(i32) nocapture %unused) !prof !14 { define void @f_pgso(i8* %p, i8* %q, i32* inalloca(i32) nocapture %unused) !prof !14 {
; CHECK-LABEL: f_pgso:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: andl $-8, %esp
; CHECK-NEXT: subl $40, %esp
; CHECK-NEXT: movl 8(%ebp), %edi
; CHECK-NEXT: movl 12(%ebp), %esi
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: movl $6, %ecx
; CHECK-NEXT: rep;movsl (%esi), %es:(%edi)
; CHECK-NEXT: leal {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: LBB1_1: # %while.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: decl (%esp)
; CHECK-NEXT: sete %bl
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: calll _g
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: je LBB1_1
; CHECK-NEXT: # %bb.2: # %while.end
; CHECK-NEXT: leal -12(%ebp), %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: popl %ebx
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
entry: entry:
%g = alloca %struct.T, align 8 %g = alloca %struct.T, align 8
%r = alloca i32, align 8 %r = alloca i32, align 8
store i32 0, i32* %r, align 4 store i32 0, i32* %r, align 4
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %p, i8* align 8 %q, i32 24, i1 false) call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %p, i8* align 8 %q, i32 24, i1 false)
br label %while.body br label %while.body
while.body: ; preds = %while.body, %entry while.body: ; preds = %while.body, %entry
%load = load i32, i32* %r, align 4 %load = load i32, i32* %r, align 4
%dec = add nsw i32 %load, -1 %dec = add nsw i32 %load, -1
store i32 %dec, i32* %r, align 4 store i32 %dec, i32* %r, align 4
call void @g(%struct.T* %g) call void @g(%struct.T* %g)
%tobool = icmp eq i32 %dec, 0 %tobool = icmp eq i32 %dec, 0
br i1 %tobool, label %while.end, label %while.body br i1 %tobool, label %while.end, label %while.body
while.end: ; preds = %while.body while.end: ; preds = %while.body
ret void ret void
} }
; Function Attrs: argmemonly nounwind ; Function Attrs: argmemonly nounwind
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1) #1 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1) #1
declare void @g(%struct.T*) declare void @g(%struct.T*)
; CHECK-LABEL: _f:
; CHECK: pushl %ebp
; CHECK: movl %esp, %ebp
; CHECK: andl $-8, %esp
; CHECK-NOT: movl %esp, %esi
; CHECK: rep;movsl
; CHECK: leal 8(%esp), %esi
; CHECK: decl (%esp)
; CHECK: setne %[[NE_REG:.*]]
; CHECK: pushl %esi
; CHECK: calll _g
; CHECK: addl $4, %esp
; CHECK: testb %[[NE_REG]], %[[NE_REG]]
; CHECK: jne
; CHECK-LABEL: _f_pgso:
; CHECK: pushl %ebp
; CHECK: movl %esp, %ebp
; CHECK: andl $-8, %esp
; CHECK-NOT: movl %esp, %esi
; CHECK: rep;movsl
; CHECK: leal 8(%esp), %esi
; CHECK: decl (%esp)
; CHECK: setne %[[NE_REG:.*]]
; CHECK: pushl %esi
; CHECK: calll _g
; CHECK: addl $4, %esp
; CHECK: testb %[[NE_REG]], %[[NE_REG]]
; CHECK: jne
attributes #0 = { nounwind optsize } attributes #0 = { nounwind optsize }
attributes #1 = { argmemonly nounwind } attributes #1 = { argmemonly nounwind }
!llvm.module.flags = !{!0} !llvm.module.flags = !{!0}
!0 = !{i32 1, !"ProfileSummary", !1} !0 = !{i32 1, !"ProfileSummary", !1}
!1 = !{!2, !3, !4, !5, !6, !7, !8, !9} !1 = !{!2, !3, !4, !5, !6, !7, !8, !9}
!2 = !{!"ProfileFormat", !"InstrProf"} !2 = !{!"ProfileFormat", !"InstrProf"}
!3 = !{!"TotalCount", i64 10000} !3 = !{!"TotalCount", i64 10000}
Show All 11 Lines

llvm/test/CodeGen/X86/x86-shrink-wrapping.ll

Show First 20 Lines • Show All 813 Lines • ▼ Show 20 Lines
; ENABLE-NEXT: .cfi_offset %rbp, -16 ; ENABLE-NEXT: .cfi_offset %rbp, -16
; ENABLE-NEXT: movq %rsp, %rbp ; ENABLE-NEXT: movq %rsp, %rbp
; ENABLE-NEXT: .cfi_def_cfa_register %rbp ; ENABLE-NEXT: .cfi_def_cfa_register %rbp
; ENABLE-NEXT: pushq %rbx ; ENABLE-NEXT: pushq %rbx
; ENABLE-NEXT: pushq %rax ; ENABLE-NEXT: pushq %rax
; ENABLE-NEXT: .cfi_offset %rbx, -24 ; ENABLE-NEXT: .cfi_offset %rbx, -24
; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: xorl %eax, %eax
; ENABLE-NEXT: testb %al, %al ; ENABLE-NEXT: testb %al, %al
; ENABLE-NEXT: jne LBB10_3 ; ENABLE-NEXT: je LBB10_3
; ENABLE-NEXT: ## %bb.1: ## %if.then ; ENABLE-NEXT: ## %bb.1: ## %if.then
; ENABLE-NEXT: movq %rsp, %rcx ; ENABLE-NEXT: movq %rsp, %rcx
; ENABLE-NEXT: addq $-16, %rcx ; ENABLE-NEXT: addq $-16, %rcx
; ENABLE-NEXT: movq %rcx, %rsp ; ENABLE-NEXT: movq %rcx, %rsp
; ENABLE-NEXT: ## InlineAsm Start ; ENABLE-NEXT: ## InlineAsm Start
; ENABLE-NEXT: movl $1, %edx ; ENABLE-NEXT: movl $1, %edx
; ENABLE-NEXT: ## InlineAsm End ; ENABLE-NEXT: ## InlineAsm End
; ENABLE-NEXT: .p2align 4, 0x90 ; ENABLE-NEXT: .p2align 4, 0x90
Show All 15 Lines
; DISABLE-NEXT: .cfi_offset %rbp, -16 ; DISABLE-NEXT: .cfi_offset %rbp, -16
; DISABLE-NEXT: movq %rsp, %rbp ; DISABLE-NEXT: movq %rsp, %rbp
; DISABLE-NEXT: .cfi_def_cfa_register %rbp ; DISABLE-NEXT: .cfi_def_cfa_register %rbp
; DISABLE-NEXT: pushq %rbx ; DISABLE-NEXT: pushq %rbx
; DISABLE-NEXT: pushq %rax ; DISABLE-NEXT: pushq %rax
; DISABLE-NEXT: .cfi_offset %rbx, -24 ; DISABLE-NEXT: .cfi_offset %rbx, -24
; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: xorl %eax, %eax
; DISABLE-NEXT: testb %al, %al ; DISABLE-NEXT: testb %al, %al
; DISABLE-NEXT: jne LBB10_3 ; DISABLE-NEXT: je LBB10_3
; DISABLE-NEXT: ## %bb.1: ## %if.then ; DISABLE-NEXT: ## %bb.1: ## %if.then
; DISABLE-NEXT: movq %rsp, %rcx ; DISABLE-NEXT: movq %rsp, %rcx
; DISABLE-NEXT: addq $-16, %rcx ; DISABLE-NEXT: addq $-16, %rcx
; DISABLE-NEXT: movq %rcx, %rsp ; DISABLE-NEXT: movq %rcx, %rsp
; DISABLE-NEXT: ## InlineAsm Start ; DISABLE-NEXT: ## InlineAsm Start
; DISABLE-NEXT: movl $1, %edx ; DISABLE-NEXT: movl $1, %edx
; DISABLE-NEXT: ## InlineAsm End ; DISABLE-NEXT: ## InlineAsm End
; DISABLE-NEXT: .p2align 4, 0x90 ; DISABLE-NEXT: .p2align 4, 0x90
Show All 34 Lines
; ENABLE-NEXT: .cfi_offset %rbp, -16 ; ENABLE-NEXT: .cfi_offset %rbp, -16
; ENABLE-NEXT: movq %rsp, %rbp ; ENABLE-NEXT: movq %rsp, %rbp
; ENABLE-NEXT: .cfi_def_cfa_register %rbp ; ENABLE-NEXT: .cfi_def_cfa_register %rbp
; ENABLE-NEXT: pushq %rbx ; ENABLE-NEXT: pushq %rbx
; ENABLE-NEXT: pushq %rax ; ENABLE-NEXT: pushq %rax
; ENABLE-NEXT: .cfi_offset %rbx, -24 ; ENABLE-NEXT: .cfi_offset %rbx, -24
; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: xorl %eax, %eax
; ENABLE-NEXT: testb %al, %al ; ENABLE-NEXT: testb %al, %al
; ENABLE-NEXT: jne LBB11_5 ; ENABLE-NEXT: je LBB11_5
; ENABLE-NEXT: ## %bb.1: ## %if.then ; ENABLE-NEXT: ## %bb.1: ## %if.then
; ENABLE-NEXT: movq %rsp, %rcx ; ENABLE-NEXT: movq %rsp, %rcx
; ENABLE-NEXT: addq $-16, %rcx ; ENABLE-NEXT: addq $-16, %rcx
; ENABLE-NEXT: movq %rcx, %rsp ; ENABLE-NEXT: movq %rcx, %rsp
; ENABLE-NEXT: xorl %edx, %edx ; ENABLE-NEXT: xorl %edx, %edx
; ENABLE-NEXT: jmp LBB11_2 ; ENABLE-NEXT: jmp LBB11_2
; ENABLE-NEXT: .p2align 4, 0x90 ; ENABLE-NEXT: .p2align 4, 0x90
; ENABLE-NEXT: LBB11_4: ## %body2 ; ENABLE-NEXT: LBB11_4: ## %body2
; ENABLE-NEXT: ## in Loop: Header=BB11_2 Depth=1 ; ENABLE-NEXT: ## in Loop: Header=BB11_2 Depth=1
; ENABLE-NEXT: ## InlineAsm Start ; ENABLE-NEXT: ## InlineAsm Start
; ENABLE-NEXT: nop ; ENABLE-NEXT: nop
; ENABLE-NEXT: ## InlineAsm End ; ENABLE-NEXT: ## InlineAsm End
; ENABLE-NEXT: movl $1, %edx ; ENABLE-NEXT: movl $1, %edx
; ENABLE-NEXT: LBB11_2: ## %for.body ; ENABLE-NEXT: LBB11_2: ## %for.body
; ENABLE-NEXT: ## =>This Inner Loop Header: Depth=1 ; ENABLE-NEXT: ## =>This Inner Loop Header: Depth=1
; ENABLE-NEXT: movl %edx, %esi ; ENABLE-NEXT: movl %edx, %esi
; ENABLE-NEXT: ## InlineAsm Start ; ENABLE-NEXT: ## InlineAsm Start
; ENABLE-NEXT: movl $1, %edx ; ENABLE-NEXT: movl $1, %edx
; ENABLE-NEXT: ## InlineAsm End ; ENABLE-NEXT: ## InlineAsm End
; ENABLE-NEXT: addl %esi, %edx ; ENABLE-NEXT: addl %esi, %edx
; ENABLE-NEXT: movl %edx, (%rcx) ; ENABLE-NEXT: movl %edx, (%rcx)
; ENABLE-NEXT: testb %al, %al ; ENABLE-NEXT: testb %al, %al
; ENABLE-NEXT: jne LBB11_4 ; ENABLE-NEXT: je LBB11_4
; ENABLE-NEXT: ## %bb.3: ## %body1 ; ENABLE-NEXT: ## %bb.3: ## %body1
; ENABLE-NEXT: ## in Loop: Header=BB11_2 Depth=1 ; ENABLE-NEXT: ## in Loop: Header=BB11_2 Depth=1
; ENABLE-NEXT: ## InlineAsm Start ; ENABLE-NEXT: ## InlineAsm Start
; ENABLE-NEXT: nop ; ENABLE-NEXT: nop
; ENABLE-NEXT: ## InlineAsm End ; ENABLE-NEXT: ## InlineAsm End
; ENABLE-NEXT: jmp LBB11_2 ; ENABLE-NEXT: jmp LBB11_2
; ENABLE-NEXT: LBB11_5: ## %if.end ; ENABLE-NEXT: LBB11_5: ## %if.end
; ENABLE-NEXT: leaq -8(%rbp), %rsp ; ENABLE-NEXT: leaq -8(%rbp), %rsp
; ENABLE-NEXT: popq %rbx ; ENABLE-NEXT: popq %rbx
; ENABLE-NEXT: popq %rbp ; ENABLE-NEXT: popq %rbp
; ENABLE-NEXT: retq ; ENABLE-NEXT: retq
; ;
; DISABLE-LABEL: infiniteloop2: ; DISABLE-LABEL: infiniteloop2:
; DISABLE: ## %bb.0: ## %entry ; DISABLE: ## %bb.0: ## %entry
; DISABLE-NEXT: pushq %rbp ; DISABLE-NEXT: pushq %rbp
; DISABLE-NEXT: .cfi_def_cfa_offset 16 ; DISABLE-NEXT: .cfi_def_cfa_offset 16
; DISABLE-NEXT: .cfi_offset %rbp, -16 ; DISABLE-NEXT: .cfi_offset %rbp, -16
; DISABLE-NEXT: movq %rsp, %rbp ; DISABLE-NEXT: movq %rsp, %rbp
; DISABLE-NEXT: .cfi_def_cfa_register %rbp ; DISABLE-NEXT: .cfi_def_cfa_register %rbp
; DISABLE-NEXT: pushq %rbx ; DISABLE-NEXT: pushq %rbx
; DISABLE-NEXT: pushq %rax ; DISABLE-NEXT: pushq %rax
; DISABLE-NEXT: .cfi_offset %rbx, -24 ; DISABLE-NEXT: .cfi_offset %rbx, -24
; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: xorl %eax, %eax
; DISABLE-NEXT: testb %al, %al ; DISABLE-NEXT: testb %al, %al
; DISABLE-NEXT: jne LBB11_5 ; DISABLE-NEXT: je LBB11_5
; DISABLE-NEXT: ## %bb.1: ## %if.then ; DISABLE-NEXT: ## %bb.1: ## %if.then
; DISABLE-NEXT: movq %rsp, %rcx ; DISABLE-NEXT: movq %rsp, %rcx
; DISABLE-NEXT: addq $-16, %rcx ; DISABLE-NEXT: addq $-16, %rcx
; DISABLE-NEXT: movq %rcx, %rsp ; DISABLE-NEXT: movq %rcx, %rsp
; DISABLE-NEXT: xorl %edx, %edx ; DISABLE-NEXT: xorl %edx, %edx
; DISABLE-NEXT: jmp LBB11_2 ; DISABLE-NEXT: jmp LBB11_2
; DISABLE-NEXT: .p2align 4, 0x90 ; DISABLE-NEXT: .p2align 4, 0x90
; DISABLE-NEXT: LBB11_4: ## %body2 ; DISABLE-NEXT: LBB11_4: ## %body2
; DISABLE-NEXT: ## in Loop: Header=BB11_2 Depth=1 ; DISABLE-NEXT: ## in Loop: Header=BB11_2 Depth=1
; DISABLE-NEXT: ## InlineAsm Start ; DISABLE-NEXT: ## InlineAsm Start
; DISABLE-NEXT: nop ; DISABLE-NEXT: nop
; DISABLE-NEXT: ## InlineAsm End ; DISABLE-NEXT: ## InlineAsm End
; DISABLE-NEXT: movl $1, %edx ; DISABLE-NEXT: movl $1, %edx
; DISABLE-NEXT: LBB11_2: ## %for.body ; DISABLE-NEXT: LBB11_2: ## %for.body
; DISABLE-NEXT: ## =>This Inner Loop Header: Depth=1 ; DISABLE-NEXT: ## =>This Inner Loop Header: Depth=1
; DISABLE-NEXT: movl %edx, %esi ; DISABLE-NEXT: movl %edx, %esi
; DISABLE-NEXT: ## InlineAsm Start ; DISABLE-NEXT: ## InlineAsm Start
; DISABLE-NEXT: movl $1, %edx ; DISABLE-NEXT: movl $1, %edx
; DISABLE-NEXT: ## InlineAsm End ; DISABLE-NEXT: ## InlineAsm End
; DISABLE-NEXT: addl %esi, %edx ; DISABLE-NEXT: addl %esi, %edx
; DISABLE-NEXT: movl %edx, (%rcx) ; DISABLE-NEXT: movl %edx, (%rcx)
; DISABLE-NEXT: testb %al, %al ; DISABLE-NEXT: testb %al, %al
; DISABLE-NEXT: jne LBB11_4 ; DISABLE-NEXT: je LBB11_4
; DISABLE-NEXT: ## %bb.3: ## %body1 ; DISABLE-NEXT: ## %bb.3: ## %body1
; DISABLE-NEXT: ## in Loop: Header=BB11_2 Depth=1 ; DISABLE-NEXT: ## in Loop: Header=BB11_2 Depth=1
; DISABLE-NEXT: ## InlineAsm Start ; DISABLE-NEXT: ## InlineAsm Start
; DISABLE-NEXT: nop ; DISABLE-NEXT: nop
; DISABLE-NEXT: ## InlineAsm End ; DISABLE-NEXT: ## InlineAsm End
; DISABLE-NEXT: jmp LBB11_2 ; DISABLE-NEXT: jmp LBB11_2
; DISABLE-NEXT: LBB11_5: ## %if.end ; DISABLE-NEXT: LBB11_5: ## %if.end
; DISABLE-NEXT: leaq -8(%rbp), %rsp ; DISABLE-NEXT: leaq -8(%rbp), %rsp
Show All 31 Lines
; ENABLE-LABEL: infiniteloop3: ; ENABLE-LABEL: infiniteloop3:
; ENABLE: ## %bb.0: ## %entry ; ENABLE: ## %bb.0: ## %entry
; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: xorl %eax, %eax
; ENABLE-NEXT: testb %al, %al ; ENABLE-NEXT: testb %al, %al
; ENABLE-NEXT: jne LBB12_2 ; ENABLE-NEXT: jne LBB12_2
; ENABLE-NEXT: ## %bb.1: ## %body ; ENABLE-NEXT: ## %bb.1: ## %body
; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: xorl %eax, %eax
; ENABLE-NEXT: testb %al, %al ; ENABLE-NEXT: testb %al, %al
; ENABLE-NEXT: jne LBB12_7 ; ENABLE-NEXT: je LBB12_7
; ENABLE-NEXT: LBB12_2: ## %loop2a.preheader ; ENABLE-NEXT: LBB12_2: ## %loop2a.preheader
; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: xorl %eax, %eax
; ENABLE-NEXT: xorl %ecx, %ecx ; ENABLE-NEXT: xorl %ecx, %ecx
; ENABLE-NEXT: movq %rax, %rsi ; ENABLE-NEXT: movq %rax, %rsi
; ENABLE-NEXT: jmp LBB12_4 ; ENABLE-NEXT: jmp LBB12_4
; ENABLE-NEXT: .p2align 4, 0x90 ; ENABLE-NEXT: .p2align 4, 0x90
; ENABLE-NEXT: LBB12_3: ## %loop2b ; ENABLE-NEXT: LBB12_3: ## %loop2b
; ENABLE-NEXT: ## in Loop: Header=BB12_4 Depth=1 ; ENABLE-NEXT: ## in Loop: Header=BB12_4 Depth=1
Show All 15 Lines
; DISABLE-LABEL: infiniteloop3: ; DISABLE-LABEL: infiniteloop3:
; DISABLE: ## %bb.0: ## %entry ; DISABLE: ## %bb.0: ## %entry
; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: xorl %eax, %eax
; DISABLE-NEXT: testb %al, %al ; DISABLE-NEXT: testb %al, %al
; DISABLE-NEXT: jne LBB12_2 ; DISABLE-NEXT: jne LBB12_2
; DISABLE-NEXT: ## %bb.1: ## %body ; DISABLE-NEXT: ## %bb.1: ## %body
; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: xorl %eax, %eax
; DISABLE-NEXT: testb %al, %al ; DISABLE-NEXT: testb %al, %al
; DISABLE-NEXT: jne LBB12_7 ; DISABLE-NEXT: je LBB12_7
; DISABLE-NEXT: LBB12_2: ## %loop2a.preheader ; DISABLE-NEXT: LBB12_2: ## %loop2a.preheader
; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: xorl %eax, %eax
; DISABLE-NEXT: xorl %ecx, %ecx ; DISABLE-NEXT: xorl %ecx, %ecx
; DISABLE-NEXT: movq %rax, %rsi ; DISABLE-NEXT: movq %rax, %rsi
; DISABLE-NEXT: jmp LBB12_4 ; DISABLE-NEXT: jmp LBB12_4
; DISABLE-NEXT: .p2align 4, 0x90 ; DISABLE-NEXT: .p2align 4, 0x90
; DISABLE-NEXT: LBB12_3: ## %loop2b ; DISABLE-NEXT: LBB12_3: ## %loop2b
; DISABLE-NEXT: ## in Loop: Header=BB12_4 Depth=1 ; DISABLE-NEXT: ## in Loop: Header=BB12_4 Depth=1
▲ Show 20 Lines • Show All 519 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/xmulo.ll

Show First 20 Lines • Show All 1,341 Lines • ▼ Show 20 Lines
; WIN32-NEXT: orb %bh, %cl ; WIN32-NEXT: orb %bh, %cl
; WIN32-NEXT: addl %edi, %esi ; WIN32-NEXT: addl %edi, %esi
; WIN32-NEXT: movl %edx, %eax ; WIN32-NEXT: movl %edx, %eax
; WIN32-NEXT: mull %ebp ; WIN32-NEXT: mull %ebp
; WIN32-NEXT: addl %esi, %edx ; WIN32-NEXT: addl %esi, %edx
; WIN32-NEXT: setb %al ; WIN32-NEXT: setb %al
; WIN32-NEXT: orb %cl, %al ; WIN32-NEXT: orb %cl, %al
; WIN32-NEXT: orb %bl, %al ; WIN32-NEXT: orb %bl, %al
; WIN32-NEXT: subb $1, %al ; WIN32-NEXT: testb %al, %al
; WIN32-NEXT: je LBB22_1 ; WIN32-NEXT: jne LBB22_1
; WIN32-NEXT: # %bb.3: # %continue ; WIN32-NEXT: # %bb.3: # %continue
; WIN32-NEXT: movb $1, %al ; WIN32-NEXT: movb $1, %al
; WIN32-NEXT: LBB22_2: # %overflow ; WIN32-NEXT: LBB22_2: # %overflow
; WIN32-NEXT: popl %esi ; WIN32-NEXT: popl %esi
; WIN32-NEXT: popl %edi ; WIN32-NEXT: popl %edi
; WIN32-NEXT: popl %ebx ; WIN32-NEXT: popl %ebx
; WIN32-NEXT: popl %ebp ; WIN32-NEXT: popl %ebp
; WIN32-NEXT: retl ; WIN32-NEXT: retl
▲ Show 20 Lines • Show All 1,006 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/xor-combine-debugloc.ll

; RUN: llc -stop-after=finalize-isel < %s | FileCheck %s ; RUN: llc -stop-after=finalize-isel < %s | FileCheck %s
; ;
; Make sure that when the entry block of IR below is lowered, an instruction ; Make sure that when the entry block of IR below is lowered, an instruction
; that implictly defines $eflags has a same debug location with the icmp ; that implictly defines $eflags has a same debug location with the icmp
; instruction, and the branch instructions have a same debug location with the ; instruction, and the branch instructions have a same debug location with the
; br instruction. ; br instruction.
; ;
; CHECK: [[DLOC1:![0-9]+]] = !DILocation(line: 5, column: 9, scope: !{{[0-9]+}}) ; CHECK: [[DLOC1:![0-9]+]] = !DILocation(line: 5, column: 9, scope: !{{[0-9]+}})
; CHECK: [[DLOC2:![0-9]+]] = !DILocation(line: 5, column: 7, scope: !{{[0-9]+}}) ; CHECK: [[DLOC2:![0-9]+]] = !DILocation(line: 5, column: 7, scope: !{{[0-9]+}})
; CHECK-DAG: [[VREG1:%[^ ]+]]:gr32 = COPY $esi ; CHECK-DAG: [[VREG1:%[^ ]+]]:gr32 = COPY $esi
; CHECK-DAG: [[VREG2:%[^ ]+]]:gr32 = COPY $edi ; CHECK-DAG: [[VREG2:%[^ ]+]]:gr32 = COPY $edi
; CHECK: SUB32rr [[VREG2]], [[VREG1]], implicit-def $eflags, debug-location [[DLOC1]] ; CHECK: SUB32rr [[VREG2]], [[VREG1]], implicit-def $eflags, debug-location [[DLOC1]]
; CHECK-NEXT: JCC_1{{.*}} 4, implicit $eflags, debug-location [[DLOC2]] ; CHECK-NEXT: JCC_1{{.*}} {{.*}}, implicit $eflags, debug-location [[DLOC2]]
; CHECK-NEXT: JMP_1{{.*}} debug-location [[DLOC2]] ; CHECK-NEXT: JMP_1{{.*}} debug-location [[DLOC2]]
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define i32 @foo(i32 %x, i32 %y) !dbg !4 { define i32 @foo(i32 %x, i32 %y) !dbg !4 {
entry: entry:
tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !9, metadata !11), !dbg !12 tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !9, metadata !11), !dbg !12
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llvm/test/CodeGen/X86/xor-icmp.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define i32 @t2(i32 %x, i32 %y) nounwind ssp { define i32 @t2(i32 %x, i32 %y) nounwind ssp {
; X86-LABEL: t2: ; X86-LABEL: t2:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; X86-NEXT: sete %al ; X86-NEXT: sete %al
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; X86-NEXT: sete %cl ; X86-NEXT: sete %cl
; X86-NEXT: cmpb %al, %cl ; X86-NEXT: xorb %al, %cl
; X86-NEXT: je .LBB1_1 ; X86-NEXT: je .LBB1_1
; X86-NEXT: # %bb.2: # %bb ; X86-NEXT: # %bb.2: # %bb
; X86-NEXT: jmp foo # TAILCALL ; X86-NEXT: jmp foo # TAILCALL
; X86-NEXT: .LBB1_1: # %return ; X86-NEXT: .LBB1_1: # %return
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: t2: ; X64-LABEL: t2:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: testl %edi, %edi ; X64-NEXT: testl %edi, %edi
; X64-NEXT: sete %al ; X64-NEXT: sete %al
; X64-NEXT: testl %esi, %esi ; X64-NEXT: testl %esi, %esi
; X64-NEXT: sete %cl ; X64-NEXT: sete %cl
; X64-NEXT: cmpb %al, %cl ; X64-NEXT: xorb %al, %cl
; X64-NEXT: je .LBB1_1 ; X64-NEXT: je .LBB1_1
; X64-NEXT: # %bb.2: # %bb ; X64-NEXT: # %bb.2: # %bb
; X64-NEXT: xorl %eax, %eax ; X64-NEXT: xorl %eax, %eax
; X64-NEXT: jmp foo # TAILCALL ; X64-NEXT: jmp foo # TAILCALL
; X64-NEXT: .LBB1_1: # %return ; X64-NEXT: .LBB1_1: # %return
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
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llvm/test/CodeGen/XCore/threads.ll

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 LinesConstantExpPhiNode:
br label %ConstantExpPhiNode br label %ConstantExpPhiNode
exit: exit:
ret void ret void
} }
define void @phiNode2( i1 %bool) { define void @phiNode2( i1 %bool) {
; N.B. check an extra 'Node_crit_edge' (LBB12_1) is inserted ; N.B. check an extra 'Node_crit_edge' (LBB12_1) is inserted
; PHINODE-LABEL: phiNode2: ; PHINODE-LABEL: phiNode2:
; PHINODE: bf {{r[0-9]}}, .LBB12_3 ; PHINODE: bt {{r[0-9]}}, .LBB12_1
; PHINODE: bu .LBB12_1 ; PHINODE: bu .LBB12_3
; PHINODE-LABEL: .LBB12_1: ; PHINODE-LABEL: .LBB12_1:
; PHINODE: get r11, id ; PHINODE: get r11, id
; PHINODE-LABEL: .LBB12_2: ; PHINODE-LABEL: .LBB12_2:
; PHINODE: get r11, id ; PHINODE: get r11, id
; PHINODE: bu .LBB12_2 ; PHINODE: bu .LBB12_2
; PHINODE-LABEL: .LBB12_3: ; PHINODE-LABEL: .LBB12_3:
entry: entry:
br i1 %bool, label %ConstantExpPhiNode, label %exit br i1 %bool, label %ConstantExpPhiNode, label %exit
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