[RISCV] Support scalable-vector integer reduction intrinsics

[frasercrmck]

Summary

This patch adds support for the integer reduction intrinsics supported
by RVV. This excludes "mul" which has no corresponding instruction.

The reduction instructions in RVV have slightly complicated type
constraints given they always produce a single "M1" vector register.

They are lowered to custom nodes including the second "scalar" reduction
operand to simplify the patterns and in the hope that they can be useful
for future DAG combines.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1681

Doesn't this need to be the identify value for the operation not always 0? I think AND would need -1. SMIN would need INT_MAX, SMAX would need INT_MIN, UMAX would need UINT_MAX.

1681

Doesn't this need to be the identify value for the operation not always 0? I think AND would need -1. SMIN would need INT_MAX, SMAX would need INT_MIN, UMAX would need UINT_MAX.

Oops UMAX would need 0, UMIN would need UINT_MAX

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1681

Wow, of course they would. Can't believe I missed that. Thanks! Must have been too focused on "add".

[frasercrmck]

• fix identity values for smax,smin,umax,and reductions
• fix RV32 64-bit reductions using 32-bit identity values

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1681

Okay that should be that. I had to ensure it's minIntN, maxIntN, maxUIntN for the element type. The splatting still recognises when it's sign-extended so generates e.g. -1 for the INT_MIN cases.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

916

Shouldn't we always lower EXTRACT_ELEMENT for types less than XLen to VMV_X_S? Why is knowing sign extension important for this operation, but not any extract element?

1685

Rename this since its not a Splat of 0 anymore. Also update the commit message.

[frasercrmck]

• fix variable name

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

916

Yes, we really should. I'll put up a patch which addresses that first, then can rebase this on top of that.

1685

Done, thanks for reminding me.

[HsiangKai]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

440

You list ISD::VECREDUCE_MUL here, but you did not handle ISD::VECREDUCE_MUL in LowerOperation.

[frasercrmck]

• rebase on child revision
• use generic EXTRACT_VECTOR_ELT rather than VMV_S_X

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

440

Thanks for spotting that. Copy/paste mistake.

[frasercrmck]

• rebase

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
   VSLIDEUP,
   VSLIDEDOWN,
   // Matches the semantics of the unmasked vid.v instruction.
   VID,
   // Matches the semantics of the vfcnvt.rod function (Convert double-width
   // float to single-width float, rounding towards odd). Takes a double-width
   // float vector and produces a single-width float vector.
   VFNCVT_ROD,
+  // These nodes match the semantics of the corresponding RVV vector reduction
+  // instructions. They produce a vector result which is the reduction
+  // performed over the first vector operand plus the first element of the
+  // second vector operand. The first operand is an unconstrained vector type,
+  // and the result and second operand's types are expected to be the
+  // corresponding full-width LMUL=1 type for the first operand:
+  //   nxv8i8 = vecreduce_add nxv32i8, nxv8i8
+  //   nxv2i32 = vecreduce_add nxv8i32, nxv2i32
+  // The different in types does introduce extra vsetvli instructions but
+  // similarly it reduces the number of registers consumed per reduction.
+  VECREDUCE_ADD,
+  VECREDUCE_UMAX,
+  VECREDUCE_SMAX,
+  VECREDUCE_UMIN,
+  VECREDUCE_SMIN,
+  VECREDUCE_AND,
+  VECREDUCE_OR,
+  VECREDUCE_XOR,
 };
 } // namespace RISCVISD
 
 class RISCVTargetLowering : public TargetLowering {
   const RISCVSubtarget &Subtarget;
 
 public:
   explicit RISCVTargetLowering(const TargetMachine &TM,
private:
   SDValue lowerSPLATVECTOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
                              int64_t ExtTrueVal) const;
   SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
 
   bool isEligibleForTailCallOptimization(
       CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
       const SmallVector<CCValAssign, 16> &ArgLocs) const;
 
   /// Generate error diagnostics if any register used by CC has been marked
   /// reserved.
   void validateCCReservedRegs(

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.is64Bit()) {
       setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
       setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::i32, Custom);
     } else {
       // We must custom-lower certain vXi64 operations on RV32 due to the vector
       // element type being illegal.
       setOperationAction(ISD::SPLAT_VECTOR, MVT::i64, Custom);
       setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::i64, Custom);
       setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::i64, Custom);
+
+      setOperationAction(ISD::VECREDUCE_ADD, MVT::i64, Custom);
+      setOperationAction(ISD::VECREDUCE_AND, MVT::i64, Custom);
+      setOperationAction(ISD::VECREDUCE_OR, MVT::i64, Custom);
+      setOperationAction(ISD::VECREDUCE_XOR, MVT::i64, Custom);
+      setOperationAction(ISD::VECREDUCE_SMAX, MVT::i64, Custom);
+      setOperationAction(ISD::VECREDUCE_SMIN, MVT::i64, Custom);
+      setOperationAction(ISD::VECREDUCE_UMAX, MVT::i64, Custom);
+      setOperationAction(ISD::VECREDUCE_UMIN, MVT::i64, Custom);
     }
 
     for (MVT VT : BoolVecVTs) {
       setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
 
       // Mask VTs are custom-expanded into a series of standard nodes
       setOperationAction(ISD::TRUNCATE, VT, Custom);
     }
for (MVT VT : IntVecVTs) {
 
       // Integer VTs are lowered as a series of "RISCVISD::TRUNCATE_VECTOR"
       // nodes which truncate by one power of two at a time.
       setOperationAction(ISD::TRUNCATE, VT, Custom);
 
       // Custom-lower insert/extract operations to simplify patterns.
       setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
       setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
+
+      // Custom-lower reduction operations to set up the corresponding custom
+      // nodes' operands.
+      setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
     }
 
     // Expand various CCs to best match the RVV ISA, which natively supports UNE
     // but no other unordered comparisons, and supports all ordered comparisons
     // except ONE. Additionally, we expand GT,OGT,GE,OGE for optimization
     // purposes; they are expanded to their swapped-operand CCs (LT,OLT,LE,OLE),
     // and we pattern-match those back to the "original", swapping operands once
     // more. This way we catch both operations and both "vf" and "fv" forms with
if (SrcEltSize > EltSize && (SrcEltSize / EltSize >= 4)) {
           MVT::getVectorVT(MVT::getIntegerVT(SrcEltVT.getSizeInBits() / 2),
                            VT.getVectorElementCount());
       SDValue FP2Int = DAG.getNode(Op.getOpcode(), DL, IVecVT, Src);
       return DAG.getNode(ISD::TRUNCATE, DL, VT, FP2Int);
     }
 
     return Op;
   }
+  case ISD::VECREDUCE_ADD:
+  case ISD::VECREDUCE_UMAX:
+  case ISD::VECREDUCE_SMAX:
+  case ISD::VECREDUCE_UMIN:
+  case ISD::VECREDUCE_SMIN:
+  case ISD::VECREDUCE_AND:
+  case ISD::VECREDUCE_OR:
+  case ISD::VECREDUCE_XOR:
+    return lowerVECREDUCE(Op, DAG);
   }
 }
 
 static SDValue getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty,
                              SelectionDAG &DAG, unsigned Flags) {
   return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
 }
 
 static SDValue getTargetNode(BlockAddressSDNode *N, SDLoc DL, EVT Ty,
SDValue ReadVL =
         SDValue(DAG.getMachineNode(RISCV::PseudoReadVL, DL, Op->getValueType(1),
                                    Load.getValue(2)),
                 0);
     return DAG.getMergeValues({Load, ReadVL, Load.getValue(1)}, DL);
   }
   }
 }
 
+static std::pair<unsigned, uint64_t>
+getRVVReductionOpAndIdentityVal(unsigned ISDOpcode, unsigned EltSizeBits) {
+  switch (ISDOpcode) {
+  default:
+    llvm_unreachable("Unhandled reduction");
+  case ISD::VECREDUCE_ADD:
+    return {RISCVISD::VECREDUCE_ADD, 0};
+  case ISD::VECREDUCE_UMAX:
+    return {RISCVISD::VECREDUCE_UMAX, 0};
+  case ISD::VECREDUCE_SMAX:
+    return {RISCVISD::VECREDUCE_SMAX, minIntN(EltSizeBits)};
+  case ISD::VECREDUCE_UMIN:
+    return {RISCVISD::VECREDUCE_UMIN, maxUIntN(EltSizeBits)};
+  case ISD::VECREDUCE_SMIN:
+    return {RISCVISD::VECREDUCE_SMIN, maxIntN(EltSizeBits)};
+  case ISD::VECREDUCE_AND:
+    return {RISCVISD::VECREDUCE_AND, -1};
+  case ISD::VECREDUCE_OR:
+    return {RISCVISD::VECREDUCE_OR, 0};
+  case ISD::VECREDUCE_XOR:
+    return {RISCVISD::VECREDUCE_XOR, 0};
+  }
+}
+
+// Take a (supported) standard ISD reduction opcode and transform it to a RISCV
+// reduction opcode. Note that this returns a vector type, which must be
+// further processed to access the scalar result in element 0.
+SDValue RISCVTargetLowering::lowerVECREDUCE(SDValue Op,
+                                            SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  assert(Op.getValueType().isSimple() &&
+         Op.getOperand(0).getValueType().isSimple() &&
+         "Unexpected vector-reduce lowering");
+  MVT VecEltVT = Op.getOperand(0).getSimpleValueType().getVectorElementType();
+  unsigned RVVOpcode;
+  uint64_t IdentityVal;
+  std::tie(RVVOpcode, IdentityVal) =
+      getRVVReductionOpAndIdentityVal(Op.getOpcode(), VecEltVT.getSizeInBits());
+  // We have to perform a bit of a dance to get from our vector type to the
+  // correct LMUL=1 vector type. We divide our minimum VLEN (64) by the vector
+  // element type to find the type which fills a single register. Be careful to
+  // use the operand's vector element type rather than the reduction's value
+  // type, as that has likely been extended to XLEN.
+  unsigned NumElts = 64 / VecEltVT.getSizeInBits();
+  MVT M1VT = MVT::getScalableVectorVT(VecEltVT, NumElts);
+  SDValue IdentitySplat =
+      DAG.getSplatVector(M1VT, DL, DAG.getConstant(IdentityVal, DL, VecEltVT));
+  SDValue Reduction =
+      DAG.getNode(RVVOpcode, DL, M1VT, Op.getOperand(0), IdentitySplat);
+  SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VecEltVT, Reduction,
+                             DAG.getConstant(0, DL, Subtarget.getXLenVT()));
+  return DAG.getSExtOrTrunc(Elt0, DL, Op.getValueType());
+}
+
 // Returns the opcode of the target-specific SDNode that implements the 32-bit
 // form of the given Opcode.
 static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) {
   switch (Opcode) {
   default:
     llvm_unreachable("Unexpected opcode");
   case ISD::SHL:
     return RISCVISD::SLLW;
case Intrinsic::riscv_vmv_x_s: {
       SDValue Extract = DAG.getNode(RISCVISD::VMV_X_S, DL,
                                     Subtarget.getXLenVT(), N->getOperand(1));
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Extract));
       break;
     }
     }
     break;
   }
+  case ISD::VECREDUCE_ADD:
+  case ISD::VECREDUCE_AND:
+  case ISD::VECREDUCE_OR:
+  case ISD::VECREDUCE_XOR:
+  case ISD::VECREDUCE_SMAX:
+  case ISD::VECREDUCE_UMAX:
+  case ISD::VECREDUCE_SMIN:
+  case ISD::VECREDUCE_UMIN:
+    // The custom-lowering for these nodes returns a vector whose first element
+    // is the result of the reduction. Extract its first element and let the
+    // legalization for EXTRACT_VECTOR_ELT do the rest of the job.
+    Results.push_back(lowerVECREDUCE(SDValue(N, 0), DAG));
+    break;
   }
 }
 
 // A structure to hold one of the bit-manipulation patterns below. Together, a
 // SHL and non-SHL pattern may form a bit-manipulation pair on a single source:
 //   (or (and (shl x, 1), 0xAAAAAAAA),
 //       (and (srl x, 1), 0x55555555))
 struct RISCVBitmanipPat {
#define NODE_NAME_CASE(NODE)                                                   \
   NODE_NAME_CASE(READ_VLENB)
   NODE_NAME_CASE(TRUNCATE_VECTOR)
   NODE_NAME_CASE(VLEFF)
   NODE_NAME_CASE(VLEFF_MASK)
   NODE_NAME_CASE(VSLIDEUP)
   NODE_NAME_CASE(VSLIDEDOWN)
   NODE_NAME_CASE(VID)
   NODE_NAME_CASE(VFNCVT_ROD)
+  NODE_NAME_CASE(VECREDUCE_ADD)
+  NODE_NAME_CASE(VECREDUCE_UMAX)
+  NODE_NAME_CASE(VECREDUCE_SMAX)
+  NODE_NAME_CASE(VECREDUCE_UMIN)
+  NODE_NAME_CASE(VECREDUCE_SMIN)
+  NODE_NAME_CASE(VECREDUCE_AND)
+  NODE_NAME_CASE(VECREDUCE_OR)
+  NODE_NAME_CASE(VECREDUCE_XOR)
   }
   // clang-format on
   return nullptr;
 #undef NODE_NAME_CASE
 }
 
 /// getConstraintType - Given a constraint letter, return the type of
 /// constraint it is for this target.

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

 
 def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", []>;
 def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", []>;
 
 class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
    dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
 }
 
+def SDTRVVVecReduce : SDTypeProfile<1, 2, [
+  SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>
+]>;
+
+foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR"] in
+  def rvv_vecreduce_#kind : SDNode<"RISCVISD::VECREDUCE_"#kind, SDTRVVVecReduce>;
+
 multiclass VPatUSLoadStoreSDNode<LLVMType type,
                                  LLVMType mask_type,
                                  int sew,
                                  LMULInfo vlmul,
                                  OutPatFrag avl,
                                  RegisterClass reg_rs1,
                                  VReg reg_class>
 {
foreach vtiToWti = AllWidenableIntToFloatVectors in {
     defvar vti = vtiToWti.Vti;
     defvar fwti = vtiToWti.Wti;
     def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1))),
               (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX)
                   fwti.RegClass:$rs1, vti.AVL, vti.SEW)>;
   }
 }
 
+multiclass VPatReductionSDNode<SDNode vop, string instruction_name> {
+  foreach vti = AllIntegerVectors in {
+    defvar vti_m1 = !cast<VTypeInfo>("VI" # vti.SEW # "M1");
+    def: Pat<(vti_m1.Vector (vop (vti.Vector vti.RegClass:$rs1), VR:$rs2)),
+        (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX)
+            (vti_m1.Vector (IMPLICIT_DEF)),
+            (vti.Vector vti.RegClass:$rs1),
+            (vti_m1.Vector VR:$rs2),
+            vti.AVL, vti.SEW)>;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Patterns.
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtV] in {
 
 // 7.4. Vector Unit-Stride Instructions
 defm "" : VPatUSLoadStoreSDNodes<GPR>;
def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), (SplatPat XLenVT:$rs1),
                  vti.RegClass:$rs2, GPR:$rs1, VMV0:$vm, vti.AVL, vti.SEW)>;
 
   def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), (SplatPat_simm5 simm5:$rs1),
                                                       vti.RegClass:$rs2)),
             (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX)
                  vti.RegClass:$rs2, simm5:$rs1, VMV0:$vm, vti.AVL, vti.SEW)>;
 }
 
+// 15.1. Vector Single-Width Integer Reduction Instructions
+defm "" : VPatReductionSDNode<rvv_vecreduce_ADD,  "PseudoVREDSUM">;
+defm "" : VPatReductionSDNode<rvv_vecreduce_UMAX, "PseudoVREDMAXU">;
+defm "" : VPatReductionSDNode<rvv_vecreduce_SMAX, "PseudoVREDMAX">;
+defm "" : VPatReductionSDNode<rvv_vecreduce_UMIN, "PseudoVREDMINU">;
+defm "" : VPatReductionSDNode<rvv_vecreduce_SMIN, "PseudoVREDMIN">;
+defm "" : VPatReductionSDNode<rvv_vecreduce_AND,  "PseudoVREDAND">;
+defm "" : VPatReductionSDNode<rvv_vecreduce_OR,   "PseudoVREDOR">;
+defm "" : VPatReductionSDNode<rvv_vecreduce_XOR,  "PseudoVREDXOR">;
+
 // 16.1. Vector Mask-Register Logical Instructions
 foreach mti = AllMasks in {
   def : Pat<(mti.Mask (and VR:$rs1, VR:$rs2)),
             (!cast<Instruction>("PseudoVMAND_MM_"#mti.LMul.MX)
                  VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
   def : Pat<(mti.Mask (or VR:$rs1, VR:$rs2)),
             (!cast<Instruction>("PseudoVMOR_MM_"#mti.LMul.MX)
                  VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

explicit RISCVTTIImpl(const RISCVTargetMachine *TM, const Function &F)
         TLI(ST->getTargetLowering()) {}
 
   int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind);
   int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
                         Type *Ty, TTI::TargetCostKind CostKind,
                         Instruction *Inst = nullptr);
   int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
                           Type *Ty, TTI::TargetCostKind CostKind);
+
+  bool shouldExpandReduction(const IntrinsicInst *II) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

 }
 
 int RISCVTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
                                       const APInt &Imm, Type *Ty,
                                       TTI::TargetCostKind CostKind) {
   // Prevent hoisting in unknown cases.
   return TTI::TCC_Free;
 }
+
+bool RISCVTTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {
+  // Currently, the ExpandReductions pass can't expand scalable-vector
+  // reductions, but we still request expansion as RVV doesn't support certain
+  // reductions and the SelectionDAG can't legalize them either.
+  switch (II->getIntrinsicID()) {
+  default:
+    return false;
+  case Intrinsic::vector_reduce_mul:
+  case Intrinsic::vector_reduce_fadd:
+  case Intrinsic::vector_reduce_fmul:
+  case Intrinsic::vector_reduce_fmax:
+  case Intrinsic::vector_reduce_fmin:
+    return true;
+  }
+}

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+declare i8 @llvm.vector.reduce.add.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_add_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_add_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.add.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.umax.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_umax_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_umax_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.umax.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.smax.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_smax_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_smax_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -128
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.smax.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.umin.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_umin_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_umin_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.umin.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.smin.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_smin_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_smin_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 127
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.smin.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.and.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_and_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_and_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.and.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.or.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_or_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_or_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.or.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.xor.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_xor_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_xor_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.xor.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.add.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_add_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_add_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.add.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.umax.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_umax_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_umax_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.umax.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.smax.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_smax_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_smax_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -128
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.smax.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.umin.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_umin_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_umin_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.umin.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.smin.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_smin_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_smin_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 127
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.smin.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.and.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_and_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_and_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.and.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.or.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_or_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_or_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.or.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.xor.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_xor_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_xor_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.xor.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.add.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_add_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_add_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.add.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.umax.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_umax_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_umax_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.umax.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.smax.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_smax_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_smax_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -128
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.smax.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.umin.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_umin_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_umin_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.umin.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.smin.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_smin_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_smin_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 127
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.smin.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.and.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_and_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_and_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.and.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.or.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_or_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_or_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.or.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.xor.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_xor_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_xor_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.xor.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_add_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_add_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.umax.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_umax_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_umax_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.umax.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.smax.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_smax_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_smax_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048568
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.smax.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.umin.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_umin_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_umin_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.umin.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.smin.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_smin_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_smin_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.smin.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.and.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_and_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_and_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.and.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.or.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_or_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_or_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.or.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.xor.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_xor_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_xor_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.xor.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_add_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_add_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.umax.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_umax_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_umax_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.umax.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.smax.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_smax_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_smax_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048568
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.smax.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.umin.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_umin_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_umin_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.umin.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.smin.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_smin_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_smin_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.smin.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.and.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_and_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_and_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.and.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.or.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_or_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_or_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.or.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_xor_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_xor_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_add_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_add_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.umax.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_umax_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_umax_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.umax.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.smax.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_smax_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_smax_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048568
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.smax.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.umin.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_umin_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_umin_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.umin.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.smin.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_smin_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_smin_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.smin.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.and.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_and_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_and_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.and.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.or.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_or_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_or_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.or.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.xor.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_xor_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_xor_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.xor.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32>)
+
+define i32 @vreduce_add_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_add_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.umax.nxv1i32(<vscale x 1 x i32>)
+
+define i32 @vreduce_umax_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_umax_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.umax.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.smax.nxv1i32(<vscale x 1 x i32>)
+
+define i32 @vreduce_smax_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_smax_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.smax.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.umin.nxv1i32(<vscale x 1 x i32>)
+
+define i32 @vreduce_umin_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_umin_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.umin.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.smin.nxv1i32(<vscale x 1 x i32>)
+
+define i32 @vreduce_smin_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_smin_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.smin.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.and.nxv1i32(<vscale x 1 x i32>)
+
+define i32 @vreduce_and_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_and_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.and.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.or.nxv1i32(<vscale x 1 x i32>)
+
+define i32 @vreduce_or_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_or_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.or.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.xor.nxv1i32(<vscale x 1 x i32>)
+
+define i32 @vreduce_xor_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_xor_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.xor.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32>)
+
+define i32 @vreduce_add_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_add_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32>)
+
+define i32 @vreduce_umax_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_umax_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32>)
+
+define i32 @vreduce_smax_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_smax_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32>)
+
+define i32 @vreduce_umin_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_umin_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32>)
+
+define i32 @vreduce_smin_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_smin_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32>)
+
+define i32 @vreduce_and_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_and_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32>)
+
+define i32 @vreduce_or_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_or_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32>)
+
+define i32 @vreduce_xor_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_xor_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32>)
+
+define i32 @vreduce_add_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_add_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32>)
+
+define i32 @vreduce_umax_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_umax_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32>)
+
+define i32 @vreduce_smax_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_smax_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32>)
+
+define i32 @vreduce_umin_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_umin_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32>)
+
+define i32 @vreduce_smin_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_smin_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32>)
+
+define i32 @vreduce_and_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_and_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32>)
+
+define i32 @vreduce_or_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_or_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32>)
+
+define i32 @vreduce_xor_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_xor_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_add_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_add_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.umax.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_umax_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_umax_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.umax.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.smax.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_smax_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_smax_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a1
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vsrl.vx v26, v26, a1
+; CHECK-NEXT:    vor.vv v25, v26, v25
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.smax.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.umin.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_umin_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_umin_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.umin.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_smin_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_smin_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a1
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vor.vv v25, v25, v26
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.and.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_and_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_and_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.and.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.or.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_or_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_or_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.or.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.xor.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_xor_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_xor_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.xor.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_add_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_add_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_umax_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_umax_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_smax_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_smax_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a1
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vsrl.vx v26, v26, a1
+; CHECK-NEXT:    vor.vv v25, v26, v25
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_umin_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_umin_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_smin_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_smin_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a1
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vor.vv v25, v25, v26
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_and_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_and_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_or_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_or_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_xor_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_xor_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_add_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_add_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_umax_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_umax_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_smax_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_smax_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a1
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vsrl.vx v26, v26, a1
+; CHECK-NEXT:    vor.vv v25, v26, v25
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_umin_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_umin_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_smin_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_smin_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a1
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vor.vv v25, v25, v26
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_and_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_and_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_or_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_or_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_xor_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_xor_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+declare i8 @llvm.vector.reduce.add.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_add_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_add_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.add.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.umax.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_umax_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_umax_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.umax.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.smax.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_smax_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_smax_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -128
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.smax.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.umin.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_umin_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_umin_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.umin.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.smin.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_smin_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_smin_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 127
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.smin.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.and.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_and_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_and_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.and.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.or.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_or_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_or_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.or.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.xor.nxv1i8(<vscale x 1 x i8>)
+
+define signext i8 @vreduce_xor_nxv1i8(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: vreduce_xor_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.xor.nxv1i8(<vscale x 1 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.add.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_add_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_add_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.add.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.umax.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_umax_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_umax_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.umax.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.smax.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_smax_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_smax_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -128
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.smax.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.umin.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_umin_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_umin_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.umin.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.smin.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_smin_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_smin_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 127
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.smin.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.and.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_and_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_and_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.and.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.or.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_or_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_or_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.or.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.xor.nxv2i8(<vscale x 2 x i8>)
+
+define signext i8 @vreduce_xor_nxv2i8(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: vreduce_xor_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.xor.nxv2i8(<vscale x 2 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.add.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_add_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_add_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.add.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.umax.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_umax_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_umax_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.umax.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.smax.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_smax_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_smax_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -128
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.smax.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.umin.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_umin_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_umin_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.umin.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.smin.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_smin_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_smin_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 127
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.smin.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.and.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_and_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_and_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.and.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.or.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_or_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_or_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.or.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i8 @llvm.vector.reduce.xor.nxv4i8(<vscale x 4 x i8>)
+
+define signext i8 @vreduce_xor_nxv4i8(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: vreduce_xor_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i8 @llvm.vector.reduce.xor.nxv4i8(<vscale x 4 x i8> %v)
+  ret i8 %red
+}
+
+declare i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_add_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_add_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.umax.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_umax_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_umax_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.umax.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.smax.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_smax_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_smax_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048568
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.smax.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.umin.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_umin_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_umin_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.umin.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.smin.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_smin_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_smin_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addiw a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.smin.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.and.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_and_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_and_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.and.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.or.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_or_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_or_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.or.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.xor.nxv1i16(<vscale x 1 x i16>)
+
+define signext i16 @vreduce_xor_nxv1i16(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: vreduce_xor_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.xor.nxv1i16(<vscale x 1 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_add_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_add_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.umax.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_umax_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_umax_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.umax.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.smax.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_smax_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_smax_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048568
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.smax.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.umin.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_umin_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_umin_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.umin.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.smin.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_smin_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_smin_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addiw a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.smin.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.and.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_and_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_and_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.and.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.or.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_or_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_or_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.or.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16>)
+
+define signext i16 @vreduce_xor_nxv2i16(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: vreduce_xor_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_add_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_add_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.umax.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_umax_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_umax_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.umax.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.smax.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_smax_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_smax_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048568
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.smax.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.umin.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_umin_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_umin_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.umin.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.smin.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_smin_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_smin_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addiw a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.smin.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.and.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_and_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_and_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.and.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.or.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_or_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_or_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.or.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i16 @llvm.vector.reduce.xor.nxv4i16(<vscale x 4 x i16>)
+
+define signext i16 @vreduce_xor_nxv4i16(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: vreduce_xor_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i16 @llvm.vector.reduce.xor.nxv4i16(<vscale x 4 x i16> %v)
+  ret i16 %red
+}
+
+declare i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32>)
+
+define signext i32 @vreduce_add_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_add_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.umax.nxv1i32(<vscale x 1 x i32>)
+
+define signext i32 @vreduce_umax_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_umax_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.umax.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.smax.nxv1i32(<vscale x 1 x i32>)
+
+define signext i32 @vreduce_smax_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_smax_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.smax.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.umin.nxv1i32(<vscale x 1 x i32>)
+
+define signext i32 @vreduce_umin_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_umin_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.umin.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.smin.nxv1i32(<vscale x 1 x i32>)
+
+define signext i32 @vreduce_smin_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_smin_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    addiw a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.smin.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.and.nxv1i32(<vscale x 1 x i32>)
+
+define signext i32 @vreduce_and_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_and_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.and.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.or.nxv1i32(<vscale x 1 x i32>)
+
+define signext i32 @vreduce_or_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_or_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.or.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.xor.nxv1i32(<vscale x 1 x i32>)
+
+define signext i32 @vreduce_xor_nxv1i32(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: vreduce_xor_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.xor.nxv1i32(<vscale x 1 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32>)
+
+define signext i32 @vreduce_add_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_add_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32>)
+
+define signext i32 @vreduce_umax_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_umax_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32>)
+
+define signext i32 @vreduce_smax_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_smax_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32>)
+
+define signext i32 @vreduce_umin_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_umin_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32>)
+
+define signext i32 @vreduce_smin_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_smin_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    addiw a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32>)
+
+define signext i32 @vreduce_and_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_and_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32>)
+
+define signext i32 @vreduce_or_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_or_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32>)
+
+define signext i32 @vreduce_xor_nxv2i32(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: vreduce_xor_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32>)
+
+define signext i32 @vreduce_add_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_add_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32>)
+
+define signext i32 @vreduce_umax_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_umax_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32>)
+
+define signext i32 @vreduce_smax_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_smax_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32>)
+
+define signext i32 @vreduce_umin_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_umin_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32>)
+
+define signext i32 @vreduce_smin_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_smin_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    addiw a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32>)
+
+define signext i32 @vreduce_and_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_and_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32>)
+
+define signext i32 @vreduce_or_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_or_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32>)
+
+define signext i32 @vreduce_xor_nxv4i32(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: vreduce_xor_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32> %v)
+  ret i32 %red
+}
+
+declare i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_add_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_add_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.umax.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_umax_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_umax_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.umax.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.smax.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_smax_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_smax_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -1
+; CHECK-NEXT:    slli a0, a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.smax.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.umin.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_umin_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_umin_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.umin.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_smin_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_smin_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -1
+; CHECK-NEXT:    slli a0, a0, 63
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.and.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_and_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_and_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.and.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.or.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_or_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_or_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.or.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.xor.nxv1i64(<vscale x 1 x i64>)
+
+define i64 @vreduce_xor_nxv1i64(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: vreduce_xor_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.xor.nxv1i64(<vscale x 1 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_add_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_add_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_umax_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_umax_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_smax_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_smax_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -1
+; CHECK-NEXT:    slli a0, a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_umin_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_umin_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_smin_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_smin_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -1
+; CHECK-NEXT:    slli a0, a0, 63
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_and_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_and_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_or_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_or_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64>)
+
+define i64 @vreduce_xor_nxv2i64(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: vreduce_xor_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_add_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_add_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredsum.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_umax_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_umax_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_smax_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_smax_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -1
+; CHECK-NEXT:    slli a0, a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredmax.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_umin_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_umin_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredminu.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_smin_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_smin_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -1
+; CHECK-NEXT:    slli a0, a0, 63
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredmin.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_and_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_and_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredand.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_or_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_or_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}
+
+declare i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64>)
+
+define i64 @vreduce_xor_nxv4i64(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: vreduce_xor_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vredxor.vs v25, v8, v25
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %red = call i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64> %v)
+  ret i64 %red
+}