[RISCV][GlobalISel] Select register banks for GPR ALU instructions

[craig.topper]

Summary

This patch implements the getInstrMapping hook for RISCVRegisterBankInfo and others in order to correctly select the GPR register bank for operands of ALU instructions, and the associated operations introduced by the legalizer.

[simoncook]

llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp

15

This looks strange this way round, does this still build if you swap lines 14 and 15?

98

reigsters -> registers, nitpick: RV32

[lewis-revill]

Address comments

[lewis-revill]

Support AND/OR/XOR.

[lewis-revill]

Use utils/update_mir_test_checks.py

[lewis-revill]

Expand patch to include operations for other types as introduced by the legalizer.

[lewis-revill]

Add more operand mappings and expand tests over more types.

[lewis-revill]

Bug fix - don't try to access the size of a $noreg register.

[lewis-revill]

Rebased. Updated tests to match the output of the legalizer.

[arsenm]

llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp

95

I'd recommend keeping the subtarget cached in the class

99

I don't see the point of this loop. It seems like you're just doing a rough legality check, but the function is already required (and enforced by the verifier) to be legal at this point

102

You shouldn't see noreg on a generic instruction so I'm not sure what you're addressing here

llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu32.mir

8

You can drop the IR section

[lewis-revill]

Remove unnecessary loop checking legality

[craig.topper]

Rebase

[craig.topper]

Re-add tests

[craig.topper]

Use size from LLT instead of from Subtarget.getXLen. This will make it easier to support D157770.

[nitinjohnraj]

llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

123 ↗

(On Diff #551388)

Should we consider adding new entries to ValueMappings so that we don't create this array locally? All the binary operations above don't create local arrays for this (though they could).

131 ↗

(On Diff #551388)

Should we consider adding new entries to ValueMappings so that we don't create this array locally? All the binary operations above don't create local arrays for this (though they could).

llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu32.mir

2

Missing test for G_CONSTANT and G_ICMP

7

This test is identical to add_i32 below.

52

I don't think we need this test since we're separately testing for shl and ashr.

79

We don't have a test for G_CONSTANT, but if we make one, we may not need this test. We have tests for G_AND.

287

It's impossible to get a legal G_MUL on RISCV unless the +m or +zmmul attributes are enabled. It might be fine to have this test here to simply demonstrate how we select register banks for G_MUL.

385

I'm not sure we need separate tests for _i64.

llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu64.mir

2

Missing test for G_CONSTANT and G_ICMP

7

Duplicate test, see add_i64

44

I don't think we need this test since we're separately testing for shl and ashr.

79

Once we have a test for G_CONSTANT, we may not need this test.

86

All the _i32 tests are duplicates of the _i64 tests.

665

I don't think that the _i128 tests are meaningful, since we test for each of these generic opcodes separately.

[craig.topper]

llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

123 ↗

(On Diff #551388)

This implementation is consistent with ARM, AArch64, and Mips. I don't think it is possible to put a nullptr entry in the table. It needs to be a null RegisterBankInfo::ValueMapping* but the table row is an array of RegisterBankInfo::ValueMapping.

[craig.topper]

Address review comments

[craig.topper]

Add G_SEXT_INREG

[craig.topper]

Change back to using Subtarget to get register size. I think even with s32 being legal
on RV64 we still want to use a 64 bit size for the GPR.

[craig.topper]

clang-format

[craig.topper]

Add more instructions that we currently legalize.

[craig.topper]

Use the size of the GPR register bank to determine RV32 vs RV64.

[nitinjohnraj]

LGTM

llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir

7 ↗

(On Diff #551866)

Should this global be an i64?

[craig.topper]

llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir

7 ↗

(On Diff #551866)

The type doesn't matter. We're interested in the pointer to the variable not the type of the variable itself. The variable could be any type, even FP or a struct/array.

llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h

 #define GET_TARGET_REGBANK_CLASS
 #include "RISCVGenRegisterBank.inc"
 };
 
 /// This class provides the information for the target register banks.
 class RISCVRegisterBankInfo final : public RISCVGenRegisterBankInfo {
 public:
   RISCVRegisterBankInfo(unsigned HwMode);
+
+  const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
+                                             LLT Ty) const override;
+
+  const InstructionMapping &
+  getInstrMapping(const MachineInstr &MI) const override;
 };
 } // end namespace llvm
 #endif

llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp

 //===-- RISCVRegisterBankInfo.cpp -------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 /// \file
 /// This file implements the targeting of the RegisterBankInfo class for RISCV.
 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #include "RISCVRegisterBankInfo.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
+#include "RISCVSubtarget.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 
 #define GET_TARGET_REGBANK_IMPL
 #include "RISCVGenRegisterBank.inc"
 
+namespace llvm {
+namespace RISCV {
+
+RegisterBankInfo::PartialMapping PartMappings[] = {
+    {0, 32, GPRRegBank},
+    {0, 64, GPRRegBank}
+};
+
+enum PartialMappingIdx {
+  PMI_GPR32 = 0,
+  PMI_GPR64 = 1
+};
+
+RegisterBankInfo::ValueMapping ValueMappings[] = {
+    // Invalid value mapping.
+    {nullptr, 0},
+    // Maximum 3 GPR operands; 32 bit.
+    {&PartMappings[PMI_GPR32], 1},
+    {&PartMappings[PMI_GPR32], 1},
+    {&PartMappings[PMI_GPR32], 1},
+    // Maximum 3 GPR operands; 64 bit.
+    {&PartMappings[PMI_GPR64], 1},
+    {&PartMappings[PMI_GPR64], 1},
+    {&PartMappings[PMI_GPR64], 1}
+};
+
+enum ValueMappingsIdx {
+  InvalidIdx = 0,
+  GPR32Idx = 1,
+  GPR64Idx = 4
+};
+} // namespace RISCV
+} // namespace llvm
+
 using namespace llvm;
 
 RISCVRegisterBankInfo::RISCVRegisterBankInfo(unsigned HwMode)
     : RISCVGenRegisterBankInfo(HwMode) {}
+
+const RegisterBank &
+RISCVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
+                                              LLT Ty) const {
+  switch (RC.getID()) {
+  default:
+    llvm_unreachable("Register class not supported");
+  case RISCV::GPRRegClassID:
+  case RISCV::GPRNoX0RegClassID:
+  case RISCV::GPRNoX0X2RegClassID:
+  case RISCV::GPRTCRegClassID:
+  case RISCV::GPRCRegClassID:
+  case RISCV::GPRC_and_GPRTCRegClassID:
+  case RISCV::GPRX0RegClassID:
+  case RISCV::SPRegClassID:
+    return getRegBank(RISCV::GPRRegBankID);
+  case RISCV::FPR32RegClassID:
+  case RISCV::FPR32CRegClassID:
+  case RISCV::FPR64RegClassID:
+  case RISCV::FPR64CRegClassID:
+    llvm_unreachable("Register class not supported");
+  }
+}
+
+const RegisterBankInfo::InstructionMapping &
+RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
+  const auto &Mapping = getInstrMappingImpl(MI);
+  if (Mapping.isValid())
+    return Mapping;
+
+  const MachineFunction &MF = *MI.getParent()->getParent();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+
+  bool IsRV64 = MF.getSubtarget<RISCVSubtarget>().is64Bit();
+
+  // Indicate if LLT sizes don't match available register banks.
+  // TODO: Fixed size FPR registers on both RV32/RV64.
+  for (const auto &Op : MI.operands()) {
+    if (Op.isReg()) {
+      LLT RegTy = MRI.getType(Op.getReg());
+      unsigned Size = RegTy.getSizeInBits();
+
+      if (IsRV64) {
+        if (Size != 64)
+          return getInvalidInstructionMapping();
+      } else {
+        if (Size != 32)
+          return getInvalidInstructionMapping();
+      }
+    }
+  }
+
+  size_t NumOperands = MI.getNumOperands();
+  const ValueMapping *OperandsMapping =
+      &RISCV::ValueMappings[IsRV64 ? RISCV::GPR64Idx : RISCV::GPR32Idx];
+  unsigned MappingID = DefaultMappingID;
+
+  switch (MI.getOpcode()) {
+  case TargetOpcode::G_ADD:
+  case TargetOpcode::G_SUB:
+  case TargetOpcode::G_MUL:
+  case TargetOpcode::G_SDIV:
+  case TargetOpcode::G_SREM:
+  case TargetOpcode::G_UDIV:
+  case TargetOpcode::G_UREM:
+  case TargetOpcode::G_AND:
+  case TargetOpcode::G_OR:
+  case TargetOpcode::G_XOR:
+    break;
+  default:
+    return getInvalidInstructionMapping();
+  }
+
+  return getInstructionMapping(MappingID, /*Cost=*/1, OperandsMapping,
+                               NumOperands);
+}

llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu32.mir

+# RUN: llc -march=riscv32 -x mir -run-pass=regbankselect -disable-gisel-legality-check -simplify-mir -verify-machineinstrs < %s \
+# RUN: | FileCheck -check-prefix=RV32I %s
+
+--- |
+
+  define void @add_i32() { entry: ret void }
+  define void @sub_i32() { entry: ret void }
+  define void @mul_i32() { entry: ret void }
+  define void @sdiv_i32() { entry: ret void }
+  define void @srem_i32() { entry: ret void }
+  define void @udiv_i32() { entry: ret void }
+  define void @urem_i32() { entry: ret void }
+  define void @and_i32() { entry: ret void }
+  define void @or_i32() { entry: ret void }
+  define void @xor_i32() { entry: ret void }
+
+...
+---
+name:            add_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: add_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT:   [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[ADD]](s32)
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_ADD %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sub_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: sub_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT:   [[SUB:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[SUB]](s32)
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_SUB %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            mul_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: mul_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT:   [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[MUL]](s32)
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_MUL %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sdiv_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: sdiv_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT:   [[SDIV:%[0-9]+]]:gprb(s32) = G_SDIV [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[SDIV]](s32)
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_SDIV %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            srem_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: srem_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT:   [[SREM:%[0-9]+]]:gprb(s32) = G_SREM [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[SREM]](s32)
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_SREM %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            udiv_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: udiv_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT:   [[UDIV:%[0-9]+]]:gprb(s32) = G_UDIV [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[UDIV]](s32)
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_UDIV %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            urem_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: urem_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT:   [[UREM:%[0-9]+]]:gprb(s32) = G_UREM [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[UREM]](s32)
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_UREM %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            and_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: and_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT:   [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[AND]](s32)
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_AND %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            or_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: or_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT:   [[OR:%[0-9]+]]:gprb(s32) = G_OR [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[OR]](s32)
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_OR %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            xor_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: xor_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT:   [[XOR:%[0-9]+]]:gprb(s32) = G_XOR [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[XOR]](s32)
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_XOR %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...

llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu64.mir

+# RUN: llc -march=riscv64 -x mir -run-pass=regbankselect -disable-gisel-legality-check -simplify-mir -verify-machineinstrs < %s \
+# RUN: | FileCheck -check-prefix=RV64I %s
+
+--- |
+
+  define void @add_i64() { entry: ret void }
+  define void @sub_i64() { entry: ret void }
+  define void @mul_i64() { entry: ret void }
+  define void @sdiv_i64() { entry: ret void }
+  define void @srem_i64() { entry: ret void }
+  define void @udiv_i64() { entry: ret void }
+  define void @urem_i64() { entry: ret void }
+  define void @and_i64() { entry: ret void }
+  define void @or_i64() { entry: ret void }
+  define void @xor_i64() { entry: ret void }
+
+...
+---
+name:            add_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: add_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT:   [[ADD:%[0-9]+]]:gprb(s64) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[ADD]](s64)
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_ADD %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sub_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: sub_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT:   [[SUB:%[0-9]+]]:gprb(s64) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[SUB]](s64)
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_SUB %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            mul_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: mul_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT:   [[MUL:%[0-9]+]]:gprb(s64) = G_MUL [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[MUL]](s64)
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_MUL %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sdiv_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: sdiv_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT:   [[SDIV:%[0-9]+]]:gprb(s64) = G_SDIV [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[SDIV]](s64)
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_SDIV %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            srem_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: srem_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT:   [[SREM:%[0-9]+]]:gprb(s64) = G_SREM [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[SREM]](s64)
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_SREM %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            udiv_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: udiv_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT:   [[UDIV:%[0-9]+]]:gprb(s64) = G_UDIV [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[UDIV]](s64)
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_UDIV %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            urem_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: urem_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT:   [[UREM:%[0-9]+]]:gprb(s64) = G_UREM [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[UREM]](s64)
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_UREM %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            and_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: and_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT:   [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[AND]](s64)
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_AND %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            or_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: or_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT:   [[OR:%[0-9]+]]:gprb(s64) = G_OR [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[OR]](s64)
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_OR %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            xor_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: xor_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT:   [[XOR:%[0-9]+]]:gprb(s64) = G_XOR [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[XOR]](s64)
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_XOR %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...