Lowering CPI/JTI/BA to assembly

[Xiangling_L]

Summary

• On AIX, jump table is always relative;
• Put CPI and JTI into ReadOnlySection;
• Create the temp symbol for block address symbol;
• Update MIR testcases and add related assembly part;

[sfertile]

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

1757

Nit: Formatting.

llvm/lib/CodeGen/MachineModuleInfo.cpp

124

IIUC we expect that the functions entry point symbol already exists, and has its containing csect properly set. If so it be more appropriate to use Context.lookupSymbol and have appropriate error handling if the symbol doesn't exist or if its containing csect is not set.

[jasonliu]

I'm not able to apply this patch cleanly please rebase. Thank you.

[jasonliu]

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

1757

We could call member function of triple instead of raw comparison:
TM.getTargetTriple().isOSAIX or TM.getTargetTriple().isOSBinFormatXCOFF
Same for all the raw comparison below.

[Xiangling_L]

Update testcases;
Address 1st round reviews.

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

1757

Sorry, but can you point out the formatting issue more explicitly? And the formatting here is got from clang-format.

1757

Thanks, I will update it.

llvm/lib/CodeGen/MachineModuleInfo.cpp

124

Thanks, I will add an assertion after we do lookupSymbol for FnEntryPointSym. And since in getContainingCsect(), we already add assertion to test if the csect for the sym exists or not, I will omit the assertion here.

[jasonliu]

When I apply your patch to master, it didn't apply cleanly. So please rebase.
And when I did some work to manually apply it, and run through clang-format, clang-format changed several places.
I suspect it's due to the tabs vs space issue.
I suggest to update this patch with after running the clang-format on it.

llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h

237

Format looks off here. You might used tabs instead of space.

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

1758

Format issue:
This line doesn't look like aligned.

[Xiangling_L]

Rebase the patch on the latest master;
Fix some formatting issues;

[Xiangling_L]

In D70243#1748063, @jasonliu wrote:

When I apply your patch to master, it didn't apply cleanly. So please rebase.
And when I did some work to manually apply it, and run through clang-format, clang-format changed several places.
I suspect it's due to the tabs vs space issue.
I suggest to update this patch with after running the clang-format on it.

Thanks for your advice, I rebased this PR and fixed the format issue. Please try again to see if you can apply it on latest master.

[sfertile]

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

1757

Its fixed now, but phabricator was showing the code inside the if block was indented less then the if statement itself.

llvm/lib/CodeGen/MachineModuleInfo.cpp

125

minor nit: has --> have.

llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp

1875

Minor nit: IIUC then Comdats aren't supported by the XCOFF specification. The yet at the ned makes it sound to me like its something supported but not implemented in LLVM yet.

llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll

87

I don't understand why we have a check-not in each of the tests for .tc. Is it because we haven't implemented the emission of the toc entries yet and its a reminder to fixup the test when we do implement that?

[jasonliu]

The "make check-all" did not return clean for the test case you just added.
There is mismatch for the test result and assertions. You might be missing something in the code that you modified.

[jasonliu]

Sorry, please ignore the test did not come clean comments. I realized my branch did not have D70182 in it. After pulling it in, the test works as expected.
I will continue my review.

[sfertile]

Other then the few nits I mentioned LGTM.

In D70243#1750631, @jasonliu wrote:

Sorry, please ignore the test did not come clean comments. I realized my branch did not have D70182 in it. After pulling it in, the test works as expected.
I will continue my review.

I did the same thing :)

llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll

87

Spoke offline with @Xiangling_L and the CHECK-NOTS are there so we can update the tests when we start writing out the toc entries.

[jasonliu]

Some observation for constant pool lowering:
We put all the constant pool data into rodata section, and create one TC entry per constant pool reference.
It hinders the ability for linker to garbage collect unused data. (Generates them into a separate RO section helps a bit, but won't fully solve this issue)
And we would also create a lot of TC entries for constant pool that might not get cleanup.

For comparison, gcc generates the value of constant pool data directly into the TC entry. It's faster and garbage collectable if not used.
xlC generates all the constant pool data in a single csect, but reference different data with one TC entry. Less efficient, but still less TC entry generated, and it does not mess with the other rodata.

So with this implementation, it would work functionally. But performance and space wise, could not compare to the other two compilers.
I'm Okay with moving forward with some TODOs in our mind.

[jasonliu]

llvm/lib/CodeGen/MachineModuleInfo.cpp

127

nit: CSect -> Csect

[Xiangling_L]

In D70243#1750779, @jasonliu wrote:

Some observation for constant pool lowering:
We put all the constant pool data into rodata section, and create one TC entry per constant pool reference.
It hinders the ability for linker to garbage collect unused data. (Generates them into a separate RO section helps a bit, but won't fully solve this issue)
And we would also create a lot of TC entries for constant pool that might not get cleanup.

For comparison, gcc generates the value of constant pool data directly into the TC entry. It's faster and garbage collectable if not used.

I did some investigation about LLVM constant pool, as I remember, except for int value which will be put directly into TC entry, others like double, float etc. will be put into constant pool in LLVM. If we want to mimic GCC behavior, it probably would be a large piece of refactoring.

xlC generates all the constant pool data in a single csect, but reference different data with one TC entry. Less efficient, but still less TC entry generated, and it does not mess with the other rodata.

Sorry, but can you list your testcase and some explanatory emitted results here, I am not able to reproduce what you said. And based on my observation, xlC generates one RO csect and one TC entry for each global const value [eg. float a = 5.56].

So with this implementation, it would work functionally. But performance and space wise, could not compare to the other two compilers.
I'm Okay with moving forward with some TODOs in our mind.

Thank you for your advice. Some plan I have in mind for emitting jump table index is that once we start supporting unique sections something like -fdata-sections, then we can emit each JTI to unique RO section. So I put an assertion in getSectionForJumpTable. And based on your suggestion I think I can do something similar in getSectionForConstant. Please let me know if this will resolve your concerns.

[jasonliu]

For comparison, gcc generates the value of constant pool data directly into the TC entry. It's faster and garbage collectable if not used.

I did some investigation about LLVM constant pool, as I remember, except for int value which will be put directly into TC entry, others like double, float etc. will be put into constant pool in LLVM. If we want to mimic GCC behavior, it probably would be a large piece of refactoring.

I don't think llvm actually try to put int directly into TC entry, it always put a label in TC entry, or we just use that integer value directly in the assembly. But please correct me if I'm wrong.
We don't need to switch to that behavior right now, but later when we care about performance then we might want to think about it.
Here's my test case:

float foo(){
  return 1.2;
}
double bar(){
  return 3.4;
}

GCC generates:

LC..0:
  .tc FS_3f99999a[TC],0x3f99999a
lfs 0,LC..0(2)

LC..1:
  .tc FD_400b3333_33333333[TC],0x400b3333,0x33333333
lfd 0,LC..1(2)

• Notice that the value is store directly into the TC entry.

xlc:

  .csect  H.20.NO_SYMBOL{RO}, 3
  .long 0x3ff33333              # "?\36333"
  .long 0x33333333              # "3333"
  .long 0x400b3333              # "@\v33"
  .long 0x33333333              # "3333"

T.18.NO_SYMBOL:
  .tc H.18.NO_SYMBOL{TC},H.20.NO_SYMBOL{RO}

  l          r31,T.18.NO_SYMBOL(RTOC)
  lfd        fp1,0(r31)

  l          r31,T.18.NO_SYMBOL(RTOC)
  lfd        fp1,8(r31)

• Notice that xlc only used 1 tc entry to access this RO data. It use a dedicate csect for constant pool instead of mixing with the other read only data. (you could add a "const int a= 10;" into the test case, and it won't use the same csect as constant pool)

xlC generates all the constant pool data in a single csect, but reference different data with one TC entry. Less efficient, but still less TC entry generated, and it does not mess with the other rodata.

Sorry, but can you list your testcase and some explanatory emitted results here, I am not able to reproduce what you said. And based on my observation, xlC generates one RO csect and one TC entry for each global const value [eg. float a = 5.56].

See my test case and explanations above.

So with this implementation, it would work functionally. But performance and space wise, could not compare to the other two compilers.
I'm Okay with moving forward with some TODOs in our mind.

Thank you for your advice. Some plan I have in mind for emitting jump table index is that once we start supporting unique sections something like -fdata-sections, then we can emit each JTI to unique RO section. So I put an assertion in getSectionForJumpTable. And based on your suggestion I think I can do something similar in getSectionForConstant. Please let me know if this will resolve your concerns.

-fdata-sections would help for the garbage collection case. But for performance wise, we might still want to investigate if we could do something similar like what GCC does (at least for constant pool).

[Xiangling_L]

I don't think llvm actually try to put int directly into TC entry, it always put a label in there. But please correct me if I'm wrong.

Sorry, actually I meant that LLVM put int directly into instruction, there even won't be any TC entry for it. Others, like float, double etc. will be put into constant pool and each of them has a TC entry.

-fdata-sections would help for the garbage collection case. But for performance wise, we might still want to investigate if we could do something similar like what GCC does (at least for constant pool).

Yes, I agree that GCC behavior is faster because there is no one extra step to load real value from the place TC entry points to. I will do more investigation about this and see if we want to address this in this PR.

llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h

public:
 
   const MCExpr *lowerRelativeReference(const GlobalValue *LHS,
                                        const GlobalValue *RHS,
                                        const TargetMachine &TM) const override;
 
   MCSection *SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind,
                                     const TargetMachine &TM) const override;
 
+  MCSection *getSectionForJumpTable(const Function &F,
+                                    const TargetMachine &TM) const override;
+
+  /// Given a constant with the SectionKind, return a section that it should be
+  /// placed in.
+  MCSection *getSectionForConstant(const DataLayout &DL, SectionKind Kind,
+                                   const Constant *C,
+                                   unsigned &Align) const override;
+
   static XCOFF::StorageClass getStorageClassForGlobal(const GlobalObject *GO);
 };
 
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_TARGETLOWERINGOBJECTFILEIMPL_H

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

void AsmPrinter::EmitConstantPool() {
   unsigned Offset = 0;
   for (unsigned i = 0, e = CPSections.size(); i != e; ++i) {
     for (unsigned j = 0, ee = CPSections[i].CPEs.size(); j != ee; ++j) {
       unsigned CPI = CPSections[i].CPEs[j];
       MCSymbol *Sym = GetCPISymbol(CPI);
       if (!Sym->isUndefined())
         continue;
 
+      if (TM.getTargetTriple().isOSBinFormatXCOFF()) {
+        cast<MCSymbolXCOFF>(Sym)->setContainingCsect(
+            cast<MCSectionXCOFF>(CPSections[i].S));
+      }
+
       if (CurSection != CPSections[i].S) {
         OutStreamer->SwitchSection(CPSections[i].S);
         EmitAlignment(Align(CPSections[i].Alignment));
         CurSection = CPSections[i].S;
         Offset = 0;
       }
 
       MachineConstantPoolEntry CPE = CP[CPI];
for (unsigned JTI = 0, e = JT.size(); JTI != e; ++JTI) {
     }
 
     // On some targets (e.g. Darwin) we want to emit two consecutive labels
     // before each jump table.  The first label is never referenced, but tells
     // the assembler and linker the extents of the jump table object.  The
     // second label is actually referenced by the code.
     if (JTInDiffSection && DL.hasLinkerPrivateGlobalPrefix())
       // FIXME: This doesn't have to have any specific name, just any randomly
-      // named and numbered 'l' label would work.  Simplify GetJTISymbol.
+      // named and numbered local label started with 'l' would work.  Simplify
+      // GetJTISymbol.
       OutStreamer->EmitLabel(GetJTISymbol(JTI, true));
 
-    OutStreamer->EmitLabel(GetJTISymbol(JTI));
+    MCSymbol* JTISymbol = GetJTISymbol(JTI);
+    if (TM.getTargetTriple().isOSBinFormatXCOFF()) {
+      cast<MCSymbolXCOFF>(JTISymbol)->setContainingCsect(
+          cast<MCSectionXCOFF>(TLOF.getSectionForJumpTable(F, TM)));
+    }
+    OutStreamer->EmitLabel(JTISymbol);
 
     for (unsigned ii = 0, ee = JTBBs.size(); ii != ee; ++ii)
       EmitJumpTableEntry(MJTI, JTBBs[ii], JTI);
   }
   if (!JTInDiffSection)
     OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
 }
 

llvm/lib/CodeGen/MachineModuleInfo.cpp

 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/Module.h"
 #include "llvm/IR/Value.h"
 #include "llvm/IR/ValueHandle.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCSymbol.h"
+#include "llvm/MC/MCSymbolXCOFF.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Target/TargetLoweringObjectFile.h"
 #include "llvm/Target/TargetMachine.h"
 #include <algorithm>
 #include <cassert>
 #include <memory>
ArrayRef<MCSymbol *> MMIAddrLabelMap::getAddrLabelSymbolToEmit(BasicBlock *BB) {
   }
 
   // Otherwise, this is a new entry, create a new symbol for it and add an
   // entry to BBCallbacks so we can be notified if the BB is deleted or RAUWd.
   BBCallbacks.emplace_back(BB);
   BBCallbacks.back().setMap(this);
   Entry.Index = BBCallbacks.size() - 1;
   Entry.Fn = BB->getParent();
-  Entry.Symbols.push_back(Context.createTempSymbol(!BB->hasAddressTaken()));
+  MCSymbol *Sym = Context.createTempSymbol(!BB->hasAddressTaken());
+  if (Context.getObjectFileInfo()->getTargetTriple().isOSBinFormatXCOFF()) {
+    MCSymbol *FnEntryPointSym =
+        Context.lookupSymbol("." + Entry.Fn->getName());
+    assert(FnEntryPointSym && "The function entry pointer symbol should have"
+                  " already been initialized.");
+    MCSectionXCOFF *Csect =
+        cast<MCSymbolXCOFF>(FnEntryPointSym)->getContainingCsect();
+    cast<MCSymbolXCOFF>(Sym)->setContainingCsect(Csect);
+  }
+  Entry.Symbols.push_back(Sym);
   return Entry.Symbols;
 }
 
 /// If we have any deleted symbols for F, return them.
 void MMIAddrLabelMap::
 takeDeletedSymbolsForFunction(Function *F, std::vector<MCSymbol*> &Result) {
   DenseMap<AssertingVH<Function>, std::vector<MCSymbol*>>::iterator I =
     DeletedAddrLabelsNeedingEmission.find(F);

llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp

MCSection *TargetLoweringObjectFileXCOFF::SelectSectionForGlobal(
 
   if (Kind.isReadOnly() && !Kind.isMergeableConst() &&
       !Kind.isMergeableCString())
     return ReadOnlySection;
 
   report_fatal_error("XCOFF other section types not yet implemented.");
 }
 
+MCSection *TargetLoweringObjectFileXCOFF::getSectionForJumpTable(
+    const Function &F, const TargetMachine &TM) const {
+  assert (!TM.getFunctionSections() && "Unique sections not supported on XCOFF"
+          " yet.");
+  assert (!F.getComdat() && "Comdat not supported on XCOFF.");
+  //TODO: Enable emiting jump table to unique sections when we support it.
+  return ReadOnlySection;
+}
+
 bool TargetLoweringObjectFileXCOFF::shouldPutJumpTableInFunctionSection(
     bool UsesLabelDifference, const Function &F) const {
-  report_fatal_error("TLOF XCOFF not yet implemented.");
+  return false;
+}
+
+/// Given a mergeable constant with the specified size and relocation
+/// information, return a section that it should be placed in.
+MCSection *TargetLoweringObjectFileXCOFF::getSectionForConstant(
+    const DataLayout &DL, SectionKind Kind, const Constant *C,
+    unsigned &Align) const {
+  //TODO: Enable emiting constant pool to unique sections when we support it.
+  if (Kind.isReadOnly() && ReadOnlySection != nullptr)
+    return ReadOnlySection;
 }
 
 void TargetLoweringObjectFileXCOFF::Initialize(MCContext &Ctx,
                                                const TargetMachine &TgtM) {
   TargetLoweringObjectFile::Initialize(Ctx, TgtM);
   TTypeEncoding = 0;
   PersonalityEncoding = 0;
   LSDAEncoding = 0;

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (isJumpTableRelative())
     return MachineJumpTableInfo::EK_LabelDifference32;
 
   return TargetLowering::getJumpTableEncoding();
 }
 
 bool PPCTargetLowering::isJumpTableRelative() const {
   if (UseAbsoluteJumpTables)
     return false;
-  if (Subtarget.isPPC64())
+  if (Subtarget.isPPC64() || Subtarget.isAIXABI())
     return true;
   return TargetLowering::isJumpTableRelative();
 }
 
 SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
                                                     SelectionDAG &DAG) const {
-  if (!Subtarget.isPPC64())
+  if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
     return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
 
   switch (getTargetMachine().getCodeModel()) {
   case CodeModel::Small:
   case CodeModel::Medium:
     return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
   default:
     return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
                        getPointerTy(DAG.getDataLayout()));
   }
 }
 
 const MCExpr *
 PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
                                                 unsigned JTI,
                                                 MCContext &Ctx) const {
-  if (!Subtarget.isPPC64())
+  if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
     return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
 
   switch (getTargetMachine().getCodeModel()) {
   case CodeModel::Small:
   case CodeModel::Medium:
     return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
   default:
     return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);

llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32SMALL-MIR %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32LARGE-MIR %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64SMALL-MIR %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64LARGE-MIR %s
 
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,CHECK %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,CHECK %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,CHECK %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,CHECK %s
+
 define void @foo() {
 entry:
   %tmp = alloca i64
   br label %__here
 
 __here:
   store i64 ptrtoint (i8* blockaddress(@foo, %__here) to i64), i64* %tmp
   ret void
 }
 
 ; 32SMALL-MIR: renamable $r[[REG1:[0-9]+]] = LWZtoc blockaddress(@foo, %ir-block.__here), $r2 :: (load 4 from got)
 
 ; 32LARGE-MIR: renamable $r[[REG1:[0-9]+]] = ADDIStocHA $r2, blockaddress(@foo, %ir-block.__here)
 ; 32LARGE-MIR: renamable $r[[REG2:[0-9]+]] = LWZtocL blockaddress(@foo, %ir-block.__here), killed renamable $r[[REG1]], implicit $r2 :: (load 4 from got)
 
 ; 64SMALL-MIR: renamable $x[[REG1:[0-9]+]] = LDtocBA blockaddress(@foo, %ir-block.__here), $x2 :: (load 8 from got)
 
 ; 64LARGE-MIR: renamable $x[[REG1:[0-9]+]] = ADDIStocHA8 $x2, blockaddress(@foo, %ir-block.__here)
 ; 64LARGE-MIR: renamable $x[[REG2:[0-9]+]] = LDtocL blockaddress(@foo, %ir-block.__here), killed renamable $x[[REG1]], implicit $x2 :: (load 8 from got)
+
+; 32SMALL-ASM-LABEL: foo
+; 32SMALL-ASM: .foo:
+; 32SMALL-ASM: Ltmp0:
+; 32SMALL-ASM:         lwz [[REG1:[0-9]+]], LC0(2)
+
+; 32LARGE-ASM-LABEL: foo
+; 32LARGE-ASM: .foo:
+; 32LARGE-ASM: Ltmp0:
+; 32LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
+; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], LC0@l([[REG1]])
+
+; 64SMALL-ASM-LABEL: foo
+; 64SMALL-ASM: .foo:
+; 64SMALL-ASM: Ltmp0:
+; 64SMALL-ASM:         ld [[REG1:[0-9]+]], LC0(2)
+
+; 64LARGE-ASM-LABEL: foo
+; 64LARGE-ASM: .foo:
+; 64LARGE-ASM: Ltmp0:
+; 64LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
+; 64LARGE-ASM:         ld [[REG2:[0-9]+]], LC0@l([[REG1]])
+
+; CHECK: .toc
+; CHECK-NOT: .tc

llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32SMALL-MIR %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32LARGE-MIR %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64SMALL-MIR %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64LARGE-MIR %s
 
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,CHECK %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,CHECK %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,CHECK %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,CHECK %s
+
 define float @test_float() {
 entry:
   ret float 5.500000e+00
 }
 
 ; 32SMALL-MIR: renamable $r[[REG1:[0-9]+]] = LWZtoc %const.0, $r2 :: (load 4 from got)
 ; 32SMALL-MIR: renamable $f[[REG2:[0-9]+]] = LFS 0, killed renamable $r[[REG1]] :: (load 4 from constant-pool)
 
 ; 32LARGE-MIR: renamable $r[[REG1:[0-9]+]] = ADDIStocHA $r2, %const.0
 ; 32LARGE-MIR: renamable $r[[REG2:[0-9]+]] = LWZtocL %const.0, killed renamable $r[[REG1]], implicit $r2 :: (load 4 from got)
 ; 32LARGE-MIR: renamable $f[[REG3:[0-9]+]] = LFS 0, killed renamable $r[[REG2]] :: (load 4 from constant-pool)
 
 ; 64SMALL-MIR: renamable $x[[REG1:[0-9]+]] = LDtocCPT %const.0, $x2 :: (load 8 from got)
 ; 64SMALL-MIR: renamable $f[[REG2:[0-9]+]] = LFS 0, killed renamable $x[[REG1]] :: (load 4 from constant-pool)
 
 ; 64LARGE-MIR: renamable $x[[REG1:[0-9]+]] = ADDIStocHA8 $x2, %const.0
 ; 64LARGE-MIR: renamable $x[[REG2:[0-9]+]] = LDtocL %const.0, killed renamable $x[[REG1]], implicit $x2 :: (load 8 from got)
 ; 64LARGE-MIR: renamable $f[[REG3:[0-9]+]] = LFS 0, killed renamable $x[[REG2]] :: (load 4 from constant-pool)
+
+; 32SMALL-ASM:         .csect .rodata[RO]
+; 32SMALL-ASM:         .align  2
+; 32SMALL-ASM: .LCPI0_0:
+; 32SMALL-ASM:         .long  1085276160
+; 32SMALL-ASM: .test_float:
+; 32SMALL-ASM:         lwz [[REG1:[0-9]+]], LC0(2)
+; 32SMALL-ASM:         lfs 1, 0([[REG1]])
+; 32SMALL-ASM:         blr
+
+; 32LARGE-ASM:         .csect .rodata[RO]
+; 32LARGE-ASM:         .align  2
+; 32LARGE-ASM: .LCPI0_0:
+; 32LARGE-ASM:         .long   1085276160
+; 32LARGE-ASM: .test_float:
+; 32LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
+; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], LC0@l([[REG1]])
+; 32LARGE-ASM:         lfs 1, 0([[REG2]])
+; 32LARGE-ASM:         blr
+
+; 64SMALL-ASM:         .csect .rodata[RO]
+; 64SMALL-ASM:         .align  2
+; 64SMALL-ASM: .LCPI0_0:
+; 64SMALL-ASM:         .long   1085276160
+; 64SMALL-ASM: .test_float:
+; 64SMALL-ASM:         ld [[REG1:[0-9]+]], LC0(2)
+; 64SMALL-ASM:         lfs 1, 0([[REG1]])
+; 64SMALL-ASM:         blr
+
+; 64LARGE-ASM:         .csect .rodata[RO]
+; 64LARGE-ASM:         .align  2
+; 64LARGE-ASM: .LCPI0_0:
+; 64LARGE-ASM:         .long   1085276160
+; 64LARGE-ASM: .test_float:
+; 64LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
+; 64LARGE-ASM:         ld [[REG2:[0-9]+]], LC0@l([[REG1]])
+; 64LARGE-ASM:         lfs 1, 0([[REG2]])
+; 64LARGE-ASM:         blr
+
+; CHECK: .toc
+; CHECK-NOT: .tc

llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32SMALL-MIR %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32LARGE-MIR %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64SMALL-MIR %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64LARGE-MIR %s
 
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=small < %s | FileCheck \
+; RUN: --check-prefixes=32SMALL-ASM,CHECK %s
+
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=large < %s | FileCheck \
+; RUN: --check-prefixes=32LARGE-ASM,CHECK %s
+
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -code-model=small < %s | FileCheck \
+; RUN: --check-prefixes=64SMALL-ASM,CHECK %s
+
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -code-model=large < %s | FileCheck \
+; RUN: --check-prefixes=64LARGE-ASM,CHECK %s
+
   define i32 @jump_table(i32 %a) {
   entry:
     switch i32 %a, label %sw.epilog [
       i32 1, label %sw.bb
       i32 2, label %sw.bb1
       i32 3, label %sw.bb2
       i32 4, label %sw.bb3
     ]
; RUN: --check-prefixes=64LARGE-ASM,CHECK %s
 
   sw.epilog:
     ret i32 0
   }
 
 
 ; 32SMALL-MIR: renamable $r[[REG1:[0-9]+]] = LWZtoc %jump-table.0, $r2 :: (load 4 from got)
 ; 32SMALL-MIR: renamable $r[[REG3:[0-9]+]] = RLWINM killed renamable $r[[REG2:[0-9]+]], 2, 0, 29
-; 32SMALL-MIR: renamable $r[[REG4:[0-9]+]] = LWZX killed renamable $r[[REG3]], killed renamable $r[[REG1]] :: (load 4 from jump-table)
+; 32SMALL-MIR: renamable $r[[REG4:[0-9]+]] = LWZX killed renamable $r[[REG3]], renamable $r[[REG1]] :: (load 4 from jump-table)
+; 32SMALL-MIR: renamable $r[[REG5:[0-9]+]] = ADD4 killed renamable $r[[REG4]], killed renamable $r[[REG1]]
 
 ; 32LARGE-MIR: renamable $r[[REG1:[0-9]+]] = ADDIStocHA $r2, %jump-table.0
 ; 32LARGE-MIR: renamable $r[[REG2:[0-9]+]] = LWZtocL %jump-table.0, killed renamable $r[[REG1]], implicit $r2 :: (load 4 from got)
 ; 32LARGE-MIR: renamable $r[[REG4:[0-9]+]] = RLWINM killed renamable $r[[REG3:[0-9]+]], 2, 0, 29
-; 32LARGE-MIR: renamable $r[[REG5:[0-9]+]] = LWZX killed renamable $r[[REG4]], killed renamable $r[[REG2]] :: (load 4 from jump-table)
+; 32LARGE-MIR: renamable $r[[REG5:[0-9]+]] = LWZX killed renamable $r[[REG4]], renamable $r[[REG2]] :: (load 4 from jump-table)
+; 32LARGE-MIR: renamable $r[[REG6:[0-9]+]] = ADD4 killed renamable $r[[REG5]], killed renamable $r[[REG2]]
 
 ; 64SMALL-MIR: renamable $x[[REG1:[0-9]+]] = LDtocJTI %jump-table.0, $x2 :: (load 8 from got)
 ; 64SMALL-MIR: renamable $x[[REG3:[0-9]+]] = RLDIC killed renamable $x[[REG2:[0-9]+]], 2, 30
 ; 64SMALL-MIR: renamable $x[[REG4:[0-9]+]] = LWAX killed renamable $x[[REG3]], renamable $x[[REG1]] :: (load 4 from jump-table)
+; 64SMALL-MIR: renamable $x[[REG6:[0-9]+]] = ADD8 killed renamable $x[[REG4]], killed renamable $x[[REG1]]
 
 ; 64LARGE-MIR: renamable $x[[REG1:[0-9]+]] = ADDIStocHA8 $x2, %jump-table.0
 ; 64LARGE-MIR: renamable $x[[REG2:[0-9]+]] = LDtocL %jump-table.0, killed renamable $x[[REG1]], implicit $x2 :: (load 8 from got)
 ; 64LARGE-MIR: renamable $x[[REG4:[0-9]+]] = RLDIC killed renamable $x[[REG3:[0-9]+]], 2, 30
-; 64LARGE-MIR: renamable $x[[REG5:[0-9]+]] = LWAX killed renamable $x[[REG4]], killed renamable $x[[REG2]] :: (load 4 from jump-table)
+; 64LARGE-MIR: renamable $x[[REG5:[0-9]+]] = LWAX killed renamable $x[[REG4]], renamable $x[[REG2]] :: (load 4 from jump-table)
+; 64LARGE-MIR: renamable $x[[REG6:[0-9]+]] = ADD8 killed renamable $x[[REG5]], killed renamable $x[[REG2]]
+
+; 32SMALL-ASM-LABEL: jump_table
+; 32SMALL-ASM: .jump_table:
+; 32SMALL-ASM:      addi 3, 3, -1
+; 32SMALL-ASM:      cmplwi 3, 3
+; 32SMALL-ASM:      bgt 0, LBB0_6
+; 32SMALL-ASM:      lwz 4, LC0(2)
+; 32SMALL-ASM:      slwi 3, 3, 2
+; 32SMALL-ASM:      lwzx 3, 3, 4
+; 32SMALL-ASM:      add 3, 3, 4
+; 32SMALL-ASM:      mtctr 3
+; 32SMALL-ASM:      bctr
+; 32SMALL-ASM: LBB0_2:
+; 32SMALL-ASM: LBB0_3:
+; 32SMALL-ASM: LBB0_4:
+; 32SMALL-ASM: LBB0_5:
+; 32SMALL-ASM: LBB0_6:
+; 32SMALL-ASM:      li 3, 0
+; 32SMALL-ASM:      blr
+; 32SMALL-ASM:      .csect .rodata[RO]
+; 32SMALL-ASM:      .align  2
+; 32SMALL-ASM: .LJTI0_0:
+; 32SMALL-ASM:      .long   LBB0_2-.LJTI0_0
+; 32SMALL-ASM:      .long   LBB0_3-.LJTI0_0
+; 32SMALL-ASM:      .long   LBB0_4-.LJTI0_0
+; 32SMALL-ASM:      .long   LBB0_5-.LJTI0_0
+
+; 32LARGE-ASM-LABEL: jump_table
+; 32LARGE-ASM: .jump_table:
+; 32LARGE-ASM:      addi 3, 3, -1
+; 32LARGE-ASM:      cmplwi  3, 3
+; 32LARGE-ASM:      bgt     0, LBB0_6
+; 32LARGE-ASM:      addis 4, LC0@u(2)
+; 32LARGE-ASM:      slwi 3, 3, 2
+; 32LARGE-ASM:      lwz 4, LC0@l(4)
+; 32LARGE-ASM:      lwzx 3, 3, 4
+; 32LARGE-ASM:      add 3, 3, 4
+; 32LARGE-ASM:      mtctr 3
+; 32LARGE-ASM:      bctr
+; 32LARGE-ASM: LBB0_2:
+; 32LARGE-ASM: LBB0_3:
+; 32LARGE-ASM: LBB0_4:
+; 32LARGE-ASM: LBB0_5:
+; 32LARGE-ASM: LBB0_6:
+; 32LARGE-ASM:      li 3, 0
+; 32LARGE-ASM:      blr
+; 32LARGE-ASM:      .csect .rodata[RO]
+; 32LARGE-ASM:      .align  2
+; 32LARGE-ASM: .LJTI0_0:
+; 32LARGE-ASM:      .long   LBB0_2-.LJTI0_0
+; 32LARGE-ASM:      .long   LBB0_3-.LJTI0_0
+; 32LARGE-ASM:      .long   LBB0_4-.LJTI0_0
+; 32LARGE-ASM:      .long   LBB0_5-.LJTI0_0
+
+; 64SMALL-ASM-LABEL: jump_table
+; 64SMALL-ASM: .jump_table:
+; 64SMALL-ASM:      addi 3, 3, -1
+; 64SMALL-ASM:      cmplwi  3, 3
+; 64SMALL-ASM:      bgt     0, LBB0_6
+; 64SMALL-ASM:      ld 4, LC0(2)
+; 64SMALL-ASM:      rldic 3, 3, 2, 30
+; 64SMALL-ASM:      lwax 3, 3, 4
+; 64SMALL-ASM:      add 3, 3, 4
+; 64SMALL-ASM:      mtctr 3
+; 64SMALL-ASM:      bctr
+; 64SMALL-ASM: LBB0_2:
+; 64SMALL-ASM: LBB0_3:
+; 64SMALL-ASM: LBB0_4:
+; 64SMALL-ASM: LBB0_5:
+; 64SMALL-ASM: LBB0_6:
+; 64SMALL-ASM:      li 3, 0
+; 64SMALL-ASM:      blr
+; 64SMALL-ASM:      .csect .rodata[RO]
+; 64SMALL-ASM:      .align  2
+; 64SMALL-ASM: .LJTI0_0:
+; 64SMALL-ASM:      .long   LBB0_2-.LJTI0_0
+; 64SMALL-ASM:      .long   LBB0_3-.LJTI0_0
+; 64SMALL-ASM:      .long   LBB0_4-.LJTI0_0
+; 64SMALL-ASM:      .long   LBB0_5-.LJTI0_0
+
+; 64LARGE-ASM-LABEL: jump_table
+; 64LARGE-ASM: .jump_table:
+; 64LARGE-ASM:      addi 3, 3, -1
+; 64LARGE-ASM:      cmplwi  3, 3
+; 64LARGE-ASM:      bgt     0, LBB0_6
+; 64LARGE-ASM:      addis 4, LC0@u(2)
+; 64LARGE-ASM:      rldic 3, 3, 2, 30
+; 64LARGE-ASM:      ld 4, LC0@l(4)
+; 64LARGE-ASM:      lwax 3, 3, 4
+; 64LARGE-ASM:      add 3, 3, 4
+; 64LARGE-ASM:      mtctr 3
+; 64LARGE-ASM:      bctr
+; 64LARGE-ASM: LBB0_2:
+; 64LARGE-ASM: LBB0_3:
+; 64LARGE-ASM: LBB0_4:
+; 64LARGE-ASM: LBB0_5:
+; 64LARGE-ASM: LBB0_6:
+; 64LARGE-ASM:      li 3, 0
+; 64LARGE-ASM:      blr
+; 64LARGE-ASM:      .csect .rodata[RO]
+; 64LARGE-ASM:      .align  2
+; 64LARGE-ASM: .LJTI0_0:
+; 64LARGE-ASM:      .long   LBB0_2-.LJTI0_0
+; 64LARGE-ASM:      .long   LBB0_3-.LJTI0_0
+; 64LARGE-ASM:      .long   LBB0_4-.LJTI0_0
+; 64LARGE-ASM:      .long   LBB0_5-.LJTI0_0
+
+; CHECK: .toc
+; CHECK-NOT: .tc