[RISCV][MC] MC layer support for xcvmem and xcvelw extensions

[liaolucy]

Summary

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Several other extensions have been merged.
Spec:
https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst
Contributors: @CharKeaney, @jeremybennett, @lewis-revill, Nandni Jamnadas, @PaoloS, @simoncook, @xmj, @realqhc, @melonedo, @adeelahmad81299

[sunshaoce]

llvm/lib/Target/RISCV/RISCVFeatures.td

825

"'XCVelw' (CORE-V Event Load Word)"

[liaolucy]

address comments, thanks.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2578

core-v -> CORE-V to be consistent with other places?

[liaolucy]

1. core-v -> CORE-V to be consistent with other places
2. rebase

[Jim]

It is also needed to add pre-defined macro test in clang/test/Preprocessor/riscv-target-features.c

llvm/docs/RISCVUsage.rst

267

prefixed with cv. ?

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

565

Indent.

581

Indent.

632

Indent.

636

// Event load

llvm/test/MC/RISCV/corev/XCVelw-valid.s

3

Indent is not the same with others.

[liaolucy]

Address comments from Jim, thanks.

[liaolucy]

1. Rebase.
2. Update RISCVISAInfoTest.cpp

[liaolucy]

ping

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2577

Is it possible to use a custom parser instead of adding a special case to the generic parser?

[liaolucy]

1. use a custom parser to parse Register-Register load/store
2. Rebase

Thanks

[craig.topper]

LGTM

clang/test/Preprocessor/riscv-target-features.c

 // CHECK-NOT: __riscv_v_elen {{.*$}}
 // CHECK-NOT: __riscv_v_elen_fp {{.*$}}
 // CHECK-NOT: __riscv_v_intrinsic {{.*$}}
 // CHECK-NOT: __riscv_v_min_vlen {{.*$}}
 // CHECK-NOT: __riscv_vector {{.*$}}
 // CHECK-NOT: __riscv_xcvalu {{.*$}}
 // CHECK-NOT: __riscv_xcvbi {{.*$}}
 // CHECK-NOT: __riscv_xcvbitmanip {{.*$}}
+// CHECK-NOT: __riscv_xcvelw {{.*$}}
 // CHECK-NOT: __riscv_xcvmac {{.*$}}
+// CHECK-NOT: __riscv_xcvmem {{.*$}}
 // CHECK-NOT: __riscv_xcvsimd {{.*$}}
 // CHECK-NOT: __riscv_xsfcie {{.*$}}
 // CHECK-NOT: __riscv_xsfvcp {{.*$}}
 // CHECK-NOT: __riscv_xsfvfnrclipxfqf {{.*$}}
 // CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
 // CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
 // CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
 // CHECK-NOT: __riscv_xtheadba {{.*$}}

llvm/docs/RISCVUsage.rst

``XVentanaCondOps``
   LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`_ by Ventana Micro Systems.  All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above.  These instructions are only available for riscv64 at this time.
 
 ``XSfvcp``
   LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification <https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf>`_ by SiFive.  All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above.
 
 ``XCVbitmanip``
   LLVM implements `version 1.0.0 of the CORE-V Bit Manipulation custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.` as described in the specification.
 
+``XCVelw``
+  LLVM implements `version 1.0.0 of the CORE-V Event load custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
+
 ``XCVmac``
   LLVM implements `version 1.0.0 of the CORE-V Multiply-Accumulate (MAC) custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.mac` as described in the specification. These instructions are only available for riscv32 at this time.
 
+``XCVmem``
+  LLVM implements `version 1.0.0 of the CORE-V Post-Increment load and stores custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
+
 ``XCValu``
   LLVM implements `version 1.0.0 of the Core-V ALU custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
 
 ``XCVsimd``
   LLVM implements `version 1.0.0 of the CORE-V SIMD custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.` as described in the specification.
 
 ``XCVbi``
   LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
 
 ``XSfcie``
   LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.  All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time.

llvm/lib/Support/RISCVISAInfo.cpp

 //===-- RISCVISAInfo.cpp - RISC-V Arch String Parser ------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
static const RISCVSupportedExtension SupportedExtensions[] = {
     {"svpbmt", RISCVExtensionVersion{1, 0}},
 
     {"v", RISCVExtensionVersion{1, 0}},
 
     // vendor-defined ('X') extensions
     {"xcvalu", RISCVExtensionVersion{1, 0}},
     {"xcvbi", RISCVExtensionVersion{1, 0}},
     {"xcvbitmanip", RISCVExtensionVersion{1, 0}},
+    {"xcvelw", RISCVExtensionVersion{1, 0}},
     {"xcvmac", RISCVExtensionVersion{1, 0}},
+    {"xcvmem", RISCVExtensionVersion{1, 0}},
     {"xcvsimd", RISCVExtensionVersion{1, 0}},
     {"xsfcie", RISCVExtensionVersion{1, 0}},
     {"xsfvcp", RISCVExtensionVersion{1, 0}},
     {"xsfvfnrclipxfqf", RISCVExtensionVersion{1, 0}},
     {"xsfvfwmaccqqq", RISCVExtensionVersion{1, 0}},
     {"xsfvqmaccdod", RISCVExtensionVersion{1, 0}},
     {"xsfvqmaccqoq", RISCVExtensionVersion{1, 0}},
     {"xtheadba", RISCVExtensionVersion{1, 0}},

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

 //===-- RISCVAsmParser.cpp - Parse RISC-V assembly to MCInst instructions -===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
#include "RISCVGenAsmMatcher.inc"
   ParseStatus parseVTypeI(OperandVector &Operands);
   ParseStatus parseMaskReg(OperandVector &Operands);
   ParseStatus parseInsnDirectiveOpcode(OperandVector &Operands);
   ParseStatus parseInsnCDirectiveOpcode(OperandVector &Operands);
   ParseStatus parseGPRAsFPR(OperandVector &Operands);
   ParseStatus parseFRMArg(OperandVector &Operands);
   ParseStatus parseFenceArg(OperandVector &Operands);
   ParseStatus parseReglist(OperandVector &Operands);
+  ParseStatus parseRegReg(OperandVector &Operands);
   ParseStatus parseRetval(OperandVector &Operands);
   ParseStatus parseZcmpSpimm(OperandVector &Operands);
 
   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
 
   bool parseDirectiveOption();
   bool parseDirectiveAttribute();
   bool parseDirectiveInsn(SMLoc L);
enum class KindTy {
     Immediate,
     FPImmediate,
     SystemRegister,
     VType,
     FRM,
     Fence,
     Rlist,
     Spimm,
+    RegReg,
   } Kind;
 
   struct RegOp {
     MCRegister RegNum;
     bool IsGPRAsFPR;
   };
 
   struct ImmOp {
struct RISCVOperand final : public MCParsedAsmOperand {
   struct RlistOp {
     unsigned Val;
   };
 
   struct SpimmOp {
     unsigned Val;
   };
 
+  struct RegRegOp {
+    MCRegister Reg1;
+    MCRegister Reg2;
+  };
+
   SMLoc StartLoc, EndLoc;
   union {
     StringRef Tok;
     RegOp Reg;
     ImmOp Imm;
     FPImmOp FPImm;
     struct SysRegOp SysReg;
     struct VTypeOp VType;
     struct FRMOp FRM;
     struct FenceOp Fence;
     struct RlistOp Rlist;
     struct SpimmOp Spimm;
+    struct RegRegOp RegReg;
   };
 
   RISCVOperand(KindTy K) : Kind(K) {}
 
 public:
   RISCVOperand(const RISCVOperand &o) : MCParsedAsmOperand() {
     Kind = o.Kind;
     StartLoc = o.StartLoc;
case KindTy::Fence:
       Fence = o.Fence;
       break;
     case KindTy::Rlist:
       Rlist = o.Rlist;
       break;
     case KindTy::Spimm:
       Spimm = o.Spimm;
       break;
+    case KindTy::RegReg:
+      RegReg = o.RegReg;
+      break;
     }
   }
 
   bool isToken() const override { return Kind == KindTy::Token; }
   bool isReg() const override { return Kind == KindTy::Register; }
   bool isV0Reg() const {
     return Kind == KindTy::Register && Reg.RegNum == RISCV::V0;
   }
   bool isAnyReg() const {
     return Kind == KindTy::Register &&
            (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum) ||
             RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg.RegNum) ||
             RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg.RegNum));
   }
   bool isAnyRegC() const {
     return Kind == KindTy::Register &&
            (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(
                 Reg.RegNum) ||
             RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(
                 Reg.RegNum));
   }
   bool isImm() const override { return Kind == KindTy::Immediate; }
   bool isMem() const override { return false; }
   bool isSystemRegister() const { return Kind == KindTy::SystemRegister; }
+  bool isRegReg() const { return Kind == KindTy::RegReg; }
   bool isRlist() const { return Kind == KindTy::Rlist; }
   bool isSpimm() const { return Kind == KindTy::Spimm; }
 
   bool isGPR() const {
     return Kind == KindTy::Register &&
            RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum);
   }
 
case KindTy::Rlist:
       RISCVZC::printRlist(Rlist.Val, OS);
       OS << '>';
       break;
     case KindTy::Spimm:
       OS << "<Spimm: ";
       RISCVZC::printSpimm(Spimm.Val, OS);
       OS << '>';
       break;
+    case KindTy::RegReg:
+      OS << "<RegReg:  Reg1 " << RegName(RegReg.Reg1);
+      OS << " Reg2 " << RegName(RegReg.Reg2);
+      break;
     }
   }
 
   static std::unique_ptr<RISCVOperand> createToken(StringRef Str, SMLoc S) {
     auto Op = std::make_unique<RISCVOperand>(KindTy::Token);
     Op->Tok = Str;
     Op->StartLoc = S;
     Op->EndLoc = S;
public:
   static std::unique_ptr<RISCVOperand> createRlist(unsigned RlistEncode,
                                                    SMLoc S) {
     auto Op = std::make_unique<RISCVOperand>(KindTy::Rlist);
     Op->Rlist.Val = RlistEncode;
     Op->StartLoc = S;
     return Op;
   }
 
+  static std::unique_ptr<RISCVOperand> createRegReg(unsigned Reg1No,
+                                                    unsigned Reg2No, SMLoc S) {
+    auto Op = std::make_unique<RISCVOperand>(KindTy::RegReg);
+    Op->RegReg.Reg1 = Reg1No;
+    Op->RegReg.Reg2 = Reg2No;
+    Op->StartLoc = S;
+    Op->EndLoc = S;
+    return Op;
+  }
+
   static std::unique_ptr<RISCVOperand> createSpimm(unsigned Spimm, SMLoc S) {
     auto Op = std::make_unique<RISCVOperand>(KindTy::Spimm);
     Op->Spimm.Val = Spimm;
     Op->StartLoc = S;
     return Op;
   }
 
   static void addExpr(MCInst &Inst, const MCExpr *Expr, bool IsRV64Imm) {
void addVTypeIOperands(MCInst &Inst, unsigned N) const {
     Inst.addOperand(MCOperand::createImm(Imm));
   }
 
   void addRlistOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createImm(Rlist.Val));
   }
 
+  void addRegRegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(RegReg.Reg1));
+    Inst.addOperand(MCOperand::createReg(RegReg.Reg2));
+  }
+
   void addSpimmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createImm(Spimm.Val));
   }
 
   void addFRMArgOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createImm(getFRM()));
case Match_InvalidSpimm: {
     return Error(
         ErrorLoc,
         "stack adjustment is invalid for this instruction and register list; "
         "refer to Zc spec for a detailed range of stack adjustment");
   }
   case Match_InvalidRnumArg: {
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
   }
+  case Match_InvalidRegReg: {
+    SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
+    return Error(ErrorLoc, "operands must be register and register");
+  }
   }
 
   llvm_unreachable("Unknown match type detected!");
 }
 
 // Attempts to match Name as a register (either using the default name or
 // alternative ABI names), setting RegNo to the matching register. Upon
 // failure, returns a non-valid MCRegister. If IsRVE, then registers x16-x31
ParseStatus RISCVAsmParser::parseZeroOffsetMemOp(OperandVector &Operands) {
   if (OptionalImmOp && !OptionalImmOp->isImmZero())
     return Error(
         OptionalImmOp->getStartLoc(), "optional integer offset must be 0",
         SMRange(OptionalImmOp->getStartLoc(), OptionalImmOp->getEndLoc()));
 
   return ParseStatus::Success;
 }
 
+ParseStatus RISCVAsmParser::parseRegReg(OperandVector &Operands) {
+  // RR : a2(a1)
+  if (getLexer().getKind() != AsmToken::Identifier)
+    return ParseStatus::NoMatch;
+
+  StringRef RegName = getLexer().getTok().getIdentifier();
+  MCRegister Reg = matchRegisterNameHelper(isRVE(), RegName);
+  if (!Reg)
+    return Error(getLoc(), "invalid register");
+  getLexer().Lex();
+
+  if (parseToken(AsmToken::LParen, "expected '(' or invalid operand"))
+    return ParseStatus::Failure;
+
+  if (getLexer().getKind() != AsmToken::Identifier)
+    return Error(getLoc(), "expected register");
+
+  StringRef Reg2Name = getLexer().getTok().getIdentifier();
+  MCRegister Reg2 = matchRegisterNameHelper(isRVE(), Reg2Name);
+  if (!Reg2)
+    return Error(getLoc(), "invalid register");
+  getLexer().Lex();
+
+  if (parseToken(AsmToken::RParen, "expected ')'"))
+    return ParseStatus::Failure;
+
+  Operands.push_back(RISCVOperand::createRegReg(Reg, Reg2, getLoc()));
+
+  return ParseStatus::Success;
+}
+
 ParseStatus RISCVAsmParser::parseReglist(OperandVector &Operands) {
   // Rlist: {ra [, s0[-sN]]}
   // XRlist: {x1 [, x8[-x9][, x18[-xN]]]}
   SMLoc S = getLoc();
 
   if (parseToken(AsmToken::LCurly, "register list must start with '{'"))
     return ParseStatus::Failure;
 
bool RISCVAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
   ParseStatus Result =
       MatchOperandParserImpl(Operands, Mnemonic, /*ParseForAllFeatures=*/true);
   if (Result.isSuccess())
     return false;
   if (Result.isFailure())
     return true;
 
   // Attempt to parse token as a register.
   if (parseRegister(Operands, true).isSuccess())
     return false;
 
   // Attempt to parse token as an immediate
   if (parseImmediate(Operands).isSuccess()) {
     // Parse memory base register if present
     if (getLexer().is(AsmToken::LParen))
       return !parseMemOpBaseReg(Operands).isSuccess();
     return false;
   }

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

 //===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 
 static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
                                         uint64_t Address,
                                         const MCDisassembler *Decoder);
 
 static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm,
                                     uint64_t Address, const void *Decoder);
 
+static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder);
+
 static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
                                     uint64_t Address, const void *Decoder);
 
 #include "RISCVGenDisassemblerTables.inc"
 
 static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
                                                uint64_t Address,
                                                const MCDisassembler *Decoder) {

 static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm,
                                     uint64_t Address, const void *Decoder) {
   if (Imm <= 3)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
+  uint32_t Rs1 = fieldFromInstruction(Insn, 0, 5);
+  uint32_t Rs2 = fieldFromInstruction(Insn, 5, 5);
+  DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
+  DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
+  return MCDisassembler::Success;
+}
+
 // spimm is based on rlist now.
 static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
                                     uint64_t Address, const void *Decoder) {
   // TODO: check if spimm matches rlist
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
if ((Bytes[0] & 0x3) == 0x3) {
     TRY_TO_DECODE_FEATURE(
         RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
         "SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32,
                           "Sifive CIE custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
                           DecoderTableXCVbitmanip32,
                           "CORE-V Bit Manipulation custom opcode table");
+    TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
+                          "CORE-V Event load custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
                           "CORE-V MAC custom opcode table");
+    TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
+                          "CORE-V MEM custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
                           "CORE-V ALU custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
                           "CORE-V SIMD extensions custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
                           "CORE-V Immediate Branching custom opcode table");
     TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h

 //===-- RISCVInstPrinter.h - Convert RISC-V MCInst to asm syntax --*- C++ -*--//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
public:
   void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                    raw_ostream &O);
   void printVMaskReg(const MCInst *MI, unsigned OpNo,
                      const MCSubtargetInfo &STI, raw_ostream &O);
   void printRlist(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                   raw_ostream &O);
   void printSpimm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                   raw_ostream &O);
-
+  void printRegReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+                   raw_ostream &O);
   // Autogenerated by tblgen.
   std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
   void printInstruction(const MCInst *MI, uint64_t Address,
                         const MCSubtargetInfo &STI, raw_ostream &O);
   bool printAliasInstr(const MCInst *MI, uint64_t Address,
                        const MCSubtargetInfo &STI, raw_ostream &O);
   void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
                                unsigned OpIdx, unsigned PrintMethodIdx,
                                const MCSubtargetInfo &STI, raw_ostream &O);
   static const char *getRegisterName(MCRegister Reg);
   static const char *getRegisterName(MCRegister Reg, unsigned AltIdx);
 };
 } // namespace llvm
 
 #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

 //===-- RISCVInstPrinter.cpp - Convert RISC-V MCInst to asm syntax --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
markup(O, Markup::Register) << getRegisterName(
                           : Imm - RISCVZC::RLISTENCODE::RA_S0_S3));
     break;
   default:
     llvm_unreachable("invalid register list");
   }
   O << "}";
 }
 
+void RISCVInstPrinter::printRegReg(const MCInst *MI, unsigned OpNo,
+                                   const MCSubtargetInfo &STI, raw_ostream &O) {
+  const MCOperand &MO = MI->getOperand(OpNo);
+
+  assert(MO.isReg() && "printRegReg can only print register operands");
+  if (MO.getReg() == RISCV::NoRegister)
+    return;
+  printRegName(O, MO.getReg());
+
+  O << "(";
+  const MCOperand &MO1 = MI->getOperand(OpNo + 1);
+  assert(MO1.isReg() && "printRegReg can only print register operands");
+  printRegName(O, MO1.getReg());
+  O << ")";
+}
+
 void RISCVInstPrinter::printSpimm(const MCInst *MI, unsigned OpNo,
                                   const MCSubtargetInfo &STI, raw_ostream &O) {
   int64_t Imm = MI->getOperand(OpNo).getImm();
   unsigned Opcode = MI->getOpcode();
   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
   bool IsEABI = STI.hasFeature(RISCV::FeatureRVE);
   int64_t Spimm = 0;
   auto RlistVal = MI->getOperand(0).getImm();

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

 //===-- RISCVMCCodeEmitter.cpp - Convert RISC-V code to machine code ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
public:
 
   unsigned getVMaskReg(const MCInst &MI, unsigned OpNo,
                        SmallVectorImpl<MCFixup> &Fixups,
                        const MCSubtargetInfo &STI) const;
 
   unsigned getRlistOpValue(const MCInst &MI, unsigned OpNo,
                            SmallVectorImpl<MCFixup> &Fixups,
                            const MCSubtargetInfo &STI) const;
+
+  unsigned getRegReg(const MCInst &MI, unsigned OpNo,
+                     SmallVectorImpl<MCFixup> &Fixups,
+                     const MCSubtargetInfo &STI) const;
 };
 } // end anonymous namespace
 
 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
                                               MCContext &Ctx) {
   return new RISCVMCCodeEmitter(Ctx, MCII);
 }
 
unsigned RISCVMCCodeEmitter::getRlistOpValue(const MCInst &MI, unsigned OpNo,
                                              const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
   assert(MO.isImm() && "Rlist operand must be immediate");
   auto Imm = MO.getImm();
   assert(Imm >= 4 && "EABI is currently not implemented");
   return Imm;
 }
 
+unsigned RISCVMCCodeEmitter::getRegReg(const MCInst &MI, unsigned OpNo,
+                                       SmallVectorImpl<MCFixup> &Fixups,
+                                       const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+  const MCOperand &MO1 = MI.getOperand(OpNo + 1);
+  assert(MO.isReg() && MO1.isReg() && "Expected registers.");
+
+  unsigned Op = Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
+  unsigned Op1 = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg());
+
+  return Op | Op1 << 5;
+}
+
 #include "RISCVGenMCCodeEmitter.inc"

llvm/lib/Target/RISCV/RISCVFeatures.td

def FeatureVendorXSfcie
     : SubtargetFeature<"xsfcie", "HasVendorXSfcie", "true",
                        "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
 def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">,
                         AssemblerPredicate<(all_of FeatureVendorXSfcie),
                         "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
 
 def FeatureVendorXSfvqmaccdod
     : SubtargetFeature<"xsfvqmaccdod", "HasVendorXSfvqmaccdod", "true",
                        "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",
                        [FeatureStdExtZve32x]>;
 def HasVendorXSfvqmaccdod : Predicate<"Subtarget->hasVendorXSfvqmaccdod()">,
                          AssemblerPredicate<(all_of FeatureVendorXSfvqmaccdod),
                          "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))">;
 
 def FeatureVendorXSfvqmaccqoq
     : SubtargetFeature<"xsfvqmaccqoq", "HasVendorXSfvqmaccqoq", "true",
                        "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))",

 
 def FeatureVendorXSfvfnrclipxfqf
     : SubtargetFeature<"xsfvfnrclipxfqf", "HasVendorXSfvfnrclipxfqf", "true",
                        "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)",
                        [FeatureStdExtZve32f]>;
 def HasVendorXSfvfnrclipxfqf : Predicate<"Subtarget->hasVendorXSfvfnrclipxfqf()">,
                                AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf),
                                "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">;
+def FeatureVendorXCVelw
+   : SubtargetFeature<"xcvelw", "HasVendorXCVelw", "true",
+                      "'XCVelw' (CORE-V Event Load Word)">;
+def HasVendorXCVelw
+   : Predicate<"Subtarget->hasVendorXCVelw()">,
+              AssemblerPredicate<(any_of FeatureVendorXCVelw),
+              "'XCVelw' (CORE-V Event Load Word)">;
 
 def FeatureVendorXCVbitmanip
     : SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true",
                        "'XCVbitmanip' (CORE-V Bit Manipulation)">;
 def HasVendorXCVbitmanip : Predicate<"Subtarget->hasVendorXCVbitmanip()">,
                                 AssemblerPredicate<(all_of FeatureVendorXCVbitmanip),
                                 "'XCVbitmanip' (CORE-V Bit Manipulation)">;
 
 def FeatureVendorXCVmac
     : SubtargetFeature<"xcvmac", "HasVendorXCVmac", "true",
                        "'XCVmac' (CORE-V Multiply-Accumulate)">;
 def HasVendorXCVmac : Predicate<"Subtarget->hasVendorXCVmac()">,
                                 AssemblerPredicate<(all_of FeatureVendorXCVmac),
                                 "'XCVmac' (CORE-V Multiply-Accumulate)">;
 
+def FeatureVendorXCVmem
+    : SubtargetFeature<"xcvmem", "HasVendorXCVmem", "true",
+                       "'XCVmem' (CORE-V Post-incrementing Load & Store)">;
+def HasVendorXCVmem
+    : Predicate<"Subtarget->hasVendorXCVmem()">,
+               AssemblerPredicate<(any_of FeatureVendorXCVmem),
+               "'XCVmem' (CORE-V Post-incrementing Load & Store)">;
+
 def FeatureVendorXCValu
     : SubtargetFeature<"xcvalu", "HasVendorXCValu", "true",
                        "'XCValu' (CORE-V ALU Operations)">;
 def HasVendorXCValu : Predicate<"Subtarget->hasVendorXCValu()">,
                                 AssemblerPredicate<(all_of FeatureVendorXCValu),
                                 "'XCValu' (CORE-V ALU Operations)">;
 
 def FeatureVendorXCVsimd

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

let Predicates = [HasVendorXCVbi, IsRV32], hasSideEffects = 0, mayLoad = 0,
   // Immediate branching operations
   def CV_BEQIMM : CVInstImmBranch<0b110, (outs),
         (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
         "cv.beqimm", "$rs1, $imm5, $imm12">, Sched<[]>;
   def CV_BNEIMM : CVInstImmBranch<0b111, (outs),
         (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
         "cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>;
 }
+
+def CVrrAsmOperand : AsmOperandClass {
+  let Name = "RegReg";
+  let ParserMethod = "parseRegReg";
+  let DiagnosticType = "InvalidRegReg";
+}
+
+def CVrr : Operand<OtherVT> {
+   let ParserMatchClass = CVrrAsmOperand;
+   let EncoderMethod =  "getRegReg";
+   let DecoderMethod = "decodeRegReg";
+   let PrintMethod = "printRegReg";
+}
+
+class CVLoad_ri_inc<bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, simm12:$imm12),
+              opcodestr, "$rd, (${rs1}), ${imm12}"> {
+  let Constraints = "$rs1_wb = $rs1";
+  let DecoderNamespace = "XCVmem";
+}
+
+class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, GPR:$rs2),
+              opcodestr, "$rd, (${rs1}), ${rs2}"> {
+  let Constraints = "$rs1_wb = $rs1";
+  let DecoderNamespace = "XCVmem";
+}
+
+class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd), (ins CVrr:$cvrr),
+              opcodestr, "$rd, $cvrr"> {
+  bits<5> rd;
+  bits<10> cvrr;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = cvrr{4-0};
+  let Inst{19-15} = cvrr{9-5};
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let DecoderNamespace = "XCVmem";
+}
+
+let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
+                 mayLoad = 1, mayStore = 0, Constraints = "$rs1_wb = $rs1" in {
+  // Register-Immediate load with post-increment
+  def CV_LB_ri_inc  : CVLoad_ri_inc<0b000, "cv.lb">;
+  def CV_LBU_ri_inc : CVLoad_ri_inc<0b100, "cv.lbu">;
+  def CV_LH_ri_inc  : CVLoad_ri_inc<0b001, "cv.lh">;
+  def CV_LHU_ri_inc : CVLoad_ri_inc<0b101, "cv.lhu">;
+  def CV_LW_ri_inc  : CVLoad_ri_inc<0b010, "cv.lw">;
+
+  // Register-Register load with post-increment
+  def CV_LB_rr_inc  : CVLoad_rr_inc<0b0000000, 0b011, "cv.lb">;
+  def CV_LBU_rr_inc : CVLoad_rr_inc<0b0001000, 0b011, "cv.lbu">;
+  def CV_LH_rr_inc  : CVLoad_rr_inc<0b0000001, 0b011, "cv.lh">;
+  def CV_LHU_rr_inc : CVLoad_rr_inc<0b0001001, 0b011, "cv.lhu">;
+  def CV_LW_rr_inc  : CVLoad_rr_inc<0b0000010, 0b011, "cv.lw">;
+}
+
+let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0, 
+                 mayLoad = 1, mayStore = 0 in {
+  // Register-Register load
+  def CV_LB_rr  : CVLoad_rr<0b0000100, 0b011, "cv.lb">;
+  def CV_LBU_rr : CVLoad_rr<0b0001100, 0b011, "cv.lbu">;
+  def CV_LH_rr  : CVLoad_rr<0b0000101, 0b011, "cv.lh">;
+  def CV_LHU_rr : CVLoad_rr<0b0001101, 0b011, "cv.lhu">;
+  def CV_LW_rr  : CVLoad_rr<0b0000110, 0b011, "cv.lw">;
+}
+
+class CVStore_ri_inc<bits<3> funct3, string opcodestr>
+    : RVInstS<funct3, OPC_CUSTOM_1, (outs GPR:$rs1_wb), 
+              (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
+              opcodestr, "$rs2, (${rs1}), ${imm12}"> {
+  let Constraints = "$rs1_wb = $rs1";
+  let DecoderNamespace = "XCVmem";
+}
+
+class CVStore_rr_inc<bits<3> funct3, bits<7> funct7, dag outs, dag ins,
+                     string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+  bits<5> rs3;
+  bits<5> rs2;
+  bits<5> rs1;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rs3;
+  let Inst{6-0} = OPC_CUSTOM_1.Value;
+  let DecoderNamespace = "XCVmem";
+}
+
+
+class CVStore_rr<bits<3> funct3, bits<7> funct7, dag outs, dag ins,
+                     string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+  bits<5> rs2;
+  bits<10> cvrr;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = cvrr{9-5};
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = cvrr{4-0};
+  let Inst{6-0} = OPC_CUSTOM_1.Value;
+  let DecoderNamespace = "XCVmem";
+}
+
+let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0, 
+                 mayLoad = 0, mayStore = 1, Constraints = "$rs1_wb = $rs1" in {
+  // Register-Immediate store with post-increment
+  def CV_SB_ri_inc : CVStore_ri_inc<0b000, "cv.sb">;
+  def CV_SH_ri_inc : CVStore_ri_inc<0b001, "cv.sh">;
+  def CV_SW_ri_inc : CVStore_ri_inc<0b010, "cv.sw">;
+
+  // Register-Register store with post-increment
+  def CV_SB_rr_inc : CVStore_rr_inc<0b011, 0b0010000, 
+                     (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+                      "cv.sb", "$rs2, (${rs1}), ${rs3}">;
+  def CV_SH_rr_inc : CVStore_rr_inc<0b011, 0b0010001, 
+                     (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+                      "cv.sh", "$rs2, (${rs1}), ${rs3}">;
+  def CV_SW_rr_inc : CVStore_rr_inc<0b011, 0b0010010, 
+                     (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+                      "cv.sw", "$rs2, (${rs1}), ${rs3}">;
+}
+
+
+let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0, 
+                  mayLoad = 0, mayStore = 1 in {
+  // Register-Register store
+  def CV_SB_rr : CVStore_rr<0b011, 0b0010100,
+                 (outs), (ins GPR:$rs2, CVrr:$cvrr),
+                 "cv.sb", "$rs2, $cvrr">;
+  def CV_SH_rr : CVStore_rr<0b011, 0b0010101,
+                 (outs), (ins GPR:$rs2, CVrr:$cvrr),
+                 "cv.sh", "$rs2, $cvrr">;
+  def CV_SW_rr : CVStore_rr<0b011, 0b0010110,
+                 (outs), (ins GPR:$rs2, CVrr:$cvrr),
+                 "cv.sw", "$rs2, $cvrr">;
+} 
+
+let DecoderNamespace = "XCVelw" in
+class CVLoad_ri<bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd), 
+      (ins GPRMem:$rs1, simm12:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
+
+let Predicates = [HasVendorXCVelw, IsRV32], hasSideEffects = 0, 
+    mayLoad = 1, mayStore = 0 in {
+  // Event load
+  def CV_ELW : CVLoad_ri<0b011, "cv.elw">;
+}

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck --check-prefix=RV32XCVALU %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvbitmanip %s -o - | FileCheck --check-prefix=RV32XCVBITMANIP %s
+; RUN: llc -mtriple=riscv32 -mattr=+xcvelw %s -o - | FileCheck --check-prefix=RV32XCVELW %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvmac %s -o - | FileCheck --check-prefix=RV32XCVMAC %s
+; RUN: llc -mtriple=riscv32 -mattr=+xcvmem %s -o - | FileCheck --check-prefix=RV32XCVMEM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvsimd %s -o - | FileCheck --check-prefix=RV32XCVSIMD %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvbi %s -o - | FileCheck --check-prefix=RV32XCVBI %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadcmo %s -o - | FileCheck --check-prefix=RV32XTHEADCMO %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadcondmov %s -o - | FileCheck --check-prefix=RV32XTHEADCONDMOV %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadfmemidx %s -o - | FileCheck --check-prefix=RV32XTHEADFMEMIDX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac %s -o - | FileCheck --check-prefixes=CHECK,RV32XTHEADMAC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmemidx %s -o - | FileCheck --check-prefix=RV32XTHEADMEMIDX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV32XTHEADMEMPAIR %s

 ; RV32ZICBOM: .attribute 5, "rv32i2p1_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p1_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p1_zicbop1p0"
 ; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0"
 ; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0"
 ; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0"
 ; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0"
 ; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0"
+; RV32XCVELW: .attribute 5, "rv32i2p1_xcvelw1p0"
 ; RV32XCVMAC: .attribute 5, "rv32i2p1_xcvmac1p0"
+; RV32XCVMEM: .attribute 5, "rv32i2p1_xcvmem1p0"
 ; RV32XCVSIMD: .attribute 5, "rv32i2p1_xcvsimd1p0"
 ; RV32XCVBI: .attribute 5, "rv32i2p1_xcvbi1p0"
 ; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0"
 ; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0"
 ; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0"
 ; RV32XTHEADMAC: .attribute 5, "rv32i2p1_xtheadmac1p0"
 ; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p1_xtheadmemidx1p0"
 ; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"

llvm/test/MC/RISCV/attribute-arch.s

 # CHECK: attribute      5, "rv32i2p1_a2p1_zacas1p0"
 
 .attribute arch, "rv32i_xcvalu"
 # CHECK: attribute      5, "rv32i2p1_xcvalu1p0"
 
 .attribute arch, "rv32i_xcvbitmanip"
 # CHECK: attribute      5, "rv32i2p1_xcvbitmanip1p0"
 
+.attribute arch, "rv32i_xcvelw"
+# CHECK: attribute      5, "rv32i2p1_xcvelw1p0"
+
 .attribute arch, "rv32i_xcvmac"
 # CHECK: attribute      5, "rv32i2p1_xcvmac1p0"
 
+.attribute arch, "rv32i_xcvmem"
+# CHECK: attribute      5, "rv32i2p1_xcvmem1p0"
+
 .attribute arch, "rv32i_xcvsimd"
 # CHECK: attribute      5, "rv32i2p1_xcvsimd1p0"
 
 .attribute arch, "rv32i_xcvbi"
 # CHECK: attribute      5, "rv32i2p1_xcvbi1p0"
 
 .attribute arch, "rv32i_zicfilp0p2"
 # CHECK: attribute      5, "rv32i2p1_zicfilp0p2"

llvm/test/MC/RISCV/corev/XCVelw-invalid.s

+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvelw %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+cv.elw t0, 0(0)
+# CHECK-ERROR: expected register
+
+cv.elw 0, 0(x6)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.elw x12, 2048(x6)
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.elw x12, x1(2047)
+# CHECK-ERROR: unexpected token
+
+cv.elw 0, x12(x6)
+# CHECK-ERROR: unexpected token
+
+cv.elw x12, x12(x6)
+# CHECK-ERROR: unexpected token
+
+cv.elw 0, 0(x6)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.elw x0
+# CHECK-ERROR: too few operands for instruction

llvm/test/MC/RISCV/corev/XCVelw-valid.s

+# RUN: llvm-mc -triple=riscv32 --mattr=+xcvelw -show-encoding %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvelw < %s \
+# RUN:     | llvm-objdump --mattr=+xcvelw -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-INSTR %s
+# RUN: not llvm-mc -triple riscv32 %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-NO-EXT %s
+
+cv.elw a0, 1024(a0)
+# CHECK-INSTR: cv.elw a0, 1024(a0)
+# CHECK-ENCODING: [0x0b,0x35,0x05,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVelw' (CORE-V Event Load Word){{$}} 
+
+cv.elw a1, 1(a1)
+# CHECK-INSTR: cv.elw a1, 1(a1)
+# CHECK-ENCODING: [0x8b,0xb5,0x15,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVelw' (CORE-V Event Load Word){{$}}
+
+cv.elw a2, -1024(a3)
+# CHECK-INSTR: cv.elw  a2, -1024(a3)
+# CHECK-ENCODING: [0x0b,0xb6,0x06,0xc0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVelw' (CORE-V Event Load Word){{$}}

llvm/test/MC/RISCV/corev/XCVmem-invalid.s

+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvmem %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+cv.lb t0, (0), 0
+# CHECK-ERROR: operands must be register and register
+
+cv.lb 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lb 0, (0), t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lb t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lb t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lb t0, (0), t1
+# CHECK-ERROR: operands must be register and register
+
+cv.lb 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lb t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lb t0, (t2)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lb t0, (t1), t2, t3
+# CHECK-ERROR: invalid operand for instruction 
+
+cv.lbu t0, (0), 0
+# CHECK-ERROR: operands must be register and register
+
+cv.lbu 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lbu 0, (0), t0 
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lbu t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lbu t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lbu t0, (0), t1
+# CHECK-ERROR: operands must be register and register
+
+cv.lbu 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lbu t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lbu t0, (t2)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lbu t0, (t1), t2, t3 
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh t0, (0), 0
+# CHECK-ERROR: operands must be register and register
+
+cv.lh 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh 0, (0), t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lh t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lh t0, (0), t1
+# CHECK-ERROR: operands must be register and register
+
+cv.lh t0, t1(0)
+# CHECK-ERROR: expected register
+
+cv.lh 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lh t0, (t1)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lh t0, (t1), t2, t3
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu t0, (0), 0
+# CHECK-ERROR: operands must be register and register
+
+cv.lhu 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu 0, 0(t1)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lhu t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lhu t0, (0), t1
+# CHECK-ERROR: operands must be register and register 
+
+cv.lhu t0, t1(0)
+# CHECK-ERROR: expected register
+
+cv.lhu 0, t0, t1
+# CHECK-ERROR: expected '(' or invalid operand
+
+cv.lhu t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lhu t0, (t1)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lhu t0, (t1), t2, t3
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw t0, (0), 0
+# CHECK-ERROR: operands must be register and register
+
+cv.lw 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw 0, (0), t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lw t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lw t0, (0), t1
+# CHECK-ERROR: operands must be register and register
+
+cv.lw t0, t1(0)
+# CHECK-ERROR: expected register
+
+cv.lw 0, (t0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lw t0, (t1)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lw t0, (t1), t2, t3
+# CHECK-ERROR: invalid operand for instruction 
+
+cv.sb t0, (0), 0
+# CHECK-ERROR: operands must be register and register
+
+cv.sb 0, (t0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sb t0, 0(t1)
+# CHECK-ERROR: operands must be register and register
+
+cv.sb t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.sb t0, (0), t1
+# CHECK-ERROR: operands must be register and register
+
+cv.sb 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sb t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.sh t0, (0), 0
+# CHECK-ERROR: operands must be register and register
+
+cv.sh 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sh t0, 0(t1)
+# CHECK-ERROR: operands must be register and register
+
+cv.sh t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.sh t0, (0), t1
+# CHECK-ERROR: operands must be register and register
+
+cv.sh 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sh t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.sw t0, (0), 0
+# CHECK-ERROR: operands must be register and register
+
+cv.sw 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sw t0, 0(t1)
+# CHECK-ERROR: operands must be register and register
+
+cv.sw t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.sw t0, (0), t1
+# CHECK-ERROR: operands must be register and register
+
+cv.sw 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sw t0
+# CHECK-ERROR: too few operands for instruction

llvm/test/MC/RISCV/corev/XCVmem-valid.s

+# RUN: llvm-mc -triple=riscv32 --mattr=+xcvmem -show-encoding %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvmem < %s \
+# RUN:     | llvm-objdump --mattr=+xcvmem -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-INSTR %s
+# RUN: not llvm-mc -triple riscv32 %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-NO-EXT %s
+
+cv.lb t0, (t1), 0
+# CHECK-INSTR: cv.lb t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x02,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lb a0, (a1), 2047
+# CHECK-INSTR: cv.lb a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0x85,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lb t0, (t1), t2
+# CHECK-INSTR: cv.lb t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lb a0, (a1), a2
+# CHECK-INSTR: cv.lb a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lb t0, t2(t1)
+# CHECK-INSTR: cv.lb t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x08]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lb a0, a2(a1)
+# CHECK-INSTR: cv.lb a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x08]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lbu t0, (t1), 0
+# CHECK-INSTR: cv.lbu t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x42,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lbu a0, (a1), 2047
+# CHECK-INSTR: cv.lbu a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0xc5,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lbu t0, (t1), t2
+# CHECK-INSTR: cv.lbu t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x10]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lbu a0, (a1), a2
+# CHECK-INSTR: cv.lbu a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x10]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lbu t0, t2(t1)
+# CHECK-INSTR: cv.lbu t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x18]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lbu a0, a2(a1)
+# CHECK-INSTR: cv.lbu a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x18]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lh t0, (t1), 0
+# CHECK-INSTR: cv.lh t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x12,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lh a0, (a1), 2047
+# CHECK-INSTR: cv.lh a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0x95,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lh t0, (t1), t2
+# CHECK-INSTR: cv.lh t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x02]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lh a0, (a1), a2
+# CHECK-INSTR: cv.lh a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x02]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lh t0, t2(t1)
+# CHECK-INSTR: cv.lh t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x0a]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lh a0, a2(a1)
+# CHECK-INSTR: cv.lh a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x0a]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lhu t0, (t1), 0
+# CHECK-INSTR: cv.lhu t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x52,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lhu a0, (a1), 2047
+# CHECK-INSTR: cv.lhu a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0xd5,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lhu t0, (t1), t2
+# CHECK-INSTR: cv.lhu t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x12]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lhu a0, (a1), a2
+# CHECK-INSTR: cv.lhu a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x12]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lhu t0, t2(t1)
+# CHECK-INSTR: cv.lhu t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x1a]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lhu a0, a2(a1)
+# CHECK-INSTR: cv.lhu a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x1a]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lw t0, (t1), 0
+# CHECK-INSTR: cv.lw t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x22,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lw a0, (a1), 2047
+# CHECK-INSTR: cv.lw a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0xa5,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lw t0, (t1), t2
+# CHECK-INSTR: cv.lw t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x04]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lw a0, (a1), a2
+# CHECK-INSTR: cv.lw a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x04]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lw t0, t2(t1)
+# CHECK-INSTR: cv.lw t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x0c]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lw a0, a2(a1)
+# CHECK-INSTR: cv.lw a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x0c]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sb t0, (t1), 0
+# CHECK-INSTR: cv.sb t0, (t1), 0
+# CHECK-ENCODING: [0x2b,0x00,0x53,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sb a0, (a1), 2047
+# CHECK-INSTR: cv.sb a0, (a1), 2047
+# CHECK-ENCODING: [0xab,0x8f,0xa5,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sb t0, (t1), t2
+# CHECK-INSTR: cv.sb t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x33,0x53,0x20]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sb a0, (a1), a2
+# CHECK-INSTR: cv.sb a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x20]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sb t0, t2(t1)
+# CHECK-INSTR: cv.sb t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x33,0x53,0x28]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sb a0, a2(a1)
+# CHECK-INSTR: cv.sb a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x28]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sh t0, (t1), 0
+# CHECK-INSTR: cv.sh t0, (t1), 0
+# CHECK-ENCODING: [0x2b,0x10,0x53,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sh a0, (a1), 2047
+# CHECK-INSTR: cv.sh a0, (a1), 2047
+# CHECK-ENCODING: [0xab,0x9f,0xa5,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sh t0, (t1), t2
+# CHECK-INSTR: cv.sh t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x33,0x53,0x22]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sh a0, (a1), a2
+# CHECK-INSTR: cv.sh a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x22]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sh t0, t2(t1)
+# CHECK-INSTR: cv.sh t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x33,0x53,0x2a]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sh a0, a2(a1)
+# CHECK-INSTR: cv.sh a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x2a]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sw t0, (t1), 0
+# CHECK-INSTR: cv.sw t0, (t1), 0
+# CHECK-ENCODING: [0x2b,0x20,0x53,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sw a0, (a1), 2047
+# CHECK-INSTR: cv.sw a0, (a1), 2047
+# CHECK-ENCODING: [0xab,0xaf,0xa5,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sw t0, (t1), t2
+# CHECK-INSTR: cv.sw t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x33,0x53,0x24]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sw a0, (a1), a2
+# CHECK-INSTR: cv.sw a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x24]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sw t0, t2(t1)
+# CHECK-INSTR: cv.sw t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x33,0x53,0x2c]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sw a0, a2(a1)
+# CHECK-INSTR: cv.sw a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x2c]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}

llvm/unittests/Support/RISCVISAInfoTest.cpp

 //===-- unittests/RISCVISAInfoTest.cpp ------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
R"(All available -march extensions for RISC-V
     smaia               1.0
     ssaia               1.0
     svinval             1.0
     svnapot             1.0
     svpbmt              1.0
     xcvalu              1.0
     xcvbi               1.0
     xcvbitmanip         1.0
+    xcvelw              1.0
     xcvmac              1.0
+    xcvmem              1.0
     xcvsimd             1.0
     xsfcie              1.0
     xsfvcp              1.0
     xsfvfnrclipxfqf     1.0
     xsfvfwmaccqqq       1.0
     xsfvqmaccdod        1.0
     xsfvqmaccqoq        1.0
     xtheadba            1.0