[RISCV][MC] MC layer support for xcvmem and xcvelw extensions

[liaolucy]

Summary

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Several other extensions have been merged.
Spec:
https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst
Contributors: @CharKeaney, @jeremybennett, @lewis-revill, Nandni Jamnadas, @PaoloS, @simoncook, @xmj, @realqhc, @melonedo, @adeelahmad81299

[sunshaoce]

llvm/lib/Target/RISCV/RISCVFeatures.td

818

"'XCVelw' (CORE-V Event Load Word)"

[liaolucy]

address comments, thanks.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2512

core-v -> CORE-V to be consistent with other places?

[liaolucy]

1. core-v -> CORE-V to be consistent with other places
2. rebase

[Jim]

It is also needed to add pre-defined macro test in clang/test/Preprocessor/riscv-target-features.c

llvm/docs/RISCVUsage.rst

273

prefixed with cv. ?

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

565

Indent.

581

Indent.

632

Indent.

636

// Event load

llvm/test/MC/RISCV/corev/XCVelw-valid.s

3

Indent is not the same with others.

[liaolucy]

Address comments from Jim, thanks.

[liaolucy]

1. Rebase.
2. Update RISCVISAInfoTest.cpp

[liaolucy]

ping

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2511–2516

Is it possible to use a custom parser instead of adding a special case to the generic parser?

[liaolucy]

1. use a custom parser to parse Register-Register load/store
2. Rebase

Thanks

[craig.topper]

LGTM

llvm/docs/RISCVUsage.rst

``XVentanaCondOps``
   LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`_ by Ventana Micro Systems.  All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above.  These instructions are only available for riscv64 at this time.
 
 ``XSfvcp``
   LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification <https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf>`_ by SiFive.  All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above.
 
 ``XCVbitmanip``
   LLVM implements `version 1.0.0 of the CORE-V Bit Manipulation custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.` as described in the specification.
 
+``XCVelw``
+  LLVM implements `version 1.0.0 of the CORE-V Event load custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.mac` as described in the specification. These instructions are only available for riscv32 at this time.
+
 ``XCVmac``
   LLVM implements `version 1.0.0 of the CORE-V Multiply-Accumulate (MAC) custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.mac` as described in the specification. These instructions are only available for riscv32 at this time.
 
+``XCVmem``
+  LLVM implements `version 1.0.0 of the CORE-V Post-Increment load and stores custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
+
 ``XCValu``
   LLVM implements `version 1.0.0 of the Core-V ALU custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
 
 ``XCVsimd``
   LLVM implements `version 1.0.0 of the CORE-V SIMD custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.` as described in the specification.
 
 ``XCVbi``
   LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
 
 ``XSfcie``
   LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.  All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time.

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExtensions[] = {
     {"svpbmt", RISCVExtensionVersion{1, 0}},
 
     {"v", RISCVExtensionVersion{1, 0}},
 
     // vendor-defined ('X') extensions
     {"xcvalu", RISCVExtensionVersion{1, 0}},
     {"xcvbi", RISCVExtensionVersion{1, 0}},
     {"xcvbitmanip", RISCVExtensionVersion{1, 0}},
+    {"xcvelw", RISCVExtensionVersion{1, 0}},
     {"xcvmac", RISCVExtensionVersion{1, 0}},
+    {"xcvmem", RISCVExtensionVersion{1, 0}},
     {"xcvsimd", RISCVExtensionVersion{1, 0}},
     {"xsfcie", RISCVExtensionVersion{1, 0}},
     {"xsfvcp", RISCVExtensionVersion{1, 0}},
     {"xtheadba", RISCVExtensionVersion{1, 0}},
     {"xtheadbb", RISCVExtensionVersion{1, 0}},
     {"xtheadbs", RISCVExtensionVersion{1, 0}},
     {"xtheadcmo", RISCVExtensionVersion{1, 0}},
     {"xtheadcondmov", RISCVExtensionVersion{1, 0}},

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

bool RISCVAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
   ParseStatus Result =
       MatchOperandParserImpl(Operands, Mnemonic, /*ParseForAllFeatures=*/true);
   if (Result.isSuccess())
     return false;
   if (Result.isFailure())
     return true;
 
   // Attempt to parse token as a register.
-  if (parseRegister(Operands, true).isSuccess())
+  if (parseRegister(Operands, true).isSuccess()) {
+    // Parse memory base register if present (core-v only)
+    if (getSTI().getFeatureBits()[RISCV::FeatureVendorXCVmem]) {
+      if (getLexer().is(AsmToken::LParen))
+        return !parseMemOpBaseReg(Operands).isSuccess();
+    }
     return false;
+  }
 
   // Attempt to parse token as an immediate
   if (parseImmediate(Operands).isSuccess()) {
     // Parse memory base register if present
     if (getLexer().is(AsmToken::LParen))
       return !parseMemOpBaseReg(Operands).isSuccess();
     return false;
   }

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableXTHeadVdot32,
                           "XTHeadVdot custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
                           "SiFive VCIX custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32,
                           "Sifive CIE custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
                           DecoderTableXCVbitmanip32,
                           "CORE-V Bit Manipulation custom opcode table");
+    TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
+                          "CORE-V Event load custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
                           "CORE-V MAC custom opcode table");
+    TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
+                          "CORE-V MEM custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
                           "CORE-V ALU custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
                           "CORE-V SIMD extensions custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
                           "CORE-V Immediate Branching custom opcode table");
     TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
 

llvm/lib/Target/RISCV/RISCVFeatures.td

 
 def FeatureVendorXSfcie
     : SubtargetFeature<"xsfcie", "HasVendorXSfcie", "true",
                        "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
 def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">,
                         AssemblerPredicate<(all_of FeatureVendorXSfcie),
                         "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
 
+def FeatureVendorXCVelw
+   : SubtargetFeature<"xcvelw", "HasVendorXCVelw", "true",
+                      "'XCVelw' (CORE-V Event Load Word)">;
+def HasVendorXCVelw
+   : Predicate<"Subtarget->hasVendorXCVelw()">,
+              AssemblerPredicate<(any_of FeatureVendorXCVelw),
+              "'XCVelw' (CORE-V Event Load Word)">;
+
 def FeatureVendorXCVbitmanip
     : SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true",
                        "'XCVbitmanip' (CORE-V Bit Manipulation)">;
 def HasVendorXCVbitmanip : Predicate<"Subtarget->hasVendorXCVbitmanip()">,
                                 AssemblerPredicate<(all_of FeatureVendorXCVbitmanip),
                                 "'XCVbitmanip' (CORE-V Bit Manipulation)">;
 
 def FeatureVendorXCVmac
     : SubtargetFeature<"xcvmac", "HasVendorXCVmac", "true",
                        "'XCVmac' (CORE-V Multiply-Accumulate)">;
 def HasVendorXCVmac : Predicate<"Subtarget->hasVendorXCVmac()">,
                                 AssemblerPredicate<(all_of FeatureVendorXCVmac),
                                 "'XCVmac' (CORE-V Multiply-Accumulate)">;
 
+def FeatureVendorXCVmem
+    : SubtargetFeature<"xcvmem", "HasVendorXCVmem", "true",
+                       "'XCVmem' (CORE-V Post-incrementing Load & Store)">;
+def HasVendorXCVmem
+    : Predicate<"Subtarget->hasVendorXCVmem()">,
+               AssemblerPredicate<(any_of FeatureVendorXCVmem),
+               "'XCVmem' (CORE-V Post-incrementing Load & Store)">;
+
 def FeatureVendorXCValu
     : SubtargetFeature<"xcvalu", "HasVendorXCValu", "true",
                        "'XCValu' (CORE-V ALU Operations)">;
 def HasVendorXCValu : Predicate<"Subtarget->hasVendorXCValu()">,
                                 AssemblerPredicate<(all_of FeatureVendorXCValu),
                                 "'XCValu' (CORE-V ALU Operations)">;
 
 def FeatureVendorXCVsimd

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

let Predicates = [HasVendorXCVbi, IsRV32], hasSideEffects = 0, mayLoad = 0,
   // Immediate branching operations
   def CV_BEQIMM : CVInstImmBranch<0b110, (outs),
         (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
         "cv.beqimm", "$rs1, $imm5, $imm12">, Sched<[]>;
   def CV_BNEIMM : CVInstImmBranch<0b111, (outs),
         (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
         "cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>;
 }
+
+class CVLoad_ri_inc<bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, simm12:$imm12),
+              opcodestr, "$rd, (${rs1}), ${imm12}"> {
+  let Constraints = "$rs1_wb = $rs1";
+  let DecoderNamespace = "XCVmem";
+}
+
+class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, GPR:$rs2),
+              opcodestr, "$rd, (${rs1}), ${rs2}"> {
+  let Constraints = "$rs1_wb = $rs1";
+  let DecoderNamespace = "XCVmem";
+}
+
+class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+              opcodestr, "$rd, ${rs2}(${rs1})"> {
+   let DecoderNamespace = "XCVmem";
+}
+
+let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
+                 mayLoad = 1, mayStore = 0, Constraints = "$rs1_wb = $rs1" in {
+  // Register-Immediate load with post-increment
+  def CV_LB_ri_inc  : CVLoad_ri_inc<0b000, "cv.lb">;
+  def CV_LBU_ri_inc : CVLoad_ri_inc<0b100, "cv.lbu">;
+  def CV_LH_ri_inc  : CVLoad_ri_inc<0b001, "cv.lh">;
+  def CV_LHU_ri_inc : CVLoad_ri_inc<0b101, "cv.lhu">;
+  def CV_LW_ri_inc  : CVLoad_ri_inc<0b010, "cv.lw">;
+
+  // Register-Register load with post-increment
+  def CV_LB_rr_inc  : CVLoad_rr_inc<0b0000000, 0b011, "cv.lb">;
+  def CV_LBU_rr_inc : CVLoad_rr_inc<0b0001000, 0b011, "cv.lbu">;
+  def CV_LH_rr_inc  : CVLoad_rr_inc<0b0000001, 0b011, "cv.lh">;
+  def CV_LHU_rr_inc : CVLoad_rr_inc<0b0001001, 0b011, "cv.lhu">;
+  def CV_LW_rr_inc  : CVLoad_rr_inc<0b0000010, 0b011, "cv.lw">;
+}
+
+let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0, 
+                 mayLoad = 1, mayStore = 0 in {
+  // Register-Register load
+  def CV_LB_rr  : CVLoad_rr<0b0000100, 0b011, "cv.lb">;
+  def CV_LBU_rr : CVLoad_rr<0b0001100, 0b011, "cv.lbu">;
+  def CV_LH_rr  : CVLoad_rr<0b0000101, 0b011, "cv.lh">;
+  def CV_LHU_rr : CVLoad_rr<0b0001101, 0b011, "cv.lhu">;
+  def CV_LW_rr  : CVLoad_rr<0b0000110, 0b011, "cv.lw">;
+}
+
+class CVStore_ri_inc<bits<3> funct3, string opcodestr>
+    : RVInstS<funct3, OPC_CUSTOM_1, (outs GPR:$rs1_wb), 
+              (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
+              opcodestr, "$rs2, (${rs1}), ${imm12}"> {
+  let Constraints = "$rs1_wb = $rs1";
+  let DecoderNamespace = "XCVmem";
+}
+
+class CVStore_rr_inc<bits<3> funct3, bits<7> funct7, dag outs, dag ins,
+                        string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+  bits<5> rs3;
+  bits<5> rs2;
+  bits<5> rs1;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rs3;
+  let Inst{6-0} = OPC_CUSTOM_1.Value;
+  let DecoderNamespace = "XCVmem";
+}
+
+class CVStore_rr<bits<3> funct3, bits<7> funct7, dag outs, dag ins,
+                    string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+  bits<5> rs3;
+  bits<5> rs2;
+  bits<5> rs1;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rs3;
+  let Inst{6-0} = OPC_CUSTOM_1.Value;
+  let DecoderNamespace = "XCVmem";
+}
+
+let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0, 
+                 mayLoad = 0, mayStore = 1, Constraints = "$rs1_wb = $rs1" in {
+  // Register-Immediate store with post-increment
+  def CV_SB_ri_inc : CVStore_ri_inc<0b000, "cv.sb">;
+  def CV_SH_ri_inc : CVStore_ri_inc<0b001, "cv.sh">;
+  def CV_SW_ri_inc : CVStore_ri_inc<0b010, "cv.sw">;
+
+  // Register-Register store with post-increment
+  def CV_SB_rr_inc : CVStore_rr_inc<0b011, 0b0010000, 
+                     (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+                      "cv.sb", "$rs2, (${rs1}), ${rs3}">;
+  def CV_SH_rr_inc : CVStore_rr_inc<0b011, 0b0010001, 
+                     (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+                      "cv.sh", "$rs2, (${rs1}), ${rs3}">;
+  def CV_SW_rr_inc : CVStore_rr_inc<0b011, 0b0010010, 
+                     (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+                      "cv.sw", "$rs2, (${rs1}), ${rs3}">;
+} 
+
+let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0, 
+                  mayLoad = 0, mayStore = 1 in {
+  // Register-Register store
+  def CV_SB_rr : CVStore_rr<0b011, 0b0010100, 
+                 (outs), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+                 "cv.sb", "$rs2, ${rs3}(${rs1})">;
+  def CV_SH_rr : CVStore_rr<0b011, 0b0010101, 
+                 (outs), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+                 "cv.sh", "$rs2, ${rs3}(${rs1})">;
+  def CV_SW_rr : CVStore_rr<0b011, 0b0010110, 
+                 (outs), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+                 "cv.sw", "$rs2, ${rs3}(${rs1})">;
+} 
+
+let DecoderNamespace = "XCVelw" in
+class CVLoad_ri<bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd), 
+        (ins GPRMem:$rs1, simm12:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
+
+let Predicates = [HasVendorXCVelw, IsRV32], hasSideEffects = 0, 
+    mayLoad = 1, mayStore = 0 in {
+  //Event load
+  def CV_ELW : CVLoad_ri<0b011, "cv.elw">;
+}

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck --check-prefix=RV32XCVALU %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvbitmanip %s -o - | FileCheck --check-prefix=RV32XCVBITMANIP %s
+; RUN: llc -mtriple=riscv32 -mattr=+xcvelw %s -o - | FileCheck --check-prefix=RV32XCVELW %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvmac %s -o - | FileCheck --check-prefix=RV32XCVMAC %s
+; RUN: llc -mtriple=riscv32 -mattr=+xcvmem %s -o - | FileCheck --check-prefix=RV32XCVMEM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvsimd %s -o - | FileCheck --check-prefix=RV32XCVSIMD %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvbi %s -o - | FileCheck --check-prefix=RV32XCVBI %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadcmo %s -o - | FileCheck --check-prefix=RV32XTHEADCMO %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadcondmov %s -o - | FileCheck --check-prefix=RV32XTHEADCONDMOV %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadfmemidx %s -o - | FileCheck --check-prefix=RV32XTHEADFMEMIDX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac %s -o - | FileCheck --check-prefixes=CHECK,RV32XTHEADMAC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmemidx %s -o - | FileCheck --check-prefix=RV32XTHEADMEMIDX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV32XTHEADMEMPAIR %s

 ; RV32ZICBOM: .attribute 5, "rv32i2p1_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p1_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p1_zicbop1p0"
 ; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0"
 ; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0"
 ; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0"
 ; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0"
 ; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0"
+; RV32XCVELW: .attribute 5, "rv32i2p1_xcvelw1p0"
 ; RV32XCVMAC: .attribute 5, "rv32i2p1_xcvmac1p0"
+; RV32XCVMEM: .attribute 5, "rv32i2p1_xcvmem1p0"
 ; RV32XCVSIMD: .attribute 5, "rv32i2p1_xcvsimd1p0"
 ; RV32XCVBI: .attribute 5, "rv32i2p1_xcvbi1p0"
 ; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0"
 ; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0"
 ; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0"
 ; RV32XTHEADMAC: .attribute 5, "rv32i2p1_xtheadmac1p0"
 ; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p1_xtheadmemidx1p0"
 ; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"

llvm/test/MC/RISCV/attribute-arch.s

 # CHECK: attribute      5, "rv32i2p1_a2p1_zacas1p0"
 
 .attribute arch, "rv32i_xcvalu"
 # CHECK: attribute      5, "rv32i2p1_xcvalu1p0"
 
 .attribute arch, "rv32i_xcvbitmanip"
 # CHECK: attribute      5, "rv32i2p1_xcvbitmanip1p0"
 
+.attribute arch, "rv32i_xcvelw"
+# CHECK: attribute      5, "rv32i2p1_xcvelw1p0"
+
 .attribute arch, "rv32i_xcvmac"
 # CHECK: attribute      5, "rv32i2p1_xcvmac1p0"
 
+.attribute arch, "rv32i_xcvmem"
+# CHECK: attribute      5, "rv32i2p1_xcvmem1p0"
+
 .attribute arch, "rv32i_xcvsimd"
 # CHECK: attribute      5, "rv32i2p1_xcvsimd1p0"
 
 .attribute arch, "rv32i_xcvbi"
 # CHECK: attribute      5, "rv32i2p1_xcvbi1p0"
 
 .attribute arch, "rv32i_zicfilp0p2"
 # CHECK: attribute      5, "rv32i2p1_zicfilp0p2"

llvm/test/MC/RISCV/corev/XCVelw-invalid.s

+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvelw %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+cv.elw t0, 0(0)
+# CHECK-ERROR: expected register
+
+cv.elw 0, 0(x6)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.elw x12, 2048(x6)
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.elw x12, x1(2047)
+# CHECK-ERROR: unexpected token
+
+cv.elw 0, x12(x6)
+# CHECK-ERROR: unexpected token
+
+cv.elw x12, x12(x6)
+# CHECK-ERROR: unexpected token
+
+cv.elw 0, 0(x6)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.elw x0
+# CHECK-ERROR: too few operands for instruction

llvm/test/MC/RISCV/corev/XCVelw-valid.s

+# RUN: llvm-mc -triple=riscv32 --mattr=+xcvelw -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvelw < %s \
+# RUN:     | llvm-objdump --mattr=+xcvelw -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-INSTR %s
+# RUN: not llvm-mc -triple riscv32 %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-NO-EXT %s
+
+cv.elw a0, 1024(a0)
+# CHECK-INSTR: cv.elw a0, 1024(a0)
+# CHECK-ENCODING: [0x0b,0x35,0x05,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVelw' (Event Load Word){{$}} 
+
+cv.elw a1, 1(a1)
+# CHECK-INSTR: cv.elw a1, 1(a1)
+# CHECK-ENCODING: [0x8b,0xb5,0x15,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVelw' (Event Load Word){{$}}
+
+cv.elw a2, -1024(a3)
+# CHECK-INSTR: cv.elw  a2, -1024(a3)
+# CHECK-ENCODING: [0x0b,0xb6,0x06,0xc0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVelw' (Event Load Word){{$}}

llvm/test/MC/RISCV/corev/XCVmem-invalid.s

+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvmem %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+cv.lb t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lb 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lb 0, (0), t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lb t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lb t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lb t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lb 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lb t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lb t0, (t2)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lb t0, (t1), t2, t3
+
+cv.lbu t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lbu 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lbu 0, (0), t0 
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lbu t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lbu t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lbu t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lbu 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lbu t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lbu t0, (t2)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lbu t0, (t1), t2, t3 
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh 0, (0), t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lh t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lh t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh t0, t1(0)
+# CHECK-ERROR: expected register
+
+cv.lh 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lh t0, (t1)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lh t0, (t1), t2, t3
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu 0, 0(t1)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lhu t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lhu t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu t0, t1(0)
+# CHECK-ERROR: expected register
+
+cv.lhu 0, t0, t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lhu t0, (t1)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lhu t0, (t1), t2, t3
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw 0, (0), t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lw t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lw t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw t0, t1(0)
+# CHECK-ERROR: expected register
+
+cv.lw 0, (t0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lw t0, (t1)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lw t0, (t1), t2, t3
+# CHECK-ERROR: invalid operand for instruction 
+
+cv.sb t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sb 0, (t0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sb t0, 0(t1)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sb t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.sb t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sb 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sb t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.sh t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sh 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sh t0, 0(t1)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sh t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.sh t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sh 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sh t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.sw t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sw 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sw t0, 0(t1)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sw t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.sw t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sw 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sw t0
+# CHECK-ERROR: too few operands for instruction

llvm/test/MC/RISCV/corev/XCVmem-valid.s

+# RUN: llvm-mc -triple=riscv32 --mattr=+xcvmem -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvmem < %s \
+# RUN:     | llvm-objdump --mattr=+xcvmem -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-INSTR %s
+# RUN: not llvm-mc -triple riscv32 %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-NO-EXT %s
+
+cv.lb t0, (t1), 0
+# CHECK-INSTR: cv.lb t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x02,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lb a0, (a1), 2047
+# CHECK-INSTR: cv.lb a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0x85,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lb t0, (t1), t2
+# CHECK-INSTR: cv.lb t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lb a0, (a1), a2
+# CHECK-INSTR: cv.lb a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lb t0, t2(t1)
+# CHECK-INSTR: cv.lb t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x08]
+# CHECK-NO-EXT: unexpected token
+
+cv.lb a0, a2(a1)
+# CHECK-INSTR: cv.lb a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x08]
+# CHECK-NO-EXT: unexpected token
+
+cv.lbu t0, (t1), 0
+# CHECK-INSTR: cv.lbu t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x42,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lbu a0, (a1), 2047
+# CHECK-INSTR: cv.lbu a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0xc5,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lbu t0, (t1), t2
+# CHECK-INSTR: cv.lbu t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x10]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lbu a0, (a1), a2
+# CHECK-INSTR: cv.lbu a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x10]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lbu t0, t2(t1)
+# CHECK-INSTR: cv.lbu t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x18]
+# CHECK-NO-EXT: unexpected token
+
+cv.lbu a0, a2(a1)
+# CHECK-INSTR: cv.lbu a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x18]
+# CHECK-NO-EXT: unexpected token
+
+cv.lh t0, (t1), 0
+# CHECK-INSTR: cv.lh t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x12,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lh a0, (a1), 2047
+# CHECK-INSTR: cv.lh a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0x95,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lh t0, (t1), t2
+# CHECK-INSTR: cv.lh t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x02]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lh a0, (a1), a2
+# CHECK-INSTR: cv.lh a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x02]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lh t0, t2(t1)
+# CHECK-INSTR: cv.lh t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x0a]
+# CHECK-NO-EXT: unexpected token
+
+cv.lh a0, a2(a1)
+# CHECK-INSTR: cv.lh a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x0a]
+# CHECK-NO-EXT: unexpected token
+
+cv.lhu t0, (t1), 0
+# CHECK-INSTR: cv.lhu t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x52,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lhu a0, (a1), 2047
+# CHECK-INSTR: cv.lhu a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0xd5,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lhu t0, (t1), t2
+# CHECK-INSTR: cv.lhu t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x12]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lhu a0, (a1), a2
+# CHECK-INSTR: cv.lhu a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x12]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lhu t0, t2(t1)
+# CHECK-INSTR: cv.lhu t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x1a]
+# CHECK-NO-EXT: unexpected token
+
+cv.lhu a0, a2(a1)
+# CHECK-INSTR: cv.lhu a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x1a]
+# CHECK-NO-EXT: unexpected token
+
+cv.lw t0, (t1), 0
+# CHECK-INSTR: cv.lw t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x22,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lw a0, (a1), 2047
+# CHECK-INSTR: cv.lw a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0xa5,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lw t0, (t1), t2
+# CHECK-INSTR: cv.lw t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x04]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lw a0, (a1), a2
+# CHECK-INSTR: cv.lw a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x04]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.lw t0, t2(t1)
+# CHECK-INSTR: cv.lw t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x0c]
+# CHECK-NO-EXT: unexpected token
+
+cv.lw a0, a2(a1)
+# CHECK-INSTR: cv.lw a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x0c]
+# CHECK-NO-EXT: unexpected token
+
+cv.sb t0, (t1), 0
+# CHECK-INSTR: cv.sb t0, (t1), 0
+# CHECK-ENCODING: [0x2b,0x00,0x53,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.sb a0, (a1), 2047
+# CHECK-INSTR: cv.sb a0, (a1), 2047
+# CHECK-ENCODING: [0xab,0x8f,0xa5,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.sb t0, (t1), t2
+# CHECK-INSTR: cv.sb t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x33,0x53,0x20]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.sb a0, (a1), a2
+# CHECK-INSTR: cv.sb a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x20]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.sb t0, t2(t1)
+# CHECK-INSTR: cv.sb t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x33,0x53,0x28]
+# CHECK-NO-EXT: unexpected token
+
+cv.sb a0, a2(a1)
+# CHECK-INSTR: cv.sb a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x28]
+# CHECK-NO-EXT: unexpected token
+
+cv.sh t0, (t1), 0
+# CHECK-INSTR: cv.sh t0, (t1), 0
+# CHECK-ENCODING: [0x2b,0x10,0x53,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.sh a0, (a1), 2047
+# CHECK-INSTR: cv.sh a0, (a1), 2047
+# CHECK-ENCODING: [0xab,0x9f,0xa5,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.sh t0, (t1), t2
+# CHECK-INSTR: cv.sh t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x33,0x53,0x22]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.sh a0, (a1), a2
+# CHECK-INSTR: cv.sh a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x22]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.sh t0, t2(t1)
+# CHECK-INSTR: cv.sh t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x33,0x53,0x2a]
+# CHECK-NO-EXT: unexpected token
+
+cv.sh a0, a2(a1)
+# CHECK-INSTR: cv.sh a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x2a]
+# CHECK-NO-EXT: unexpected token
+
+cv.sw t0, (t1), 0
+# CHECK-INSTR: cv.sw t0, (t1), 0
+# CHECK-ENCODING: [0x2b,0x20,0x53,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.sw a0, (a1), 2047
+# CHECK-INSTR: cv.sw a0, (a1), 2047
+# CHECK-ENCODING: [0xab,0xaf,0xa5,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.sw t0, (t1), t2
+# CHECK-INSTR: cv.sw t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x33,0x53,0x24]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.sw a0, (a1), a2
+# CHECK-INSTR: cv.sw a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x24]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (Post-incrementing Load & Store){{$}}
+
+cv.sw t0, t2(t1)
+# CHECK-INSTR: cv.sw t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x33,0x53,0x2c]
+# CHECK-NO-EXT: unexpected token
+
+cv.sw a0, a2(a1)
+# CHECK-INSTR: cv.sw a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x2c]
+# CHECK-NO-EXT: unexpected token