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[RISCV][MC] MC layer support for xcvmem and xcvelw extensions
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Authored by liaolucy on Aug 25 2023, 1:29 AM.

Details

Summary

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Several other extensions have been merged.
Spec:
https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst
Contributors: @CharKeaney, @jeremybennett, @lewis-revill, Nandni Jamnadas, @PaoloS, @simoncook, @xmj, @realqhc, @melonedo, @adeelahmad81299

Diff Detail

Event Timeline

liaolucy created this revision.Aug 25 2023, 1:29 AM
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liaolucy requested review of this revision.Aug 25 2023, 1:29 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 25 2023, 1:29 AM
sunshaoce added inline comments.Aug 25 2023, 1:59 AM
llvm/lib/Target/RISCV/RISCVFeatures.td
818

"'XCVelw' (CORE-V Event Load Word)"

liaolucy updated this revision to Diff 553459.Aug 25 2023, 6:48 AM

address comments, thanks.

craig.topper added inline comments.Aug 25 2023, 10:56 AM
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
2512

core-v -> CORE-V to be consistent with other places?

liaolucy updated this revision to Diff 553822.Aug 27 2023, 6:11 PM
  1. core-v -> CORE-V to be consistent with other places
  2. rebase
liaolucy edited the summary of this revision. (Show Details)Aug 27 2023, 6:14 PM
liaolucy added subscribers: CharKeaney, melonedo, realqhc and 3 others.
Jim added a comment.Aug 27 2023, 7:09 PM

It is also needed to add pre-defined macro test in clang/test/Preprocessor/riscv-target-features.c

llvm/docs/RISCVUsage.rst
273

prefixed with cv. ?

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
565

Indent.

581

Indent.

632

Indent.

636

// Event load

llvm/test/MC/RISCV/corev/XCVelw-valid.s
3

Indent is not the same with others.

liaolucy updated this revision to Diff 553911.Aug 28 2023, 6:30 AM

Address comments from Jim, thanks.

Herald added a project: Restricted Project. · View Herald TranscriptAug 28 2023, 6:30 AM
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liaolucy updated this revision to Diff 556222.Sep 7 2023, 7:44 PM
  1. Rebase.
  2. Update RISCVISAInfoTest.cpp
liaolucy edited the summary of this revision. (Show Details)Nov 3 2023, 12:37 AM
liaolucy edited the summary of this revision. (Show Details)
liaolucy added a subscriber: adeelahmad81299.
craig.topper added inline comments.Nov 7 2023, 11:17 PM
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
2511–2516

Is it possible to use a custom parser instead of adding a special case to the generic parser?

liaolucy updated this revision to Diff 558107.Nov 15 2023, 5:52 AM
  1. use a custom parser to parse Register-Register load/store
  2. Rebase

Thanks

This revision is now accepted and ready to land.Nov 15 2023, 2:39 PM