[X86] Add SM3 instructions.

[FreddyYe]

Summary

For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

[pengfei]

llvm/test/MC/Disassembler/X86/sm3-32.txt

2

Remove blank line

llvm/test/MC/Disassembler/X86/sm3-64.txt

2–3

Remove

5

We can merge 64-bit tests into 32-bit ones. The same below.

[skan]

llvm/lib/Target/X86/X86InstrSSE.td

8331

Is the schedule appropriate?

llvm/test/MC/Disassembler/X86/sm3-32.txt

4

Drop -x86-asm-syntax=intel

[FreddyYe]

Address comments.

[FreddyYe]

llvm/lib/Target/X86/X86InstrSSE.td

8331

I referred to SHA1MSG1's, any good ideas? I'll add a FIXME first here.

llvm/test/MC/Disassembler/X86/sm3-64.txt

5

Due to these instructions support rm form, hard to merge here?

[RKSimon]

clang/lib/Headers/sm3intrin.h

22

Doxygen descriptions?

llvm/test/MC/Disassembler/X86/sm3-64.txt

5

I'd prefer to see 32/64 test coverage kept separate, but it'd be more useful for 64 to use xmm8-xmm15 and 64-specific gpr registers etc. to increase coverage.

[FreddyYe]

Remove #include <stddef.h>

[FreddyYe]

Address commments.

[FreddyYe]

Refine doxygen

[RKSimon]

clang/lib/Headers/sm3intrin.h

32

VPDPBSSD ?

[FreddyYe]

Address comments.

[RKSimon]

@pengfei Are you happy with the intrinsics doxygen descriptions?

[pengfei]

clang/lib/Headers/sm3intrin.h

29

Add return type too.

86

ditto.

149

ditto.

231

Missing __ for variables.

[pengfei]

clang/lib/Headers/sm3intrin.h

70

DEST[MAX:128] := 0 the same to below.

[FreddyYe]

Address comments.

clang/lib/Headers/sm3intrin.h

231

MACROs prefer no __ for prefix and the operation defines A, B, C, ... So I used another naming convention in doxygen for parameters.

[pengfei]

LGTM.

[pengfei]

clang/lib/Headers/sm3intrin.h

162–165

The description should invert

[FreddyYe]

Address comment.

[pengfei]

clang/lib/Headers/sm3intrin.h

163

This is int

[FreddyYe]

Address comments.

[FreddyYe]

rebase and fix lit fail

clang/docs/ReleaseNotes.rst

 ^^^^^^^^^^^
 
 - Add ISA of ``AMX-COMPLEX`` which supports ``tcmmimfp16ps`` and
   ``tcmmrlfp16ps``.
 - Support ISA of ``SHA512``.
   * Support intrinsic of ``_mm256_sha512msg1_epi64``.
   * Support intrinsic of ``_mm256_sha512msg2_epi64``.
   * Support intrinsic of ``_mm256_sha512rnds2_epi64``.
+- Support ISA of ``SM3``.
+  * Support intrinsic of ``_mm_sm3msg1_epi32``.
+  * Support intrinsic of ``_mm_sm3msg2_epi32``.
+  * Support intrinsic of ``_mm_sm3rnds2_epi32``.
 
 Arm and AArch64 Support
 ^^^^^^^^^^^^^^^^^^^^^^^
 
 - The hard-float ABI is now available in Armv8.1-M configurations that
   have integer MVE instructions (and therefore have FP registers) but
   no scalar or vector floating point computation. Previously, trying
   to select the hard-float ABI on such a target (via

clang/include/clang/Basic/BuiltinsX86.def

 TARGET_HEADER_BUILTIN(_InterlockedDecrement64,   "WiWiD*",   "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedExchange64,    "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd64, "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedExchangeSub64, "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedIncrement64,   "WiWiD*",   "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedOr64,          "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedXor64,         "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
 
+// SM3
+TARGET_BUILTIN(__builtin_ia32_vsm3msg1, "V4UiV4UiV4UiV4Ui", "nV:128:", "sm3")
+TARGET_BUILTIN(__builtin_ia32_vsm3msg2, "V4UiV4UiV4UiV4Ui", "nV:128:", "sm3")
+TARGET_BUILTIN(__builtin_ia32_vsm3rnds2, "V4UiV4UiV4UiV4UiIUi", "nV:128:", "sm3")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN
 #undef TARGET_HEADER_BUILTIN

clang/include/clang/Driver/Options.td

 def mserialize : Flag<["-"], "mserialize">, Group<m_x86_Features_Group>;
 def mno_serialize : Flag<["-"], "mno-serialize">, Group<m_x86_Features_Group>;
 def msgx : Flag<["-"], "msgx">, Group<m_x86_Features_Group>;
 def mno_sgx : Flag<["-"], "mno-sgx">, Group<m_x86_Features_Group>;
 def msha : Flag<["-"], "msha">, Group<m_x86_Features_Group>;
 def mno_sha : Flag<["-"], "mno-sha">, Group<m_x86_Features_Group>;
 def msha512 : Flag<["-"], "msha512">, Group<m_x86_Features_Group>;
 def mno_sha512 : Flag<["-"], "mno-sha512">, Group<m_x86_Features_Group>;
+def msm3 : Flag<["-"], "msm3">, Group<m_x86_Features_Group>;
+def mno_sm3 : Flag<["-"], "mno-sm3">, Group<m_x86_Features_Group>;
 def mtbm : Flag<["-"], "mtbm">, Group<m_x86_Features_Group>;
 def mno_tbm : Flag<["-"], "mno-tbm">, Group<m_x86_Features_Group>;
 def mtsxldtrk : Flag<["-"], "mtsxldtrk">, Group<m_x86_Features_Group>;
 def mno_tsxldtrk : Flag<["-"], "mno-tsxldtrk">, Group<m_x86_Features_Group>;
 def muintr : Flag<["-"], "muintr">, Group<m_x86_Features_Group>;
 def mno_uintr : Flag<["-"], "mno-uintr">, Group<m_x86_Features_Group>;
 def mvaes : Flag<["-"], "mvaes">, Group<m_x86_Features_Group>;
 def mno_vaes : Flag<["-"], "mno-vaes">, Group<m_x86_Features_Group>;

clang/lib/Basic/Targets/X86.h

class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
   bool HasAVX512VBMI = false;
   bool HasAVX512VBMI2 = false;
   bool HasAVXIFMA = false;
   bool HasAVX512IFMA = false;
   bool HasAVX512VP2INTERSECT = false;
   bool HasSHA = false;
   bool HasSHA512 = false;
   bool HasSHSTK = false;
+  bool HasSM3 = false;
   bool HasSGX = false;
   bool HasCX8 = false;
   bool HasCX16 = false;
   bool HasFXSR = false;
   bool HasXSAVE = false;
   bool HasXSAVEOPT = false;
   bool HasXSAVEC = false;
   bool HasXSAVES = false;

clang/lib/Basic/Targets/X86.cpp

for (const auto &Feature : Features) {
     } else if (Feature == "+avx512vp2intersect") {
       HasAVX512VP2INTERSECT = true;
     } else if (Feature == "+sha") {
       HasSHA = true;
     } else if (Feature == "+sha512") {
       HasSHA512 = true;
     } else if (Feature == "+shstk") {
       HasSHSTK = true;
+    } else if (Feature == "+sm3") {
+      HasSM3 = true;
     } else if (Feature == "+movbe") {
       HasMOVBE = true;
     } else if (Feature == "+sgx") {
       HasSGX = true;
     } else if (Feature == "+cx8") {
       HasCX8 = true;
     } else if (Feature == "+cx16") {
       HasCX16 = true;
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   if (HasCLWB)
     Builder.defineMacro("__CLWB__");
   if (HasWBNOINVD)
     Builder.defineMacro("__WBNOINVD__");
   if (HasSHSTK)
     Builder.defineMacro("__SHSTK__");
   if (HasSGX)
     Builder.defineMacro("__SGX__");
+  if (HasSM3)
+    Builder.defineMacro("__SM3__");
   if (HasPREFETCHI)
     Builder.defineMacro("__PREFETCHI__");
   if (HasPREFETCHWT1)
     Builder.defineMacro("__PREFETCHWT1__");
   if (HasCLZERO)
     Builder.defineMacro("__CLZERO__");
   if (HasKL)
     Builder.defineMacro("__KL__");
return llvm::StringSwitch<bool>(Name)
       .Case("rdseed", true)
       .Case("rtm", true)
       .Case("sahf", true)
       .Case("serialize", true)
       .Case("sgx", true)
       .Case("sha", true)
       .Case("sha512", true)
       .Case("shstk", true)
+      .Case("sm3", true)
       .Case("sse", true)
       .Case("sse2", true)
       .Case("sse3", true)
       .Case("ssse3", true)
       .Case("sse4", true)
       .Case("sse4.1", true)
       .Case("sse4.2", true)
       .Case("sse4a", true)
return llvm::StringSwitch<bool>(Feature)
       .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
       .Case("rtm", HasRTM)
       .Case("sahf", HasLAHFSAHF)
       .Case("serialize", HasSERIALIZE)
       .Case("sgx", HasSGX)
       .Case("sha", HasSHA)
       .Case("sha512", HasSHA512)
       .Case("shstk", HasSHSTK)
+      .Case("sm3", HasSM3)
       .Case("sse", SSELevel >= SSE1)
       .Case("sse2", SSELevel >= SSE2)
       .Case("sse3", SSELevel >= SSE3)
       .Case("ssse3", SSELevel >= SSSE3)
       .Case("sse4.1", SSELevel >= SSE41)
       .Case("sse4.2", SSELevel >= SSE42)
       .Case("sse4a", XOPLevel >= SSE4A)
       .Case("tbm", HasTBM)

clang/lib/Headers/CMakeLists.txt

# Intrinsics
   raointintrin.h
   rdpruintrin.h
   rdseedintrin.h
   rtmintrin.h
   serializeintrin.h
   sgxintrin.h
   sha512intrin.h
   shaintrin.h
+  sm3intrin.h
   smmintrin.h
   tbmintrin.h
   tmmintrin.h
   tsxldtrkintrin.h
   uintrintrin.h
   vaesintrin.h
   vpclmulqdqintrin.h
   waitpkgintrin.h

clang/lib/Headers/immintrin.h

 #endif
 
 #if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
     defined(__SHA512__)
 #include <sha512intrin.h>
 #endif
 
 #if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
+    defined(__SM3__)
+#include <sm3intrin.h>
+#endif
+
+#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
     defined(__RDPID__)
 /// Returns the value of the IA32_TSC_AUX MSR (0xc0000103).
 ///
 /// \headerfile <immintrin.h>
 ///
 /// This intrinsic corresponds to the <c> RDPID </c> instruction.
 static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__, __target__("rdpid")))
 _rdpid_u32(void) {

clang/lib/Headers/sm3intrin.h

+/*===-------------------- sm3intrin.h - SM3 intrinsics ---------------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __IMMINTRIN_H
+#error "Never use <sm3intrin.h> directly; include <immintrin.h> instead."
+#endif // __IMMINTRIN_H
+
+#ifndef __SM3INTRIN_H
+#define __SM3INTRIN_H
+
+#define __DEFAULT_FN_ATTRS128                                                  \
+  __attribute__((__always_inline__, __nodebug__, __target__("sm3"),            \
+                 __min_vector_width__(128)))
+
+/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
+///    intrinsic performs an initial calculation for the next four SM3 message
+///    words. The calculated results are stored in \a dst.
+///
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m128i _mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C)
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSM3MSG1 instruction.
+///
+/// \param __A
+///    A 128-bit vector of [4 x int].
+/// \param __B
+///    A 128-bit vector of [4 x int].
+/// \param __C
+///    A 128-bit vector of [4 x int].
+/// \returns
+///    A 128-bit vector of [4 x int].
+///
+/// \code{.operation}
+/// DEFINE ROL32(dword, n) {
+///   count := n % 32
+///   dest := (dword << count) | (dword >> (32 - count))
+///   RETURN dest
+/// }
+/// DEFINE P1(x) {
+///   RETURN x ^ ROL32(x, 15) ^ ROL32(x, 23)
+/// }
+/// W[0] := __C.dword[0]
+/// W[1] := __C.dword[1]
+/// W[2] := __C.dword[2]
+/// W[3] := __C.dword[3]
+/// W[7] := __A.dword[0]
+/// W[8] := __A.dword[1]
+/// W[9] := __A.dword[2]
+/// W[10] := __A.dword[3]
+/// W[13] := __B.dword[0]
+/// W[14] := __B.dword[1]
+/// W[15] := __B.dword[2]
+/// TMP0 := W[7] ^ W[0] ^ ROL32(W[13], 15)
+/// TMP1 := W[8] ^ W[1] ^ ROL32(W[14], 15)
+/// TMP2 := W[9] ^ W[2] ^ ROL32(W[15], 15)
+/// TMP3 := W[10] ^ W[3]
+/// dst.dword[0] := P1(TMP0)
+/// dst.dword[1] := P1(TMP1)
+/// dst.dword[2] := P1(TMP2)
+/// dst.dword[3] := P1(TMP3)
+/// dst[MAX:128] := 0
+/// \endcode
+static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg1_epi32(__m128i __A,
+                                                                  __m128i __B,
+                                                                  __m128i __C) {
+  return (__m128i)__builtin_ia32_vsm3msg1((__v4su)__A, (__v4su)__B,
+                                          (__v4su)__C);
+}
+
+/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
+///    intrinsic performs the final calculation for the next four SM3 message
+///    words. The calculated results are stored in \a dst.
+///
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m128i _mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C)
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSM3MSG2 instruction.
+///
+/// \param __A
+///    A 128-bit vector of [4 x int].
+/// \param __B
+///    A 128-bit vector of [4 x int].
+/// \param __C
+///    A 128-bit vector of [4 x int].
+/// \returns
+///    A 128-bit vector of [4 x int].
+///
+/// \code{.operation}
+/// DEFINE ROL32(dword, n) {
+///   count := n % 32
+///   dest := (dword << count) | (dword >> (32-count))
+///   RETURN dest
+/// }
+/// WTMP[0] := __A.dword[0]
+/// WTMP[1] := __A.dword[1]
+/// WTMP[2] := __A.dword[2]
+/// WTMP[3] := __A.dword[3]
+/// W[3] := __B.dword[0]
+/// W[4] := __B.dword[1]
+/// W[5] := __B.dword[2]
+/// W[6] := __B.dword[3]
+/// W[10] := __C.dword[0]
+/// W[11] := __C.dword[1]
+/// W[12] := __C.dword[2]
+/// W[13] := __C.dword[3]
+/// W[16] := ROL32(W[3], 7) ^ W[10] ^ WTMP[0]
+/// W[17] := ROL32(W[4], 7) ^ W[11] ^ WTMP[1]
+/// W[18] := ROL32(W[5], 7) ^ W[12] ^ WTMP[2]
+/// W[19] := ROL32(W[6], 7) ^ W[13] ^ WTMP[3]
+/// W[19] := W[19] ^ ROL32(W[16], 6) ^ ROL32(W[16], 15) ^ ROL32(W[16], 30)
+/// dst.dword[0] := W[16]
+/// dst.dword[1] := W[17]
+/// dst.dword[2] := W[18]
+/// dst.dword[3] := W[19]
+/// dst[MAX:128] := 0
+/// \endcode
+static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg2_epi32(__m128i __A,
+                                                                  __m128i __B,
+                                                                  __m128i __C) {
+  return (__m128i)__builtin_ia32_vsm3msg2((__v4su)__A, (__v4su)__B,
+                                          (__v4su)__C);
+}
+
+/// This intrinsic performs two rounds of SM3 operation using initial SM3 state
+///    (C, D, G, H) from \a __A, an initial SM3 states (A, B, E, F)
+///    from \a __B and a pre-computed words from the \a __C. \a __A with
+///    initial SM3 state of (C, D, G, H) assumes input of non-rotated left
+///    variables from previous state. The updated SM3 state (A, B, E, F) is
+///    written to \a __A. The \a imm8 should contain the even round number
+///    for the first of the two rounds computed by this instruction. The
+///    computation masks the \a imm8 value by AND’ing it with 0x3E so that only
+///    even round numbers from 0 through 62 are used for this operation. The
+///    calculated results are stored in \a dst.
+///
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m128i _mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C, const int
+/// imm8) \endcode
+///
+/// This intrinsic corresponds to the \c VSM3RNDS2 instruction.
+///
+/// \param __A
+///    A 128-bit vector of [4 x int].
+/// \param __B
+///    A 128-bit vector of [4 x int].
+/// \param __C
+///    A 128-bit vector of [4 x int].
+/// \param imm8
+///    A 8-bit constant integer.
+/// \returns
+///    A 128-bit vector of [4 x int].
+///
+/// \code{.operation}
+/// DEFINE ROL32(dword, n) {
+///   count := n % 32
+///   dest := (dword << count) | (dword >> (32-count))
+///   RETURN dest
+/// }
+/// DEFINE P0(dword) {
+///   RETURN dword ^ ROL32(dword, 9) ^ ROL32(dword, 17)
+/// }
+/// DEFINE FF(x,y,z, round){
+///   IF round < 16
+///     RETURN (x ^ y ^ z)
+///   ELSE
+///     RETURN (x & y) | (x & z) | (y & z)
+///   FI
+/// }
+/// DEFINE GG(x, y, z, round){
+///   IF round < 16
+///     RETURN (x ^ y ^ z)
+///   ELSE
+///     RETURN (x & y) | (~x & z)
+///   FI
+/// }
+/// A[0] := __B.dword[3]
+/// B[0] := __B.dword[2]
+/// C[0] := __A.dword[3]
+/// D[0] := __A.dword[2]
+/// E[0] := __B.dword[1]
+/// F[0] := __B.dword[0]
+/// G[0] := __A.dword[1]
+/// H[0] := __A.dword[0]
+/// W[0] := __C.dword[0]
+/// W[1] := __C.dword[1]
+/// W[4] := __C.dword[2]
+/// W[5] := __C.dword[3]
+/// C[0] := ROL32(C[0], 9)
+/// D[0] := ROL32(D[0], 9)
+/// G[0] := ROL32(G[0], 19)
+/// H[0] := ROL32(H[0], 19)
+/// ROUND := __D & 0x3E
+/// IF ROUND < 16
+///   CONST := 0x79CC4519
+/// ELSE
+///   CONST := 0x7A879D8A
+/// FI
+/// CONST := ROL32(CONST,ROUND)
+/// FOR i:= 0 to 1
+///   S1 := ROL32((ROL32(A[i], 12) + E[i] + CONST), 7)
+///   S2 := S1 ^ ROL32(A[i], 12)
+///   T1 := FF(A[i], B[i], C[i], ROUND) + D[i] + S2 + (W[i] ^ W[i+4])
+///   T2 := GG(E[i], F[i], G[i], ROUND) + H[i] + S1 + W[i]
+///   D[i+1] := C[i]
+///   C[i+1] := ROL32(B[i],9)
+///   B[i+1] := A[i]
+///   A[i+1] := T1
+///   H[i+1] := G[i]
+///   G[i+1] := ROL32(F[i], 19)
+///   F[i+1] := E[i]
+///   E[i+1] := P0(T2)
+///   CONST := ROL32(CONST, 1)
+/// ENDFOR
+/// dst.dword[3] := A[2]
+/// dst.dword[2] := B[2]
+/// dst.dword[1] := E[2]
+/// dst.dword[0] := F[2]
+/// dst[MAX:128] := 0
+/// \endcode
+#define _mm_sm3rnds2_epi32(A, B, C, D)                                         \
+  (__m128i) __builtin_ia32_vsm3rnds2((__v4su)A, (__v4su)B, (__v4su)C, (int)D)
+
+#undef __DEFAULT_FN_ATTRS128
+
+#endif // __SM3INTRIN_H

clang/lib/Sema/SemaChecking.cpp

bool Sema::CheckX86BuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
   case X86::BI__builtin_ia32_pternlogd128_mask:
   case X86::BI__builtin_ia32_pternlogd128_maskz:
   case X86::BI__builtin_ia32_pternlogd256_mask:
   case X86::BI__builtin_ia32_pternlogd256_maskz:
   case X86::BI__builtin_ia32_pternlogq128_mask:
   case X86::BI__builtin_ia32_pternlogq128_maskz:
   case X86::BI__builtin_ia32_pternlogq256_mask:
   case X86::BI__builtin_ia32_pternlogq256_maskz:
+  case X86::BI__builtin_ia32_vsm3rnds2:
     i = 3; l = 0; u = 255;
     break;
   case X86::BI__builtin_ia32_gatherpfdpd:
   case X86::BI__builtin_ia32_gatherpfdps:
   case X86::BI__builtin_ia32_gatherpfqpd:
   case X86::BI__builtin_ia32_gatherpfqps:
   case X86::BI__builtin_ia32_scatterpfdpd:
   case X86::BI__builtin_ia32_scatterpfdps:

clang/test/CodeGen/X86/sm3-builtins.c

+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +sm3 -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +sm3 -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include <immintrin.h>
+
+__m128i test_mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C) {
+  // CHECK-LABEL: @test_mm_sm3msg1_epi32(
+  // CHECK: call <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
+  return _mm_sm3msg1_epi32(__A, __B, __C);
+}
+
+__m128i test_mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C) {
+  // CHECK-LABEL: @test_mm_sm3msg2_epi32(
+  // CHECK: call <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
+  return _mm_sm3msg2_epi32(__A, __B, __C);
+}
+
+__m128i test_mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C) {
+  // CHECK-LABEL: @test_mm_sm3rnds2_epi32(
+  // CHECK: call <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 127)
+  return _mm_sm3rnds2_epi32(__A, __B, __C, 127);
+}

clang/test/CodeGen/X86/sm3-error.c

+// RUN: %clang_cc1 %s -ffreestanding -triple=i686-unknown-unknown -target-feature +sm3  -emit-llvm -fsyntax-only -verify
+
+#include <immintrin.h>
+
+__m128i test_mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C) {
+  return _mm_sm3rnds2_epi32(__A, __B, __C, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}

clang/test/CodeGen/attr-target-x86.c

 // CHECK: qax{{.*}} #5
 // CHECK: qq{{.*}} #6
 // CHECK: lake{{.*}} #7
 // CHECK: use_before_def{{.*}} #7
 // CHECK: walrus{{.*}} #8
 // CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" "tune-cpu"="i686"
 // CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
 // CHECK-NOT: tune-cpu
-// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sha512,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
+// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sha512,-sm3,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
 // CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+crc32,+cx8,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" "tune-cpu"="i686"
-// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
+// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sm3,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
 // CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes,-vaes"
 // CHECK-NOT: tune-cpu
 // CHECK: #6 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-3dnow,-3dnowa,-mmx"
 // CHECK: #7 = {{.*}}"target-cpu"="lakemont" "target-features"="+cx8,+mmx"
 // CHECK-NOT: tune-cpu
 // CHECK: #8 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" "tune-cpu"="sandybridge"
 
 // CHECK: "target-cpu"="x86-64-v2"
 // CHECK-SAME: "target-features"="+cmov,+crc32,+cx16,+cx8,+fxsr,+mmx,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
 // CHECK: "target-cpu"="x86-64-v3"
 // CHECK-SAME: "target-features"="+avx,+avx2,+bmi,+bmi2,+cmov,+crc32,+cx16,+cx8,+f16c,+fma,+fxsr,+lzcnt,+mmx,+movbe,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave"
 // CHECK: "target-cpu"="x86-64-v4"
 // CHECK-SAME: "target-features"="+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+cmov,+crc32,+cx16,+cx8,+f16c,+fma,+fxsr,+lzcnt,+mmx,+movbe,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave"

clang/test/Driver/x86-target-features.c

 // AVXNECONVERT: "-target-feature" "+avxneconvert"
 // NO-AVXNECONVERT: "-target-feature" "-avxneconvert"
 
 // RUN: %clang --target=i386 -msha512 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=SHA512 %s
 // RUN: %clang --target=i386 -mno-sha512 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-SHA512 %s
 // SHA512: "-target-feature" "+sha512"
 // NO-SHA512: "-target-feature" "-sha512"
 
+// RUN: %clang --target=i386 -msm3 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=SM3 %s
+// RUN: %clang --target=i386 -mno-sm3 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-SM3 %s
+// SM3: "-target-feature" "+sm3"
+// NO-SM3: "-target-feature" "-sm3"
+
 // RUN: %clang --target=i386 -march=i386 -mcrc32 %s -### 2>&1 | FileCheck -check-prefix=CRC32 %s
 // RUN: %clang --target=i386 -march=i386 -mno-crc32 %s -### 2>&1 | FileCheck -check-prefix=NO-CRC32 %s
 // CRC32: "-target-feature" "+crc32"
 // NO-CRC32: "-target-feature" "-crc32"
 
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=return %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=SLS-RET,NO-SLS %s
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=indirect-jmp %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=SLS-IJMP,NO-SLS %s
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=none -mharden-sls=all %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=SLS-IJMP,SLS-RET %s

clang/test/Preprocessor/x86_target_features.c

 // RUN: %clang -target i386-unknown-linux-gnu -march=atom -mno-sha512 -x c -E -dM -o - %s | FileCheck  -check-prefix=NOSHA512 %s
 // NOSHA512-NOT: #define __SHA512__ 1
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=atom -msha512 -mno-avx -x c -E -dM -o - %s | FileCheck  -check-prefix=SHA512NOAVX %s
 
 // SHA512NOAVX-NOT: #define __AVX__ 1
 // SHA512NOAVX-NOT: #define __SHA512__ 1
 
+// RUN: %clang -target i686-unknown-linux-gnu -march=atom -msm3 -x c -E -dM -o - %s | FileCheck  -check-prefix=SM3 %s
+
+// SM3: #define __AVX__ 1
+// SM3: #define __SM3__ 1
+
+// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mno-sm3 -x c -E -dM -o - %s | FileCheck  -check-prefix=NOSM3 %s
+
+// NOSM3-NOT: #define __SM3__ 1
+
+// RUN: %clang -target i686-unknown-linux-gnu -march=atom -msm3 -mno-avx -x c -E -dM -o - %s | FileCheck  -check-prefix=SM3NOAVX %s
+
+// SM3NOAVX-NOT: #define __SM3__ 1
+// SM3NOAVX-NOT: #define __AVX__ 1
+
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mcrc32 -x c -E -dM -o - %s | FileCheck -check-prefix=CRC32 %s
 
 // CRC32: #define __CRC32__ 1
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-crc32 -x c -E -dM -o - %s | FileCheck -check-prefix=NOCRC32 %s
 
 // NOCRC32-NOT: #define __CRC32__ 1
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mrdpru -x c -E -dM -o - %s | FileCheck -check-prefix=RDPRU %s
 
 // RDPRU: #define __RDPRU__ 1
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-rdpru -x c -E -dM -o - %s | FileCheck -check-prefix=NORDPRU %s
 
 // NORDPRU-NOT: #define __RDPRU__ 1

llvm/docs/ReleaseNotes.rst

 
 Changes to the X86 Backend
 --------------------------
 
 * ``__builtin_unpredictable`` (unpredictable metadata in LLVM IR), is handled by X86 Backend.
   ``X86CmovConversion`` pass now respects this builtin and does not convert CMOVs to branches.
 * Add support for the ``PBNDKB`` instruction.
 * Support ISA of ``SHA512``.
+* Support ISA of ``SM3``.
 
 Changes to the OCaml bindings
 -----------------------------
 
 Changes to the Python bindings
 ------------------------------
 
 * The python bindings have been removed.

llvm/include/llvm/IR/IntrinsicsX86.td

 def int_x86_vcvtneps2bf16128
     : ClangBuiltin<"__builtin_ia32_vcvtneps2bf16128">,
       DefaultAttrsIntrinsic<[llvm_v8bf16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 def int_x86_vcvtneps2bf16256
     : ClangBuiltin<"__builtin_ia32_vcvtneps2bf16256">,
       DefaultAttrsIntrinsic<[llvm_v8bf16_ty], [llvm_v8f32_ty], [IntrNoMem]>;
 }
 //===----------------------------------------------------------------------===//
+// SM3 intrinsics
+let TargetPrefix = "x86" in {
+  def int_x86_vsm3msg1
+      : ClangBuiltin<"__builtin_ia32_vsm3msg1">,
+        DefaultAttrsIntrinsic<[llvm_v4i32_ty],
+        [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+        [IntrNoMem]>;
+  def int_x86_vsm3msg2
+      : ClangBuiltin<"__builtin_ia32_vsm3msg2">,
+        DefaultAttrsIntrinsic<[llvm_v4i32_ty],
+        [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+        [IntrNoMem]>;
+  def int_x86_vsm3rnds2
+      : ClangBuiltin<"__builtin_ia32_vsm3rnds2">,
+        DefaultAttrsIntrinsic<[llvm_v4i32_ty],
+        [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty],
+        [ImmArg<ArgIndex<3>>, IntrNoMem]>;
+}
+//===----------------------------------------------------------------------===//
 // RAO-INT intrinsics
 let TargetPrefix = "x86" in {
   def int_x86_aadd32
       : ClangBuiltin<"__builtin_ia32_aadd32">,
         Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrArgMemOnly]>;
   def int_x86_aadd64
       : ClangBuiltin<"__builtin_ia32_aadd64">,
         Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], [IntrArgMemOnly]>;

llvm/include/llvm/TargetParser/X86TargetParser.def

 X86_FEATURE       (X87,             "x87")
 X86_FEATURE       (XSAVE,           "xsave")
 X86_FEATURE       (XSAVEC,          "xsavec")
 X86_FEATURE       (XSAVEOPT,        "xsaveopt")
 X86_FEATURE       (XSAVES,          "xsaves")
 X86_FEATURE       (HRESET,          "hreset")
 X86_FEATURE       (RAOINT,          "raoint")
 X86_FEATURE       (AVX512FP16,      "avx512fp16")
+X86_FEATURE       (SM3,             "sm3")
 X86_FEATURE       (AMX_FP16,        "amx-fp16")
 X86_FEATURE       (CMPCCXADD,       "cmpccxadd")
 X86_FEATURE       (AVXNECONVERT,    "avxneconvert")
 X86_FEATURE       (AVXVNNI,         "avxvnni")
 X86_FEATURE       (AVXIFMA,         "avxifma")
 X86_FEATURE       (AVXVNNIINT8,     "avxvnniint8")
 X86_FEATURE       (SHA512,          "sha512")
 // These features aren't really CPU features, but the frontend can set them.
 X86_FEATURE       (RETPOLINE_EXTERNAL_THUNK,    "retpoline-external-thunk")
 X86_FEATURE       (RETPOLINE_INDIRECT_BRANCHES, "retpoline-indirect-branches")
 X86_FEATURE       (RETPOLINE_INDIRECT_CALLS,    "retpoline-indirect-calls")
 X86_FEATURE       (LVI_CFI,                     "lvi-cfi")
 X86_FEATURE       (LVI_LOAD_HARDENING,          "lvi-load-hardening")
 #undef X86_FEATURE_COMPAT
 #undef X86_FEATURE

llvm/lib/Target/X86/X86.td

def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
                                       [FeatureSSE2]>;
 def FeatureSHA512  : SubtargetFeature<"sha512", "HasSHA512", "true",
                                       "Support SHA512 instructions",
                                       [FeatureAVX]>;
 // Processor supports CET SHSTK - Control-Flow Enforcement Technology
 // using Shadow Stack
 def FeatureSHSTK   : SubtargetFeature<"shstk", "HasSHSTK", "true",
                        "Support CET Shadow-Stack instructions">;
+def FeatureSM3     : SubtargetFeature<"sm3", "HasSM3", "true",
+                                      "Support SM3 instructions",
+                                      [FeatureAVX]>;
 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
                                       "Support PRFCHW instructions">;
 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
                                       "Support RDSEED instruction">;
 def FeatureLAHFSAHF64 : SubtargetFeature<"sahf", "HasLAHFSAHF64", "true",
                            "Support LAHF and SAHF instructions in 64-bit mode">;
 def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
                                       "Enable MONITORX/MWAITX timer functionality">;

llvm/lib/Target/X86/X86InstrInfo.td

 def HasIFMA      : Predicate<"Subtarget->hasIFMA()">;
 def HasAVXIFMA   : Predicate<"Subtarget->hasAVXIFMA()">;
 def NoVLX_Or_NoIFMA : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasIFMA()">;
 def HasRTM       : Predicate<"Subtarget->hasRTM()">;
 def HasADX       : Predicate<"Subtarget->hasADX()">;
 def HasSHA       : Predicate<"Subtarget->hasSHA()">;
 def HasSHA512    : Predicate<"Subtarget->hasSHA512()">;
 def HasSGX       : Predicate<"Subtarget->hasSGX()">;
+def HasSM3       : Predicate<"Subtarget->hasSM3()">;
 def HasRDSEED    : Predicate<"Subtarget->hasRDSEED()">;
 def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">;
 def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">;
 def HasPRFCHW    : Predicate<"Subtarget->hasPRFCHW()">;
 def HasPREFETCHI : Predicate<"Subtarget->hasPREFETCHI()">;
 def HasPrefetchW : Predicate<"Subtarget->hasPrefetchW()">;
 def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">;
 def HasLAHFSAHF  : Predicate<"Subtarget->hasLAHFSAHF()">;

llvm/lib/Target/X86/X86InstrSSE.td

def VSHA512MSG2rr : I<0xcd, MRMSrcReg, (outs VR256:$dst),
                      VEX, T8XD, Sched<[WriteVecIMul]>;
 def VSHA512RNDS2rr : I<0xcb, MRMSrcReg, (outs VR256:$dst),
                       (ins VR256:$src1, VR256:$src2, VR128:$src3),
                       "vsha512rnds2\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                       [(set VR256:$dst,
                         (int_x86_vsha512rnds2 VR256:$src1, VR256:$src2, VR128:$src3))]>,
                       VEX_L, VEX_4V, T8XD, Sched<[WriteVecIMul]>;
 }
+
+// FIXME: Is there a better scheduler class for SM3 than WriteVecIMul?
+let Predicates = [HasSM3], Constraints = "$src1 = $dst" in {
+  multiclass SM3_Base<string OpStr> {
+    def rr : I<0xda, MRMSrcReg, (outs VR128:$dst),
+              (ins VR128:$src1, VR128:$src2, VR128:$src3),
+              !strconcat(OpStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+              [(set VR128:$dst,
+               (!cast<Intrinsic>("int_x86_"#OpStr) VR128:$src1,
+                VR128:$src2, VR128:$src3))]>,
+              Sched<[WriteVecIMul]>, VEX_4V;
+    def rm : I<0xda, MRMSrcMem, (outs VR128:$dst),
+              (ins VR128:$src1, VR128:$src2, i128mem:$src3),
+              !strconcat(OpStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+              [(set VR128:$dst,
+               (!cast<Intrinsic>("int_x86_"#OpStr) VR128:$src1,
+                VR128:$src2, (loadv4i32 addr:$src3)))]>,
+              Sched<[WriteVecIMul]>, VEX_4V;
+  }
+
+  multiclass VSM3RNDS2_Base {
+    def rr : Ii8<0xde, MRMSrcReg, (outs VR128:$dst),
+              (ins VR128:$src1, VR128:$src2, VR128:$src3, i32u8imm:$src4),
+              "vsm3rnds2\t{$src4, $src3, $src2, $dst|$dst, $src2, $src3, $src4}",
+              [(set VR128:$dst,
+               (int_x86_vsm3rnds2 VR128:$src1,
+                VR128:$src2, VR128:$src3, timm:$src4))]>,
+              Sched<[WriteVecIMul]>;
+    def rm : Ii8<0xde, MRMSrcMem, (outs VR128:$dst),
+              (ins VR128:$src1, VR128:$src2, i128mem:$src3, i32u8imm:$src4),
+              "vsm3rnds2\t{$src4, $src3, $src2, $dst|$dst, $src2, $src3, $src4}",
+              [(set VR128:$dst,
+               (int_x86_vsm3rnds2 VR128:$src1,
+                VR128:$src2, (loadv4i32 addr:$src3), timm:$src4))]>,
+              Sched<[WriteVecIMul]>;
+  }
+}
+
+defm VSM3MSG1 : SM3_Base<"vsm3msg1">, T8PS;
+defm VSM3MSG2 : SM3_Base<"vsm3msg2">, T8PD;
+defm VSM3RNDS2 : VSM3RNDS2_Base, VEX_4V, TAPD;

llvm/lib/TargetParser/Host.cpp

#endif
   Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
   Features["amx-bf16"]   = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
   Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save;
   Features["amx-tile"]   = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
   Features["amx-int8"]   = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
   bool HasLeaf7Subleaf1 =
       MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
   Features["sha512"]     = HasLeaf7Subleaf1 && ((EAX >> 0) & 1);
+  Features["sm3"]        = HasLeaf7Subleaf1 && ((EAX >> 1) & 1);
   Features["raoint"]     = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);
   Features["avxvnni"]    = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
   Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
   Features["amx-fp16"]   = HasLeaf7Subleaf1 && ((EAX >> 21) & 1) && HasAMXSave;
   Features["cmpccxadd"]  = HasLeaf7Subleaf1 && ((EAX >> 7) & 1);
   Features["hreset"]     = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);
   Features["avxifma"]    = HasLeaf7Subleaf1 && ((EAX >> 23) & 1) && HasAVXSave;
   Features["avxvnniint8"] = HasLeaf7Subleaf1 && ((EDX >> 4) & 1) && HasAVXSave;

llvm/lib/TargetParser/X86TargetParser.cpp

 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
+constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX;
 
 // AVX512 features.
 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;

llvm/test/CodeGen/X86/sm3-intrinsics.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sm3 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sm3 | FileCheck %s
+
+define <4 x i32> @test_int_x86_vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: test_int_x86_vsm3msg1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsm3msg1 %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x70,0xda,0xc2]
+; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
+  ret <4 x i32> %ret
+}
+declare <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
+
+define <4 x i32> @test_int_x86_vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: test_int_x86_vsm3msg2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsm3msg2 %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x71,0xda,0xc2]
+; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
+  ret <4 x i32> %ret
+}
+declare <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
+
+define <4 x i32> @test_int_x86_vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: test_int_x86_vsm3rnds2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsm3rnds2 $127, %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe3,0x71,0xde,0xc2,0x7f]
+; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32 127)
+  ret <4 x i32> %ret
+}
+declare <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32 %D)
+

llvm/test/MC/Disassembler/X86/sm3-32.txt

+# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:        vsm3msg1 %xmm4, %xmm3, %xmm2
+# INTEL:      vsm3msg1 xmm2, xmm3, xmm4
+0xc4,0xe2,0x60,0xda,0xd4
+
+# ATT:        vsm3msg1  268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL:      vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        vsm3msg1  291(%edi,%eax,4), %xmm3, %xmm2
+# INTEL:      vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        vsm3msg1  (%eax), %xmm3, %xmm2
+# INTEL:      vsm3msg1 xmm2, xmm3, xmmword ptr [eax]
+0xc4,0xe2,0x60,0xda,0x10
+
+# ATT:        vsm3msg1  -512(,%ebp,2), %xmm3, %xmm2
+# INTEL:      vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        vsm3msg1  2032(%ecx), %xmm3, %xmm2
+# INTEL:      vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032]
+0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00
+
+# ATT:        vsm3msg1  -2048(%edx), %xmm3, %xmm2
+# INTEL:      vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048]
+0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff
+
+# ATT:        vsm3msg2 %xmm4, %xmm3, %xmm2
+# INTEL:      vsm3msg2 xmm2, xmm3, xmm4
+0xc4,0xe2,0x61,0xda,0xd4
+
+# ATT:        vsm3msg2  268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL:      vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        vsm3msg2  291(%edi,%eax,4), %xmm3, %xmm2
+# INTEL:      vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        vsm3msg2  (%eax), %xmm3, %xmm2
+# INTEL:      vsm3msg2 xmm2, xmm3, xmmword ptr [eax]
+0xc4,0xe2,0x61,0xda,0x10
+
+# ATT:        vsm3msg2  -512(,%ebp,2), %xmm3, %xmm2
+# INTEL:      vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        vsm3msg2  2032(%ecx), %xmm3, %xmm2
+# INTEL:      vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032]
+0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00
+
+# ATT:        vsm3msg2  -2048(%edx), %xmm3, %xmm2
+# INTEL:      vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048]
+0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff
+
+# ATT:        vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
+# INTEL:      vsm3rnds2 xmm2, xmm3, xmm4, 123
+0xc4,0xe3,0x61,0xde,0xd4,0x7b
+
+# ATT:        vsm3rnds2  $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL:      vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT:        vsm3rnds2  $123, 291(%edi,%eax,4), %xmm3, %xmm2
+# INTEL:      vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT:        vsm3rnds2  $123, (%eax), %xmm3, %xmm2
+# INTEL:      vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123
+0xc4,0xe3,0x61,0xde,0x10,0x7b
+
+# ATT:        vsm3rnds2  $123, -512(,%ebp,2), %xmm3, %xmm2
+# INTEL:      vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b
+
+# ATT:        vsm3rnds2  $123, 2032(%ecx), %xmm3, %xmm2
+# INTEL:      vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123
+0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b
+
+# ATT:        vsm3rnds2  $123, -2048(%edx), %xmm3, %xmm2
+# INTEL:      vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123
+0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b
+

llvm/test/MC/Disassembler/X86/sm3-64.txt

+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   vsm3msg1 %xmm4, %xmm13, %xmm12
+# INTEL: vsm3msg1 xmm12, xmm13, xmm4
+0xc4,0x62,0x10,0xda,0xe4
+
+# ATT:   vsm3msg1  268435456(%rbp,%r14,8), %xmm13, %xmm12
+# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10
+
+# ATT:   vsm3msg1  291(%r8,%rax,4), %xmm13, %xmm12
+# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00
+
+# ATT:   vsm3msg1  (%rip), %xmm13, %xmm12
+# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00
+
+# ATT:   vsm3msg1  -512(,%rbp,2), %xmm13, %xmm12
+# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:   vsm3msg1  2032(%rcx), %xmm13, %xmm12
+# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00
+
+# ATT:   vsm3msg1  -2048(%rdx), %xmm13, %xmm12
+# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff
+
+# ATT:   vsm3msg2 %xmm4, %xmm13, %xmm12
+# INTEL: vsm3msg2 xmm12, xmm13, xmm4
+0xc4,0x62,0x11,0xda,0xe4
+
+# ATT:   vsm3msg2  268435456(%rbp,%r14,8), %xmm13, %xmm12
+# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10
+
+# ATT:   vsm3msg2  291(%r8,%rax,4), %xmm13, %xmm12
+# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00
+
+# ATT:   vsm3msg2  (%rip), %xmm13, %xmm12
+# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00
+
+# ATT:   vsm3msg2  -512(,%rbp,2), %xmm13, %xmm12
+# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:   vsm3msg2  2032(%rcx), %xmm13, %xmm12
+# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00
+
+# ATT:   vsm3msg2  -2048(%rdx), %xmm13, %xmm12
+# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff
+
+# ATT:   vsm3rnds2 $123, %xmm4, %xmm13, %xmm12
+# INTEL: vsm3rnds2 xmm12, xmm13, xmm4, 123
+0xc4,0x63,0x11,0xde,0xe4,0x7b
+
+# ATT:   vsm3rnds2  $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12
+# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT:   vsm3rnds2  $123, 291(%r8,%rax,4), %xmm13, %xmm12
+# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT:   vsm3rnds2  $123, (%rip), %xmm13, %xmm12
+# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
+0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b
+
+# ATT:   vsm3rnds2  $123, -512(,%rbp,2), %xmm13, %xmm12
+# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123
+0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b
+
+# ATT:   vsm3rnds2  $123, 2032(%rcx), %xmm13, %xmm12
+# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123
+0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b
+
+# ATT:   vsm3rnds2  $123, -2048(%rdx), %xmm13, %xmm12
+# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123
+0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b
+

llvm/test/MC/X86/sm3-att-32.s

+// RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK:      vsm3msg1 %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
+               vsm3msg1 %xmm4, %xmm3, %xmm2
+
+// CHECK:      vsm3msg1  268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+               vsm3msg1  268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK:      vsm3msg1  291(%edi,%eax,4), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+               vsm3msg1  291(%edi,%eax,4), %xmm3, %xmm2
+
+// CHECK:      vsm3msg1  (%eax), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x10]
+               vsm3msg1  (%eax), %xmm3, %xmm2
+
+// CHECK:      vsm3msg1  -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+               vsm3msg1  -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK:      vsm3msg1  2032(%ecx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
+               vsm3msg1  2032(%ecx), %xmm3, %xmm2
+
+// CHECK:      vsm3msg1  -2048(%edx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
+               vsm3msg1  -2048(%edx), %xmm3, %xmm2
+
+// CHECK:      vsm3msg2 %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
+               vsm3msg2 %xmm4, %xmm3, %xmm2
+
+// CHECK:      vsm3msg2  268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+               vsm3msg2  268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK:      vsm3msg2  291(%edi,%eax,4), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+               vsm3msg2  291(%edi,%eax,4), %xmm3, %xmm2
+
+// CHECK:      vsm3msg2  (%eax), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x10]
+               vsm3msg2  (%eax), %xmm3, %xmm2
+
+// CHECK:      vsm3msg2  -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+               vsm3msg2  -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK:      vsm3msg2  2032(%ecx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
+               vsm3msg2  2032(%ecx), %xmm3, %xmm2
+
+// CHECK:      vsm3msg2  -2048(%edx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
+               vsm3msg2  -2048(%edx), %xmm3, %xmm2
+
+// CHECK:      vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
+               vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
+
+// CHECK:      vsm3rnds2  $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+               vsm3rnds2  $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK:      vsm3rnds2  $123, 291(%edi,%eax,4), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+               vsm3rnds2  $123, 291(%edi,%eax,4), %xmm3, %xmm2
+
+// CHECK:      vsm3rnds2  $123, (%eax), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x10,0x7b]
+               vsm3rnds2  $123, (%eax), %xmm3, %xmm2
+
+// CHECK:      vsm3rnds2  $123, -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+               vsm3rnds2  $123, -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK:      vsm3rnds2  $123, 2032(%ecx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b]
+               vsm3rnds2  $123, 2032(%ecx), %xmm3, %xmm2
+
+// CHECK:      vsm3rnds2  $123, -2048(%edx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b]
+               vsm3rnds2  $123, -2048(%edx), %xmm3, %xmm2
+

llvm/test/MC/X86/sm3-att-64.s

+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 %xmm4, %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4]
+          vsm3msg1 %xmm4, %xmm13, %xmm12
+
+// CHECK: vsm3msg1  268435456(%rbp,%r14,8), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+          vsm3msg1  268435456(%rbp,%r14,8), %xmm13, %xmm12
+
+// CHECK: vsm3msg1  291(%r8,%rax,4), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+          vsm3msg1  291(%r8,%rax,4), %xmm13, %xmm12
+
+// CHECK: vsm3msg1  (%rip), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00]
+          vsm3msg1  (%rip), %xmm13, %xmm12
+
+// CHECK: vsm3msg1  -512(,%rbp,2), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+          vsm3msg1  -512(,%rbp,2), %xmm13, %xmm12
+
+// CHECK: vsm3msg1  2032(%rcx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00]
+          vsm3msg1  2032(%rcx), %xmm13, %xmm12
+
+// CHECK: vsm3msg1  -2048(%rdx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff]
+          vsm3msg1  -2048(%rdx), %xmm13, %xmm12
+
+// CHECK: vsm3msg2 %xmm4, %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4]
+          vsm3msg2 %xmm4, %xmm13, %xmm12
+
+// CHECK: vsm3msg2  268435456(%rbp,%r14,8), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+          vsm3msg2  268435456(%rbp,%r14,8), %xmm13, %xmm12
+
+// CHECK: vsm3msg2  291(%r8,%rax,4), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+          vsm3msg2  291(%r8,%rax,4), %xmm13, %xmm12
+
+// CHECK: vsm3msg2  (%rip), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00]
+          vsm3msg2  (%rip), %xmm13, %xmm12
+
+// CHECK: vsm3msg2  -512(,%rbp,2), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+          vsm3msg2  -512(,%rbp,2), %xmm13, %xmm12
+
+// CHECK: vsm3msg2  2032(%rcx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00]
+          vsm3msg2  2032(%rcx), %xmm13, %xmm12
+
+// CHECK: vsm3msg2  -2048(%rdx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff]
+          vsm3msg2  -2048(%rdx), %xmm13, %xmm12
+
+// CHECK: vsm3rnds2 $123, %xmm4, %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b]
+          vsm3rnds2 $123, %xmm4, %xmm13, %xmm12
+
+// CHECK: vsm3rnds2  $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+          vsm3rnds2  $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12
+
+// CHECK: vsm3rnds2  $123, 291(%r8,%rax,4), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b]
+          vsm3rnds2  $123, 291(%r8,%rax,4), %xmm13, %xmm12
+
+// CHECK: vsm3rnds2  $123, (%rip), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b]
+          vsm3rnds2  $123, (%rip), %xmm13, %xmm12
+
+// CHECK: vsm3rnds2  $123, -512(,%rbp,2), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+          vsm3rnds2  $123, -512(,%rbp,2), %xmm13, %xmm12
+
+// CHECK: vsm3rnds2  $123, 2032(%rcx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b]
+          vsm3rnds2  $123, 2032(%rcx), %xmm13, %xmm12
+
+// CHECK: vsm3rnds2  $123, -2048(%rdx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b]
+          vsm3rnds2  $123, -2048(%rdx), %xmm13, %xmm12
+

llvm/test/MC/X86/sm3-intel-32.s

+// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:      vsm3msg1 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
+               vsm3msg1 xmm2, xmm3, xmm4
+
+// CHECK:      vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+               vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+
+// CHECK:      vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+               vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+
+// CHECK:      vsm3msg1 xmm2, xmm3, xmmword ptr [eax]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x10]
+               vsm3msg1 xmm2, xmm3, xmmword ptr [eax]
+
+// CHECK:      vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+               vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+
+// CHECK:      vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
+               vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032]
+
+// CHECK:      vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
+               vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048]
+
+// CHECK:      vsm3msg2 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
+               vsm3msg2 xmm2, xmm3, xmm4
+
+// CHECK:      vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+               vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+
+// CHECK:      vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+               vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+
+// CHECK:      vsm3msg2 xmm2, xmm3, xmmword ptr [eax]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x10]
+               vsm3msg2 xmm2, xmm3, xmmword ptr [eax]
+
+// CHECK:      vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+               vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+
+// CHECK:      vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
+               vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032]
+
+// CHECK:      vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
+               vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048]
+
+// CHECK:      vsm3rnds2 xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
+               vsm3rnds2 xmm2, xmm3, xmm4, 123
+
+// CHECK:      vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+               vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK:      vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+               vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+
+// CHECK:      vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x10,0x7b]
+               vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123
+
+// CHECK:      vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+               vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+
+// CHECK:      vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b]
+               vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123
+
+// CHECK:      vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b]
+               vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123
+

llvm/test/MC/X86/sm3-intel-64.s

+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4]
+          vsm3msg1 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+          vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+          vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00]
+          vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+          vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00]
+          vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff]
+          vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4]
+          vsm3msg2 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+          vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+          vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00]
+          vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+          vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00]
+          vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff]
+          vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmm4, 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b]
+          vsm3rnds2 xmm12, xmm13, xmm4, 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+          vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b]
+          vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b]
+          vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+          vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b]
+          vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b]
+          vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123
+

llvm/test/TableGen/x86-fold-tables.inc

   {X86::VSHUFI64X2Z256rrikz, X86::VSHUFI64X2Z256rmikz, 0},
   {X86::VSHUFI64X2Zrrikz, X86::VSHUFI64X2Zrmikz, 0},
   {X86::VSHUFPDZ128rrikz, X86::VSHUFPDZ128rmikz, 0},
   {X86::VSHUFPDZ256rrikz, X86::VSHUFPDZ256rmikz, 0},
   {X86::VSHUFPDZrrikz, X86::VSHUFPDZrmikz, 0},
   {X86::VSHUFPSZ128rrikz, X86::VSHUFPSZ128rmikz, 0},
   {X86::VSHUFPSZ256rrikz, X86::VSHUFPSZ256rmikz, 0},
   {X86::VSHUFPSZrrikz, X86::VSHUFPSZrmikz, 0},
+  {X86::VSM3MSG1rr, X86::VSM3MSG1rm, 0},
+  {X86::VSM3MSG2rr, X86::VSM3MSG2rm, 0},
+  {X86::VSM3RNDS2rr, X86::VSM3RNDS2rm, 0},
   {X86::VSQRTPDZ128rk, X86::VSQRTPDZ128mk, 0},
   {X86::VSQRTPDZ256rk, X86::VSQRTPDZ256mk, 0},
   {X86::VSQRTPDZrk, X86::VSQRTPDZmk, 0},
   {X86::VSQRTPHZ128rk, X86::VSQRTPHZ128mk, 0},
   {X86::VSQRTPHZ256rk, X86::VSQRTPHZ256mk, 0},
   {X86::VSQRTPHZrk, X86::VSQRTPHZmk, 0},
   {X86::VSQRTPSZ128rk, X86::VSQRTPSZ128mk, 0},
   {X86::VSQRTPSZ256rk, X86::VSQRTPSZ256mk, 0},