[2/N][RISCV] Model vxrm in LLVM intrinsics and machine instructions for RVV fixed-point instructions

[eopXD]

Summary

Depends on D151395.

This is the 2nd patch of the patch-set. For the cover letter of the
patch-set, please checkout D151395. This patch originates from
D121376.

This commit models vxrm by adding an immediate operand into intrinsics
and machine instructions of RVV fixed-point instruction vaadd,
vaaddu, vasub, and vasubu. This commit only covers intrinsics of
the four instructions, the proceeding patches of the patch-set will do
the same to other RVV fixed-point instructions.

The current naiive approach is to have a write to vxrm inserted before
every fixed-point instruction. This is done by the new added pass
RISCVInsertReadWriteCSR. The reason to name the pass in a more general
term is because we will also model rounding mode for the RVV floating-
point instructions. The approach will be improved in the future,
implementing partial redundancy elimination algorithms to it.

The original LLVM intrinsics and machine instructions, take vaadd as
an example, does not model the rounding mode is not removed in this
patch. That is, int.riscv.vaadd.* co-exists with
int.riscv.vaadd.rm.* after this patch. The next patch will add C
intrinsics of vaadd with an additional operand that models the control
of the rounding mode, in this patch, int.riscv.vaadd.rm.* will
replace int.riscv.vaadd.*.

Authored-by: ShihPo Hung <[e-mail]>
Co-Authored-by: eop Chen <[e-mail]>

[eopXD]

Bump CI.

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

118

Extra blank line

llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp

2

Incorrect file name and description

12

naive*

"insertion a write" -> "insertion of a write"?

84

Use operator* instead of optional::value. See many patches like 1792821c8308755593c114c3b7ae8ce33bdb08e9

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

2037

80 characters

2038

This isn't indented far enought to line up with RetClass.

6713

I would kind of prefer you do this 4 instruction group together.

[eopXD]

Address comments from Craig and resolve other test failures.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp

23

RISCV -> RISC-V

87

We need to add an implicit use of VXRM to the vector instruction. That's how we do it in the InsertVSETVLI pass. See

MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false,      
                                        /*isImp*/ true));

from RISCVInsertVSETVLI::emitVSETVLIs

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

6043–6044

The Pseudos don't use VXRM until the VXRM write instruction is inserted.

6045

Line up the colons

llvm/test/CodeGen/RISCV/O0-pipeline.ll

44

RISCV -> RISC-V

llvm/test/CodeGen/RISCV/rvv/vxrm.mir

27–28

Should we delete the existing WriteVXRMImm instruction from this test?

[eopXD]

Address comments from Craig.

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/vxrm.mir

17

I would expect there to be two $vxrm operands since you started with one and the pass added one.

28

Drop the implicit $vxrm here. It shouldn't exist until the pass runs.

The implicit $vl, implicit $vtype operands shouldn't exist until the InsertVSETVLI pass runs.